11/5/2020 Power ISA - Wikipedia

Power ISA
The Power ISA is an instruction set architecture (ISA) developed
by the OpenPOWER Foundation, led by IBM. It was originally Power ISA
developed by the now defunct Power.org industry group. Power ISA Designer Power.org
is an evolution of the PowerPC ISA, created by the mergers of the OpenPOWER
core PowerPC ISA and the optional Book E for embedded
Foundation
applications. The merger of these two components in 2006 was led
by Power.org founders IBM and Freescale Semiconductor. The ISA Bits 32-bit/64-bit (32 →
is divided into several categories and every component is defined as 64)
a part of a category; each category resides within a certain Book.
Introduced 2006
Processors implement a set of these categories. Different classes of
processors are required to implement certain categories, for example Version 3.1
a server class processor includes the categories Base, Server, Design RISC
Floating-Point, 64-Bit, etc. All processors implement the Base
Type Register-Register
category.
Encoding Fixed/Variable
Power ISA is a RISC load/store architecture. It has multiple sets of
Branching Condition code
registers:
Endianness Big/Bi
32 × 32-bit or 64-bit general purpose registers (GPRs) for integer Extensions AltiVec, APU, DSP,
operations.
CBEA
64 × 128-bit vector scalar registers (VSRs) for vector operations
and floating point operations. Open Yes, and royalty free
Registers
32 × 64-bit floating-point registers (FPRs) as part of the
VSRs for floating point operations.
32× 64/32-bit general purpose
32 × 128-bit vector registers (VRs) as part of the VSRs for
registers
vector operations.
8 × 4-bit condition register fields (CRs) for comparison and 32× 64-bit floating point registers
control flow. 32× 128-bit vector registers
11 special registers of various sizes: Counter Register (CTR), 32-bit condition code register
link register (LR), time base (TBU, TBL), alternate time base
32-bit link register
(ATBU, ATBL), accumulator (ACC), status registers (XER,
FPSCR, VSCR, SPEFSCR). 32-bit count register
+ more
Instructions have a length of 32 bits, with the exception of the VLE
(variable-length encoding) subset that provides for higher code density for low-end embedded
applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and
double precision IEEE-754 compliant floating point operations are supported, including additional fused
multiply–add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations
on integer and floating point data on up to 16 elements in a single instruction.

Power ISA has support for Harvard cache, i.e. split data and instruction caches, as well as support for
unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is
also support for both big and little-endian addressing with separate categories for moded and per-page
endianness, as well as support for both 32-bit and 64-bit addressing.

Different modes of operation include user, supervisor and hypervisor.

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Contents
Categories
Books
Specifications
Power ISA v.2.03
Power ISA v.2.04
Power ISA v.2.05
Power ISA v.2.06
Power ISA v.2.07
A highly schematic diagram over a
Power ISA v.3.0 generic Power ISA processor.
Power ISA v.3.1
See also
References

Categories
Base – Most of Book I and Book II
Server – Book III-S
Embedded – Book III-E
Misc – floating point, vector, signal processing, cache locking, decimal floating point, etc.

Books
The Power ISA specification is divided into five parts, called "books":

Book I – User Instruction Set Architecture covers the base instruction set available to the application
programmer. Memory reference, flow control, Integer, floating point, numeric acceleration,
application-level programming. It includes chapters regarding auxiliary processing units like DSPs
and the AltiVec extension.
Book II – Virtual Environment Architecture defines the storage model available to the application
programmer, including timing, synchronization, cache management, storage features, byte ordering.
Book III – Operating Environment Architecture includes exceptions, interrupts, memory
management, debug facilities and special control functions. It's divided into two parts.
Book III-S – Defines the supervisor instructions used for general purpose/server
implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
Book III-E – Defines the supervisor instructions used for embedded applications. It is derived
from the former PowerPC Book E.
Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and
definitions from Book I-III, intended for higher instruction density and very-low-end applications. They
use 16-bit instructions and big endian byte ordering.

Specifications
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Power ISA v.2.03

The specification for Power ISA v.2.03[1] is based on the former PowerPC ISA v.2.02[2] in POWER5+ and
the Book E[3] extension of the PowerPC specification. The Book I included five new chapters regarding
auxiliary processing units like DSPs and the AltiVec extension.

Compliant cores

Freescale PowerPC e200, e500

IBM PowerPC 405, 440, 460, 970, POWER5 and POWER6
IBM Cell PPE

Power ISA v.2.04

The specification for Power ISA v.2.04[4] was finalized in June 2007. It is based on Power ISA v.2.03 and
includes changes primarily to the Book III-S part regarding virtualization, hypervisor functionality,
logical partitioning and virtual page handling.

Compliant cores

All cores that comply with previous versions of the Power ISA
The PA6T core from P.A. Semi
Titan from AMCC

Power ISA v.2.05

The specification for Power ISA v.2.05[5] was released in December 2007. It is based on Power ISA
v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements
such as decimal arithmetic (Category: Decimal Floating-Point in Book I) and server hypervisor
improvements.

Compliant cores

All cores that comply with previous versions of the Power ISA
POWER6
PowerPC 476

Power ISA v.2.06

The specification for Power ISA v.2.06[6] was released in February 2009, and revised in July 2010.[7] It
is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One
significant new feature is vector-scalar floating-point instructions (VSX).[8] Book III-E also includes
significant enhancement for the embedded specification regarding hypervisor and virtualisation on
single and multi core implementations.

The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing
virtualization features.[7][9]

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Compliant cores

All cores that comply with previous versions of the Power ISA
POWER7
A2I
e500-mc
e5500

Power ISA v.2.07

The specification for Power ISA v.2.07[10] was released in May 2013. It is based on Power ISA v.2.06 and
includes major enhancements to logical partition functionality, transactional memory, expanded
performance monitoring, new storage control features, additions to the VMX and VSX vector facilities
(VSX-2), along with AES[10]:257[11] and Galois Counter Mode (GCM), SHA-224, SHA-256,[10]:258 SHA-
384 and SHA-512[10]:258 (SHA-2) cryptographic extensions and cyclic redundancy check (CRC)
algorithms.[12]

The spec was revised in April 2015 to the Power ISA v.2.07 B spec.[13]

Compliant cores

All cores that comply with previous versions of the Power ISA
POWER8
e6500 core
A2O

Power ISA v.3.0

The specification for Power ISA v.3.0[14][15] was released in November 2015. It is the first to come out
after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of
workloads and removes the server and embedded categories while retaining backwards compatibility
and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point
operations, a random number generator, hardware-assisted garbage collection and hardware-enforced
trusted computing.

The spec was revised in March 2017 to the Power ISA v.3.0 B spec.[16]

Compliant cores

All cores that comply with previous versions of the Power ISA
POWER9[17]

Power ISA v.3.1

The specification for Power ISA v.3.1[18] was released in May 2020. Mainly giving support for new
functionality introduced in POWER10, but also includes the notion of optionality to the PowerISA
specification. Instructions can now be eight bytes long, "prefixed instructions", compared to the usual
four byte "word instructions". A lot of new functionality to SIMD and VSX instructions are also added.
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Compliant cores

All cores that comply with previous versions of the Power ISA
POWER10[19]

See also
Open-source computing hardware

References
1. "Power ISA v.2.03" (https://web.archive.org/web/20121124005736/https://www.power.org/technology-
introduction/standards-specifications/). Power.org. 2006-09-29. Archived from the original (https://ww
w.power.org/technology-introduction/standards-specifications/) on 2012-11-24. Retrieved
2010-10-20.
2. "PowerPC Architecture Book, Version 2.02" (http://www.ibm.com/developerworks/eserver/library/es-a
rchguide-v2.html). IBM. 2005-02-24. Retrieved 2007-03-16.
3. "PowerPC Book E v.1.0" (https://www.nxp.com/docs/en/user-guide/BOOK_EUM.pdf?&fsrch=1)
(PDF). IBM. 2002-05-07. Retrieved 2007-03-16.
4. "Power ISA Version 2.04" (https://web.archive.org/web/20070927235845/http://www.power.org/resou
rces/downloads/PowerISA_Public.pdf) (PDF). Power.org. 2007-06-12. Archived from the original (htt
p://www.power.org/resources/downloads/PowerISA_Public.pdf) (PDF) on 2007-09-27. Retrieved
2007-06-14.
5. "Power ISA Version 2.05" (https://web.archive.org/web/20121124005736/https://www.power.org/tech
nology-introduction/standards-specifications/). Power.org. 2007-10-23. Archived from the original (htt
ps://www.power.org/technology-introduction/standards-specifications/) on 2012-11-24. Retrieved
2007-12-18.
6. "Power.org Debuts Specification Advances and New Services At Power Architecture Developer
Conference" (https://web.archive.org/web/20071012121931/http://www.power.org/news/pr/view?item
_key=20eea4d0ce638d7641d7d04d529d9369fee9e280) (Press release). Power.org. 2007-09-24.
Archived from the original (http://www.power.org/news/pr/view?item_key=20eea4d0ce638d7641d7d0
4d529d9369fee9e280) on 2007-10-12. Retrieved 2007-09-24.
7. "Power ISA Version 2.06 Revision B" (https://web.archive.org/web/20121124005736/https://www.pow
er.org/technology-introduction/standards-specifications/). Power.org. 2010-07-23. Archived from the
original (https://www.power.org/technology-introduction/standards-specifications/) on 2012-11-24.
Retrieved 2011-02-12.
8. "Workload acceleration with the IBM POWER vector-scalar architecture" (https://www.researchgate.n
et/publication/299472451). IBM. 2016-03-01. Retrieved 2017-05-02.
9. "Power ISA 2.06 Rev. B enables full hardware virtualization for embedded space" (http://www.eetime
s.com/electronics-products/electronic-product-reviews/power-products/4210382/Power-ISA-2-06-Re
v-B). EETimes. 2010-11-03. Retrieved 2011-06-08.
10. "Power ISA Version 2.07" (http://fileadmin.cs.lth.se/cs/education/EDAN25/PowerISA_V2.07_PUBLI
C.pdf) (PDF). Power.org. 2013-05-15. Retrieved 2015-05-23.
11. Leonidas Barbosa (2014-09-21). "POWER8 in-core cryptography" (http://www.ibm.com/developerwo
rks/library/se-power8-in-core-cryptography/index.html). IBM.
12. Performance Optimization and Tuning Techniques for IBM Power Systems Processors Including IBM
POWER8 (https://books.google.com/books?id=7ph0CgAAQBAJ&q=Power+ISA+v.2.07+aes+gcm+s
ha&pg=PA48). IBM. August 2015. p. 48. ISBN 9780738440927.

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13. "Power ISA Version 2.07 B" (https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-

2-07-b). Power.org. 2015-04-09. Retrieved 2017-01-06.
14. Announcing a New Era of Openness with Power 3.0 (https://www.ibm.com/developerworks/communi
ty/blogs/fe313521-2e95-46f2-817d-44a4f27eba32/entry/Announcing_a_New_Era_of_Openness_wit
h_Power_3_0?lang=en)
15. "Power ISA Version 3.0" (https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0).
openpowerfoundation.org. 2016-11-30. Retrieved 2017-01-06.
16. "Power ISA Version 3.0 B" (https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0).
Power.org. 2017-03-27. Retrieved 2019-08-11.
17. [PATCH, COMMITTED] Add full Power ISA 3.0 / POWER9 binutils support (https://sourceware.org/m
l/binutils/2015-11/msg00071.html)
18. "Power ISA Version 3.1" (https://ibm.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0).
openpowerfoundation.org. 2020-05-01. Retrieved 2020-05-23.
19. Carlos Eduardo Seo (2020-05-12). "We released the Instruction Set Architecture for POWER10.
Power ISA v3.1 is available at the IBM Portal for OpenPOWER" (https://twitter.com/carlos_seo/statu
s/1259976682158555139?s=20). twitter.com. Retrieved 2020-05-23.

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