A Front-End Circuit with 16-channel 12-bit 100-kSps

RC-Hybrid SAR ADC for Industrial Monitoring

Application

Zhelu Li, Jianxiong Xi, Lenian He Kexu Sun

Institute of VLSI Design Department of Electrical Engineering
Zhejiang University Southern Methodist University
Hangzhou, China Dallas, Texas, USA
lizl@vlsi.zju.edu.cn sunkexu@gmail.com

Abstract—A front-end circuit with 16-channel 12-bit 100-kSps
RC-hybrid successive approximation register (SAR) analog-to-
digital converter (ADC) for industrial monitoring application is
presented. The front-end circuit can process a wide range input
voltage as large as 10 V which is beyond the supply voltage, with
the help of voltage divider preceding an analog multiplexer. A
programmable gain amplifier (PGA) is used to convert different
input voltage ranges into a same one. A RC hybrid digital-to-
analog converter (DAC) is employed in SAR ADC to avoid
calibration requirement for the bridge capacitor which is usually
needed for a split capacitor SAR ADC architecture. Serial
peripheral interface (SPI) is integrated in the design for
communication and configuration. The prototype circuit
fabricated in a 0.18 um 3.3 V CMOS process shows the measured
DNL and INL within -0.82/+0.68 LSB and -0.85/+0.82 LSB,
respectively. The circuit consumes 2.04 mW with a 3.3 V supply
voltage. The whole chip occupies an area of 1.844 x 1.387 mm2.
Keywords—Front-End; Industrial Monitoring; Successive
Approximation Register (SAR); Analog-to-Digital Converter (ADC);
RC Hybrid
I. INTRODUCTION
In today’s competitive industry marketplace, the companies
face growing demands to improve process efficiencies, comply
with environmental regulation and meet corporate financial
objectives. Thus an integrated smart sensor platform for
industrial monitoring is a compulsory choice [1-2]. Many
sensors with different kinds of interface standards are
integrated in an industrial monitoring system. To match
different kinds of sensor signal ranges, a variable gain and
multi-channel front-end circuit is often needed. Ref. [3]
presents a 10-bit front-end pipeline ADC with relatively large
presents the architecture of the proposed circuit. Section III
shows the circuit-level implementation. The experimental
results are discussed in section IV. A conclusion is drawn in
section V.
II. ARCHITECTURE
Fig. 1 shows a block diagram of the proposed front-end
circuit. It consists of an analog input multiplexer (MUX), a
PGA, a reference generator (REF), a SAR ADC core, a SPI bus
interface, a temperature sensor, a power-on reset circuit (POR),
and a bias generator. The input multiplexer selects two input
signals to PGA from 16 channels as differential inputs or one
input signal to PGA from 16 channels as single input. There are
16 resistor voltage dividers preceding the multiplexer to
process different input voltage ranges which may beyond the
supply voltage. The reference generator generates 2.5 V
voltage and switches the internal or external reference voltage
for the SAR ADC. The SAR ADC consists of a RC hybrid
DAC, a 12-bit SAR logic controller, and a comparator which
has three stage pre-amplifiers and a dynamic latch. A master
chip communicate with the proposed circuit through the SPI
bus interface and configure the operation of the input
multiplexer, PGA and the reference generator. The temperature
sensor is to detect the chip temperature. Thus, the temperature
drift of the circuit performance can be compensated.
Fig. 2 shows the timing diagram of the proposed circuit. (a)
AVDD AGND DVDD DGND REF
CH VINP
0~15
PGA VIN SAR
ADC
VINN

power consumption. A multi-channel SAR ADC with PGA is REF

attractive for industrial monitoring application with its low Input
MUX SDO
power dissipation and high resolution [4]. SDI
SPI Bus Interface
SCK
In this paper, we present a front-end circuit with 16-channel CS
12-bit 100-kSps RC-hybrid SAR ADC for industrial Temp
POR BIAS
Sensor
monitoring application. An analog multiplexer matches large
input voltage ranges is employed. A RC-hybrid SAR ADC RST
requires no calibration techniques for 12-bit resolution and
reduces the total number of capacitors to save area and power Fig. 1. Block diagram of the proposed circuit.
dissipation. The paper is organized as follows. Section II

978-1-5090-1570-2/16/$31.00 ©2016 IEEE 340 APCCAS 2016

 CS

SPC

SDI

Donÿt Care
SDO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Input range, PGA gain and other registers configuration

(a)
CS

SPC

Donÿt Care
SDI
Donÿt Care
SDO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Channel selection Sampling SAR conversion

(b)
Fig. 2. Timing diagram of the proposed circuit (a) writing timing, (b) reading timing.

is the writing timing, and (b) is the reading timing. Writing
timing is for input range, PGA and reference configuration of
the circuit. Reading timing is for channel selection and analog
to digital conversion operation of the circuit. CS, SPC, SDI,
SDO are all SPI bus signals. CS stands for chip selection. SPC
stands for serial peripheral clock, which is also used as the
conversion clock of the SAR ADC core. SDI is to be written to
the chip configuration registers, which stands for serial data in.
SDO is the serial converted digital code, which stands for serial
data out. The interval from the 0th SPC cycle to the 21st one in
(a) represents writing operation to configure the input voltage
range, the PGA gain and others. The interval from the 0th SPC
cycle to the 6th one in (b) represents writing operation to select
channels. The interval from the 7th SPC cycle to the 9th one
represents sampling operation of SAR ADC. The interval from
the 10th SPC cycle to the 21st one represents conversion
operation of SAR ADC. Apparently, 22 clock cycles are
needed for a single conversion. Thus, 100 kSps rates requires a
2.2 MHz external clock or SPC signal.
III. CIRCUIT IMPLEMENTATION
A. Input Multiplexer and Preceding Voltage Divider
Fig 3. shows the details of the Input MUX. Fig.3 (a) shows
a resistor voltage divider. Three switches are employed to
match different kinds of input ranges. The circuits are designed
in 3.3 V CMOS process. However, the target is to process input
voltages as large as 10 V. With S1 connected and S0, S2
disconnected, 5 V input signal can be scaled to 2.5 V. With S2
connected and S0, S1 disconnected, 10 V input signal can be
scaled to 2.5 V. With S0 connected and S1, S2 disconnected,
small signals can be shifted by a half of reference voltage. For
the input signal AIN is in the range of ± 20 mV, AIN_D can be
shifted to 1.25 V ± 10 mV which is much easier to be
mode, 8 analog transmission gates are employed to select
VINP from 8 inputs, while 8 analog transmission gates are
employed to select VINN from the remaining 8 inputs.
B. PGA
Fig. 4 shows a modified three-opamp PGA. S1, S2, S3 and
S4 select the gain of PGA from 1, 2.5, 12.5 and 125. S5
determines the single-ended mode or differential-ended mode.
The DC voltage of VO is switched by S5 from AGND and a
half of the reference voltage. S6 is to reduce the overall gain of
PGA by 10 %. Thus 10 % over range input voltage can be
processed.
Three op-amplifiers of PGA all requires rail-to-rail input
and output capability and small output resistance to drive a
large capacitor array in SAR ADC. A rail-to-rail input and
output class-AB op-amplifier as shown in Fig. 5 is adopted in
PGA [5]. Rail-to-rail input capability is achieved by M1 to M4
which are operated in sub-threshold region and the aspect ratio
of M5 or M6 is three times that of M1, M3 or M2, M4. Thus
the transconductance of the input stage keeps constant over the
entire range. M7 to M10 forms a floating current source. M21,
M22, M24 and M26 or M19, M20, M23 and M25 forms a
translinear loop which determines the quiescent current
through the output stage. During a positive slewing period,
M24 will be cut off, M23 carries all current. Thus, the gate
voltage of M25 and M26 will be pull high to drive the output to
be low as M25 will be cut off and M26 will be fully on.
VREF AGND
AIN_D<0>
S0
To ESD and
3R
3R
Internal Circuits AIN_D<1> AIN_D<1>
AIN AIN_D
R VINP VINN
2R
AIN_D<14> AIN_D<13>

processed by PGA and SAR ADC. Fig. 3 (b) shows a 16- S1 S2

channel input multiplexer with differential outputs or single AGND

AIN_D<15> AIN_D<15>

output. VINP and VINN are two signals to PGA as shown in

Fig. 1. AIN_Ds are 16 input signals each divided by a (a) (b)
preceding voltage divider. In the single-ended mode, 16 analog Fig. 3. The Input MUX compises 16 voltage dividers and an multiplexer
transmission gates are employed to select VINP from 16 inputs, configured by SPI. (a) resistor voltage divider, (b) 16-channel
and VINN is connected to AGND. In the differential-ended multiplexer.

978-1-5090-1570-2/16/$31.00 ©2016 IEEE 341 APCCAS 2016

 VCM
VIN OP1

S6 S6 VM 5R7C Hybrid DAC

S1
75R1 Ă
VP Cu Ru Ru
S2 R2 Ru Ru Ru Ru

32Cu
16Cu
64Cu
40R1 Ă

8Cu
4Cu
2Cu
Cu
Ru Ru Ru Ru
S3 10R2
9R1 10R2
VIN
S4 VREF
R1 AGND

Bit[11]

Bit[10]

Bit[9]

Bit[8]

Bit[7]

Bit[6]

Bit[5]

Bit[4]

Bit[3]

Bit[0]
Ă
OP2 VO

STROBE
COMP
AGND S5 5R7C Hybrid DAC
R1
10R2 S5 12 Bit Switch Control Signals
S4 AGND COMP
9R1 SAMPLE
12 Bit SAR Logic CLK
VREF/2 RST
S3 10R2 S5
40R1

S2 75R1 R2 Fig. 6. 5R7C Hybrid SAR ADC

S1 S6 S6
VCM
VIP OP1
STROBE
VIP VOP
Fig. 4. A modified three-opamp PGA. VIN Latch VON

AVDD (a)
AVDD
VBP1 VBP1 M22 VBP1 AVDD
M16 M17 STROBE STROBE
VBP VBP

M21 VBP2 M26 VOP

M15 M18 VON VOP VON

VIP VIN
M6 M9 C1
VIN VIP M7 M24 VIP VIN
VO VBN
M2 M1 M3 M4 M8 M23
M10 C0
M5 AGND STROBE

AGND
M11 M13 VBN2 M19 (b) (c)
M25

VBN1 VBN1 M12 M14 VBN1 M20 Fig. 7. Comparator in SAR ADC, (a) three stage pre-amplifiers and a
AGND
dynamic latch, (b) pre-amplifier, (c) dynamic latch.

Fig. 5. A rail-to-rail input and output class-AB op-amplifier in the PGA.
The operation of a negative slewing period is totally opposite.
OP2 in Fig. 4 requires stronger driving capability than OP1,
thus the width of output stage transistors of OP2 is designed to
be larger than that of OP1.
C. RC Hybrid SAR ADC
Fig. 6 shows the proposed 5R7C hybrid SAR ADC core.
The RC hybrid architecture is insensitive to the parasitic value
of the bridge capacitor and doesn’t occupy a large number of
capacitors. Thus, low power, small area and high precision can
be achieved without calibration [6]. Only positive side of the
DAC is shown in the figure. For a matching input circumstance
of the comparator in SAR ADC, a dummy 5R7C DAC is
employed in the negative side. 7-bit binary weighted capacitor
array forms the MSB DAC, and 5-bit R-2R resistor network
MSB capacitor array, a scaled 5-bit LSB voltage is generated
on the top plates of the capacitors. As the voltage on the bottom
plate of the bridge capacitor is always a specific value
determined by the R-2R resistor network in each cycle, the
bottom parasitic capacitance of the bridge capacitor is of no
concern. The resolution of capacitor array is not sensitive to the
parasitic capacitance to AGND as the voltage of the top plates
of the capacitors keep the same in the sampling phase and in
the end of cycling phase as VCM. Thus, calibration is of no
need with careful layout techniques that all signal routes of the
capacitors are shielded with ground plates and vias in four
directions to eliminate parasitic coupling from top plates to
RDAC

forms the LSB DAC. The MSB DAC also acts as a sampling
Bias and Ref

capacitor. During the sampling phase, all of the capacitors’

bottom plates are connected to the input voltage VIN, and all PGA Input
the top plates are connected to a common voltage VCM. In the CDAC
Mux
MSB conversion phase, the bottom sides of all resistors are
Logic

connected to AGND, and the bottom plate of the bridge

capacitor is connected to the resistor network which is also
AGND. The MSB DAC operates as a traditional binary based
capacitor SAR ADC. In the LSB conversion, the R-2R network Comparator SPI
generates unscaled binary divided LSB voltages successively,
such as VREF/2, VREF/4, VREF/8, on the bottom plate of the
bridge capacitor. By the attenuation of the bridge capacitor and Fig. 8. Micro-photo of the proposed chip.

978-1-5090-1570-2/16/$31.00 ©2016 IEEE 342 APCCAS 2016

 0.8
DNL = +0.68 / -0.82 LSB TABLE II. PERFORMANCE COMPARISON WITH OTHER WORKS
0.6
[4] [7] [8] This work
DNL [LSB]

0.4
0.2
0 Technology 0.35um 0.35um 0.25um 0.18um
-0.2
-0.4 Resolution 12 12 12 12
-0.6
-0.8 Supply
-1
0 500 1000 1500 2000 2500 3000 3500 4000 3 3.3 3.3 3.3
Code Voltage/V
1
INL = +0.82 / +0.85 LSB Sampling
0.8 5M 1M 55.55 k 100 k
0.6 Rate
INL [LSB]

0.4
0.2 -1.21 -0.6 -0.998 -0.82
0 DNL/LSB
-0.2
-0.4 +1.32 +0.85 +0.512 +0.68
-0.6
-0.8 -0.93 -0.8 -1.335 -0.85
-1
0 500 1000 1500 2000 2500 3000 3500 4000 INL/LSB
Code +1.1 +0.75 +1.945 +0.82
Fig. 9. Measured results of DNL and INL of the proposed circuit in 2.5 V Channel 2 1 8 16
TABLE I. MEASURED PERFOMANCE SUMMARY Power/mW 56 3 1.683 2.04
Technology 0.18um 1P4M CMOS Area/mm2 6.61 0.69 2.28 2.55
Power Supply 3.3 V PGA N Y N Y
Resolution 12 bit Calibration Y N N N
±20 mV, ±1V differential
Input Range
200 mV, 2.5V, 5V, 10V single V. CONCLUSION
Sampling A front-end circuit with 16-channel 12-bit 100-kSps RC-
100 kSps
Rate hybrid SAR ADC for industrial monitoring application is
±1V 200mV 2.5V 5V 10V presented in this paper. Resistor voltage dividers and an analog
-0.92 -0.93 -0.82 -0.88 -0.86 multiplexer are implemented to match different kinds of input
DNL/LSB
+0.87 +0.98 +0.68 +0.78 +0.80 range. A rail-to-rail class AB PGA is implemented to convert
-0.89 -1.08 -0.85 -0.86 -0.89 kinds of input range to the same range for the SAR ADC core.
INL/LSB
+0.92 +1.04 +0.82 +0.88 +0.84 A 5R7C hybrid SAR ADC without calibration is implemented
SNDR/dB 62.13 ( fin = 10 kHz, Vin = -0.72 dBFS) to achieve high resolution and low power. The measured
Power 2.04 mW results of the prototype chip fabricated in 0.18 um CMOS
process verify the operation of the proposed architecture.
Area 2.55 mm2

bottom plates of capacitors when designing a 12-bit resolution REFERENCES

SAR ADC.
The comparator consists of three stage pre-amplifiers and a
dynamic latch as shown Fig. 7 (a). Two pairs of offset
cancelling capacitors are inserted between three stage pre-
amplifiers. The pre-amplifiers aims to reduce the equivalent
offset of the comparator and isolate the latch from DAC to
eliminate the kickback noise effect. A simple diode-connected
PMOS in parallel with PMOS current source load amplifier
which has a moderate gain and bandwidth is employed as the
pre-amplifier as shown in Fig. 7 (b). A dynamic latch as shown
in Fig. 7 (c) is employed for sake of power dissipation. The
latch is reset when STROBE is low. As STROBE goes high,
latch begin to regenerate.
IV. EXPERIMENTAL RESULTS
The prototype front-end circuit was fabricated in 0.18 um
CMOS technology, and occupies an area of 1.844 x 1.387 mm2.
The chip photo is shown in Fig. 8. The experimental results of
the differential and integral nonlinearities (DNL and INL)
when the input range is in 2.5 V are illustrated in Fig. 9. The
SNDR is 62.13 dB in 2.5 V range. The input range could be as
large as 10 V. The performance of the chip is summarized in
Table I. The proposed circuit is compared with recently
reported front-end circuits with 12-bit SAR ADC in Table II.
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