ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: JUNE 2020

DEC50143 – CMOS IC DESIGN AND FABRICATION
Layout Design and Simulation of NMOS and PMOS
PRACTICAL WORK 1 :
Transistors
PRACTICAL WORK
25/08/2020
DATE :
LECTURER’S NAME: NOOR LAILA ASHA’ARI
TOTAL
STUDENT ID & NAME : MARKS
(100%)

HERYANSHAH BIN SUHIMI @SUHAIMI [07DTK18F1016]

DATE SUBMIT : 31/08/2020 DATE RETURN :

 PROCEDURES:

PART 1

a) Microwind window editor has been opened.

b) The Foundry file has been selected from File menu. “cmos06.rul” file has been selected and
opened, as shown in Figure 1.1. (Using the 0.6micron transistor technology)

Figure 1.1

c) The new file have been created and named “nmos.msk”.

d) The drawing is start.

The NMOS device has been draw by using those steps:

a. The palette has been used as show on Figure 1.2

b. From the palette window, the “polysilicon” has been clicked.

Figure 1.2
 c. a “polysilicon” box with width not less than 2λ has been draw, which is the minimum width of
the polysilicon as shown in Figure 1.3.

d. N+ Diffusion has been draw as shown in Figure 1.3. The channel of the NMOS device have
been created at the intersection between diffusion and polysilicon

Figure 1.3

e) The DRC have been run.

Output: No message have been appeared.

PART 2: CHANGE THE LAYOUT BACKGROUND COLOUR

Before: After:
PART 3: GENERATING TRANSISTOR CROSS SECTION

Output in 2D Transistor Cross Section:

Output in 3D Transistor Cross Section:

PART 4: SIMULATING NMOS TRANSISTOR CHARACTERISTICS

NMOS Characteristic ID VS VD:

PART 5: SIMULATING NMOS DYNAMIC BEHAVIOUR

a) The clock has been putted to the left diffusion as shown as figure below.
b) A clock has been applied to the gate and clicked to the polysilicon. The time low and time
high have been set up as below.

c) A visible icon has been added as shown on figure below.

d) This is NMOS layout that have been finished.

e) This is the timing diagram of NMOS

PART 6 : DESIGNING AND SIMULATING PMOS LAYOUT

Design:

- All the simulation will be show at result section.

RESULT:

1. NMOS
a. Transistor layout without DRC error

b. Transistor cross section

i) 2D Cross section

ii) 3D Cross section

c. Id/Vd Characteristics Curve

d. Input/Output timing diagram

2. PMOS
a. Transistor layout without DRC error

b. Transistor cross section

c. Id/Vd Characteristics Curve

d. Input/Output timing diagram

DISCUSSION:

1. Explain the terminology ‘technology feature’.

- Stands for "Complementary Metal Oxide Semiconductor." It is a technology used to produce

integrated circuits. The "MOS" in CMOS refers to the transistors in a CMOS component, called
MOSFETs

2. Describe the difference between micron and lambda unit in layout design process.

- Lambda-based rules Allow first order scaling by linearizing the resolution of the
complete wafer implementation, while Micron rules need a list of minimum feature
sizes and spacings for all masks, e.g., 3.25 microns for contact-poly-contact and 2.75
micron metal 1 contact-to-contact pitch.

3. Explain the functions of design rules.

- A design rule set specifies certain geometric and connectivity restrictions to ensure
sufficient margins to account for variability in semiconductor manufacturing processes,
so as to ensure that most of the parts work correctly.

4. PMOS transistor is usually larger than NMOS transistor in layout. Give an explanation.

- PMOS is larger than NMOS because NMOS has electrons as majority charge carriers and
PMOS has holes as majority charge carriers. ... Electrons has mobility ~2.7 times higher
the holes.

5. State TWO (2) differences between NMOS transistor layout and PMOS transistor layout.

- NMOS is built with n-type source and drain and a p-type substrate, while PMOS is built
with p-type source and drain and a n-type substrate.

- In a NMOS, carriers are electrons, while in a PMOS, carriers are holes. When a high
voltage is applied to the gate, NMOS will conduct, while PMOS will not.

6. NMOS and PMOS transistors are good at passing which logic level? Explain your answer.

- So an NMOS passes weak 1 and PMOS passes weak 0 whereas no such situations occur
when an NMOS passes 0 and a PMOS passes 1. So PMOS is good to pass logic 1 and
NMOS is good to pass logic 0.
CONCLUSION:

- We can design CMOS using Microwind and simulate it to check if any error before
perform the real action.
- We know what is the timing diagram and Id vs Vd of the MOS
- The cross-section of the designed PMOS and NMOS is different.
 PRACTICAL WORK ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 1

Student Name : HERYANSHAH BIN SUHIMI @SUHAIMI Class : DTK5A – S1

Student ID# : 07DTK18F1016 Date : 25/08/2020

SCORE DESCRIPTION

ASPECTS EXCELLENT MODERATE POOR SCALE SCORE

ITEM
4-5 2-3 1

Set to correct technology feature for Set to incorrect technology feature Did not set to any technology
A. Technology feature x1 /5
the transistor layout. for the transistor layout. feature.
Able to draw polysilicon width and Able to draw polysilicon width Not able to draw the polysilicon
B. Polysilicon width x1 /5
length correctly. correctly. width incorrectly.
Draw basic NMOS / Able to draw NMOS / PMOS Able to draw NMOS / PMOS Not able to draw NMOS / PMOS
C. PMOS transistor layout transistor layout correctly and transistor layout partly correct. transistor layout correctly. x1 /5
precisely.
Transistor cross-section The transistor cross-section is correct. The transistor cross section is The transistor cross section not
D. incorrect. produced at all. x1 /5

‘No DRC error’ display Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x1 /5
display for ALL layouts. display for some of the layouts. error’ display at ALL.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and NMOS
F. Transistor size transistor size. transistor size. transistor size. x2 / 10

Able to produce ALL layout Able to produce SOME simulations Not able to produce any
G. Layout simulation x2 / 10
simulations correctly and precisely. correctly. simulation result.
Layout size (end product) Produce small layout size (end Produce acceptable layout size (end Produce large layout size (end
H. product). product). product). x2 / 10

IC Layout Design – Produce good floorplan and input / Produce appropriate floorplan and Produce acceptable floorplan and
I. input/output/floorplan input / output layout design. x2 / 10
output layout design. input / output layout design.
Able to save the layout file correctly Able to save the layout file with
J. Save file as .msk Did not save the layout file. x1 /5
under designated folder. correct name and extension.
Total Practical Skill : / 70

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Supervisor Name & Signature