ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: DECEMBER 2019

DEC50143 - CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 5 : Layout Design and Simulation of Half Adder
PRACTICAL WORK
DATE :
LECTURER’S NAME: Noor Laila Binti Asha’ari
GROUP NO. :
TOTAL
STUDENT ID & NAME : MARKS
(100%)

(1) HERYANSHAH BIN SUHIMI @SUHAIMI (07DTK18F1016)

DATE SUBMIT : DATE RETURN :

Part A: Designing the layout of 1-bit half adder

1) 1-bit half adder has been designed by combining AND gate and XOR gate layout that
are inserted from practical work 3 and 4. All the appropriate setting such as input A
and B has been putted on input. Visible node “carry” and “sum” has been putted
respectively on AND gate output and XOR gate output.

Figure A.1 – Half Adder Layout Design

Part B: Simulating the layout of 1-bit half adder

1) For each input A and B has been added clock.

The clock setting for input A:

Time Low = 0.2 ns
Time High = 0.2 ns
Rise Time = Fall Time = 0.001 ns

The clock setting for input B:

Time Low = 0.4 ns
Time High = 0.4 ns
Rise Time = Fall Time = 0.001 ns

2) To make sure that the output voltage is visible on simulation, the visible output for
“Carry” and “Sum” has been added as shown on Figure A.1.

3) After all of the setting applied, the layout has been tested with simulation.

Figure B.1 – Simulation test

4) The layout area size has been measured.

Figure B.2 -The optimized area = 172 λ x 210 λ = 36,120 λ2

RESULT:

The layout of Half Adder (without any DRC error).

The timing diagram of Half Adder.
The optimized area of the IC layout.
Layout Area

(All these things are provided on procedure part)

DISCUSSION:

1. Explain the operation of a 1-bit half-adder circuit.

- A 1-bit half adder takes two inputs, a and b, and generates two outputs, the carry and
the sum.
- There are two inputs and two outputs in a Half Adder. Inputs are named as A and B,
and the outputs are named as Sum (S) and Carry (C). The Sum is X-OR of the input A
and B. Carry is AND of the input A and B. With the help of half adder, one can
design a circuit that is capable of performing simple addition with the help of logic
gates.
(4 marks)
2. Produce a truth table of a 1-bit half adder.

Inputs Outputs
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

(2 marks)
3. From the truth table, produce the equation for SUM and CARRY OUT.

Sum = AB + AB

Carry = A B .
(2 marks)
4. Figure 5.5 shows a block diagram of 1-bit half adder. Draw the logic circuit for 1-bit half
adder using XOR and AND gate.

Sum

Carry Out

Figure 5.5 – Block diagram of 1-bit half adder

CONCLUSION:

- The Half adder layout can be designed using XOR gate and AND gate layout.
- XOR gate functions as sum while AND gate functions as carry.So that, it can be
used as binary calculator that can perform addition on binary number.
 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 5
Student Name : HERYANSHAH BIN SUHIMI @SUHAIMI Class : DTK5A – S1
Date :
Student ID# : 07DTK18F1016

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

…………….…………………….
Supervisor Name & Signature
 SUSTAINABILITY AND ENVIRONMENT FRIENDLY SKILL RUBRIC - CLO3
ITEM ASPECTS EXCELLENT
4-5
Layout Performance Total using technology feature
& Low Power Design having green elements to achieve
technology feature both layout performance
A.
efficiency and low power
consumption is evident in the
final layout.
B. Final IC Layout Size Total usage of environment
friendly, green materials /
elements or reduce, recycled and
reused concept to produce small
IC layout size is clearly evident.
SCORE DESCRIPTION
MODERATE
2-3
Using technology feature
having green elements either to
achieve layout performance
efficiency or low power
consumption in the final
layout.
Using environment friendly,
green materials / elements or
reduce, recycled and reused
concept that help to produce
acceptable IC layout size is
partly evident.
POOR SCALE SCORE
1
Not using transistor technology
feature having green elements to
achieve layout performance
x 10 / 50
efficiency and low power
consumption in the final layout.
No usage of environment
friendly, green materials /
elements or reduce, recycled and
x 10 / 50
reused concept thus producing
large IC layout size.
Total Generic Skill: / 100
…………….…………………….
Supervisor Name & Signature