CMPE-222L – Digital Logic Design

Semester: 2nd (Spring 2023)

Lab Instructor: Engr. M. Hamza Zulfiqar Session: Fall, 2022

Date:

LAB-5 Implementation of XOR and XNOR Gates using Basic and

NAND Gates

Name Reg. No. Marks

2022 – BME –
30
5.1 Objectives

The objectives of this experiment are

 To analyze the performance of XOR and XNOR gates ICs and draw their truth tables
 To implement XOR and XNOR using basic gates only
 To implement XOR and XNOR using NAND gates only
5.2 Theory

In the previous labs, we saw that by using the three principal gates, the AND Gate, the OR Gate and
the NOT Gate, we can build many other types of logic gate functions, such as a NAND Gate and a NOR
Gate or any other type of digital logic functions.

But there are two other types of digital logic gates which although they are not a basic gate in their
own right as they are constructed by combining together other logic gates, their output Boolean
function is important enough to be considered as complete logic gates. These two “hybrid” logic gates
are called the Exclusive-OR (Ex-OR) Gate and its complement the Exclusive-NOR (Ex-NOR) Gate.

5.2.1 XOR Gate

A 2-input OR gate, if A = “1”, OR B = “1”, OR BOTH A + B = “1” then the output from the digital gate
must also be at a logic level “1” and because of this, this type of logic gate is known as an Inclusive-OR
function. The logic gate gets its name from the fact that it includes the case of Q = “1” when both A
and B = “1”.

If, however, a logic output “1” is obtained when ONLY A = “1” or when ONLY B = “1” but NOT both
together at the same time, giving the binary inputs of “01” or “10”, then the output will be “1”. This
type of gate is known as an Exclusive-OR function or more commonly an Ex-Or function for short. This
is because its Boolean expression excludes the “OR BOTH” case of Q = “1” when both A and B = “1”.

In other words, the output of an Exclusive-OR gate ONLY goes “HIGH” when its two input terminals
are at “DIFFERENT” logic levels with respect to each other.

An odd number of logic “1’s” on its inputs gives a logic “1” at the output. These two inputs can be at
logic level “1” or at logic level “0” giving us the Boolean expression of: Q = (A ⊕ B) = A.B + A.B

The Exclusive-OR Gate function, or Ex-OR for short, is achieved by combining standard logic gates
together to form more complex gate functions that are used extensively in building arithmetic logic
circuits, computational logic comparators and error detection circuits.

The two-input “Exclusive-OR” gate is basically a modulo two adder, since it gives the sum of two binary
numbers and as a result are more complex in design than other basic types of logic gate. The truth
table, logic symbol and implementation of a 2-input Exclusive-OR gate is shown in Figure 5.1.

Figure 5.1 2-input Ex-OR gate.

 Figure 5.2 Ex-OR gate equivalent circuit using basic gates

One of the main disadvantages of implementing the Ex-OR function above is that it contains three
different types logic gates OR, NAND and finally AND within its design. One easier way of producing
the Ex-OR function from a single gate is to use the NAND gate as shown in Figure 5.3 below.

Figure 3.3 Ex-OR Function implementation using NAND gates

5.2.2 Ex-NOR

Basically the “Exclusive-NOR” gate is a combination of the Exclusive-OR gate and the NOT gate and an
output “1” is only obtained from Ex-NOR if BOTH of its inputs are at the same logic level, either binary
“1” or “0”. For example, “00” or “11”. This input combination would then give us the Boolean
expression of: Q = (A ⊕ B) = A.B + A.B

Then the output of a digital logic Exclusive-NOR gate ONLY goes “HIGH” when its two input terminals,
A and B are at the “SAME” logic level which can be either at a logic level “1” or at a logic level “0”. In
other words, an even number of logic “1’s” on its inputs gives a logic “1” at the output, otherwise is at
logic level “0”.

Then this type of gate gives and output “1” when its inputs are “logically equal” or “equivalent” to
each other, which is why an Exclusive-NOR gate is sometimes called an Equivalence Gate.

The logic symbol for an Exclusive-NOR gate is simply an Exclusive-OR gate with a circle or “inversion
bubble”, ( ο ) at its output to represent the NOT function. Then the Logic Exclusive-NOR Gate is the
reverse or “Complementary” form of the Exclusive-OR gate, (A ⊕ B) we have seen previously.

The Exclusive-NOR Gate, also written as: “Ex-NOR” or “XNOR”, function is achieved by combining
standard gates together to form more complex gate functions and an example of a 2-input Exclusive-
NOR gate is shown in Figure 5.4.
 Figure 5.4 2-input Ex-NOR gate

The Ex-NOR function is a combination of different basic logic gates Ex-OR and a NOT gate, and by using
the 2-input truth table above, we can expand the Ex-NOR function to: Q = A ⊕ B = (A.B) + (A.B) which
means we can realize this new expression using the following individual gates.

Figure 5.5 2-input Ex-OR gate plus a NOT gate

The Exclusive-NOR Gate, also written as: “Ex-NOR” or “XNOR”, function is achieved by combining
standard/basic gates together to form more complex gate functions and an example of a 2-input
Exclusive-NOR gate is given in Figure 5.6.

Figure 5.6 Ex-NOR gate equivalence circuit

One of the main disadvantages of implementing the Ex-NOR function above is that it contains three
different types logic gates the AND, NOT and finally an OR gate within its basic design. One easier way
of producing the Ex-NOR function from a single gate type is to use NAND gates as shown in Figure 5.7.

Figure 5.7 Ex-NOR Function implementation using NAND gates

5.3 Equipment

 DC Power Source / Power Supply

 Prototype Development Board
 Connecting Wires

5.4 Components

 ICs (7400, 7404, 7408, 7432, 7486, 74266)

 330 Ω / 1 kΩ resistor ¼ watt Measured: ________________________
 LEDs

5.5 ICs Pin Diagrams

Figure 5.8 2-input Logic XOR Gate IC Pin Diagram

Figure 5.9 2-input Logic XNOR Gate IC Pin Diagram

5.6 Procedure

1. Place the development board gently on the observation table.

2. Fix the IC which is under observation between the half shadow line of breadboard, so there is no
shortage of voltage.
3. Connect the wire to the main voltage source (Vcc) whose other end is connected to last pin of the
IC (14 place from the notch).
4. Connect the ground of IC (7th place from the notch) to the ground terminal of supply/kit.
5. Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using connecting
wires. (In accordance to IC provided).
6. Connect the interconnected inputs and outputs of different ICs.
7. Connect output pins to the led on the breadboard through current limiting resistor.
8. Switch on the power supply.
9. If led glows then output is true, if it didn’t glows then output is false, which is numerically denoted
as 1 and 0 respectively.

5.7 Precautions

1. All connections should be made neat and tight.

2. Digital lab supplies, components and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Never touch live and naked wires.

5.8 Obersvations

Table 5.1 Observation table of XOR IC

Input 1 Input 2 Output

Pin Number Logic / State Pin Number Logic / State Pin Number Logic / State

Table 5.2 Observation table of XOR IC

Input 1 Input 2 Output

Pin Number Logic / State Pin Number Logic / State Pin Number Logic / State
 Table 5.3 Observation of XOR implementation using Basic Gates

Input 1 Input 2 A+B A.B (A.B)’ (A+B).(A.B)’

Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State

Table 5.4 Observation of XOR implementation using NAND Gates

Input 1 Input 2 C D E (A’.B)+(A.B’)

Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State
 Table 5.5 Observation of XNOR implementation using Basic Gates

Input 1 Input 2 A’ B’ A.B A’.B’ (A.B)+(A’.B’)

Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State

Table 5.6 Observation of XNOR implementation using NAND Gates

Input 1 Input 2 A’ B’ (A’.B’)’ (A.B)’ (A.B)+(A’.B’)

Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State Logic / State

5.9 Results

Table 5.7 Truth table of XOR

Input 1 Input 2 Output

 Table 5.8 Truth table of XNOR

Input 1 Input 2 Output

5.10 Analysis

1. Draw the gate level implementation diagram of for XOR logic using lowest number of gates.

2. Implement the XOR logic using universal gates other than NAND and verify it through truth table
or wave diagram.

3. When any of the input of XOR gate is high, what would be the output?
4. When any of the input of XNOR gate is low, what would be the output?

5.11 Conclusion

5.12 Home Assignment

Replicate the experiment through Verilog and submit the screenshots of software implementation in
the form of brief technical report (5.13 Lab Report). Report must include the implementation of
XOR and XNOR gates using lowest number of gates, basic gates only and universal gates only.

Also include the pictures of hardware implementation.

 Assessment Rubrics
CMPE-222L – Digital Logic Design – Lab 05
Name: _______________________ Reg. No.: ____2022-CS-____________
Method: Lab reports, viva, and instructor observation during lab sessions.
Outcome Assessed:
1. Ability to conduct experiments and projects, analyze and interpret the acquired data, and synthesize information to
derive valid conclusions for digital logic circuits. (P2) (PLO – 04)
2. Ability to students will be able to demonstrate the implementation of digital logic circuits using Verilog simulations
through modern tools. (P2) (PLO – 05).
3. Ability to contribute effectively and ethically as a team member towards the completion of labs and semester project.
(A2) (PLO – 09).
4. Ability to report and explain their project, experimental results, and findings effectively in written as well as in oral
communication. (C2) (PLO – 10).

Performance Meets expectation (4-5)
Focused attention on the experiment.
Does proper calibration of equipment,
1. Conducting
carefully examines equipment and
Experiment
build circuits through relevant
[1]
components, and ensures smooth
operation and process.
Accurately conducts simple
computations and statistical analysis
using collected data; correlates
2. Data experimental results to known
Collection and theoretical values; accounts for
Analysis [1] measurement errors and parameters
that affect experimental results.
Able to interpret the lab all-important
results and data comparisons
3. Realization
correctly; good understanding of labs
[1]
is conveyed.
Use computer to replicate the
4. Modern
circuits through Verilog simulations
Tool Usage
and collect data effectively.
[2]
Actively engages in lab and
cooperates with other group members.
5. Teamwork
Also complete the labs and
[3]
submissions in an effective manner
and adhering to ethical values.
The report illustrates an accurate and
thorough understanding of scientific
concepts underlying the lab and
includes the experimental results and
6. Lab Report
findings flawlessly or with some
[4]
mistakes. All figures, graphs, tables
are correctly drawn, are numbered
and contain titles/captions or with few
formatting mistakes.
Lacking in expectation (3-2)
Focus was lost on several
occasions. Calibrates equipment,
examines equipment and build
circuits through relevant
components, and operates the
equipment with minor error.
Conducts simple computations
and statistical analysis using
collected data with minor error;
reasonably correlates
experimental results to known
theoretical values; attempts to
account for measurement errors
and parameters that affect
experimental results.
Able to interpret the lab some of
results and data comparisons
correctly; fair understanding of
labs is conveyed.
Uses computer to replicate the
DLD circuits through Verilog
simulations and collect data
with minor errors.
Cooperates with other group
members in a reasonable manner
for the conduct of the lab and
complete the labs in an effective
manner as well as ethically.
The report illustrates a limited
understanding of scientific
concepts underlying the lab and
includes the experimental
results and findings with major
deficiencies. Most figures,
graphs, tables OK, some still
missing some important or
required features.
Does not meet expectation (1-0) Marks
Students were hostile about
participating or unable to do so. Or
unable to calibrate appropriate
equipment and build circuits through
relevant components, and equipment
operation is substantially wrong.
Unable to conduct simple statistical
analysis on collected data; no
attempt to correlate experimental
results with known theoretical
values; incapable of explaining
measurement errors or parameters
that affect the experimental results.
Unable to interpret the lab results
and comparison of data, a lack of
understanding of results. Or
incorrect interpretation of data is
conveyed.
Does not know how to use
computer for the replication of
DLD circuits through Verilog
simulations and collect data.
Distracts or discourages other group
members from conducting the
experiment and effective and ethical
submission.
The report illustrates inaccurate
understanding of scientific concepts
underlying the lab or did not submit
the lab report on time or/and having
major deficiencies. Figures, graphs,
tables contain errors or are poorly
constructed, have missing titles,
captions or numbers, units missing
or incorrect, etc.

Total

Lab Instructor:
Name: __Engr. M. Hamza Zulfiqar_ Signature: _______________________

Date: __________________________