EXPERIMENT NO: 1

Objec ve: To study and analyse Basic gates using VIVADO tool.

Theory:

Basic Logic Gates

A logic gate is a basic building block of a digital circuit that has two inputs and one output. The rela onship
between the i/p and the o/p is based on a certain logic. These gates are implemented using electronic switches
like transistors, diodes. But, in prac ce, basic logic gates are built using CMOS technology, FETS,
and MOSFET(Metal Oxide Semiconductor FET)s. Logic gates are used in microprocessors, microcontrollers,
embedded system applica ons, and in electronic and electrical project circuits. The basic logic gates are
categorized into seven: AND, OR, XOR, NAND, NOR, XNOR, and NOT.

Basic Logic Gates Opera on

The basic logic gates are classified into seven types: AND gate, OR gate, XOR gate, NAND gate, NOR gate, XNOR
gate, and NOT gate. The truth table is used to show the logic gate func on. All the logic gates have two inputs
except the NOT gate, which has only one input.

Types of Logic Gates

1. AND Gate: The AND gate is a digital logic gate with ‘n’ i/p one o/p, which performs logical conjunc on
based on the combina ons of its inputs. The output of this gate is 1 only when all the inputs are 1. When one
or more inputs of the AND gate’s i/p are 0, then only the output of the AND gate is 0. The symbol and truth
table of an AND gate with two inputs is shown below.

2. OR Gate: The OR gate is a digital logic gate with ‘n’ i/p and one o/p, that performs logical conjunc on
based on the combina ons of its inputs. The output of the OR gate is 1 only when one or more inputs are 1. If
all the i/p of the gate are 0, then only the output of the OR gate is 0. The symbol and truth table of an OR gate
with two inputs is shown below.
3. NOT Gate: The NOT gate is a digital logic gate with one input and one output that operates an inverter
opera on of the input. The output of the NOT gate is the reverse of the input. When the input of the NOT gate
is 1 then the output will be 0 and vice versa. The symbol and truth table of a NOT gate with one input is shown
below. By using this gate, we can implement NOR and NAND gates

4. NAND Gate: The NAND gate is a digital logic gate with ‘n’ i/p and one o/p, that performs the opera on of
the AND gate followed by the opera on of the NOT gate.NAND gate is designed by combining the AND and
NOT gates. If the input of the NAND gate high, then the output of the gate will be low.The symbol and truth
table of the NAND gate with two inputs is shown below.

5. NOR Gate : The NOR gate is a digital logic gate with n inputs and one output, that performs the opera on
of the OR gate followed by the NOT gate. NOR gate is designed by combining the OR and NOT gate. When any
one of the i/p of the NOR gate is 1, then the output of the NOR gate will be 0. The symbol and truth table of
the NOR gate with the truth table is shown below.

6. Exclusive-OR Gate: The Exclusive-OR gate is a digital logic gate with two inputs and one output. The short
form of this gate is Ex-OR. It performs based on the opera on of the OR gate. . If any one of the inputs of this
gate is high, then the output of the EX-OR gate will be high. The symbol and truth table of the EX-OR are shown
below.
7. Exclusive-NOR Gate: The Exclusive-NOR gate is a digital logic gate with two inputs and one output. The
short form of this gate is Ex-NOR. It performs based on the opera on of the NOR gate. When both the inputs of
this gate are high, then the output of the EX-NOR gate will be high. But, if any one of the inputs is high (but not
both), then the output will be low. The symbol and truth table of the EX-NOR are shown below.

Now let us have a look at data flow codes , behavioural codes , schema c diagram and testbench
plots of all the basic gates men oned above:

1.AND GATE:

DATA FLOW CODE:

module AND_2_data_flow (output Y,

input A, B);

assign Y = A & B;

endmodule

BEHAVIOURAL CODE:
module AND_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b1 & B == 1'b1) begin

Y = 1'b1;

end

else

Y = 1'b0;

end

endmodule

SCHEMATIC DIAGRAM:
TESTBENCH OUTPUT:

2. OR GATE:

DATAFLOW CODE:
module or_df(

input a,

input b,

output c

);

assign c=(a|b);

endmodule

BEHAVIOURAL CODE:
module OR_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b0 & B == 1'b0) begin

Y = 1'b0;

end

else

Y = 1'b1;

end

endmodule

SCHEMATIC DIAGRAM:
TESTBENCH OUTPUT:

3.NAND GATE:

DATAFLOW CODE:
module nand_df(

input a,

input b,

output c

);

assign c=~(a&b);

endmodule

BEHAVIOURAL CODE:
module NAND_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b1 & B == 1'b1) begin

Y = 1'b0;

end

else

Y = 1'b1;

end

endmodule

SCHEMATIC DIAGRAM:
TESTBENCH PLOT:

4.NOR GATE:

DATAFLOW CODE:
module nor_df(

input a,

input b,

output c

);

assign c=~(a|b);

endmodule

BEHAVIOURAL CODE:
module NOR_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b0 & B == 1'b0) begin

Y = 1'b1;

end

else

Y = 1'b0;

end

endmodule

SCHEMATIC DIAGRAM:
TESTBENCH OUTPUT:

5.XOR GATE:

DATAFLOW CODE:
module exor_df(

input a,

input b,

output c

);

assign c=(a^b);

endmodule

BEHAVIOURAL CODE:
module XOR_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b0 & B == 1'b0) begin

Y = 1'b0;

end

if (A == 1'b1 & B == 1'b1) begin

Y = 1'b0;

end

else

Y = 1'b1;

end

endmodule
SCHEMATIC DIAGRAM:

TESTBENCH OUTPUT:

6.XNOR GATE:

DATAFLOW CODE:
module exnor_df(

input a,

input b,

output c

);

assign c=~(a^b);

endmodule

BEHAVIOURAL CODE:
module XNOR_2_behavioral (output reg Y, input A, B);

always @ (A or B) begin

if (A == 1'b0 & B == 1'b0) begin

Y = 1'b1;

end

else

if (A == 1'b1 & B == 1'b1) begin

Y = 1'b1;

end

else

Y = 1'b0;

End

Endmodule
SCHEMATIC DIAGRAM:

TESTBENCH OUTPUT: