ADC r/m8, reg8 $10

ADC r/m16, reg16 $11

ADC reg8, r/m8 $12
ADC reg16, r/m16 $13
ADC AL, imm8 $14
ADC AX, imm16 $15
ADC r/m8, imm8 $80 010
ADC r/m16, imm16 $81 010
ADC r/m16, imm8 $83 010
ADD r/m8, reg8 $00
ADD r/m16, reg16 $01
ADD reg8, r/m8 $02
ADD reg16, r/m16 $03
ADD AL, imm8 $04
ADD AX, imm16 $05
ADD r/m8, imm8 $80 000
ADD r/m16, imm16 $81 000
ADD r/m16, imm8 $83 000
AND r/m8, reg8 $20
AND r/m16, reg16 $21
AND reg8, r/m8 $22
AND reg16, r/m16 $23
AND AL, imm8 $24
AND AX, imm16 $25
AND r/m8, imm8 $80 100
AND r/m16, imm16 $81 100
AND r/m16, imm8 $83 100
CALL 32-bit displacement $9A
CALL 16-bit displacement $E8
CLD $FC
CMP r/m8, reg8 $38
CMP r/m16, reg16 $39
CMP reg8, r/m8 $3A
CMP reg16, r/m16 $3B
CMP AL, imm8 $3C
CMP AX, imm16 $3D
CMP r/m8, imm8 $80 111
CMP r/m16, imm16 $81 111
CMP r/m16, imm8 $83 111
CMPSB ES:[DI]==DS:[SI] $A6
CMPW ES:[DI]==DS:[SI] $A7
DEC r/m8 $FE 001
DEC r/m16 $FF 001
DEC reg16 $48
DEC reg16 $49
DEC reg16 $4A
DEC reg16 $4B
DEC reg16 $4C
DEC reg16 $4D
DEC reg16 $4E
DEC reg16 $4F
DIV r/m8 $F6 110
DIV r/m16 $F7 110
HLT $F4
IDIV r/m8 $F6 111
IDIV r/m16 $F7 111
IMUL r/m8 $F6 101
IMUL r/m16 $F7 101
IN AL, addr8 $E4
IN AX, addr8 $E5
IN AL, port[DX] $EC
IN AX, port[DX] $ED
INC r/m8 $FE 000
INC r/m16 $FF 000
INC reg16 $40
INC reg16 $41
INC reg16 $42
INC reg16 $43
INC reg16 $44
INC reg16 $45
INC reg16 $46
INC reg16 $47
IRET 48-bit POP $CF
JA 8-bit relative $77
JAE 8-bit relative $73
JB 8-bitrelative $72
JBE 8-bit relative $76
JE 8-bit relative $74
JG 8-bit relative $7F
JGE 8-bit relative $7D
JL 8-bit relative $7C
JLE 8-bit relative $7E
JMP 32-bit displacement $EA
JNE 8-bit relative $75
JZ 8-bit relative $74
LDS reg16, mem32 $C4
LES reg16, mem32 $C5
LODSB AL = DS:[SI] $AC
LODSW AX = DS:[SI] $AD
LOOP 8-bit relative $E2
MOV r/m8, reg8 $88
MOV r/m16, reg16 $89
MOV AL, mem8 $A0
MOV AX, mem16 $A1
MOV mem8, AL $A2
MOV mem16, AX $A3
MOV reg8, imm8 $B0
MOV reg8, imm8 $B1
MOV reg8, imm8 $B2
MOV reg8, imm8 $B3
MOV reg8, imm8 $B4
MOV reg8, imm8 $B5
MOV reg8, imm8 $B6
MOV reg8, imm8 $B7
MOV reg16,imm16 $B8
MOV reg16,imm16 $B9
MOV reg16,imm16 $BA
MOV reg16,imm16 $BB
MOV reg16,imm16 $BC
MOV reg16,imm16 $BD
MOV reg16,imm16 $BE
MOV reg16,imm16 $BF
MOV r/m8, imm8 $C6 000
MOV r/m16, imm16 $C7 000
MOV r/m16,sreg $8C 000
MOV r/m16,sreg $8C 001
MOV r/m16,sreg $8C 010
MOV r/m16,sreg $8C 011
MOV sreg, r/m16 $8E 000
MOV sreg, r/m16 $8E 001
MOV sreg, r/m16 $8E 010
MOV sreg, r/m16 $8E 011
MOVSB ES:[DI] = DS:[SI] $A4
MOVSW ES:[DI] = DS:[SI] $A5
MUL r/m8 $F6 100
MUL r/m16 $F7 100
NEG r/m8 $F6 011
NEG r/m16 $F7 011
NOT r/m8 $F6 010
NOT r/m16 $F7 010
OR r/m8, reg8 $08
OR r/m16, reg16 $09
OR reg8, r/m8 $0A
OR reg16, r/m16 $0B
OR AL, imm8 $0C
OR AX, imm16 $0D
OR r/m8, imm8 $80 001
OR r/m16, imm16 $81 001
OR r/m16, imm8 $83 001
OUT addr8, AL $E6
OUT addr8, AX $E7
OUT port[DX], AL $EE
OUT port[DX], AX $EF
POP r/m16 $8F 000
POP reg16 $58
POP reg16 $59
POP reg16 $5A
POP reg16 $5B
POP reg16 $5C
POP reg16 $5D
POP reg16 $5E
POP reg16 $5F
POP sreg $07
POP sreg $0F
POP sreg $17
POP sreg $1F
PUSH r/m16 $FF 110
PUSH reg16 $50
PUSH reg16 $51
PUSH reg16 $52
PUSH reg16 $53
PUSH reg16 $54
PUSH reg16 $55
PUSH reg16 $56
PUSH reg16 $57
PUSH sreg $06
PUSH sreg $0E
PUSH sreg $16
PUSH sreg $1E
REP $F3
REPNE $F2
RET 32-bit POP $CA
RET 16-bit POP $C2
SBB r/m8, reg8 $18
SBB r/m16, reg16 $19
SBB reg8, r/m8 $1A
SBB reg16, r/m16 $1B
SBB AL, imm8 $1C
SBB AX, imm16 $1D
SBB r/m8, imm8 $80 011
SBB r/m16, imm16 $81 011
SBB r/m16, imm8 $83 011
SCASB ES:[DI] == AL $AE
SCASW ES:[DI] == AX $AF
STD $FD
STOSB ES:[DI] = AL $AA
STOSW ES:[DI] = AX $AB
SUB r/m8, reg8 $28
SUB r/m16, reg16 $29
SUB reg8, r/m8 $2A
SUB reg16, r/m16 $2B
SUB AL, imm8 $2C
SUB AX, imm16 $2D
SUB r/m8, imm8 $80 101
SUB r/m16, imm16 $81 101
SUB r/m16, imm8 $83 101
XOR r/m8, reg8 $30
XOR r/m16, reg16 $31
XOR reg8, r/m8 $32
XOR reg16, r/m16 $33
XOR AL, imm8 $34
XOR AX, imm16 $35
XOR r/m8, imm8 $80 110
XOR r/m16, imm16 $81 110
XOR r/m16, imm8 $83 110