MTRL 579

Physics of Microfabrication:
Front End Processing

Instructor: Guangrui (Maggie) Xia

FF 213, Tel. 822-0478
email: gxia@mail.ubc.ca
Who am I and my journeys in this field ...

◼ Tsinghua University: B. S. in Materials Sci. & Eng.

◼ M. I. T. : M. S. and Ph. D. from Electrical and Computer and Eng.
◼ IBM : Researcher at SRDC for two years
◼ UBC Materials Engineering, associate professor since 2017
2
What do you know about semiconductors
◼ Please list as many as you can:
◼ Semiconductor materials: Si, Ge, GaAs, GaAlAs, AlAs, CdS, SiC,
ZnO2, wide bandgap semiconductors are insulators, but can be used
as semiconductors when doped.
◼ Semiconductor devices: solar cells, MOSFETs, bipolar transistors,
LED, MEMS, photodiodes, tunneling diodes, laser diodes,
modulators, waveguides
◼ Applications of semiconductor devices: ICs (digital, analog),
optoelectronic applications, energy, imaging, lighting, information
processing, computing, communications
◼ Semiconductor hardware companies: TSMC (1st foundry), Intel, IBM,
AMD (GlobalFoundry), STMicroelectronics, Texas Instruments,
Samsung, Hitachi, Sony, UMC (2nd foundry), SMIC (mainland
China).

3
579 and you

Doors opened for you

 Industry: IC fabrication, fabless

design houses, communications,
equipment/material manufacturer,
start-ups, solar cell, …

 Research: electronic/optoelectronic
materials and devices, solar cells,
MEMS, circuit design, nanotubes,
nanowires etc.

4
Local industry

◼ Communications: Microchip, Burnaby

(previously PMC-Sierra) – fabless design
◼ Design: Intel Canada
◼ Device modeling: Crosslight Software Inc.,
Lumerical Inc.

5
Si ICs (chips): an Intel processor

Processed Si wafers by IBM Intel Pentium processor die

6
 Si chips: an Intel six-core processor
Integrated circuits (IC) =chip One die

Physical Layout Breakdown

Coffee Lake Si wafer with 8th

generation core 6-core processor
dies. Coffee Lake (CFL) is a
microarchitecture designed
introduced in 2017 by Intel for
desktops and high-performance
mobile devices.

Source: https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake 7
Interconnects and MOSFETs

~109 MOSFETs
Metal-oxide-semiconductor-field-effect-transistor
8
Important device -- MOSFET

Poly Si
or metal

spacer spacer
Metal Metal
contact contact
Oxide/dielectric materials
30nm

Si

9
Cross Section Transmission Electron Micrograph
of a Si MOSFET

Gate oxide
Gate length

From: P. Packan, “Scaling Transistors into the Deep-Submicron

Regime”, MRS Bulletin, June 2000, p. 18.
◼ Switching speed of individual devices improves as:
 distance between Source and Drain (gate length) is decreased
 gate oxide thickness is reduced
◼ How are modern MOSFETs fabricated??
10
Technology leadership: TSMC and Intel

11
MOS structure: planar MOSFET vs. FinFET

https://semiengineering.com/racing-to-
107nm/

12
We Will Learn About
Distance (nm)
-100 0 100

σxx (dynes/cm2)

100
Distance (nm)
0
Si
350 – 450 MPa

-100
T. Ghani, et al.,
IEDM 2003 (Intel)
SUPREM IV Simulation
MOS Fabrication
Stress simulation

Diffusion

13
Syllabus

• Digital circuit basics

• Thermal oxidation and the Si/SiO2 interface
• Dopant diffusion
• Ion implantation and annealing:
• SUPREM IV process simulator (used in Homework Problems)
• Thin film deposition and epitaxy
• Etching
• Silicides, contacts and novel gate materials
• Global and local stress to enhance CMOS performance

14
Grading and projects

Grading:
40% homework
25% midterm exam
35% final term project

The final grade will also take into account non-numerical assessments of
your command of the material. In addition, attendance and in-class
participation will be factored into the final letter grade when it falls near
a grade boundary.

Term Project involving two parts:

(1) Report consisting of (a) a written report with max. length = 20
pages, and (b) a 20 minute in-class oral presentation with handouts.

15
Text and references

◼ Text (required – on reserve shelf):

 Silicon VLSI Technology: Fundamentals, Practice and Modeling, by
Plummer, Deal and Griffin, Prentice Hall, July 2000.

◼ Useful reading material (Books at library)

 S. Wolf and R. Tauber, Silicon Processing for the VLSI Era, Vol. 4,
Lattice Press, 2002.
 S.M. Sze, VLSI Technology, McGraw-Hill, Second Edition, 1988.
 S.A. Campbell, The Science and Engineering of Microelectronic
Fabrication, Oxford University Press, 2nd edition, 2001.

◼ Journals/Conference Proceedings:
 IEEE Transactions on Electron Devices (published monthly)
 Applied Physics Letters
 Journal of Applied Physics
 IEEE IEDM Conference Proceedings, published each December

16
Goals and Outcomes

◼ Principles of the “front-end” processes in Si ICs fabrication.

◼ Physical models and practical aspects of major processes
 thermal oxidation, solid-state diffusion, ion implantation, epitaxial
growth, etching, and silicides.
◼ Understanding of models implemented in modern process
simulators, e.g. SUPREM IV
◼ Experience using the SUPREM IV process simulator and ability
to perform comparisons to analytic model results
◼ Introduction to the impact of processing on device performance
◼ Experience reading the front-end processing literature
◼ Ability to perform process simulations related to published results

Note: the state-of-the-art changes every few years.

Keeping up with the latest developments is a continuous process.

17
Semiconductor industry
overview
 60 years of semiconductor industry

◼ First working transistor created on

December 16, 1947 at Bell
Laboratories in NJ
◼ Inventors – William Shockley, John
Bardeen, and Walter Brattain –
received Nobel Prize in Physics in
1956

• Transistor – key building block of countless electronics products that have

revolutionized virtually every aspect of human life

• 2007 the worldwide microelectronics industry produced 900 million

transistors for every person on earth – a total of 6,000,000,000,000,000,000
(6 quintillion=6e18) transistors
19
Integrated circuit evolution:
Early 1990s

1960s

Progress due to:

• feature size reduction: 0.7X every 3 years (Moore’s Law)
• increasing chip size ~ 16% increase in area per year
• innovations in implementing functions and in process technology
20
 Moore’s Law

• Exponential growth: number of transistors on a chip doubles in a certain period

(e.g. every 18 months, in 1980’s)
Source: Gordon E. Moore, Keynote Address, IEEE ISSCC 2003, from
ftp://download.intel.com/research/silicon/Gordon_Moore_ISSCC_021003.pdf 21
22
Billion dollar fab

23
24
25
 6.8%

72%

26
27
28
Technology nodes
Technology node is commonly represented by the critical dimension of a MOSFET
Gate
100000length of a MOSFET is the critical dimension. 10
Fab Cost ($M)

Linewidth (nm)
10000

Linewidth (um)
Fab Cost ($M)

1000

100
0.1

10

100mm 150mm 200mm 300mm 450mm

1 0.01
1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

29
A typical R&D cleanroom

http://www.ihp-microelectronics.com/126.0.html 30
Vidoe: inside an Intel cleanroom facility

Unit process,
Integration,
Device
Material scientists
TCAD engineers
Circuit designers

TCAD=technology CAD

Process, device, circuit

design.

System design,
verification etc.
Intel Micron Flash Technologies, dry etch area Multiple levels of
FOUP= Front Opening Unified Pod simulations.
Source: http://www.legitreviews.com/article/1179/2/

31
Industry cleanroom fabrication facility

Intel Micron Flash Technologies: photolithography area

Source: http://www.legitreviews.com/article/1179/2/

32
Semicondutor basics
Semiconductors
Source: http://media.web.britannica.com/eb-media/07/207-004-2B66F205.gif

34
Why semiconductor materials?

◼ Conductivity varies by orders of magnitudes

◼ Conductivity can be engineered and controlled
by processing and electrical fields
 Conductive mode, and non-conductive mode gives H or
L, 0 or 1 (digital circuits)
 Non-linear IV characteristics (analog circuits)

◼ Electroluminescence and photoelectric effect

 LED, lasers, solar cell, photodetectors

35
Major semiconductor materials in periodic
table

Dominant materials: Si

Si based devices occupy 93%

of semiconductor market in
2004

36
Major semiconductors

Element IV-IV III-V II-VI IV-VI

compounds Compounds compounds compounds
Si SiC BN CdS, CdSe, PbS, PbTe
CdTe

Ge AlAs, AlSb ZnS, ZnSe,

ZnTe
GaP, GaAs,
GaSb

InP, InAs,
InSb
AlGaAs,
GaAsP

Dominant materials: Si
Si based devices occupy 93% of semiconductor market in 2004
GaAs, AlAs – important for optical devices
37
Uniqueness and advantages of Si

◼ Good quality stable oxide

 SiO2easy to etch, perfect interface
 GaAs, Ge

◼ abundance
 2ndrichest element on earth -- 25.7% earth crust by
weight
 High quality single crystal

38
Si: covalent bonds

Shared electrons between atoms

Tetrahedral configuration

39
Si diamond lattice structure

a=5.43 angstrom
40
CMOS operation and digital
circuits
Video: how transistors work

How Transistors Work - The MOSFET

http://www.youtube.com/watch?v=QO5FgM7MLGg
&feature=related
MOSFETs

SiGe SiGe
~30
nm

Source: Intel Technology Journal v.12, 2008 “45nm High-k+Metal Gate Strain-Enhanced
Transistors” by C. Auth et al.

• MOSFETs are made from: Si, poly-Si, SiO2, Si3N4, SiGe, and metals.
• Stress enhances device performance.
• Stress is introduced by SiGe pockets.
43
Mainstream MOSFETs structure and
materials
1)

3)
2)
Poly-Si

4) Body terminal

p-channel MOSFET
• Body – Si
• Gate - Polycrystalline Si (traditional), TiN
(state-of-the-art)
• Source & Drain – highly doped SiGe or Si

• Gate oxide – SiO2

• Interconnects - Cu, Ti
Important device – 3D MOSFET
Source: http://www.isi.edu/~vernier/EE327/ee327_2005.html

Poly Si Si3N4 or SiO2

or metal nitride

Metal Metal
contact contact
Oxide/dielectric materials
30nm

Si

45
Important materials/elements in a
MOSFET
◼ Substrate: Si
◼ Metals for contact and interconnects: Cu,
Ti etc.
◼ Insulators: SiO2, Si3N4,
◼ Doping elements: B, In, As, P, Sb
 Source and drains are heavily doped to work
like to conductors

46
p-n junction (diode)

p-n junctions are also called p-n diodes. Currents

are allowed only when the currect direction is from
the p-side to the n-side.

47
48

MOSFET Operation: nMOS

Low V High V

Electron channel

Off state On state

• Threshold voltage for nMOS: VTn
• No conduction when VGS<VTn
• VGS>VTn, strong enough field to attract electrons to the top and
form electron channel for current flow.
• High enough voltage turns nMOS on
49

MOSFET Operation: pMOS

High V Low V

p p p hole channel p
n
n

Off state On state

• Threshold voltage for pMOS: VTp
• No conduction when VGS>VTp
• VGS<VTp, strong enough field attract holes to the top and
form a hole channel for current flow.
• Low enough voltage turns pMOS on.
Contd

◼ Gate: polycrystalline Si (poly-Si) or metal

nitride
 Voltages applied on gate VG control the
conducting properties of a MOSFET, and thus
the current IDS
◼ Source/Drain (S/D): highly doped Si or SiGe
 Normally VS=0
 Apply VD to have current IDS flow. I DS 
◼ Strong enough vertical electrical field can
form inversion channel between S and D.

50
nMOS Operation

◼ When the gate is at a high voltage:

 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

51
pMOS Transistor

◼ Similar, but doping and voltages reversed

 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

52
Transistors as Switches

◼ We can view MOS transistors as electrically

controlled switches
◼ Voltage at gate controls path from source to
drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

53
CMOS Inverter

A Y VDD
0
1
A Y
CL

A Y
GND

54
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
55
CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
56
CMOS NAND Gate

A B Y
0 0
0 1 Y
1 0 A
1 1
B

Y = A• B = A + B
57
CMOS NAND Gate

A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1 B=0
OFF

58
CMOS NAND Gate

A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1 B=1
ON

59
CMOS NAND Gate

A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1 B=0
OFF

60
CMOS NAND Gate

A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0 B=1
ON

61
Assignment this week – due next Friday
lecture time
1. Find a video or a paper or an article to share on MOSFETs such as
new structures, technologies, applications, fabrication schemes.

Resources:
IEDM – a conference with most recent research results, useful to find
magazine articles about IEDM.
TechInsights.com (previously chipworks) – a reverse engineering company,
which publishes tear-down reports of most recent IC and MOSFETs etc.

2. Give me the link and a summary of what you learn and what you don’t
understand and want to find out. 1-2 page long. Tables and bullets are
easier to read. Please do some research first on what you don’t
understand and then we can discuss in class.

Please send your assignment by email.

If you have a good video, please feel free to send me a short link so I can
see if this can be shared with all next Friday.

62
Summary and Reading

◼ Summary:
 Introduction of semiconductor industry
 Importance of MOSFET
 MOSFET structure and operation basics
 Qualitative description of a complete CMOS process.

◼ Reading:
 Plummer chapter 1

63