Microprocessors and

Microcontrollers

Sunil Mathur
Jeebananda Panda
MICROPROCESSORS AND MICROCONTROLLERS
MICROPROCESSORS AND
MICROCONTROLLERS

SUNIL MATHUR
Associate Professor
Department of Electronics and Communication Engineering
Maharaja Agrasen Institute of Technology
Guru Gobind Singh Indraprastha University, Delhi

JEEBANANDA PANDA
Associate Professor
Department of Electronics and Communication Engineering
Delhi Technological University, Delhi

Delhi-110092
2016
MICROPROCESSORS AND MICROCONTROLLERS
Sunil Mathur and Jeebananda Panda

© 2016 by PHI Learning Private Limited, Delhi. All rights reserved. No part of this book may be
reproduced in any form, by mimeograph or any other means, without permission in writing from
the publisher.

ISBN-978-81-203-5231-5

The export rights of this book are vested solely with the publisher.

Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj
Industrial Estate, Delhi-110092 and Printed by Mohan Makhijani at Rekha Printers Private Limited,
New Delhi-110020.
 To
Knowledge Seekers
 Contents

Preface xxi
Acknowledgements xxiii

PART 1
  1.  Architecture and Organization of Microprocessor 8085 3
1.1 Introduction  3
1.2 Evolution of Microprocessor   3
1.3 Microcomputer System   6
1.3.1 Arithmetic and Logic Unit   7
1.3.2 Register Unit   7
1.3.3 Control Unit   7
1.3.4 Memory   7
1.3.4 System Bus   7
1.4 Microprocessor Operations   8
1.4.1 Microprocessor Initiated Operations   8
1.4.2 Internal Data Operations   9
1.4.3 Peripheral or Externally Initiated Operations   10
1.5 Functional Description of 8085   11
1.6 Internal Architecture of 8085   12
1.6.1 Register Unit   12
1.6.2 Control Unit   15
1.6.3 Arithmetic and Logical Unit   15
1.7  System Bus of 8085   17
1.8  Pin Description of 8085   18
1.8.1 Group 1: Power Supply and Frequency Signals   19
1.8.2 Group 2: A8–A15, Higher Order Address Bus (Output)   19
1.8.3 Group 3: AD0–AD7, Multiplexed Address/Data Bus   19
1.8.4 Group 4: Control and Status Signal   19
vii
viii    Contents

1.8.5 Group 5: Serial IO Signal   20

1.8.6 Group 6: Externally or Peripheral Initiated Signals   21
1.9 Demultiplexing of AD0–AD7  23
1.10 Generation of Control Signals   24
1.11 How a Program is Executed   26
Exercises  27

  2. Instruction Set of 8085 Microprocessor 31

2.1 Introduction  31
2.2 Instruction Format   32
2.2.1 Instruction Word Size   32
2.2.2 Opcode Format   33
2.3 Addressing Modes of MP 8085   34
2.3.1 Immediate Addressing   34
2.3.2 Register Addressing   34
2.3.3 Direct Addressing   35
2.3.4 Register Indirect Addressing   35
2.3.5 Implicit Addressing   36
2.4 Timing Effects of Addressing Modes   36
2.5 Instruction Set Classification   37
2.5.1 Data Transfer (Copy) Operations   37
2.5.2 Arithmetic Operations   38
2.5.3 Logical Operations   38
2.5.4 Branching Operations   39
2.5.5 Machine Control Operations   39
2.6 Data Transfer Instructions   39
2.6.1 Arithmetic Instructions   50
2.6.2 Logical Instructions   59
2.6.3 Branching Instructions   67
2.6.4 Machine Control Instructions   72
2.7 Complete Instruction Opcodes   75
Exercises  79

  3. Instruction Timing and Operation of 8085 Microprocessor 87

3.1 Introduction  87
3.2 Instruction Cycle   87
3.3 Basic State Transitions   89
3.4 Introduction to Machine Cycles   89
3.4.1 T-state   89
3.4.2 Machine Cycle   90
3.4.3 Instruction Cycle   90
3.5 Timing Diagram   91
3.5.1 Timing Diagram of Opcode Fetch Cycle   92
 Contents    ix
3.5.2 Operand Fetch or Memory Read Cycle   96
3.5.3 Memory Write Cycle   98
3.5.4 IO Read Cycle   99
3.5.5 IO Write Cycle   100
3.6 Timing Diagram of 8085 Instructions   100
Exercises  108

  4. Stack and Subroutine 112

4.1 Introduction  112
4.2 Use of Stack for Programmer   112
4.2.1  Push Rp  113
4.2.2 Timing Diagram of the PUSH Rp  114
4.2.3 POP Rp  116
4.2.4 Timing Diagram of the POP H   117
4.3 More Stack Related Instructions   120
4.3.1 SPHL   120
4.3.2 Timing Diagram of XTHL   121
4.3.3 Dad SP   123
4.4 Use of Stack by Microprocessor Subroutine   124
4.5 Call and RET Instructions   125
4.5.1 Timing Diagram of CALL 2500H Instruction   127
4.5.2 Timing Diagram of Conditional CALL Instruction   127
4.5.3 RET   129
4.5.4 Timing Diagram of RET Instructions   130
4.5.5 Timing Diagram of Conditional RET Instructions   130
4.6 Parameter Passing Techniques   134
4.7 Multiple Ending Subroutines   135
4.7.1 Nested Subroutine   136
4.7.2 Re-entrant Subroutine   137
4.7.3 Recursive Subroutine   138
4.8 Delay Routine   139
Exercises  147

  5. Interrupts of 8085 151

5.1 Introduction  151
5.2 Interrupt Systems   152
5.2.1 Single Line or Single Level Interrupt System   152
5.2.2 Multilevel or Multi-line Interrupt System   152
5.3 Determining the Address of the Interrupting Device   153
5.3.1 Polling   153
5.3.2 Hardware Polling (Daisy Chain)   154
5.3.3 Hardware Identification (Vectored Interrupts)   155
x    Contents

5.4 Types of Interrupts in 8085   155

5.4.1 Internal Interrupts   155
5.4.2 Software Interrupts   156
5.4.3 Hardware Interrupts   156
5.5 Hardware Interrupts of 8085   157
5.5.1 TRAP   157
5.5.2 RST7.5   158
5.5.3 RST6.5 and RST5.5   158
5.5.4 INTR   159
5.6 Software Interrupts of 8085   161
5.7 Interrupt Control Logic   162
5.8 Interrupt Related Instructions   162
5.8.1 Enable Interrupts (EI)   162
5.8.2 Disable Interrupts (DI)   163
5.8.3 Set Interrupt Mask (SIM)   163
5.8.4 Read Interrupt Mask (RIM)   164
5.9 Interrupt Priority Structure   164
5.10 Interrupt Systems   165
5.11 Hardware Instruction Generator   166
5.11.1 Eight Level Interrupt System   167
5.12 Software Design Problem   168
Exercises  171

PART 2
  6. Introduction to 8086 177
6.1 Introduction  177
6.2 The 8086 Microprocessor   177
6.2.1 Bus Interface Unit (BIU)   179
6.2.2 Execution Unit   181
6.3 PIN Configuration of 8086   184
6.3.1 Pin Details of 8086—Common to Both Minimum and
Maximum Mode   185
6.3.2 Pin Details of 8086—(Minimum Mode)   186
6.3.3 Pin Details of 8086 S—(Maximum Mode)   187
6.4 Memory Organization of 8086   189
6.5 Microprocessor 8088   191
Exercises  193

  7. 8086 Based Systems 200

7.1 Introduction  200
7.2 8086 Minimum Mode Configuration   200
7.2.1 Demultiplexing of the Multiplexed Buses    201
 Contents    xi
7.2.2 Transceiver 8286   203
7.2.3 Generation of Control Signals   204
7.2.4 Clock Generator 8284 and Driver   205
7.3 Maximum Mode Configuration of 8086   208
7.3.1 Bus Controller 8288   209
7.4 Bus Cycles of 8086   213
7.4.1 Minimum Mode Bus Cycles   215
7.4.2 Maximum Mode Bus Cycles of 8086 System   216
7.4.3 Bus Request and Bus Grant Timings in Minimum and
Maximum Mode Systems   218
Exercises  218

  8. Assembler Directives 222

8.1 Introduction  222
8.2 Assembly Language   222
8.3 Assembly Language Program Development Tools   223
8.3.1 Editor    224
8.3.2 Assembler   224
8.3.3 Linker   226
8.3.4 Loader   226
8.3.5 Debugger   226
8.4 TASM Assembler   228
8.5 MASM Assembler   229
8.6 classification of Assembler Directives   231
8.6.1 Data Defining Assembler Directives   231
8.6.2 Segment Defining Directives    237
8.6.3 Combining Segments   240
8.6.4 Managing Large Programs   241
8.6.5 Processor Directives   242
8.6.6 Initialization of Program Memory Models   243
Exercises  244

  9. Instructions Set and Programming of 8086 249

9.1 Introduction    249
9.2 Addressing Modes of 8086   249
9.2.1 Data Addressing Modes    249
9.2.2 Address Addressing Modes   256
9.3 Instruction Format   259
9.4 Instruction Templates   260
9.5 Instruction Set of 8086   267
9.5.1 Data Transfer Instructions   267
9.5.2 Arithmetic Instructions   273
9.5.3 Logical Instructions   282
xii    Contents

9.5.4 Shift and Rotate Instructions   285

9.5.5 Data Adjustment Instructions    291
9.5.6 String Instructions   293
9.5.7 Flag Related Instructions   296
9.5.8 Control Transfer Instructions   298
9.5.9 Processor-control Instructions    303
Exercises  320

10. Interrupts of 8086 334

10.1 Introduction  334
10.2 Classification of Interrupts   334
10.3 Classification and Response of Interrupts of 8086   335
10.4 Interrupt pointer Table   337
10.4.1 Dedicated Interrupts of 8086   338
10.4.2 Software Interrupts of 8086   342
10.4.3 Priority of Interrupts    343
Exercises  343

PART 3
11. IO and Memory Interfacing 349
11.1 Introduction  349
11.2 IO Devices and Their Interfacing   349
11.3 Interfacing of IO Devices with Microprocessor   350
11.4 Interfacing of Input Device   351
11.5 Interfacing of Output Device   353
11.6 Basic Concepts in Memory Interfacing   360
11.6.1 Address Decoding   360
11.6.2 Address Decoding Techniques   362
11.7 Memory Organization of Microprocessor 8086   366
11.7.1 Interfacing of Memory with 8086 in Minimum Mode   367
11.7.2 Memory Interfacing with 8086 in Maximum-mode   368
11.8 Interfacing of ROM with 8086   371
Exercises  374

12. Programmable Peripheral Interfacing Chip 381

12.1 Introduction  381
12.2 Programmable Peripheral Interfacing Chip 8255   381
12.2.1 Block Diagram of 8255   382
12.2.2 Pin Description of 8255   384
12.3 Operational Description of 8255   385
12.3.1 Bit Set Reset (BSR) Mode   386
12.3.2 IO Mode   387
12.3.3 Control Word Register of 8255 in IO Mode   388
 Contents    xiii
12.4 Mode 0 (Simple Input/Output)   389
12.5 Mode 1 (Strobed Input/Output)    391
12.5.1 8255 in Input Mode of Mode 1   391
12.5.2 Input Control Signal Definition   391
12.5.3 Timing Diagram of Mode 1 (Input)   393
12.5.4 Data Transfer Modes   393
12.5.5 Mode 1 Output Mode   394
12.5.6 Control Signal Definition Output Mode   395
12.5.7 Data Transfer in Output Mode in Mode 1   395
12.5.8 Timing Diagram of Mode 1 (Output Mode)   396
12.5.9 Combination of Mode 1    396
12.6 Mode 2 (Strobed Bidirectional Bus IO)   397
12.6.1 Mode 2 Different Combinations   398
12.7 Interfacing of 8255 with 8085   399
12.7.1 IO Mapped IO   400
12.7.2 Memory Mapped IO   400
12.8 8255 Interfacing with 8086   401
12.8.1 IO Mapped IO   402
12.8.2 Memory Mapped IO   403
12.9 Interfacing and Design Problems   405
12.10 Interfacing of Stepper Motor   418
12.10.1 Interfacing of Digital to Analog Converter   423
12.10.2 Interfacing of Analog to Digital Converter   428
Exercises  434

13. Programmable Interval Timer and Interfacing with 8085 and 8086 440
13.1 Introduction  440
13.2 Functional Block Diagram of 8253/54   440
13.3 PIN Configuration of 8253/54   442
13.3.1 Pin Description of 8253/54   442
13.4 Programming the 8253/54   444
13.4.1 Control Word Format   444
13.5 Write Operations   444
13.6 Read Operations   446
13.6.1 Simple Read/Write Operations for the Desired Counter
(Common for 8253 and 8254)   446
13.6.2 Counter Latch Command (Common for 8253 and 8254)   446
13.6.3 Read Back Command (only for 8254)   447
13.7 Modes of Operations    449
13.7.1 Mode 0: Interrupt on Terminal Count    449
13.7.2 Mode 1: Hardware Retriggerable One-Shot   451
13.7.3 Mode 2: Rate Generator   452
13.7.4 Mode 3: Square Wave Mode   452
13.7.5 Mode 4: Software Triggered Mode   453
xiv    Contents

13.7.6 Mode 5: Hardware Triggered Strobe (Retriggerable)   456

13.7.7 Operation Common to All Modes   456
13.7.8 Gate Pin Operation Summary   456
13.8 Interfacing of 8253/54 with Microprocessors   458
13.8.1 Interfacing of 8253/54 in IO Mapped IO Method with 8085    458
13.8.2 Interfacing of 8253/54 in Memory Mapped IO Method with 8085   459
13.8.3 Interfacing of 8253/54 in IO Mapped IO Method with 8086   461
13.8.4 Interfacing of 8253/54 in Memory Mapped IO Method with 8086   463
13.9 Programming of 8253/54   464
Exercises  471

14. DMA Controller 8257 and 8237 475

14.1 Introduction  475
14.2 DMA Controller   475
14.3 Functional Behaviour of a DMA Data Transfer   475
14.3.1 Burst or Block Transfer DMA   477
14.3.2 Cycle Steal or Single Byte Transfer DMA   477
14.3.3 Data Transfer DMA Operation    479
14.4 Programmable DMA Controller 8257   480
14.5 The PIN Diagram of 8257   481
14.6 Block Diagram of 8257   484
14.6.1 DMA Channels   484
14.6.2 Data Bus Buffer   486
14.6.3 Read/Write Logic   487
14.6.4 Control Logic   487
14.6.5 Priority Resolver   487
14.6.6 Mode Set Register   487
14.6.7 Status Register   489
14.7 Programming and Reading the 8257 Registers   490
14.8 DMA Operation   491
14.8.1 Single Byte Transfers   491
14.8.2 Consecutive Transfers   491
14.8.3 Control Override   492
14.8.4 Not Ready   492
14.8.5 Speed  492
14.9 State Diagram of 8257   492
14.10 Operation of DMA Cycle   493
14.11 Interfacing of 8257   494
14.11.1 IO Mapped IO Configuration   494
14.11.2 Memory Mapped IO Configuration   496
14.12 The 8237 DMA Controller    496
14.13 Functional Description   496
14.13.1 Registers of 8237   498
14.13.2 Current Address Register   498
 Microprocessors And Microcontrollers

25%
OFF

Author : Sunil Mathur And

Publisher : PHI Learning ISBN : 9788120352315
Jeebananda Panda

Type the URL : http://www.kopykitab.com/product/16972

Get this eBook