This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2659381, IEEE
Transactions on Power Electronics
TPEL-Reg-2016-10-1873.R1
Single-Stage Three-Phase Grid-Tied PV System
with Universal Filtering Capability Applied to
DG Systems and AC Microgrids
Leonardo Bruno Garcia Campanhol, Sérgio Augusto Oliveira da Silva, Member, IEEE,
Azauri Albano de Oliveira Júnior, and Vinícius Dário Bacon
Abstract—This paper proposes a single-stage three-phase four-
wire grid-connected photovoltaic (PV) system operating with a
dual compensating strategy and feed-forward control loop
(FFCL). Besides injection of active power into the grid, the PV
system operates as a unified power quality conditioner (UPQC),
suppressing load harmonic currents and compensating reactive
power. Furthermore, regulated, balanced and harmonic free
output voltages are provided to the load. Since the PV-UPQC is
based on a dual compensation strategy, the series converter
operates as a sinusoidal current source, whereas the parallel
converter operates as a sinusoidal voltage source. Thus, seamless
transition can be achieved from the interconnected to the
islanding operation modes, and vice-versa, without load voltage
transients. Moreover, to overcome problems associated with
sudden solar irradiation changes, fast power balance involving
the PV array and the grid is obtained, since the FFCL acts on the
generation of the series inverter current references. As a result,
the dynamic responses of both inverter currents and dc-bus
voltage are improved. Detailed analysis involving the active
power flow through the inverters is performed allowing proper
understanding of the PV-UPQC operation. Experimental results
are presented to evaluate both dynamic and static performances
of the PV-UPQC tied to the electrical distribution system.
Index Terms—NPC inverters, feed-forward control loop,
PV-UPQC system, universal filtering capability.
I. INTRODUCTION
HE production of electrical energy from renewable energy
T sources (RES) has grown a lot in recent decades, mainly
due to increased demand for electricity, as well as the global
intensive efforts to overcome the harmful environmental
impacts caused by pollutant energy sources, such as oil, coal,
natural gas, and others.
Manuscript received October 01, 2016; revised November 11, 2016;
accepted January 13, 2017. Date of publication month day, 201x; date of
current version month day, 201x.
L. B. G. Campanhol is with the Electrical Engineering Department, Federal
University of Technology (UTFPR-AP), Apucarana, PR, CO 86812-460
Brazil (e-mail: campanhol@utfpr.edu.br).
S. A. O da Silva, and V. D. Bacon are with the Electrical Engineering
Department, Federal University of Technology (UTFPR-CP), Cornélio
Procópio, PR, CO 86300-000 Brazil (e-mail: augus@utfpr.edu.br;
vinicius_vd@hotmail.com).
A. A. de Oliveira Jr. is with the Electrical and Computing Engineering
Department, São Carlos Engineering School, University of São Paulo
(EESC-USP), São Carlos, SP, CO 13566-590 Brazil (e-mail:
azauri@sc.usp.br).
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1
Distributed generation (DG) systems based on RES have
contributed to find new modern solutions for planning
conventional power systems [1]. Inserted in this scenario,
solar energy has emerged as a promising RES due to its
abundance across the earth’s surface. In particular, by means
of photovoltaic (PV) cells, photovoltaic panels have been
properly designed to produce energy by converting sunlight
into electricity.
Normally, grid-connected PV systems can be deployed by
means of single-stage (S-S) or double-stage (D-S) power
conversion [2], [3]. S-S PV systems are usually composed of
only a grid-tied inverter (dc/ac converter) [4]-[9]. In this case,
the PV array is directly connected to the dc-bus of the grid-
tied inverter. On the other hand, in D-S PV systems, an
additional dc/dc converter is placed between the PV array and
the inverter [10]-[12]. In this configuration, the maximum
power point tracking (MPPT) is performed by the dc/dc
converter [11]. Considering SS-PV systems, the task to
perform the MPPT is assumed by the grid-tied inverter,
combined with the advantage of achieving more efficiency
when compared to DS-PV systems [7], [8]. In both mentioned
PV system topologies, the dc/ac converter controls the
amplitude of the currents injected into the grid, in order to
guarantee the balance between the power produced to the PV
array and that absorbed by the grid.
In most applications, PV systems are connected to the
electrical distribution system, as well as microgrids where
local generation is carried out [1], [13], [14]. Besides energy
production, and according to a suitably adopted control
strategy, PV systems can also carry out other roles in a
microgrid, such as active filtering and/or reactive power
compensation. In other words, PV systems can perform tasks
similar to those performed by conventional parallel active
power filters (P-APF) [11], [15], [16].
In this paper, an S-S 3P4W grid-connected PV system with
combined operation with a unified power quality conditioner
(UPQC) is presented. The power circuit of the system, which
is denominated PV-UPQC, is composed of two back-to-back
connected neutral-point clamped (NPC) inverters. Thereby,
series-parallel active power line conditioning, as well as
injection of active power into the grid and load can be
simultaneously performed. As a result, apart from the role of
P-APF (load harmonic suppressing and reactive power
compensation), the PV-UPQC system is also able to provide
regulated, balanced, and harmonic free output voltages.
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Transactions on Power Electronics
TPEL-Reg-2016-10-1873.R1
In other words, although the PV-UPQC system can also be
connected to ac microgrids, in this paper it is employed to
deliver active power to the conventional electrical distribution
system and load from a distributed generation source
composed of a PV array, while universal filtering is carried
out.
A dual compensating strategy is adopted to operate the PV-
UPQC system, where the parallel converter is controlled to act
as a sinusoidal voltage source, while the series converter is
controlled to operate as a sinusoidal current source [17]-[19].
Usually, the UPQC is controlled using a conventional
compensating strategy, in which the parallel converter behaves
as a non-sinusoidal current source and the series converter
behaves as a non-sinusoidal voltage source [20]-[22].
The PV-UPQC can work based on two operation modes. In
the first, called interconnected mode, the PV array provides
power to the electrical distribution system, as well as to the
load. In the second, called islanding mode, the PV array
provides power only to the load, similar to an uninterruptible
power supply system [17]. If the conventional compensating
strategy is being adopted to operate the PV-UPQC system, in
islanding mode, the parallel inverter mandatorily needs to
change its operation from a non-sinusoidal current source to a
sinusoidal voltage source. A contrary procedure also happens
when the PV-UPQC operates in islanding mode and changes
to interconnected mode. As a result, the need to change the
operation mode of the parallel inverter can cause voltage
transients (overvoltage) in the load. On the other hand, if the
PV-UPQC operates using a dual compensation strategy, the
aforementioned control changes do not occur, since the
parallel inverter always remains operating as a voltage source
in both interconnected and islanding modes. As a
consequence, no voltage transients occur in the load, as the
parallel inverter input control references are the output voltage
references ( VL∗_ abc ) and the estimated utility frequency ( ω ∗ ).
In a microgrid, for instance, the multifunctionality of the
proposed PV-UPQC system can be highlighted. In the case of
the grid being disconnected, the series converter is inhibited
and the parallel converter could operate as a grid-feeding
power converter [1], as the parallel converter could also be
controlled as a current source. In the case of the existence of
either a storage energy system or DG connected to the dc-bus,
the parallel converter can operate as a grid-forming power
converter [1], since it can remain controlled as a voltage
source.
Several DG systems associated with unified power quality
conditioners have been proposed in the literature [23]-[25]. In
[23], an S-S three-phase three-wire (3P3W) PV system
configuration using two 3-Leg voltage source inverters
operating associated with UPQC was presented. Nevertheless,
experimental results were presented considering its operation
only as a dynamic voltage restorer. Thereby, suppression of
the utility voltage harmonics, and its operation as a P-APF
were not taken into account. In [24], the D-S PV system was
applied to a 3P3W system by means of only computational
simulations. However, no utility voltage or load current
harmonic suppression were considered. Combined operation
of UPQC with distributed generation is presented in [25]. As a
conventional compensating strategy was employed, the
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2
parallel inverter changes its operation mode from current
source to voltage source, and vice-versa, when the system
operates either in islanding or interconnected modes,
occasioning voltage transients in the load.
In the presented PV-UPQC system, the amplitudes of the
currents drained from the grid, as well as the direction of
power flow through the series and parallel converters vary
depending on the amount of energy produced by the PV array
and how much energy is consumed by the loads. Thus, at night
or when the power generated by the PV array is not enough to
be provided to the grid, the PV-UPQC system keeps operating
as a classical UPQC.
The dc-bus control loop adjusts the amplitudes of the
sinusoidal currents injected into the grid by means of the
series converter, in which the dc-bus voltage reference is
determined by the MPPT algorithm. Normally, the dynamic
response of the dc-bus control loop must be slower than those
found in the current control loops of the grid-tied inverter [7].
Thus, adequate adjustments in the gains of both mentioned
controllers are mandatory to guarantee the injection of non-
distorted currents into the grid, since the dc-bus control loop
must not affect the performance of the current control loops.
On the other hand, abrupt solar irradiation variations can result
in significant oscillations in the dc-bus voltage [7], which
could interfere in proper PV-UPQC power balance, and,
hence, impair the computation of the inverter current
references.
To overcome this problem, this paper also proposes the use
of a feed-forward control loop (FFCL) acting in conjunction
with the dc-bus control loop to accelerate the calculation of
the series converter current references. As a consequence,
even under fast solar irradiation changes, the dc-bus voltage
oscillations are properly attenuated, speeding up the power
balance of the system. Furthermore, since the dynamic
response is improved, both the setting time and the
overvoltage/undervoltage of the dc-bus voltage are strongly
reduced.
This paper is organized as follows: Section II presents the
PV-UPQC system description, as well as the control structures
involving the two back-to-back connected NPC inverters. In
addition, the strategies employed to generate the series and
parallel converter input references, as well as the phase-locked
loop (PLL) system description are discussed. In section III
both the open-loop and closed-loop transfer functions are
presented, as well as the procedures employed to calculate the
controller gains. Section IV describes the FFCL and its main
function. In Section V the power flow through the PV-UPQC
is analyzed, while in Section VI the extended experimental
results are shown to highlight the dual compensating strategy
and the FFCL action. Finally, Section VII presents the
conclusions.
II. PV-UPQC SYSTEM DESCRIPTION
The complete power circuit scheme of the proposed S-S
3P4W grid-tied PV system is composed of two back-to-back
connected NPC inverters and their respective passive filtering
elements, and three single-phase coupling transformers
employed to connect the series NPC inverter to the grid, as
shown in Fig. 1.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2659381, IEEE
Transactions on Power Electronics
TPEL-Reg-2016-10-1873.R1
Fig. 1. Complete power circuit of the PV-UPQC system connected to a conventional electrical distribution system.
The distributed generation source, without storage, is
composed of a PV array, which is formed by a single string
with twenty series-connected PV panels, making possible the
direct connection between the PV array and the dc-bus of the
inverters.
The PV-UPQC system is designed to operate with dc-bus
voltage reference vdc ∗ determined by the MPPT algorithm.
Thus, at MPP and under standard test conditions (STC), the
PV system operates with a dc-bus voltage amplitude of around
616 V, since at MPP the PV voltage is equal to 30.8 V per-
panel. On the other hand, the lower dc-bus voltage is limited
∗
to vdc
_ min = 460 V, meaning that below this voltage limit the
PV-UPQC operates out of the MPP. Furthermore, at night, for
instance, the system is controlled to operate only as a UPQC,
such that vdc ∗
_ min is also set to 460 V.
A. UPQC with Dual Compensation Strategy
The dual compensation strategy applied to UPQC differs
from the conventional compensation strategy due to the
parallel converter being controlled to operate as a sinusoidal
voltage source providing balanced and regulated sinusoidal
voltages to the load. As the parallel converter behaves as a
sinusoidal voltage source, a low impedance path is achieved.
In this case, the flow of the load harmonic currents through the
parallel converter is allowed. On the other hand, the series
converter is controlled to operate as a sinusoidal current
source, draining balanced sinusoidal currents from the utility
grid. In this case, since a high enough impedance path is
achieved, the flow of the load harmonic currents through the
grid is blocked.
In addition, both the sinusoidal voltage and current input
references are in phase with the utility voltages. Thus, the
series converter is responsible for indirectly compensating
reactive power and unbalances of the load, as well as
suppressing harmonic currents.
Simultaneously, the parallel converter is responsible for
regulating the output voltages and, indirectly compensating
utility voltage unbalances and suppressing utility voltage
harmonics. In this case, the utility voltage disturbances, such
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3
as voltage unbalances, sags/swells, and harmonics will always
appear across the single-phase series transformers.
As can be noted, since the input references are sinusoidal,
there is no need to compute non-sinusoidal input references by
means of the specific methods normally used in the
conventional compensation strategy. Furthermore, the input
references are continuous in the dq synchronous rotating
frame, due to the controlled quantities of current and voltage
being sinusoidal in the abc stationary frame. This allows the
use of the classical proportional-integral (PI) controllers with
null errors in steady-state.
B. Series Current References and Output Voltage References
The signal flow graph shown in Fig. 2(a) presents the series
current control loop. The d-axis current into the synchronous
reference frame (SRF) iLd represents the sum of the active
and harmonic components of the load currents, which can be
computed by measuring the load currents ( iLa , iLb , iLc ), as
given by:
2 1 3 1 3  iLa 
iLd = cosθ − cosθ + sinθ − cosθ + sinθ  i Lb  (1)
3 2 2 2 2  iLc 
where sinθ and cos θ are the coordinates of the rotating unit
vector, and θ = θ pll is the estimated utility voltage phase-
angle.
As can be noted in Fig. 2(a), a low-pass filter (LPF) is used
to extract the continuous current iLd dc , which represents the
total active components of the load currents.
Finally, the input current reference of the series converter in
the d-axis is given by:
i*scd = iLd dc + idc − i ff (2)
where idc is the output signal of the dc-bus voltage PI
controller, and i ff is the feed-forward current.
The quantity idc determines the amount of active power that
will be absorbed from the grid or furnished to the grid in order
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TPEL-Reg-2016-10-1873.R1 4

for the dc-bus voltage to remain regulated. In other words, idc

will adjust the amplitude of i*scd to control the power flow
through the PV-UPQC system performing the power balance.
Acting in conjunction with idc the quantity i ff will accelerate
the power balance as detailed in Section IV.
As sinusoidal and balanced currents are expected in the grid
the quadracture current i*scq and zero sequence component i*sc0
are both set to zero.
Fig. 3. Three-phase PLL scheme.

III. PV-UPQC CONTROLLERS

In this Section, the open- and closed-loop transfer functions
(TF) of the series and parallel NPC inverters, as well as the dc-
bus voltage are described, allowing proper design of the
current and voltage controllers.
A. Current Controller
(a)
Inductive (L) output filters are adopted to connect the series
NPC inverter to the series transformers, as shown in Fig. 1. In
order to obtain the mathematical model of the converter, it is
assumed that the coupling inductors are identical to each
other, so that the inductances are Lsca = Lscb = Lscc and their
respective resistances RLsca = RLscb = RLscc . Thus, considering
the inverter scheme shown in Fig. 1, (3) can be written.
u sc _ abc _ pwm = v RLsc _ abc + vLsc _ abc + n.vTsc _ abc (3)

(b) where u sc _ abc _ pwm are the PWM output voltages of the series
Fig. 2. Signal flow graphs of the control loops of the series and parallel NPC NPC inverter; v RLsc _ abc and v Lsc _ abc are the respective
inverters: (a) reference current generation and series current control loop; (b) voltages across the resistances and inductances of the L-filters
parallel output voltage control loop.
( Lsc _ abc ); vTsc _ abc = vs _ abc − v L _ abc are the voltages across the
The signal flow graph shown in Fig. 2(b) represents the series transformers; and n is the transformation ratio, which in
parallel voltage control loop. As aforementioned, the input this paper was adopted equal to 1.
voltage references of the parallel converter are set to VL∗_ abc in The series PWM voltages can be represented in the
dq0-axes, in which the state-space equation is given by:
the stationary reference frame (abc-axes) and v ∗Ld in the SRF
direct axis (d-axis), as shown in Fig. 2(a). As sinusoidal and x& sc _ dq 0 (t ) = Asc x sc _ dq 0 (t ) + Bsc u sc _ dq 0 (t ) + Fsc wsc _ dq 0 (t ) (4)
balanced voltages are provided to the load, the quadracture
where:
voltage v∗Lq and zero sequence component v∗L 0 are both set to T
 di discq disc 0  i i i  ;
T
zero. x& sc _ dq0 (t ) =  scd  ; x (t ) =
 dt dt dt 
sc _ dq 0  scd scq sc 0 
C. Phase-Locked Loop System T
The utility voltage phase-angle detection is achieved by u sc _ dq 0 ( t ) = u scd _ pwm u scq _ pwm u sc 0 _ pwm  ;
 
means of the three-phase PLL system presented in Fig. 3 [26].
It is based on a power-based PLL system (3pPLL) and uses T
wsc _ dq 0 ( t ) = vTscd vTscq vTsc 0  ;
non-autonomous adaptive filters (AFs) to extract the  
fundamental components of the three-phase utility voltages in
order to reject utility disturbances related to voltage RLsc 1 0 0 1 0 0 1 0 0 
harmonics. After the adaptive filtering, the positive sequence Asc = − 0 1 0 ; Bsc = 1 0 1 0 ; Fsc = − 1 0 1 0 .
Lsc 0 0 1 Lsc 0 0 1  Lsc 0 0 1
components of the utility voltages are achieved using a      
positive-sequence detector (PSD) in order to reject voltage
After some mathematical manipulations in (4), the open-
unbalances, as shown in Fig. 3.
loop TF of the series converter average model is given by:
Details related to the design of the PI controller gains
( K Ppll , K Ipll ) and AF gain ( K c ), as well as the stability isc _ dq 0 ( s) Vdc / 2
Gsc _ dq 0 ( s) = = (5)
analysis requirements are presented in [26]. d sc _ dq 0 ( s) ( Lsc s + RLsc )

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where d sc _ dq 0 are the duty cycles.  RLpc   1 

− L 0 0 0 0 0 
Fig. 4 shows the signal flow graph of the current controllers  pc   L pc 0 0 
 RLpc   
and average model of the series NPC inverter, where K Pis and  1 
 0 − L pc 0 0 0 0  
0
L pc
0

K Iis are the proportional and integral (PI) gains of the series   
 0 RLpc  1 
*
current controller (PIis), isc _ dq 0 are the current references in 
0 − 0 0 0
  0 0 
L pc L pc 
Apc =   ; B pc =  
;
the dq0-axes, and Vdc is the total dc-bus voltage  1  0 0 0 
 Cp
0 0 0 0 0
 
( Vdc = vdc1 + vdc 2 ). The constant K pwm = 1/ Ppwm represents
   
 0 1   0 0 0 
the static gain of the NPC inverter [27], where Ppwm is the 0 0 0 0  
 Cp   
peak value of the PWM triangular carrier in the digital signal  1   0 0 0 
controller (DSC).  0 0 0 0 0   
 Cp 
Thus, from Fig. 4, the closed-loop TFs can be represented
by: −1 L pc 0 0 0 0 0 
 
isc _ dq0 (s) X1 ( K Pis s + K Iis )  0 −1 L pc 0 0 0 0 
= 2 + (X K
(6)  0 0 
1 Pis + RLsc )s + X 1K Iis
*
isc ( s ) L s 0 −1 L pc 0 0
Fpc = 
0 
_ dq 0 sc .
0 0 0 −1 C p 0
where X 1 = K pwm (Vdc / 2) .  
 0 0 0 0 −1 C p 0 
 0 0 0 0 0 −1 C p 
 
After some mathematical manipulations in (8), the open-
loop TF of the series converter average model is given by:
vL _ dq0 ( s) Vdc / 2
Fig. 4. Signal flow graph in dq0-axes of the current controllers and the G pc _ dq0 ( s ) = = (9)
average model of the series NPC inverter. d pc _ dq0 ( s) L pcC p s 2 + RLpcC p s + 1
B. Voltage Controller where d pc _ dq 0 are the duty cycles.
The parallel NPC inverter is connected to the output point Fig. 5 shows the signal flow graph of both the voltage
of common coupling (PCC2) by means of inductive-capacitive (outer control loop) and current (inner control loop)
(LC) filters. The mathematical model is developed considering controllers, as well as the average model of the parallel
identical inductors and capacitors, such that the inductances converter, where K Pvp and K Ivp are PIvp controller gains;
are L pca = L pcb = L pcc , and their respective resistances
K Pip is the proportional gain of the Pip controller; v∗L _ dq 0 and
RLpca = R Lpcb = R Lpcc , and C pa = C pb = C pc .
*
i Lp
By means of the parallel converter scheme shown in Fig. 1, _ dq 0 are the respective voltage and current references in

the PWM output voltages of the parallel NPC inverter the dq0-axes.
( u pc _ abc _ pwm ) can be represented by: Thereby, from Fig. 5, the closed-loop TFs are given by:

u pc _ abc _ pwm = v RLpc _ abc + v Lpc _ abc + v L _ abc (7) vL _ dq0 (s) X2 + X3
= (10)
vL∗ _ dq0 (s) Y1s 3 + Y2 s 2 + Y3s + Y4
where vRLpc _ abc and vLpc _ abc are the respective voltages
across the resistances and inductances of the L-filters where:
( L pc _ abc ), and v L _ abc are the output voltages. X 2 = K Pvp K Pip K pwm (Vdc / 2) ; X 3 = K Ivp K Pip K pwm (Vdc / 2) ;
The parallel PWM voltages can also be represented in the
dq0-axes, in which the state-space equation is given by: Y1 = L pc C p ; Y2 =  RLpc + K Pip K pwm (Vdc / 2) C p ;
 
x& pc _ dq 0 (t ) = A pc x pc _ dq 0 (t ) + B pc u pc _ dq 0 (t ) + F pc w pc _ dq 0 (t ) (8)
Y3 =  K Pvp K Pip K pwm (Vdc / 2) + 1 ; Y4 = K Ivp K Pip K pwm (Vdc / 2) .
 
where:
T
 diLpd diLpq diLp0 dvLd dvLq dvL 0 
x& pc _ dq 0 (t ) = 
dt 
;
 dt dt dt dt dt
T
x pc _ dq0 (t ) = iLpd iLpq iLp 0 vLd vLq vL 0  ;
 
T
u pc _ dq0 (t ) = u pcd _ pwm u pcq _ pwm u pc0 _ pwm  ;
 
T
w pc _ dq 0 (t ) = vLd vLq vL0 (iLd − iscd ) (iLq − iscq ) (iL 0 − isc0 ) ; Fig. 5. Signal flow graph in dq0-axes of the voltage controllers and average
  model of the parallel NPC inverter.

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Transactions on Power Electronics
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C. DC-bus Voltage Controllers
The dc-bus voltage PI controller ( PI v dc ) is presented in
Fig. 2(a). It is used to control the total dc-bus voltage at
∗ , which is obtained from the MPPT technique
reference vdc
based on perturb and observe (P&O) [16].
The procedure used for obtaining the open-loop TF of the
dc-bus voltage is detailed in [28], which is given by:
vd
Gvdc ( s) = (11)
vdcCdc s
where vd is the grid voltage into the SRF (d-axis), vdc is the
dc-bus voltage and C dc is the dc-bus equivalent capacitance.
A PI controller ( PI v dc ) is used to control the dc-bus
voltage. In this case the closed loop TF is found by:
vdc ( s) K Pvdc vd.s + K Ivdc vd
= (12)
vdc ( s) vdcCdc s 2 + K Pvdc vd .s + K Ivdc vd
∗
where K Pvdc and K Ivdc are the PI controller gains.
An additional dc-bus voltage denominated PI vdcu is used
to compensate voltage unbalances in the dc-bus voltage, as
shown in Fig. 2(b). In this case, the difference between the dc-
bus voltages ( vdc1 − vdc 2 ) is compared to the voltage reference
equal to zero. The PI v dcu output signal ( vdcu ) is added to the
zero sequence component v ∗L0 (0-axis).
In this paper, all the procedures employed for tuning the
current and voltage PI controllers are based on the frequency
response method detailed in [29]. Phase-margins and
crossover frequencies at 0dB are the input design
specifications to determine the controller gains.
IV. FEED-FORWARD CONTROL LOOP
In this Section, the functionality of the FFCL is
emphasized, since its main function is realized when the PV
array is under sudden solar radiation changes.
The FFCL is needed because the dynamic response of the
dc-bus control loop is always slower than the series converter
current control loops. Thereby, the FFCL acts in conjunction
with the dc-bus controller, determining the proper current
amplitudes of the series converter, so that fast power balance
of the PV-UPQC is achieved. In other words, the FFCL
contributes to speed up computation of the input current
references during the occurrence of fast variations in solar
radiation. As a consequence, possible disturbances in the
dc-bus, such as voltage oscillations and voltage
overshoot/undershoot are reduced. In addition, the setting time
of the dc-bus voltage during transients is also reduced.
The strategy consists of estimating, in the abc-frame, the
peak amplitudes of the fundamental series converter currents
( I s pk ) that would be injected into the grid. After that, I s pk is
transformed from the abc-frame into the dq-frame such that
i ff is obtained.
The power produced by the PV array ( Ppv ) is given by:
Ppv = v pvi pv = (vdc1 + vdc2 )i pv (13)
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where v pv and i pv are the respective PV array voltage and
current, and v dc1 and v dc 2 represent the dc-bus voltages of
the NPC inverters.
The grid-tied series inverter currents, as well as the utility
voltage grid are assumed to be balanced. In this case, the
active power ( Pac ) provided from the PV-array to the grid is
given by:
3Vs pk I s pk
Pac = 3Vs rms I s rms = (14)
2
where Vs rms and I s rms are the rms values of the respective
fundamental utility voltages and currents, respectively, and
Vs pk and I s pk are their respective peak amplitudes.
Neglecting any system losses, Ppv is assumed equal to Pac .
Thus, from (13) and (14), I s pk can be estimated by:
2v pvi pv
I s pk = (15)
3Vs pk1
where Vs pk1 represents the peak amplitude of the utility
voltage (positive sequence component). This quantity is
estimated by the PLL system shown in Fig. 3.
Finally, the current i ff represented in the dq rotating frame
is given by:
i ff = 3 2.I s pk (16)
Thus, i ff is used in (2) to compute the input series
converter reference ( i*scd ) in the dq-axes.
Therefore, as can be seen, although the PV-UPQC power
balance can be ensured only through the dc-bus voltage
controller, the current i ff allows improvement in the dynamic
responses of both the dc-bus voltage and grid-tied series
inverter currents. Furthermore, there is no need to use
additional voltage or current transducers, since the quantities
employed to calculate i ff have been previously measured
( v pv and i pv ) or estimated ( Vs pk1 ).
V. ACTIVE POWER FLOW THROUGH THE NPC INVERTERS
The active power flow through the PV-UPQC system is
presented in Fig. 6. It is determined taking into account the
following aspects: i. the amount of energy generated by the
PV array; ii. the amount of energy consumed by the load; and
iii. the difference between the rms grid voltage ( Vs ) and the
rms load voltage ( VL ). In Fig. 6 (a) to (f) the active powers
involved to establish the analysis are: grid power Ps , PV array
power Ppv , series converter power Psc , parallel converter
power Ppc and load power PL .
In Fig. 6 (a), (b) and (c) Vs > VL In Fig. 6 (a), as PL = 0 W,
all energy produced by the PV array is delivered to the grid by
means of both the series and parallel converters. The majority
of energy is always handled by the parallel converter. In
Fig. 6 (b) PL ≠ 0 W and Ppv > PL . In this case, part of the
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energy produced by the PV array is delivered to the grid by

means of the series and parallel converters and the remainder
is sent to the load through the parallel converter. In Fig. 6 (c)
PL ≠ 0 W and Ppv < PL . In this case, all energy produced by
the PV array is delivered to the load by the parallel converter
and the remainder is drained from the grid. As can be noted,
part of the energy furnished by the grid to the load goes
through the series and parallel converters. (a)
In Fig. 6 (d), (e) and (f) Vs < VL . In Fig. 6 (d), as PL = 0 W,
all energy produced from the PV array is delivered to the grid
by means of the parallel converter. In this case, the active
power consumed by the series converter goes through the
parallel converter. In Fig. 6 (e) PL ≠ 0 W and Ppv > PL . In this
case, part of the energy produced by the PV array is delivered
to the grid by means of the parallel converter and the
remainder is sent to the load. As can be noted, the series (b)
converter also consumes active power. In Fig. 6 (f) PL ≠ 0 W
and Ppv < PL . In this case, the energy produced by the PV
array is delivered to the load by the series and parallel
converters and the remainder is drained from the grid.
In an ideal case, when Vs = VL , there is no active power
flowing through the series converter.
In Table I the conditions used to determine the power flow
(c)
through the power converters are presented.
TABLE I
CONDITIONS ADOPTED TO DETERMINE THE AP-F THROUGH THE PV-UPQC
Conditions rms voltages Load Power PV Power
1 Vs > VL PL = 0 Ppv > 0
2 Vs > VL PL > 0 Ppv > PL
3 Vs > VL PL > 0 Ppv < PL
4 Vs < VL PL = 0 Ppv > 0
5 Vs < VL PL > 0 Ppv > PL
6 Vs < VL PL > 0 Ppv < PL (d)

VI. EXPERIMENTAL RESULTS

The PV-UPQC experimental setup shown in Fig. 7 was
built based on the scheme presented in Fig. 1. Six IGBT
modules (SKM100GB 12T4 - Semikron) with their respective
drivers, and six fast recovery diodes (DSEI 60 06A - IXYS)
compose each of the 3-level NPC inverters. The current and
voltage transducers, LEM LA 100-P and LEM LV 25P,
(e)
respectively, were employed in the signal conditioning boards.
In addition, the current and voltage controllers, the SRF-based
algorithm, the FFCL, the P&O-based MPPT, and PLL
algorithms were embedded in the digital signal controller
TMDXCNCD28377D – Texas Instruments. Finally, twenty
series-connected PV panels (SW 245 – SolarWorld) make up
the PV array. Table II presents the parameters of the
PV-UPQC system. The passive elements of the NPC inverters
were designed based on design procedures presented in [30], (f)
while the design specifications of the controllers included in Fig. 6. Active power flow through the PV-UPQC: (a) Vs > VL with PL = 0; (b)
Table III were achieved based on design procedures presented Vs > VL with Ppv > PL; (c) Vs > VL with Ppv < PL; (d) Vs < VL with PL = 0; (e)
in [29]. Vs < VL with Ppv > PL; (f) Vs < VL with Ppv < PL.

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neutral current ( iLn ), grid voltages ( vsa , vsb , vsc ), and load
voltages ( v La , v Lb , v Lc ) are shown. As current harmonic
suppression and load unbalance compensation are performed,
sinusoidal and balanced grid currents are achieved. In
addition, regulated and almost sinusoidal and balanced load
voltages are also obtained.
In Figs. 9 to 11, static results for the PV-UPQC system
injecting active power into the grid are presented, considering
Load 2. In Fig. 9 the load is disconnected and only active
power is being injected into the grid (OPM 2), where
Fig. 7. PV-UPQC prototype setup. Ppv ≅ 3000W. As can be seen, the source currents are
sinusoidal and in opposite phase to the respective utility
TABLE II
PARAMETERS ADOPTED IN THE EXPERIMENTAL TESTS voltages. In Fig. 10, Ppv is higher than the load active power
Nominal utility voltages (rms) Vs = 127.27 V PL (OPM 3). In this case, the load is fed by the PV-UPQC
Series inverter inductive filters Lsc = 3.5 mH
Resistance of the series inverter inductive filters RLsc = 0.5 Ω
and the surplus of the produced active power is sent to the
Parallel inverter inductive filters Lpc = 1.7 mH grid, and the series converter also synthetizes sinusoidal
Resistance of the parallel inverter inductive filters RLpc = 0.4 Ω currents in opposite phase to the respective utility voltages.
Parallel inverter capacitive filters Cp = 60 µF The OPM 4 occurs when Ppv is smaller than PL , as shown in
Equivalent dc-bus capacitance Cdc = 2350 µF Fig. 11. As can be noted, the PV-UPQC system, in
dc-bus voltage at MPP Vdc = 616 V
conjunction with the grid, supplies the load. As can be
Lower dc-bus voltage limit ∗ = 460 V
vdc observed, in both OPM 3 and 4 the PV-UPQC system
Switching frequency of the NPC inverters fsw = 20 kHz performs the active power-line conditioning.
Sampling frequency of the DSC A/D converters fad = 60 kHz Fig. 12 shows the PV-UPQC operating in the OPM 5. In
Sampling frequency of the P&O-based MPPT fMPPT = 10 Hz this case, it is connected to a programmable AC power source
P&O-based MPPT step size voltage ∆v = 1V that provides distorted input voltages, such as voltage
PWM gain Kpwm = 0.002
unbalances, harmonics, and sags. As can be noted, even under
Load 1 - Single-phase full-bridge rectifiers followed by RL and RC loads
Phase A Phase B Phase C
distorted voltage conditions, the output voltages ( vL _ abc ) are
R = 6 Ω - L = 15.6 mH R = 8 Ω - L = 24.2 mH R = 53 Ω - C = 470 µF always balanced, regulated, and harmonic free. As the output
Sa = 1730 VA Sb = 1410 VA Sc = 870 VA voltages are controlled to be sinusoidal and balanced, the
Load 2 - Three-phase full-bridge rectifier followed by R load difference between the input voltages and output voltages
R = 40 Ω appears across the series transformers ( vTsc _ abc ).
Sa = 730 VA Sb = 720 VA Sc = 730 VA
Table IV presents the total harmonic distortion (THD) and
TABLE III rms values of voltages and currents related to the grid and
DESIGN SPECIFICATIONS AND GAINS OF THE P AND PI CONTROLLERS load. As can be seen, the THDs of both grid currents and
Series inverter PI current controller output voltages were reduced in all operation modes.
PIis crossover frequency ωcis = 10,472 rad/s Furthermore, Table IV also presents the power factors (PF)
PIis phase margin PMis = 85º related to the grid and load. As can be noted, effective PF
PIis current controller gains KPis = 820.05 KIis = 860,900
corrections were achieved.
Parallel inverter PI voltage and P current controllers The dynamic results for abrupt solar radiation changes are
PIvp crossover frequency ωcvp = 3,927 rad/s
presented in Figs. 13 and 14, in which are shown the total dc-
PIvp phase margin PMvp = 85º
PIvp voltage controller gains KPvp = 0.2347 KIvp = 80.643
bus voltage ( vdc ), dc-bus controller output signal ( idc ), feed-
Pip crossover frequency ωcip = 12,560 rad/s forward current ( i ff ), and PV array power ( Ppv ). The tests
Pip current controller gain KPip = 472.624
were performed disconnecting and reconnecting the PV array
dc-bus PI voltage controller
to the dc-bus at 2.5s and 15s, respectively. Fig. 13 shows the
PIvdc crossover frequency ωv dc = 22.619 rad/s
results when i ff is used to speed up generation of the series
PIvdc phase margin PM v dc = 80º
inverter current references. Fig. 14 shows similar tests
PIvdc voltage controller gains K Pv dc = 0.1095 K Iv dc = 0.4366
disregarding the FFC action. According to the results, the
PLL parameters and PI controller gains oscillations in the dc-bus voltage are reduced when i ff is used
PIPLL controller gains KPpll = 141.7 KIpll = 7,777.4
AF gain Kc = 300 during the PV array transients.
AF adaptation step-size µ = 0.005 Table V compares the experimental results presented in
Fig. 13 (with FFCL) and 14 (without FFCL). It can be
Fig. 8 presents the static results of the PV-UPQC system observed that the dc-bus voltage ( vdc ) dynamic response
operating as a classical UPQC feeding Load 1 (OPM 1 – (setting time and overshoot/undershoot) was strongly reduced
Operation Mode 1), where the grid currents ( isa , isb , isc ), under abrupt solar radiation changes when the FFCL is
grid neutral current ( isn ), load currents ( iLa , iLb , iLc ), load employed.

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Time [s] Time [s] Time [s] Time [s]

(a) (b) (c) (d)
Fig. 8. OPM 1 (Load 1): PV-UPQC performing only active power filtering with Ppv = 0 W (50V/div, 20A/div, 5ms/div): (a) grid voltages (vsa, vsb, vsc), (b) grid
currents (isa, isb, isc, isn), (c) load voltages (vLa, vLb, vLc), (d) load currents (iLa, iLb, iLc, iLn).

Time [s] Time [s]

(a) (b)
Fig. 9. OPM 2 (Load 2): PV-UPQC performing only active power injection into the grid with PL = 0 W and Ppv = 3000 W (50V/div, 10A/div, 5ms/div): (a) grid
voltage (vsa) and grid currents (isa, isb, isc), (b) load voltage (vLa) and parallel NPC inverter currents (ipca, ipcb, ipcc).

Time [s] Time [s] Time [s]

(a) (b) (c)
Fig. 10. OPM 3 (Load 2): PV-UPQC performing active power injection plus active filtering with Ppv > PL (50V/div, 10A/div, 5ms/div): (a) grid voltage (vsa) and
grid currents (isa, isb, isc), (b) load voltage (vLa) and parallel NPC inverter currents (ipca, ipcb, ipcc), (c) load voltage (vLa) and load currents (iLa, iLb, iLc).

Time [s] Time [s] Time [s]

(a) (b) (c)
Fig. 11. OPM 4 (Load 2): PV-UPQC performing active power injection plus active filtering with Ppv < PL (50V/div, 10A/div, 5ms/div): (a) grid voltage (vsa) and
grid currents (isa, isb, isc), (b) load voltage (vLa) and parallel NPC inverter currents (ipca, ipcb, ipcc), (c) load voltage (vLa) and load currents (iLa, iLb, iLc).

Time [s] Time [s] Time [s] Time [s]

(a) (b) (c) (d)
Fig. 12. OPM 5 (Load 2): PV-UPQC connected to unbalanced and distorted utility grid Ppv = 0 W (50V/div): (a) grid voltages (vsa, vsb, vsc) (5ms/div); (b) load
voltages (vLa, vLb, vLc) (5ms/div); (c) series transformers voltages (vTsca, vTscb, vTscc) (5ms/div); (d) grid voltages (vsa, vsb, vsc) and phase “a” output voltage (vLa) for
voltage sags (30%) (100V/div, 10ms/div).

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TABLE IV
THD, RMS VALUES OF THE VOLTAGES AND CURRENTS AND POWER FACTORS
Operation Total harmonic distortion (%)
Modes vsa vsb vsc isa isb isc vLa vLb vLc iLa iLb iLc
OPM 1 1.8 1.6 1.5 2.0 1.9 2.2 3.0 2.9 3.1 29.7 30.4 77.1
OPM 2 1.7 1.9 1.8 2.8 2.7 2.6 2.3 1.9 1.4 --- --- ---
OPM 3 2.1 2.2 2.1 6.7 6.5 6.0 2.6 2.2 1.7 27.2 27.1 26.4
OPM 4 1.8 1.8 1.9 5.4 5.4 4.5 2.5 2.2 1.7 27.2 27.1 26.4
OPM 5 10.6 10.9 11.1 4.5 3.9 3.9 2.2 2.0 1.5 26.7 27.3 26.6
rms Voltages (V) and Currents (A)
OPM 1 124 125 126 10.9 10.5 10.4 128 126 128 14.2 11.4 7.5
OPM 2 130 130 130 7.2 7.1 7.1 127 127 127 --- --- ---
OPM 3 127 128 128 2.6 2.5 2.5 126 127 127 5.6 5.6 5.7
OPM 4 127 127 126 3.1 3.0 3.0 127 126 127 5.6 5.6 5.7
OPM 5 110 100 90 5.0 4.8 4.6 102 100 100 4.5 4.4 4.4
Power Factor
utility grid loads
phase A phase B phase C phase A phase B phase C
OPM 1 1.0 1.0 1.0 0.93 0.93 0.63
OPM 2 -0.99 -0.99 -0.99 --- --- ---
OPM 3 -0.99 -0.98 -0.98 0.96 0.96 0.96
OPM 4 0.98 0.99 0.99 0.96 0.96 0.96
OPM 5 1.0 0.99 0.99 0.96 0.96 0.96

Time [s] Time [s] Time [s]

(a) (b) (c)
Fig. 13. Dc-bus voltage vdc, iff current, idc current and PV array power Ppv for abrupt solar radiation change with FFCL (50V/div, 14A/div, 2kW/div): (a) solar
radiation transient (2.5s/div), (b) solar radiation step down (250ms/div), (c) solar radiation step up (250ms/div).

Time [s] Time [s] Time [s]

(a) (b) (c)
Fig. 14. Dc-bus voltage vdc, iff current, idc current and PV array power Ppv for abrupt solar radiation change without FFCL (50V/div, 14A/div, 2kW/div): (a) solar
radiation transient (2.5s/div), (b) solar radiation step down (250ms/div), (c) solar radiation step up (250ms/div).
TABLE V when the PV array is connected, the PV-UPQC system injects
DC-BUS DYNAMIC COMPARISON UNDER ABRUPT SOLAR RADIATION CHANGE
around 4000 W of active power into the grid and load.
DC-bus Voltage Without FFCL With FFCL Furthermore, Fig. 15 (a) shows that the dynamic response of
Overshoot 15 % 3% the grid current is faster than that presented in Fig. 15 (b) due
Undershoot 15 % 3%
to the use of FFCL.
Setting Time 500ms 250ms
Fig. 16 (a) and (b) presents experimental results considering
the phase “a”, when load changes are performed, such as
Fig. 15 (a) and (b) presents the grid voltage ( vsa ) and grid 100 % to 0 % and 0 % to 100 %, respectively. The active
current ( isa ) at PCC 1, the load voltage ( v La ) at PCC 2, and power consumed by the load is around 1600 W, while the
produced active power is around 3750 W. As can be noted in
the PV array current ( v pv ) during abrupt solar variation Fig. 16 (a), when the load is disconnected the energy injected
considering the operation with and without FFCL action, into the grid increases. The opposite occurs when the load is
respectively. As can be noted, when the PV array is out, up to connected again, the energy injected into the grid decreases, as
30ms, the PV-UPQC performs active filtering. After that, shown in Fig. 16 (b).

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Times [s]
(a)
Times [s]
(b)
Fig. 15. Abrupt solar radiation change from OPM 1 to OPM 3 (Load 2 for
RL = 60 Ω): PV-UPQC performing active power injection plus active filtering
with Ppv > PL (200V/div, 10A/div, 10ms/div): (a) Abrupt solar variation
change with FFCL (0 % to 100 %): Phase “a” grid voltage (vsa), grid current
(isa), load voltage (vLa) and PV array current (ipv); (b) Abrupt solar variation
change without FFCL (0 % to 100 %): Phase “a” grid voltage (vsa), grid
current (isa), load voltage (vLa) and PV array current (ipv).
Time [s]
(a)
Time [s]
(b)
Fig. 16. Load changes for OPM 3 (Load 2 for RL = 60 Ω): PV-UPQC
performing active power injection plus active filtering with Ppv > PL
(100V/div, 10A/div, 10ms/div): (a) Load change (100 % to 0 %): Phase “a”
grid voltage (vsa), grid current (isa), load voltage (vLa) and load current (iLa); (b)
Load change (0 % to 100 %): Phase “a” grid voltage (vsa), grid current (isa),
load voltage (vLa) and load current (iLa).
VII. CONCLUSION
This paper proposed a single-stage 3P4W grid-tied PV
system, performing the tasks of a UPQC operating with a dual
compensating strategy, as well as the FFCL. The system
named PV-UPQC was built by means of two back-to-back
connected 3-level NPC inverters. Along with providing active
power from the PV arrangement, the PV-UPQC system was
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11
able to perform series-parallel power-line conditioning.
Thereby, both static and dynamic performances of the system
were experimentally evaluated under distorted/disturbed grid
voltage conditions, including sags, unbalances, and harmonics.
Apart from series compensation, suppression of load harmonic
currents, as well as compensation of load reactive power were
carried out, such that an effective power factor correction was
achieved. The effectiveness of the FFCL acting on the series
converter current references was properly evaluated under
sudden solar irradiation changes. The proposed PV-UPQC
system represents a promising solution to be applied to DG
systems, as well as AC microgrids.
REFERENCES
[1] J. Rocabert, A. Luna, F. Blaabjerg, and P. Rodríguez, “Control of power
converters in AC microgrids,” IEEE Trans. Power Electron., vol. 27, no.
11, pp. 4734-4749, Nov. 2012.
[2] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review of single-phase
grid-connected inverters for photovoltaic modules,” IEEE Trans. Ind.
Appl., vol. 41, no. 5, pp. 1292-1306, Sept.-Oct. 2005.
[3] W. Li, Y. Gu, H. Luo, W. Cui, X. He, and C. Xia, “Topology review and
derivation methodology of single-phase transformerless photovoltaic
inverters for leakage current suppression,” IEEE Trans. Ind. Electron.,
vol. 62, no. 7, pp. 4537-4551, Jul. 2015.
[4] L. Zhang, K. Sun, L. Feng, H. Wu, and Y. Xing, “A family of neutral
point clamped full-bridge topologies for transformerless photovoltaic
grid-tied inverters,” IEEE Trans. Power Electron., vol. 28, no. 2, pp.
730-739, Feb. 2013.
[5] F. A. S. Neves, M. Carrasco, F. Mancilla-David, G. M. S. Azevedo, and
V. S. Santos, “Unbalanced grid fault ride-through control for single-
stage photovoltaic inverters,” IEEE Trans. Power Electron., vol. 31, no.
4, pp. 3338-3347, Apr. 2016.
[6] H. Xiao, and S. Xie, “Transformerless split-inductor neutral point
clamped three-level PV grid-connected inverter,” IEEE Trans. Power
Electron., vol. 27, no. 4, pp. 1799-1808, Apr. 2012.
[7] W. Libo, Z. Zhengming, and L. Jianzheng, “A single-stage three-phase
grid-connected photovoltaic system with modified MPPT method and
reactive power compensation,” IEEE Trans. Energy Convers., vol. 22,
no. 4, pp. 881-886, Dec. 2007.
[8] M. C. Cavalcanti, A. M. Farias, K. C. Oliveira, F. A. S. Neves, and J. L.
Afonso, “Eliminating leakage currents in neutral point clamped inverters
for photovoltaic systems,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp.
435-443, Jan. 2012.
[9] Y. Tang, W. Yao, P. C. Loh, and F. Blaabjerg, “Highly reliable
transformerless photovoltaic inverters with leakage current and pulsating
power elimination,” IEEE Trans. Ind. Electron., vol. 63, no. 2, pp. 1016-
1026, Feb. 2016.
[10] Y. Kim, H. Cha, B. M. Song, and K. Y. Lee, “Design and control of a
grid-connected three-phase 3-level NPC inverter for building integrated
photovoltaic systems,” in Proc. IEEE PES Innovative Smart Grid
Technologies (ISGT), 2012, pp. 1-7.
[11] S. A. O. Silva, L. P. Sampaio, F. M. Oliveira, and F. R. Durand, “Feed-
forward DC-bus control loop applied to a single-phase grid-connected
PV system operating with PSO-based MPPT technique and active
power-line conditioning,” IET Renewable Power Generation, 2016.
[12] G. Ding, F. Gao, H. Tian, C. Ma, M. Chen, G. He, and Y. Liu,
“Adaptive DC-link voltage control of two-stage photovoltaic inverter
during low voltage ride-through operation,” IEEE Trans. Power
Electron., vol. 31, no. 6, pp. 4182-4194, Jun. 2016.
[13] S. Bacha, D. Picault, B. Burger, I. Etxeberria-Otadui, and J. Martins,
“Photovoltaics in microgrids: An overview of grid integration and
energy management aspects,” IEEE Ind. Electron. Mag., vol. 9, no. 1,
pp. 33-46, Mar. 2015.
[14] J. M. Guerrero, P. C. Loh, T. Lee, and M. Chandorkar, “Advanced
control architectures for intelligent microgrids-Part II: Power quality,
energy storage, and AC/DC microgrids,” IEEE Trans. Ind. Electron.,
vol. 60, no. 4, pp. 1263-1270, Apr. 2013.
[15] T. Wu, H. Nien, C. Shen, and T. Chen, “A single-phase inverter system
for PV power injection and active power filtering with nonlinear
inductor consideration,” IEEE Trans. Ind. Appl., vol. 41, no. 4, pp. 1075-
1083, Jul./Aug. 2005.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2659381, IEEE
Transactions on Power Electronics

TPEL-Reg-2016-10-1873.R1 12

[16] F. M. Oliveira, S. A. O. Silva, F. R. Durand, L. P. Sampaio, V. D.
Bacon, and L. B. G. Campanhol, “Grid-tied photovoltaic system based
on PSO MPPT technique with active power line conditioning,” IET
Power Electronics, vol. 9, no. 6, pp. 1180-1191, May 2016.
[17] R. A. Modesto, S. A. O. Silva, and A. A. O. Júnior, “Power quality
improvement using a dual unified power quality
conditioner/uninterruptible power supply in three-phase four-wire
systems,” IET Power Electronics, vol. 8, no. 9, pp. 1595-1605. Aug.
2015.
[18] R. A. Modesto, S. A. O. Silva, A. A. Oliveira, and V. D. Bacon, “A
versatile unified power quality conditioner applied to three-phase four-
wire distribution systems using a dual control strategy,” IEEE Trans.
Power Electron., vol. 31, no. 8, pp. 5503-5514, Aug. 2016.
[19] B. W. França, L. F. Silva, M. A. Aredes, and M. Aredes, “An improved
iUPQC controller to provide additional grid-voltage regulation as a
STATCOM,” IEEE Trans. Ind. Electron., vol. 62, no. 3, pp. 1345-1352,
Mar. 2015.
[20] V. Khadkikar, “Enhancing electric power quality using UPQC: A
comprehensive overview,” IEEE Trans. Power Electron., vol. 27, no. 5,
pp. 2284-2297, May 2012.
[21] H. Fujita, and H. Akagi, “The unified power quality conditioner: The
integration of series- and shunt-active filters,” IEEE Trans. Power
Electron., vol. 13, no. 2, pp. 315-322, Mar. 1998.
[22] M. Aredes, K. Heumann, and E. H. Watanabe, “An universal active
power line conditioner,” IEEE Trans. Power Del., vol. 13, no. 2, pp.
545-551, Apr. 1998.
[23] M. C. Cavalcanti, G. M. S. Azevedo, B. A. Amaral, F. A. S. Neves, D.
C. Moreira, and K. C. Oliveira, “A grid connected photovoltaic
generation system with compensation of current harmonics and voltage
sags,” Brazilian Power Electronics Journal, vol. 11, no. 2, pp. 93-101,
Jul. 2006.
[24] S. Devassy, and B. Singh, “Dynamic performance of solar PV integrated
UPQC-P for critical loads,” in Proc. Annual IEEE India Conference
(INDICON), 2015, pp. 1-6.
[25] B. Han, B. Bae, H. Kim, and S Baek, “Combined operation of unified
power quality conditioner with distributed generation”, IEEE Trans.
Power Del., vol. 21, no. 1, pp. 330-338, Jan. 2006.
[26] V. D. Bacon, and S. A. O. Silva, “Performance improvement of a three-
phase phase-locked-loop algorithm under utility voltage disturbances
using non-autonomous adaptive filters,” IET Power Electronics, vol. 8,
no. 11, pp. 2237-2250, Nov. 2015.
[27] S. Buso, and P. Mattavelli, Digital Control in Power Electronics.
Lincoln, NE, USA: Morgan & Claypool, 2006.
[28] L. B. G. Campanhol, S. A. O. Silva, and A. Goedtel, “Application of
shunt active power filter for harmonic reduction and reactive power
compensation in three-phase four-wire systems,” IET Power Electronics,
vol. 7, no. 11, pp. 2825-2836, Nov. 2014.
[29] B. A. Angélico, L. B. G. Campanhol, and S. A. O. Silva, “Proportional–
integral/proportional–integral–derivative tuning procedure of a single-
phase shunt active power filter using Bode diagram,” IET Power
Electronics, vol. 7, no. 10, pp. 2647-2659, Oct. 2014.
[30] K. Karanki, G. Geddada, M. K. Mishra, and B. K. Kumar, “A modified
three-phase four-wire UPQC topology with reduced dc-link voltage
rating,” IEEE Trans. Ind. Electron., vol. 60, no. 9, pp. 3555-3566,
Sept. 2013.
Professor of Electrical Engineering. His research interests are
related to power electronics applications involving UPQC
systems, active power-line filters, photovoltaic systems, power
quality and digital signal processing and applications. He is
member of Brazilian Power Electronics Society.
Sérgio A. Oliveira da Silva (M’ 13) was
born in Joaquim Távora, Brazil, in 1964.
He received the B.S. and M.S. degrees in
electrical engineering from Federal
University of Santa Catarina (UFSC),
Florianopolis, SC, Brazil, in 1987 and
1989, respectively. He received Ph.D.
degree from Federal University of Minas
Gerais (UFMG), Belo Horizonte, MG, Brazil, in 2001.
Since 1993, he has been with the Electrical Engineering
Department of Federal University of Technology (UTFPR-
CP), Cornélio Procópio, PR, Brazil, where he is currently a
full Professor of Electrical Engineering and coordinator of the
Laboratory of Power Electronics, Power Quality and
Renewable Energies. His research interests are related to
power electronics applications involving UPS systems, active
power-line filters, photovoltaic systems, control systems and
power quality. He is member of Brazilian Power Electronics
Society and IEEE Industrial Electronics Society.
Azauri Albano de Oliveira Jr. was born
in 1955. He received the B.S and M.S.
degrees in electrical/electronic
engineering from São Carlos Engineering
School (EESC), University of São Paulo
(USP), São Carlos, SP, Brazil, in 1977
and 1984, respectively. He received the
Ph.D degree in electrical engineering
from Polytechnic School, University of São Paulo, São Paulo,
SP, Brazil, in 1991.
Since 1978, he has been with the Electrical and Computing
Engineering Department, EESC, USP, where he is currently a
professor of Electrical Engineering the coordinator of the
Power Electronics and Control Laboratory. His research
interests include power electronics, electric machinery drives,
wireless power transfer and engineering education.

Vinícius Dário Bacon was born in

Leonardo Bruno Garcia Campanhol Arapongas, PR, Brazil, in 1991. He
was born in Rolândia, PR, Brazil, in received the B.S. and M.S. degrees in
1986. He received the B.S. degree in electrical engineering from Federal
industrial automation technology and the University of Technology (UTFPR-CP),
M.S. degree in electrical engineering Cornélio Procópio, PR, Brazil, in 2013
from Federal University of Technology and 2015, respectively. He is currently
(UTFPR-CP), Cornélio Procópio, PR, pursuing the Ph.D. degree in UTFPR-CP,
Brazil, in 2009 and 2012, respectively. Cornélio Procópio, PR, Brazil. Since 2016, he has been with
He is currently pursuing the Ph.D. degree in São Carlos the Electrical Engineering Department of UTFPR-CP, where
Engineering School (EESC), University of São Paulo (USP), he is currently an adjunct Professor of Electrical Engineering.
São Carlos, SP, Brazil. His present researches involve power quality, active power
Since 2013, he has been with the Electrical Engineering filters, renewable energies and digital signal processing and
Department of Federal University of Technology (UTFPR- applications. He is member of Brazilian Power Electronics
AP), Apucarana, PR, Brazil, where he is currently an associate Society.

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