This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2904045, IEEE
Transactions on Power Electronics

Three-Step Switching Frequency Selection Criteria

for Symmetrical CLLC-Type DC Transformer in
Hybrid AC/DC Microgrid
Jingjing Huang, Member, IEEE and Xin Zhang, Member, IEEE

Abstract—In hybrid AC/DC microgrid, the symmetrical VH in permitted range to guarantee BIC works well [7]-[9].
CLLC-type DC transformer (CLLC-DCT) generally operates at For DCT, it has two typical control strategies: closed-loop
the resonant frequency with the simple and low-cost semi-regulated
control and open-loop control [9]-[14]. However, microgrid
open-loop scheme to ensure the power transmission (PT). However,
more than one resonant frequency may exist and they feature applications bring two special features to DCT: a) Since PB is
different characteristics for DCT. Meanwhile, the practical already adjusted by BIC, and DC bus voltage at low voltage
resonant frequencies are varying with temperature and power, side is hold by DC sub-grid, there is no need to carry out
which will degrade the PT ability if the switching frequency additional closed-loop control for DCT; b) For hybrid AC/DC
selection is not considered. Therefore, a switching frequency microgrid, since high switching frequency is an initial
selection criteria (SFSC) approach is put forward for the requirement for DCT to improve the power density, its control
symmetrical CLLC-DCT. For convenience, the active power
transmission ratio (APTR) is employed as evaluation index of
algorithm is expected to be as simple as possible to reduce the
SFSC. First of all, the number and accurate values of resonant program execution time. Hence, the simple and low-cost 50%
frequency are achieved in Step I. Then, in Step II, the optimal duty-cycle semi-regulated (DCSR) scheme is frequently
resonant frequency is determined as APTR based criterion. In Step utilized in DCT to get rid of heavy computational load and
III, the parameter variation-based criterion is presented to extra sensors in real hybrid AC/DC microgrid application.
determine switching frequency. Finally, the experimental results
DC bus AC bus
verify that, the semi-regulated DCT based on the proposed +
Low voltage side High voltage side
+ 50Hz
S3 S1 S30 S10
approach not only improves efficiency, but also achieves the Q5 Q3 Q1
Cr1 Lr1 T Lr2 Cr2 PB
approximate PT ability with the relatively high cost closed-loop A
iCD
C
VL iAB Lm1 Lm2 VH
controlled DCT.1 PL B 1:n D
PH Q2 Q6 Q4
CLLC-HFT
Index Terms—Active power transmission ratio (APTR), DC S4 S2 S40 S20
- -
transformer (DCT), switching frequency, symmetrical S1 S2 S3 S4 S10 S20 S30 S40 Q1 Q2 Q3 Q4 Q5 Q6
Bidirectional CLLC-type DCT Driving circuit BIC Driving circuit
CLLC-type. DCSR
Controller Controller
• Ensure the PT EMS
I. INTRODUCTION • Maintain VH to guarantee BIC works well • Regulate power to track its reference
Bidirectional resonant DCT BIC

In hybrid AC/DC microgrid [13], to match voltage grade
and realize galvanic isolation, DC and AC bus are usually
connected via bidirectional interlinking converter (BIC) and
symmetrical CLLC-type DC transformer (CLLC-DCT) [4]. By
Fig. 1, BIC and DCT cooperate as below:
• The transmitted power (PB in Fig. 1) is fully-regulated by
BIC. Its reference can be dispatched by system-level energy
management system (EMS). More details can be found in [5]
and [6]. Thus, it is not repeated here.
• There are two main functions for DCT, i.e., cooperate with
BIC to ensure power transmission (PT), and keep voltage
conversion gain (VCG) to maintain the BIC input voltage
Manuscript received December 28, 2018; revised January 16, 2019;
accepted February 25, 2019. This work is supported by ACRF Tier1 Grant: RG
85/18 and the NTU Start-up Grant for Prof Zhang Xin (Corresponding author:
X. Zhang, e-mail: jackzhang@ntu.edu.sg.)
J. Huang is with the Department of Electrical Engineering, Xi’an University
of Technology, Xi’an 710048, China, and also with the School of Electrical
and Electronic Engineering, Nanyang Technological University, Singapore
639798 (e-mail: hjj7759@163.com).
X. Zhang is with the School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore 639798 (e-mail:
jackzhang@ntu.edu.sg).
Fig. 1. Topology of CLLC-DCT and BIC.
However, since DCSR scheme is essentially an open-loop
control, if CLLC-DCT is not designed very well, it cannot
always guarantee its required VCG and PT ability in practice
[8]. To settle this issue, a parameter design methodology has
been detailedly presented in [8] for DCSR controlled
CLLC-DCT to guarantee robust VCG in entire power range to
offset parameters’ variation. It is complete to ensure robust
VCG in microgrid application, and its good PT ability is
achieved by introducing the PT based constraint. However, the
robust PT ability that depends on how to select the switching
frequency fs is not discussed in depth by [8]. Therefore, the
robust PT ability of the DCSR controlled CLLC-DCT is
further analyzed in this paper:
• fs is generally selected as the resonant frequency fr for
DCSR controlled CLLC-DCT, i.e., fs=fr, to ensure the
high-power efficiency. However, there may exist more than
one fr for the CLLC-DCT. And the value of fr derived in [8]
is also not accurate enough as bidirectional magnetizing
inductances are neglected to derive the approximate PT
based constraints. Thus, the number and accurate values of fr

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Transactions on Power Electronics

should be further derived. where iin and vin respectively denote the input current and
• The CLLC-DCT presents totally different features at voltage of CLLC-HFT; Req and Xeq respectively indicate the
mismatched fs and fr. fr is changing with power and
equivalent resistance and reactance.
parameters’ variation, but fs is fixed in DCSR control. Thus,
how to select the unique fs will be analyzed to avoid • Expressions of Req and Xeq based on Fig. 2(a)
negative impacts of the power and parameters’ variation. Based on Fig. 2(a), Xeq and Req are
Therefore, a switching frequency selection criteria (SFSC) X eq ( Lr 1, Lm1, Cr 1, ) |AB
approach is put forward to ensure the robust PT ability of
s CD (4a)
3 2 6 2 4 4 2 6
CLLC-DCT, which can effectively improve the efficiency and L C (
r1 r1 1 s 2 1 s 3 1 s 1 )/( s)

4 2 2 (4b)
make DCSR controlled CLLC-DCT achieve an approximate Req (Lr 1, Lm1,C r 1, s ) |AB CD s RH Lm 1C r 1 /
closed-loop control performance. The experimental results where s is the switching angular frequency, and 2 fs ,
s
verify the effectiveness of the proposed SFSC approach. (5a)
1 1 / Lr 1C r 1
II. ADOPTED EVALUATION INDEX OF PROPOSED SFSC FOR =R 2 2 2
C +( C r 1Lr 1 2 2
C r 1Lm1 1)2 (5b)
H s r1 s s
CLLC-DCT
1 =(1 k )(1 2k ) (>0) (5c)
A. Mathematical model of CLLC-DCT 2 2 (5d)
2 (1 k )(1 / Q 1 1 k) (4k 2 k )
CLLC-DCT analysis focuses on the CLLC-type high
frequency transformer (CLLC-HFT), with the involved symbols 3 3(1 k ) 1 / Q12 (5e)
listed below: • Expressions of Req and Xeq based on Fig. 2(b)
• Magnetizing inductances: Lm1 and Lm2;
Since the mathematical model based on Fig. 2(b) is the same
• Leakage inductances: Lr1 and Lr2;
as that based on Fig. 2(a) except for Cr1, Lr1, Lm1 and Q1
• Resonant capacitances: Cr1 and Cr2;
replaced by Cr2, Lr2, Lm2 and Q2 correspondingly, it is not
• Turn ratio of transformer: n.
further discussed here.
In the symmetrical CLLC-DCT, Lr2=n2Lr1 and Cr2=Cr1/n2.
If the power is transmitted between the low voltage (LV) and B. Evaluation index of SFSC for CLLC-DCT
high voltage (HV) side of CLLC-HFT, the equivalent topology By letting Xeq=0, fs is obtained.
is shown in Fig. 2, where the “intermediate parameters” Q1, Q2 (6)
and k are expressed as: fs fr s /2 rT / 2

(1a) Here, rT denotes resonant angular frequency. If (6) is

Q n2 L /C / R
1 r1 r1 eqH
satisfied, the reactive power (defined as Q) will be zero, i.e.,
Q2 Lr 2 / C r 2 / (n 2ReqL ) (1b) (7)
P / P 2 Q 2 =1
k Lm1 / Lr 1 Lm 2 / Lr 2 (1c) where P is the active power. Once (7) is satisfied, some
where ReqH and ReqL are the equivalent resistances, and their advantages will be exhibited in CLLC-DCT:
expressions are: • The needless reactive power is avoided to decrease
withstand voltage of the extra resonant capacitors and to
ReqH vCD / iCD |LV HV 8VH2 / (π2PH ) (2a)
reduce conduction loss.
ReqL vAB / iAB |HV LV 8VL2 / (π2PL ) (2b) • Good PT ability and high efficiency can be ensured when
where PH and PL are power at HV side and LV side cooperating with BIC in microgrid application.
respectively, as shown in Fig. 1. Therefore, the active power transmission ratio (APTR) is
LV
employed as an evaluation index of SFSC. It is expressed by:
HV LV HV
Cr1 Lr1 Lr1 Cr1 C A1
Cr2 Lr2 Lr2 Cr2
A P / P 2 Q2 R / X 2 R 2 ( 1) (8)
A 1
C PTR eq eq eq
vL Lr 2 /Cr 2 vH
vC1D1 Lr1 /Cr1
vAB
-vL kLr1 Q1 Q2
kLr2
-vH
vCD The desired range of APTR is:
B B1 D *
iAB D1 iCD APTR [APTR ,1] (9)
(a) (b) *
Fig. 2. Equivalent topology of CLLC-HFT: (a) LV→HV power flow; and (b) where A mainly depends on the real system requirement.
PTR
HV→LV power flow. Hence, the evaluation of SFSC in CLLC-DCT is
A(C) summarized as: make (9) hold with maximum possibility to
iin jXeq
vin Zin Req ensure robust PT ability and settle issues resulted by the
B(D)
changing parameters and multiple fr.
Fig. 3. Equivalent impedance model of CLLC-HFT. III. PROPOSED THREE-STEP SFSC OF THE CLLC-DCT
Based on Fig. 2, the equivalent impedance model is depicted For DCSR controlled CLLC-DCT, the deviation between fr
in Fig. 3 with Zin expressed by and fs is hard to avoid for hybrid AC/DC microgrid application.
Zin vin / iin Req jXeq (3) As a result, APTR may be severely deteriorated if improper fs is

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Transactions on Power Electronics

utilized to deal with multiple fr and changing power and For case II~IV in Table I, m=1, which indicates that only
parameters. Therefore, as shown in Fig. 4, a SFSC approach is rT 1 exists to make y1=y2.
put forward for symmetrical CLLC-DCT to alleviate negative In the following, the specific values of rT in the
impacts resulted by deviation between fr and fs. aforementioned four cases will be derived.
Preliminary: analyze the resonant frequency’s number and derive its value b) Values of the resonant frequency in the CLLC-DCT
for CLLC-DCT Step I Eqn. (10) is rewritten as
3 2 2 4 6 2 (11)
Criterion to determine optimal f r according to APTR F (x ) 1x + 2 1 x + 3 1 x 1 0 , (x s)
Step II
Apparently, (11) is a typical cubic equation. Its solution can
Criterion to select fs based on parameters variation be achieved with mature approach, see for example in [15]. To
Step III
facilitate derivation process of rT , the following definitions
Fig. 4. Flowchart of the proposed approach.
are introduced:
A. Step I. Preliminary: Resonant frequency number and its A 2
2 3 1 3, B 2 3 9 1, C 2
3 3 2 (12)
value of CLLC-DCT
Δ=B2－4AC (13)
In microgrid applications, CLLC-DCT is usually operating
with open-loop as an ideal transformer to simplify the Therefore, the number and values summary of rT is given
systematic control. Therefore, the value of magnetizing in Table II.
TABLE II.
inductance is much higher than that of leakage inductance to
NUMBER AND VALUES SUMMARY OF rT
ensure the robust VCG [9]. As a result, an approximate
equation is employed in [8] by ignoring the magnetizing Case Number rT Term
inductance to derive the resonant frequency. It is appropriate to rT 1 X min 1 , rT 3 X max 1 , Δ<0
m=3
derive the PT based constraints to ensure the robust VCG [8]. I rT 2 X mid1
However, if the robust PT ability must be guaranteed, the m=2 X min 2 , X max 2 Δ=0
rT 1 rT 2
number and accurate values of fr should be derived to guide the
m=1 rT 1 X3 A=B=C=0
fs selection, as presented in this sub-section.
m=1 rT 1 X4 Δ>0
a) Resonant frequency number of the CLLC-DCT
II~IV m=1 X4 Δ>0
Based on (7), the maximum APTR in (8) is obtained via rT 1

(10a) Note: ( X min 1 , X max 1 , X mid 1 ), ( X min 2 , X max 2 ), X 3 and

Xeq (Lr 1, Lm1,C r 1, s ) |AB CD F ( s ) y1 y2 0
X 4 can be achieved by (A1), (A5), (A7) and (A8) of Appendix respectively.
where
y1 1
4
s 2
2
1
2
s 3
4
1
(10b) B. Step II. APTR based criterion of CLLC-DCT
6 2 (10c) Based on (4) and (8), APTR is derived as
y2 1 / s

Eqn. (10) is ensured by (6), which means s rT is APTR Req / Xeq 2 Req 2 (14a)
guaranteed by y1=y2. Since σ1>0 according to 5(c), four cases 2 3 5 2 4
1/ Q ( 1 1 2 / 3 / 1/ ) /k 1
are available based on plus-minus signs of σ2 and σ3, as given
in Table I, where m indicates the number of either fr or rT . / 1 s
(14b)
TABLE I. Therefore, the determination of optimum rT is transformed
FOUR CASES TO OBTAIN y1=y2 to determine optimum (i.e., m ) from possible rT of
CASE σ2≤0 σ2>0 Table II. m can be written by
y y1c y1b y1a y (15)
Case I Case III m rT / 1
m=3 @ y =y y1
σ3≥0 y2 m=2 @ y1=y1a m=1 As a result, the APTR based criterion is converted to find
1 1b y2
m=1 @ y1=y1c
0 s
2
0 2
rT 1
2
s m to make (9) hold with maximum probability (i.e., maximum
y y shadow area of Fig. 5 or widest variable range of m ).
y1 Case II Case IV
y1 1 1
σ3<0 m=1 m=1
y2 0 y2 *
APTR *
2 2 APTR
0 2 2
APTR

APTR

rT 1 s rT 1 s

For case I in Table I, the value of m involves three 0 0

0 m 0 m
conditions to make y1=y2: (a) (b)
• m=3 @ y1=y1a. It indicates there exists three resonant angular Fig. 5. Schematic of APTR based criterion regarding shadow area: (a)
frequencies recommended as m ; (b) not recommended as m .
rT 1 , rT 2 and rT 3 , which satisfy
rT 1 rT 2 rT 3 . By (15), the waveforms of APTR vs are depicted in Fig. 6.
• m=2 @ y1=y1b, which denotes rT 1 and rT 2 are Apparently, the maximum rT , i.e., 3 of Fig.6(a), 2 of
available, and rT 1 rT 2 . Fig.6(b), and 1 of Fig.6(c) can guarantee maximum
• m=1 @ y1=y1c, which means only rT 1 exists. probability to satisfy (9), as given in Table III.

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It is concluded that, the maximum rT is selected as the m

optimum one to achieve maximum probability with 1
*
APTR [APTR ,1] . This is the APTR based criterion. 0.5
1 1 1 Q1(Q2)
*
A PTR
*
APTR
*
APTR 0
0 0.5 1

APTR
APTR

APTR
0.5 0.5 0.5
Fig. 7. Characteristic of m vs Q1(Q2).
2
0 0 0 1 The curves of APTR vs under different power (i.e.,
1 3 1 2
(a) (b) (c) Q1(Q2)) are illustrated in Fig. 8, where the shadow zone
Fig. 6. APTR vs : (a) m=3; (b) m=2; (c) m=1. *
satisfies APTR [APTR ,1] for three curves. It can be observed
*
C. Step III. Parameter variation-based criterion of from Fig. 8 that no shadow zone that satisfies APTR [APTR ,1]
CLLC-DCT for three curves will exist when mD or max ; and
The m derived by the criterion in Section III-B relies on only when min , the value of APTR will locate within
the parameters Lx, Cx, and ReqH(ReqL) (i.e., Q1(Q2) based on *
[APTR ,1] with maximum probability under the decreasing
(1)); and Lx denotes Lr1, Lr2, Lm1 and Lm2; Cx indicates Cr1 and Q1(Q2). Therefore, min is selected.
Cr2. Consequently, the impacts on m resulted by resonant
parameters’ variation and changing power are analyzed below. APTR Q1(Q2)↓
1
a) Impact on m induced by variation of resonant parameters
*
(i.e., Lx and Cx) APTR

Practically, the actual values of Lx and Cx are varying with

0
temperature, operation power, etc [8]. For simplicity, the min mD max

variation ranges of Lx and Cx are defined as: Fig. 8. APTR vs with various Q1(Q2).
LxA [(1 %)LxD , (1 %)LxD ] (16a)
In summary, the criterion based on parameter variation is
C xA [(1 %)C xD , (1 %)C xD ] (16b) (19)
s min 1D (1 %)(1 %) rT
where LxD and CxD are the respective designed value of Lx and where is achieved by (17a), and is the designed
min 1D
Cx; % and % are variable ranges of Lx and Cx respectively; value of from Step II.
1
LxA and CxA are the respective actual value of Lx and Cx.
According to (5a) and (15), the actual m is changing within D. Design example
[ min , max ]. Therefore, the value of min and max can be Table IV presents the same specification of the CLLC-DCT
achieved by as [8], where k=25, and Q1∈ [0, 1.786]. Since the converter
(17a) operates with the changing power, there is deviation of the
(1 %)(1 min%) mD
components from their nominal values. In [8], after testing its
(1 %)(1 %) (17b) actual inductors and capacitors offline under different
max mD
temperatures, the real % and % are 4%; thus, this example
where
(18) selects 4% for % and % for a fair comparison. Please note
LxDC xD
mD rT that % and % can be any values in practice due to the
rT is determined by Table III. changing of the resonant components’ structure, materials, etc.
TABLE III.
TABLE IV.
ARRANGEMENT OF m AND CORRESPONDING rT SPECIFICATIONS OF CLLC-DCT IN [8]
Number Optimum m rT Items Lr1 Lr2 Lm1 Lm2 Rated power n VL(VH) Cr1 Cr2
m=1 m 1 of Fig.6(c) rT = rT 1 Values 56µH 223µH 1.4mH 5.6mH 6kW 2 380(760)V 45nF 11nF

m=2 m 2 of Fig.6(b) rT = rT 2

m=3 of Fig.6(a) =
To make the proposed three-step SFSC approach more
m 3 rT rT 3
accessible, a realization flowchart is summarized in Fig. 9.
Note: rT 1 , rT 2 and rT 3 are given in Table II. According to the proposed selection principle, the fs can be
b) Impact on m induced by power variation (i.e., Q1 and Q2) confirmed in the following steps.
Step I: Based on Table II and (6), the number and value of fr are
Fig. 7 illustrates the characteristics of m vs Q1(Q2). By
achieved: m=3; and
(15), m is regarded as the normalized value of the optimal
• fr 1 rT 1 / (2 ) 14 kHz ;
rT . Meanwhile, Q1(Q2) is increasing with PB. As a result, Fig.
• fr 2 rT 2 / (2 ) 19.6 kHz ;
7 also explains the relationship between rT and PB. Besides,
• fr 3 rT 3 / (2 ) 99.75 kHz .
the maximum rT is obtained at the rated power, and the
An interesting result can be obtained from Step I: all the
optimum rT is proportional to PB till it reaches a constant.
values of fr are in the reasonable value range (larger than 10

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Transactions on Power Electronics

kHz) for the DCT application. All of them can be selected as when the proposed SFSC based CLLC-DCT cooperates with
the switching frequency in the traditional case. Therefore, the BIC, as shown in Fig. 10(f). The transient procedure is
purposes of the next two steps are to find the most suitable effectively completed within 10ms.
fr for the fs selection to deal with the parameters’ variation and To verify the superiority of the proposed approach at
ensure the load robustness. light-load mode (1kW), its reduced loss ratio is summarized in
Step II: To cope with the parameters’ variation, the maximum Fig. 11, and it is calculated by:
value of rT according to Table III is selected: Loss in [8] Loss in proposed SFSC
Re duced loss ratio .
• rT rT 3 , i.e., fr fr 3 99.75 kHz . Loss in [8]
Step III: To ensure the load robustness, the fs is confirmed It can be observed from Fig. 11 that compared to the loss in
based on (19): [8], the copper loss of transformer is reduced by 20%. Besides,
• fs 95.76 kHz . the others involving the line loss, driver loss, etc. are reduced
In summary, the proposed three-step SFSC not only can be by more than 70% due to the reduced current amplitude in the
utilized to improve the approach in [8], but also can be proposed SFSC. These comparisons verify the superiority of
regarded as a general approach to ensure the robust PT ability the proposed SFSC at the light-load mode. The detailed loss
with the known actual specifications. Besides, each kind of breakdown will be analyzed in subsequent section.
resonant component is recommended to select the same structure
and material to make proposed SFSC easily implement in more Proposed SFSC Approach in [8]
resonant DCTs with only one selected fs.

vin[300V/div]

vin[300V/div]

iin[15A/div]
Known specifications and resonant parameters

iin[15A/div]
C2
(e.g. Table IV)
C2
iin C3
iin
C3

• Achieve the intermediate parameters based on (1) and (2) vin vin
• Impedance model Zeq=Req+jXeq based on (3) ~ (5)
• Evaluation index based on (6)~(9) Time[2µs/div] Time[2µs/div]
Xeq=0
Step I (a) (b)
• Obtain the number of fr based on (10)
• Derive the accurate value of fr based on (11)~(13)
• Summarize accurate values and number of fr in Table II Proposed SFSC Approach in [8]

vin[300V/div]
Step II
vin[300V/div]

• Determine the optimum fr based on (14) and (15)

• Summarize the optimum fr in Table III

iin[15A/div]
C2 C2

iin[15A/div]
Step III C3 iin C3 iin
• Confirm the possible variation range of the optimum fr based on (16)~(18)
• Determine fs to ensure the desired APTR with maximum probability based on (19) vin vin
Fig. 9. Realization flowchart of the proposed approach. Time[2µs/div] Time[2µs/div]
(c) (d)
IV. EXPERIMENTAL VERIFICATION
1 AC voltage of BIC [300V/div]

According to Section III-D, a prototype as shown in Fig. 1 Closed-loop control

0.98
C2
Efficiency

has been developed with the specifications shown in Table IV. C1

0.96
A. Characteristic comparisons 0.94
Proposed SFSC AC current of BIC [10A/div]
Fig. 10(a)~(d) depict waveforms of vin and iin by the Approach in [8] C3
0.92 PB [2kW/div]
proposed SFSC and the approach in [8] at HV→LV power 0 1 2 3 4 5 6
flow. Apparently, the phase deviation of vin and iin is basically PB (kW) Time [100ms/div]
maintained at zero under either half-load or full-load mode. (e) (f)
However, the waveform of vin is better at zero point of iin in the Fig. 10. Waveforms of vin and iin at half-load mode in (a) and (b), and at
proposed SFSC than that in [8], as shown in the enlarged part full-load mode in (c) and (d). (e) Efficiency comparison when power flows
of Fig. 10(a) and (b). In practice, the copper loss of transformer from HV to LV side. (f) Bidirectional power transient of BIC and CLLC-DCT.
is proportional to the transmitted power while its core loss is 71%
Reduced loss ratio (%)

relatively stable in entire power range. Therefore, the 41.6%

efficiency exhibits the features shown in Fig. 10(e), where the 20%
8.6%
proposed SFSC designed based on the robust PT requirement -

er r s
ensures better efficiency than the approach in [8], especially e -
C T ito er
o pp or Si FE ac th
C O
C S ap
under the light-load mode. This also explains why Fig. 10(a) is M
O C

better than Fig. 10(b). Meanwhile, the proposed SFSC utilizing
the simple and low-cost DCSR control can ensure similar
efficiency as that adopting the closed-loop control, as
summarized in Fig. 10(e). When power is transferred from LV
to HV side, the similar results can be achieved.
The bidirectional power switching can also be guaranteed
Fig. 11. Reduced loss ratio at the light-load mode.
B. Verification of DC voltage characteristics
To verify the DC voltage characteristics in full power range,
the experimental tests have been carried out, as given in Fig.
12. The HFT input voltage and current, DC voltage and

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Transactions on Power Electronics

transmitted power are shown in Fig. 12(a) and (b), where the resonant current and driver voltage. It can be observed that the
power factor is close to 1 in full power range, effectively SiC-MOSFET is turned on and off when the resonant current is
reducing the conduction loss. Besides, the DC voltage is close to zero. Subsequently, the loss breakdown is detailedly
basically maintained at the same value in full power range. The illustrated in Fig. 13(b) and (c), where the main losses are from
transient characteristic from full-load to half-load mode is also SiC-MOSFET and copper. It is noteworthy the copper loss
measured, as given in Fig. 12(c), where the transient settling largely relies on the transformer design and power rating. For
time of power is less than 0.5ms while DC voltage is stable. SiC-MOSFET, since its switching loss is close to zero based
These results verify the proposed SFSC can guarantee the on Fig. 13(a), its loss mainly stems from conduction loss,
power factor and then improve the efficiency. The stable DC which depends on the device itself. Therefore, the DCT with
voltage under both steady and transient states also shows the proposed SFSC approach can ensure satisfactory efficiency.
correctness of the proposed SFSC.
V. CONCLUSION
Power [1.5kW/div]

Power [500kW/div] HFT input voltage [400V/div] A SFSC approach has been put forward in this paper for
HFT input voltage [400V/div]
C4
CLLC-DCT. With SFSC-selected constant switching
C1 C1
C3 C3 frequency, CLLC-DCT under the simple and low-cost DCSR
HFT input current [10A/div] C4 HFT input current [20A/div]
control can achieve approximately the same performance with
C2 DC voltage [400V/div] C2 DC voltage [400V/div] that under the complex and costly closed-loop control in the
Time[2μs/div] Time[2μs/div] microgrid application. In addition, adopting the proposed
(a) (b) SFSC, DCSR controlled CLLC-DCT can ensure the allowable
Power [4kW/div]
C4
HFT input voltage [400V/div] APTR with maximum probability to achieve the robust PT
C1
C3
ability against the resonant parameters’ variation in practice.
The experimental results verify the effectiveness of the
C2 DC voltage [400V/div] HFT input current [10A/div]
Time[500μs/div] proposed frequency selection approach. It is noteworthy that
Z4
for the DCSR controlled CLLC-DCT, the optimal APTR is
Z1
hardly guaranteed in face of the variations of the power and
Z3
resonant components, especially when considering the other
Z2 Time[20μs/div] performance, e.g., VCG. Therefore, only robust PT ability is
(c) considered in this paper.
Fig. 12. Waveforms of HFT input voltage and input current, transmitted
power and DC voltage (a) at 450W; (b) at 5.6kW. (c) Transient characteristic APPENDIX
from full-load to half-load mode.

C. Power loss analysis X min 1 = min(x 11, x 21, x 31 )

(A1)
To analyze the DCT loss with proposed SFSC approach, the X max 1 = max(x 11, x 21, x 31 )
loss waveforms at the rated power are given in Fig. 13. X mid 1 =x 11 x 21 x 31 X min 1 X max 1
Driver voltage [20V/div] where
2 (A2)
x 11 1 [ 2 2 A cos( / 3)] / (3 1 )
C1
C2
2
C3
x 21,31 1 { 2 A[cos( / 3) 3 sin( / 3)]} / (3 1 ) (A3)
SiC-MOSFET voltage[150V/div]
arccosT, 1<T<1 and
Resonant current [12A/div] (A4)
Time[2μs/div] 2
T=0.5(2A 2 1 3 1B ) / A3
(a)
120
Others X min 2 = min(x 12 , x 22 , x 32 ) (A5)
105.9
98.4 Capacitor 2.4%
3% X max 2 = max(x 12 , x 22 , x 32 )
Power loss(W)

80

SiC- Copper where

40 MOSFET 44%
2
8.4 6.2 5.3
47.2% x12 ( 2 / 1 B / A) 1 ,
0
2
(A6)
x 22 x 32 B / (2A)
ET
r

r
e
pe

1
to
or

rs
SF
op

e
C

ac

th
C

ap

O
-M

2 2 2 (A7)
C

Core
X3 / (3 1 ) / 3 /
C
Si

4% 2 1 3 1 2 1 3
1/3 1/3 2 (A8)
(b) (c) X 4 =( 2 Y 1 Y 2 ) 1 / (3 1 )
Fig. 13. Losses at rated power. (a) waveforms of SiC-MOSFET voltage, where
resonant current and driver voltage. (b) power loss (W); (c) power loss ratio.
Y1,2 A 2 3 1 B B2 4AC / 2 (A9)
Fig. 13(a) shows the waveforms of SiC-MOSFET voltage,

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2904045, IEEE
Transactions on Power Electronics

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