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FEATURES SUMMARY
This device is now designated as “Not for New De- Figure 1. Packages
sign”. Please use the M25P05-A in all future de-
signs (as described in application note AN1511).
■ 512 Kbit of Flash Memory
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SUMMARY DESCRIPTION
The M25P05 is a 512 Kbit (64K x 8) Serial Flash Figure 3. SO Connections
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 128 bytes at
a time, using the Page Program instruction.
The memory is organized as 2 sectors, each con- M25P05
taining 256 pages. Each page is 128 bytes wide.
Thus, the whole memory can be viewed as con-
S 1 8 VCC
sisting of 512 pages, or 65536 bytes.
Q 2 7 HOLD
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the W 3 6 C
Sector Erase instruction. VSS 4 5 D
AI04038
VCC
D Q
S M25P05
HOLD
VSS
AI04037
S Chip Select
W Write Protect
HOLD Hold
VSS Ground
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M25P05
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is (this is not the Deep Power-down mode). Driving
used to transfer data serially out of the device. Chip Select (S) Low enables the device, placing it
Data is shifted out on the falling edge of Serial in the active power mode.
Clock (C). After Power-up, a falling edge on Chip Select (S)
Serial Data Input (D). This input signal is used to is required prior to the start of any instruction.
transfer data serially into the device. It receives in- Hold (HOLD). The Hold (HOLD) signal is used to
structions, addresses, and the data to be pro- pause any serial communications with the device
grammed. Values are latched on the rising edge of without deselecting the device.
Serial Clock (C).
During the Hold condition, the Serial Data Output
Serial Clock (C). This input signal provides the (Q) is high impedance, and Serial Data Input (D)
timing of the serial interface. Instructions, address- and Serial Clock (C) are Don’t Care.
es, or data present at Serial Data Input (D) are
To start the Hold condition, the device must be se-
latched on the rising edge of Serial Clock (C). Data
lected, with Chip Select (S) driven Low.
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C). Write Protect (W). The main purpose of this in-
Chip Select (S). When this input signal is High, put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
the device is deselected and Serial Data Output
instructions (as specified by the values in the BP1
(Q) is at high impedance. Unless an internal Pro-
and BP0 bits of the Status Register).
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
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M25P05
SPI MODES
These devices can be driven by a microcontroller is available from the falling edge of Serial Clock
with its SPI peripheral running in either of the two (C).
following modes: The difference between the two modes, as shown
– CPOL=0, CPHA=0 in Figure 5, is the clock polarity when the bus mas-
– CPOL=1, CPHA=1 ter is in Stand-by mode and not transferring data:
For these two modes, input data is latched in on – C remains at 0 for (CPOL=0, CPHA=0)
the rising edge of Serial Clock (C), and output data – C remains at 1 for (CPOL=1, CPHA=1)
SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK
C Q D C Q D C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory SPI Memory SPI Memory
Device Device Device
AI03746C
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
CPOL CPHA
0 0 C
1 1 C
D or Q MSB LSB
AI01438
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M25P05
OPERATING FEATURES
Erase, Write Status Register). The device then
Page Programming goes in to the Stand-by Power mode. The device
To program one data byte, two instructions are re- consumption drops to I CC1.
quired: Write Enable (WREN), which is one byte, The Deep Power-down mode is entered when the
and a Page Program (PP) sequence, which con- specific instruction (the Enter Deep Power-down
sists of four bytes plus data. This is followed by the Mode (DP) instruction) is executed. The device
internal Program cycle (of duration tPP). consumption drops further to ICC2. The device re-
To spread this overhead, the Page Program (PP) mains in this mode until another specific instruc-
instruction allows up to 128 bytes to be pro- tion (the Release from Deep Power-down Mode
grammed at a time (changing bits from 1 to 0), pro- and Read Electronic Signature (RES) instruction)
vided that they lie in consecutive addresses on the is executed.
same page of memory. All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
Sector Erase and Bulk Erase used as an extra software protection mechanism,
The Page Program (PP) instruction allows bits to when the device is not in active use, to protect the
be reset from 1 to 0. Before this can be applied, the device from inadvertant Write, Program or Erase
bytes of memory need to have been erased to all instructions.
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk Status Register
Erase (BE) instruction. The Status Register contains a number of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instruc-
Polling During a Write, Program or Erase Cycle tions.
A further improvement in the time to Write Status WIP bit. The Write In Progress (WIP) bit indicates
Register (WRSR), Program (PP) or Erase (SE or whether the memory is busy with a Write Status
BE) can be achieved by not waiting for the worst Register, Program or Erase cycle.
case delay (tW, tPP, tSE, or tBE). The Write In WEL bit. The Write Enable Latch (WEL) bit indi-
Progress (WIP) bit is provided in the Status Regis- cates the status of the internal Write Enable Latch.
ter so that the application program can monitor its
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
value, polling it to establish when the previous are non-volatile. They define the size of the area to
Write cycle, Program cycle or Erase cycle is com-
be software protected against Program and Erase
plete.
instructions.
SRWD bit. The Status Register Write Disable
Active Power, Stand-by Power and Deep (SRWD) bit is operated in conjunction with the
Power-Down Modes Write Protect (W) signal. The Status Register
When Chip Select (S) is Low, the device is en- Write Disable (SRWD) bit and Write Protect (W)
abled, and in the Active Power mode. signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
When Chip Select (S) is High, the device is dis- of the Status Register (SRWD, BP1, BP0) become
abled, but could remain in the Active Power mode read-only bits.
until all internal cycles have completed (Program,
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M25P05
HOLD
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M25P05
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M25P05
MEMORY ORGANIZATION
The memory is organized as: or Bulk Erasable (bits are erased from 0 to 1) but
■ 65536 bytes (8 bits each) not Page Erasable.
■ 2 sectors (256 Kbits, 32768 bytes each)
Table 3. Memory Organization
■ 512 pages (128 bytes each).
Sector Address Range
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector 1 08000h 0FFFFh
0 00000h 07FFFh
HOLD
High Voltage
W Control Logic Generator
S
D
I/O Shift Register
Q
0FFFFh
Y Decoder
08000h
00000h 0007Fh
128 Bytes (Page Size)
X Decoder
AI04039
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M25P05
INSTRUCTIONS
All instructions, addresses and data are shifted in At the end of a Page Program (PP), Sector Erase
and out of the device, most significant bit first. (SE), Bulk Erase (BE) or Write Status Register
Serial Data Input (D) is sampled on the first rising (WRSR) instruction, Chip Select (S) must be driv-
edge of Serial Clock (C) after Chip Select (S) is en High exactly at a byte boundary, otherwise the
driven Low. Then, the one-byte instruction code instruction is rejected, and is not executed. That is,
must be shifted in to the device, most significant bit Chip Select (S) must driven High when the number
first, on Serial Data Input (D), each bit being of clock pulses after Chip Select (S) being driven
latched on the rising edges of Serial Clock (C). Low is an exact multiple of eight.
The instruction set is listed in Table 4. All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Depending on the instruction, the one-byte in- Erase cycle are ignored, and the internal Write
struction code is followed by address bytes, or by
Status Register cycle, Program cycle or Erase cy-
data bytes, or by both or none. Chip Select (S)
cle continues unaffected.
must be driven High after the last bit of the instruc-
tion sequence has been shifted in.
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M25P05
0 1 2 3 4 5 6 7
Instruction
High Impedance
Q
AI02281D
0 1 2 3 4 5 6 7
Instruction
High Impedance
Q
AI03750C
– Power-up
Write Disable (WRDI) – Write Disable (WRDI) instruction completion
The Write Disable (WRDI) instruction (Figure 9) – Write Status Register (WRSR) instruction com-
resets the Write Enable Latch (WEL) bit. pletion
The Write Disable (WRDI) instruction is entered by – Page Program (PP) instruction completion
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High. – Sector Erase (SE) instruction completion
The Write Enable Latch (WEL) bit is reset under – Bulk Erase (BE) instruction completion
the following conditions:
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M25P05
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
MSB MSB
AI02031C
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M25P05
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction Status
Register In
D 7 6 5 4 3 2 1 0
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M25P05
1 0 Status Register is
Writable (if the WREN
0 0 Software instruction has set the Protected against Page Ready to accept Page
Protected WEL bit) Program and Sector Program and Sector
(SPM) The values in the BP1 Erase Erase instructions
1 1 and BP0 bits can be
changed
Status Register is
Hardware Hardware write protected Protected against Page Ready to accept Page
0 1 Protected The values in the BP1 Program and Sector Program and Sector
(HPM) and BP0 bits cannot be Erase Erase instructions
changed
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
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M25P05
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB
AI03748C
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M25P05
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
1055
1050
1054
1049
1052
1053
1051
1048
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
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M25P05
0 1 2 3 4 5 6 7 8 9 29 30 31
D 23 22 2 1 0
MSB
AI03751C
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M25P05
0 1 2 3 4 5 6 7
Instruction
AI03752C
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M25P05
0 1 2 3 4 5 6 7 tDP
Instruction
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M25P05
Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Sequence
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D 23 22 21 3 2 1 0
MSB
Electronic Signature Out
High Impedance
Q 7 6 5 4 3 2 1 0
MSB
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M25P05
0 1 2 3 4 5 6 7 tRES
Instruction
High Impedance
Q
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M25P05
VCC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
tPUW
time AI04009B
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M25P05
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M25P05
MAXIMUM RATING
Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con-
Absolute Maximum Ratings" table may cause per- ditions for extended periods may affect device
manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics
ratings only and operation of the device at these or SURE Program and other relevant quality docu-
any other conditions above those indicated in the ments.
Operating sections of this specification is not im-
VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
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M25P05
DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.
CL Load Capacitance 30 pF
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825
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M25P05
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M25P05
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M25P05
tSHSL
tDVCH tCHCL
tCHDX tCLCH
D MSB IN LSB IN
High Impedance
Q
AI01447C
tHLCH
tCHHL tHHCH
tCHHH
tHLQZ tHHQX
HOLD
AI02032
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M25P05
tCH
tCLQX
Q LSB OUT
tQLQH
tQHQL
D ADDR.LSB IN
AI01449C
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M25P05
PACKAGE MECHANICAL
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
h x 45˚
A
C
B
e CP
E H
1
A1 α L
SO-a
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
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CP 0.10 0.004
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M25P05
PART NUMBERING
Example: M25P05 – V MN 6 T
Device Type
M25P
Device Function
05 = 512 Kbit (64K x 8)
Operating Voltage
V = VCC = 2.7 to 3.6V
Package
MN = SO8 (150 mil width)
Temperature Range
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
For a list of available options (speed, package, device, please contact your nearest ST Sales Of-
etc.) or for further information on any aspect of this fice.
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M25P05
REVISION HISTORY
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M25P05
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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