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06 VLSI Design Styles PDF
06 VLSI Design Styles PDF
1
VLSI Design Cycle
Chip
1. System specification
2. Functional design
3. Logic design
4. Circuit design
5. Physical design
6. Design verification
7. Fabrication
8. Packaging, testing, and debugging
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Physical Design
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n-channel Transistor
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n-channel Transistor Layout
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5
Fabrication Layers
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12
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Summary of VLSI Layers
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VLSI Fabrication
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7
Silicon Wafer
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Types of Fabrication Errors
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Poly-Diffusion Interaction
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Contacts
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10
Contact Spacing
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M2 Contact (Via)
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CMOS Layout Example
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Stick Diagrams
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12
Static CMOS Inverter
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Static CMOS NOR Gate
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Simple Static CMOS Design
Example
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VLSI Design Styles
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Introduction
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Switch
Matrix
D Q
Output Pad
Buffer
Input
CLB CLB Buffer
Q D Delay
Programmable
Interconnect I/O Blocks (IOBs)
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
G4 DIN
G3 G F'
SD
G2 Func. G' D Q
Gen. H'
G1
EC
RD
1
H G'
Y
Func. H'
S/R
F4 Gen. Control
F3 F
Func. DIN
SD
F2 Gen.
F'
G' D Q
F1 H'
EC
RD
1
H'
F'
X
K
Configurable
Logic Blocks (CLBs) 34
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XC4000E Configurable Logic Blocks
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
G4 DIN
SD
G3 G F'
G' D Q YQ
G2 Func. H'
Gen.
G1 EC
RD
1
H G'
H'
Y
Func. S/R
Gen. Control
F4
F3 F DIN
SD
Func. F'
Q XQ
F2 Gen. G'
D
H'
F1
EC
RD
1
H'
X
F'
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CLB Functionalities
• Two Registers
– Each can be configured as flip-flop or latch.
– Independent clock polarity.
– Synchronous and asynchronous Set / Reset.
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Look Up Tables
• Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB
Look Up Table
• Example: 4-bit address
Combinatorial Logic
A B C D Z
A
B 0 0 0 0 0
Z 0 0 0 1 0
C 0 0 1 0 0
D
0 0 1 1 1
0 1 0 0 1
Capacity is limited by number of 0 1 0 1 1
inputs, not complexity . . .
Choose to use each function 1 1 0 0 0
generator as 4 input logic (LUT) or 1 1 0 1 0
WE as high speed sync.dual port 1 1 1 0 0
G4 RAM 1 1 1 1 1
G3 G
G2 Func.
Gen.
G1
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Xilinx FPGA Routing
CLB CLB
Switch Switch
Matrix Matrix
CLB CLB
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Gate Array
Introduction
• In view of the fast prototyping capability, the gate array (GA)
comes after the FPGA.
– Design implementation of
• FPGA chip is done with user programming,
• Gate array is done with metal mask design and processing.
• Gate array implementation requires a two-step manufacturing
process:
a) The first phase, which is based on generic (standard) masks,
results in an array of uncommitted transistors on each GA chip.
b) These uncommitted chips can be customized later, which is
completed by defining the metal interconnects between the
transistors of the array.
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• The GA chip utilization factor is higher than that of
FPGA.
– The used chip area divided by the total chip area.
• Chip speed is also higher.
– More customized design can be achieved with metal mask
designs.
• Current gate array chips can implement as many as
hundreds of thousands of logic gates.
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Introduction
• One of the most prevalent custom design styles.
– Also called semi-custom design style.
– Requires developing full custom mask set.
• Basic idea:
– All of the commonly used logic cells are developed,
characterized, and stored in a standard cell library.
– A typical library may contain a few hundred cells.
• Inverters, NAND gates, NOR gates, complex AOI, OAI
gates, D-latches, and flip-flops.
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Standard Cells
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Floorplan for Standard Cell Design
• Inside the I/O frame which is reserved for I/O cells,
the chip area contains rows or columns of standard
cells.
– Between cell rows are channels for dedicated inter-cell
routing.
– Over-the-cell routing is also possible.
• The physical design and layout of logic cells ensure
that
– When placed into rows, their heights match.
– Neighboring cells can be abutted side-by-side, which
provides natural connections for power and ground lines in
each row.
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Full Custom Design
Introduction
• The standard-cells based design is often called semi
custom design.
– The cells are pre-designed for general use and the same
cells are utilized in many different chip designs.
• In the full custom design, the entire mask design is
done anew without use of any library.
– The development cost of such a design style is
prohibitively high.
– The concept of design reuse is becoming popular to reduce
design cycle time and cost.
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Contd.
• The most rigorous full custom design can be the
design of a memory cell.
– Static or dynamic.
– Since the same layout design is replicated, there would not
be any alternative to high density memory chip design.
• For logic chip design, a good compromise can be
achieved by using a combination of different design
styles on the same chip.
– Standard cells, data-path cells and PLAs.
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Comparison Among Various Design Styles
Design Style
FPGA Gate array Standard Full
cell custom
Cell size Fixed Fixed Fixed Variable
height
Cell type Programm Fixed Variable Variable
able
Cell placement Fixed Fixed In row Variable
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