Inputs Outputs

A B
Difference Borrow
0 0 0 0
0 1 1 1
1 0 1
1 1 0 0

Difference =AB +A B A B
Borrow AB

Full subtractor
bitsafa
combinational circuit gnor full subtractor gygu. i A,
B, BorroW 5u epsogi inputseh Difference Lobnud
Borrowut 5u gT600T Outputsa5h 2siT6IT6OT. 56T truth
table umgh logic diagramgs6m5 LIL`Bsù 8T600T6UITL. A unpmiuh
B
9 inputsh registerssfisi GLSI G.
Borrow 6T60 input pim5u 6îs560a (GbSI 6uGLD. QZI
Difference nmmu Borrowut L u gTs00T outputssmoT
2GUTGh(G.

A Difference
B
Borrown FS
Borrowu (Bu
(B)
Logic symbol
Borrown
D Difference (D)
(B) HS2
A D. Bou2
HS1
B
YB Constructions of full adder
Borrow (B)
Using half subtractors

1.51
 Outputs

Barrow,|D
Diif
ffe r e n c eBorrow
Difference Borrow
Inputs

(B
(B)

1
1
0 0
1
0
1 0
1

BorrOw
using
USing kkm
k-ma
and
D i f f e r e n c e

for
E x p r e s s i o n

Truth tableghig G h AB 00 01 11 10

AB
B 0
10
B
00 0 1 11
1
o
o o1 0
K-map for B,
K-map for Difference

+ ABB,, + ABB,
AB B + ABB,
Sum + BB,)
+ BB) + A(BB,
=
A(BB
+ A(B® B)
A(B B)
X
Consider B B =

AX
Difference A X+ B D B,)
= A X (Re place X by
Difference A B® B,
B= B + A B + B Bn

Realisation of full-subtractor
1.52
 Magnitude comparator
A ongub B 6 u gnsnot (6) s61606 6h6fl60r s160TLDL60L
pin. A=B, A<B, A>B , l u outputssfl 67Gg5ggD
armp a nh(id 9U combinational circuit gsrsr
magnitude comparator Gn. Single bit magnitude
comparatorglsor block diagramg6ng uLSsb sT60TAUm

A A>B
Single bit
Magnitude A=B
B A<B
comparator
Magnitude comparatorg implement Gauu, NOR
g AND gatesmeT uw60T LIGIGoTLD. Single bit
magnitude comparatorglr logical structure upmh truth
tableguLZdsT6TOomLD.
AB_A > B

A
-A =B
B

A <B
A B A>BA=B A<B
00 0 1 0
0 1 0 0 1
1 0 1 0
1 1 0

Truth table ga Pabsh

AB+AB = 1
IfA B then,
AB = 1

check usoT6o0T EX-NOR

6T60T6o, A=B 6160T) conditiong
gateg uu6TLIGI`GI6 Gpmb.
1.53
IfA> B then AB = 1&
For A<B, A B = 11 For that we use AND gate te
the required function. o get
Hazards and Races
9combinational circuitr LpvLD
auIT
propagation delayufsaTTsn 67DuGih Gz6moulsuau unequ
transi
ysDSUSI glitch s hazard ajgh. gT600T(6) 16n6uIT60T h-
6TT 6T 60 hazar
a. Static hazard
b. Dynamic hazard

Sequential circuitglsv shuGh hazard, essent

hazard YGh.
Static hazard
Input@s 6T uGuh Lorppo, Gsu GpT65
outputg urppgm5 STDuD$SIU.
change in input
input.

Output
Momentary output
change

Redundant
groupingglor eLpavLh adjacent cell
cover useot sgsus5sot
eypoun static hazardp
Dynamic hazard
f6som).
Outputs60T51 0sis (,L5I 16GsT g60gI 1g
0a16Gs LoTmÚuLLT), Circuit
glitcha 2TGD. 60EI 260TmIsGD \a
guuluLL uA glitchssT9
dynamic hazard ss0rLuGLh. 9-502/T

epen adjacent cellssmor 9 redundant group

hazardgsaama. cover usaTs80jaug60T eLpoDLD
yna

1.54
 input

Dynamic Hazard

Essential hazard
gT soT(6 JvaDGI BDG GuoguLL feedbacks6 o6LU
asynchronous sequential circuitsatov DLBu UébGLh
hazard essential hazard gyg.
Gimgioumes toggling circuitsfisiohu@ta.
um$esiutL path@avamount of delaysou adjust Geugi

Races

Cycle@. T 5dauns Gprssgu 96 input

variable@ad syhußib LonppsssarGuTSI GSyGluT feedback
variable DLGu unstableg6 @gsgu. i n p u t
variablegad syhuBub umppgBarGLumgi, Qgrbr(6 ingi NSDG
GoyuLL feedback variablessfsi Lomömù sypuGuuls, g
RACE condition s160TuGh.
I760T(6)J6MBLIT6OT race ssit 2 6T6T6OT.
a. Critical Race
b. Non-Critical Race

Critical Race:
Critical race rGI 6TUGLITLgSID $upT60T Bnaus(
sugy.
Non Critical Race
Non Critical race 6 0 i 6TÚGuTLgGIu 9G #fuT6OT
1 66UuITSDr Sl6movs(G Gleabgyh.

1.55
 Review Questions with wers
Part A 2 Mark Questions
level implementatio
1. Draw the transistor
gate using CMOS logic.
of tu
(Referthe page 1.16)
2. Draw the transistor level implementation
gate using CMOS logic.
of N
1.17)
(Referthe page
3. What do you meant by logic function? Give os
eone
example.
Output g input gsor function s ior
9G simple expression g logic function sT8T
ma.
Example: Light(a) =a
4. What are all universal gates?
(i) NAND
(ii) NOR
5. Why NAND and NOR gates are said to be unive
gates?
ANDonguo OR Gunsarp sm6aTGEI gates
NAND gatesmaT ULOTLI6sS DLGud
gatessm6T IL6OTLIGs) uL Gd gumfls6sumU. 6160TGo. N
L gu NOR gatesst universal
6T60T meLpssbiuGl60Tm60T.
gate
6. Calculate no of gates required
gate.
to implement
XOR gate mstsor expression
y=ab+ab
1. One NOT gate for
2. One NOT
gate for b
3. One AND
4. One AND
gate for b
5. One OR
gate for ab
gate for b + ab
ST60T o1, Glom s5in 5 gatesst u661i g
Gz6maiILIbL
1.56
 7. State Demorgan's theorems.
(0) A+B A.B
98h0s Glesnsmasul66r cpmplement smg.
91560T COmplement sorfl66r Glu(,6G,GET6D&ÉG
GiDLOIT% gGGGD.

(i) A.B= A + B
9 Augs65 Ggrmsulor cpmplement j 1
N56OT Complement 6sflsoT 6hOgGgn6ma6G
ginLoT GBGLD.
8. Expand SOP and POS.
SOP: Sum Of Product term
POS: Product Of Sum termm
9. Distinguish between combinational and sequential
circuits. (Oct 2018)

combinational
B&uTM5w input g Lo6Gu
output sipbgáGD.
Memory-less system
Example: half-adder,
full-adder
sequential
sp&uTma5w input Jb,
LP65u output JLh
output snir p,S(GsG.
Feedback opmuh memory
element g system
GlsmsoT GaT6T
Example: Flip flops

10. List few combinational circuits.

(i) Multiplexer
(ii) Demultiplexer
(ii) Encoder
(iv) Decoder
(v) Adder
(vi) Subtractor

1.57
 Questions

multiplexer a
and
n d encode
3
Mark
multiplexer
der
Part8- between

D s t i n g u i s h
encoder
1. la
multiplexer
03ta
Encoder
active
UR input
signal Oded
sa
Multioiexer
S S e i e c t
output 5 Lombgu.
inputass

a t a selector Aga
2 inputs58tto gLS
n outputse é6'ené(
output snáGih

decoder
between
encoderand

2.
Distinguish
decoder
encoder
n-bit code 2
N-DIt
NE outputsaTITES decode
inputs0T
2 deun5OutputsoTT5

cOde sencode
6605
output &6ti60T 67600T6001
L input &afiest
6T60Tsfäna
i n p u t &s T5D5
GDpT 2.6iT6T|.
Receiver side w uw6TU
uuLADE
Transmittersidesi

Draw the circuit

for a Half Adder.
3.
(Referthe page 1.48)
Adder.
4. Draw the circuit for a Full
(Refer the page 1.50 )
What do you meant by hazards in the digitd
5.
circuit? (Oct 2017) 0 6 U Lu n e q u

9gcombinationai circuit 0 yp
propagation delay wsr 51huBub Goo
transient n g glitch hazard a

1.58
6. What are the types of hazards? (Oct 2017)
Hazards g 1maÜuGh.
(i) Static hazard
(ii) Dynamic hazard
7. Define dynamic hazard.
Output JSTSI 0 6GLSI 1 6GaT gsvangI
1 goGiSI 0 yéaGar LomppúuLLma), circuit
TI
gormiés(h GtomuILL glitch g 2GuTsGL. güugLILL u
glitch ssr 2gumuGI dynamic hazard sraariuGh.
8. How do you remove static hazard? (Oct 2017)
Redundant grouping or euo adjacent
cell&meT COver u6OT SaD1OIG60T eLpaDLh static hazard
sBoTD.
9. What are the types of race? (Oct 2018)
Races g al6msÚuGuh.
(i) Critical Race
(i) Non-Critical Race
Part C- 10 Mark Questions
1. Draw the transistor level implementation of AND
and OR gates using CMOS logic. (Oct 2017, 2018)
(Referthe page 1.14)
2. Write any five Boolean laws.

(Referthe page 1.25)

3. Explain the operation of transmission gate and
implement 2: 1 multiplexer using CMOS
transmission gate?
(Referthe page 1.17 & 1.20)
4. (i) Implement the functionF = m0,2,3,7 with
minimal gates.
the above function with a 4 to 1
(ii) Implement
multiplexer.
1.59
 Answer
(i) Finding the minimal cost
Here minterm up
have the
we
to7
variables are sufficient to implement th
F(a, b,c)= abc + abc + abc + abc
ne func
a(be+ bc) +be(a+a)
a(b c ) + bc
(i) Implementing the above function with
multiplexer a 4
From the function F= 2m0,2,3,7, we can
writ
table as,
a b C

O 0 00 T
0 0 1 0
0 1
0 1 1
A 1 0
5 1 0 1
6 0
1

Consider bc as select inputs.

1.When bc = 00 C
b
a b c F a o
00
0 0 1 01 -F (a,b
10
10 0 0

2.When bc = 01 C
b
a b
0 1
a 00
01 F(a,b
0-
10
1 11

1.60
 3.When bc = 10
b
a b C F
00
1 1 0 01
10 F (a,b,c)
1 1 0 0 11

3.When bc = 11 C
b
ab_cF a0 00
1 1 1 01 F (a,b,c)
10
11 1

The final implementation with Mux is

b
C

a-o -
00
0- 01 F (a,b,c)
a 10
11
1

5. () Implement the function F-mo.2,3.7 with do

not care of 4 and 6 with minimal gates.
(i) Implement the above function with a 4 tob1
multiplexer.
Answer
(i) Finding the minimal cost
Here we have the minterm up to 7. So 3
variables are sufficient to implement the function.
If we consider don't care combination for 4 and 6
mintrem F is always '1'
F(a, b, cd) = abe + abe + abe + abe + abc + abe

= a(be + bc) + a(be +bc) + b(ac + ac)

=
a(b Dc)+a(b Dc)+ b(a Dc)
1.61
 Let X= b®e
= aX +aX + b(a c )
= a X + b(a c )
=
a b c+b(a D c)
(i) Implementing the above
function with
multiplexer h a 4
From the function F =
table as, 2m0,2,3,7, we can
writ.
rite
b C F
O O O
1 O O
1 O
O 1 1
1
5 1 1 O
6 1
1

Consider bc as select inputs.

When bc=00|When bc=01|When bc=10 When
dF
bc=
o
a a
F aF
o 1 1
1 1
oo C
1 1

b
1
O0
O 01
10
-F (a,b,c)
11

1.62
6. (i) Implement the function F m1,2,3.5,7,10,13 with
minimal gates.
(i) Implement the above function with a
multiplexer.
Answer
(i) Finding the minimal cost
Here we have the minterm up to 13. So we
need 4 variables.
Fa.b.c.d) = abcd+abcd+abcd+abcd+abcd+ abcd + abd

ab(cd+cd) +cd(b+b) + (a +a)bcd + abcd

ab(cd) +cd+ bcd+ abcd
By replicating the term abcd we get the simplified
expression,
F(a,b, c,d) = ab(c d)+ cd + bcd+abcd +bcd

ab(c® d)+ cd+ bõd+ bed(a +a)

ab(cd)+cd +bd +bcd
(ii) Implementing the above function with a
multiplexer
From the function F =m1,2,3,5,7,10,13, we can
write the table as,
ab Cd F
00 0 0 0
1 0 0 0 1
2
0 0 1 0
0 0 11
4 1 0
0 1 1 1
0 1 1 0 0
70 1 1
0 0
91 o0 1 0
101 0 1 0
11 1 1 1

1.63
 b C d F
12 1 1 0 0

13 1 11 01 1 1
14 1
15 1 1 1 1

Consider cd as
select inputs.

1. When cd = 00
d.
a b F C

0 0 0
00
0 1 01 F
1 10

L1 1 0
2. When cd 01
Simplify the truth table us
a bF
K-map for the function'F
0 0 1
1 1
1 0 0
1
111
1 F +b
b

0 00
01 F
10
2. When cd 10
bF
0
1 0
1 0 1
1
1.64
 1
Simplify the truth table using
K-map for the function 'F' o10

b F b
d
C

0 00
01
10 F

2. When cd = 11
Simplify the truth table using
abF K-map for the function'F
0 0 1 b
0 1 1 a 0

1
1 1 0

F a
b

d
C

0 00
01
10
F
11
With do
the function F-m.235,7.1013
7. (i) Implement 6 with minimal gates.
not care of 4 and
above function with a
(i) Implement the
multiplexer.

1.65
Answer
the minimal cost
(i) Finding
Here we have the minterm up to 13,
need 4 variables.If we consider the
don
combination for 4 and 6 mintrem F is
always
d)= abcd+abcd +abcd +abcd +abcd
+abcd+ aha
F(a,b.c,
ab(c d) + b(cd)+ b{c®d) d)+bc(ad+d). ah cd+a
= ab(c®d)+ab(c d+cOd) + bc(a Dd)+abcd

=abcd)+b +be(a®d)+abcd
By replicating the term abcd we get the simplis.

expression,
plifie:
ab+ be(apd)+ abd bcd
F(a,b.c,d) b(c®d)+
= +

ab(cd)+ab+be(a d)+b(ad+ãd
= ab(cd)+ab+be(a d)+bc(a d)
function with
Implementing the above
a
(i)
multiplexer
From the function F=m1,2,3,5,7,10,13, we car
write the table as,

ab
bC d F

0 0 0 0 0 0
0 0 0 1
0 1 1
2 0
00 1 1
34 0 1 0 0 1

50 1 0 1 1
1
6 0 1 1 0

701 1 1
8 10 0 0

1.66
 a b Cd F
9 1 0 01 0
10 1 0 1 0 1
11 1 0 1 0
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 11 1 0

Consider cd as select inputs.

d
C

00
F (a,b,c,d)
01

10
11

Realization of function F(a,b,c,d) using 4 x 1

multiplxer (Considering d as 1)

1.67