2020

Sheet 3
1. Design a four‐bit binary synchronous counter
with D flip‐flops.
2. What operation is performed in the up–down
counter of Fig. 1 when both the up and down
inputs are enabled? Modify the circuit so that
when both inputs are equal to 1, the counter does
not change state.
3. Obtain the input equations for a BCD counter that
uses
(a) JK flip‐flops
(b) D flip-flops.
(c) T flip-flops
Compare the three designs to determine which
one is the most efficient.
4. Enclose the 4-bit binary counter with parallel
load in a block diagram showing, all inputs and
outputs.
(a) Show the connections of four such blocks to
produce a 16‐bit counter with parallel load.
(b) Construct a binary counter that counts from 0
through binary 127.
5. Design a counter with T flip‐flops that goes
1. Fi states 010 and
through the following binary repeated sequence: 0, 1, 3, 7, 6, 4. Show that when binary
g.
101 are considered as don’t care conditions, the counter may not operate properly. Find a way to correct
the design.
6. Design a counter Using JK flip‐flops with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6.
7. Using D flip‐flops,
(a) Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6.

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(b) Design a counter with the following repeated binary sequence: 0, 2, 4, 6, 8.
8. Show a complete timing diagram for a 3-bit up/down counter that goes through the following sequence.
Indicate when the counter is in the UP mode and when it is in the DOWN mode. Assume positive edge-
triggering.
0, 1, 2, 3, 2, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1, 0
9. Design a binary counter with the sequence shown in the state
diagram of Fig. 2

Fig. 2 Fig. 3
10. Design a counter using three alternatives for a mod‐8 counter using counter IC shown in Fig. 3 which
counts from 0 to 15.