STM32L0x Ultra Low Power

- Power Control/low Power Modes

- Reset clock
- LPUART
- LPTIMER
- Connected IP
MCD Application Team

January-2014

V1.1
 2

System Peripherals

POWER CONTROL (PWR)

LOW POWER MODES
 Power Supply 3
 Power Supply Schemes
 VDD = 1.8 V (at power on) or 1.65 V (at power VDDA domain
down) to 3.6 V when the BOR is available. VDD =
A/D converter
1.65 V to 3.6 V, when BOR is not available. VREF+ D/A converter
External Power Supply for I/Os and the internal Temp. sensor
VDDA Reset block
regulator. VSSA PLL

 VDDA = External Analog Power supplies for ADC, VDD domain

VCore domain
DAC, Reset blocks, RCs and PLL.
FLASH Memory
 ADC working only if VDDA ≥ 1.8 V
I/O Rings
 VLCD = 2.5 to 3.6 V: For External power supply for
LCD controller if the internal step-up converter is STANDBY circuitry Core
(Wake-up logic, Memories
not used VSS
IWDG, RTC, LSE Digital
crystal 32K osc,
 Power pins connection: VDD
RCC CSR ) peripherals

 VDD and VDDA must be connected to the same Voltage Regulator

Dynamic Voltage
power source Scaling

 VDD_USB must be set from 3.0V to 3.6V if USB

used, otherwise from 1.65V to 3.6V. VLCD LCD Controller

 VSS, VSSA must be tight to ground

VDD_USB USB transceiver
 VREF+ ≤ VDDA
 VREF+ available only on BGA64 in other
packages it is connected to VDDA

3
 Voltage Regulator 4

• An embedded linear voltage regulator supplies all the digital

circuitries except for the Standby circuitry. The regulator output
voltage (VCORE) can be programmed by software to three different
ranges within 1.2 - 1.8 V (typical). This method is called Dynamic
Voltage Scaling.
• Regulator Voltage Range 1: VCORE = 1.8V
• Regulator Voltage Range 2: VCORE = 1.5V
• Regulator Voltage Range 3: VCORE = 1.2V

• The Voltage regulator has three different modes

• Main voltage regulator mode (MVR) for Run and Sleep modes.
• Ultra low power regulator mode for LP RUN, LP sleep and STOP
modes.
• Regulator OFF for STANDBY mode.

4
 Dynamic voltage scaling in Run mode 5
 Voltage scaling optimizes the product efficiency (Consumption vs Performance)
 User selects a Range (voltage scaling) according to :
 External VDD
 DMIPS performance required (=w/ or w/o Wait State)
 Max power consumption
MHz
32

1WS

16
1WS

0WS
8
4.2 0WS
0WS
V
VCORE 1.2 V (Range 3) 1.5 V (Range 2) 1.8 V (Range 1)

VDD 1.65V .. 3.6V 1.71V .. 3.6V

5
 Limitations depending on the operating power supply range
6

Limitations depending on the operating power supply range

Maximum CPU
Operating power supply range ADC operation USB VCORE frequency
(fCPUmax)

16MHz (1ws)
VDD = 1.65 to 1.71V Not functional Not functional Range 2 or Range 3
8MHz (0ws)

VDD = 1.71 to 1.8V** Not functional

Conversion time up to
VDD = 1.8 to 2.0V** Range 1, Range 2 or 32MHz (1ws)
500 Ksps Functional*
Range 3 16MHz (0ws)

Conversion time up to
VDD = 2.0 to 2.4V
500 Ksps

Conversion time up to
VDD = 2.4 to 3.6V
1.14 Msps

*: USB transceiver requires VDD_USB>=3.V to be compliant

**: fin range 1 the system frequency cannot be augmented more than 4 times at once 6
 Supply monitoring and Reset circuitry 7

• Full Reset circuitry / Supply Monitoring

• Power On Reset (POR) / Power Down Reset (PDR) “ZERO Power” -
always ON
• Brown Out Reset (BOR) - Can be ON/OFF in Low Power modes, two dies
flavor:
• On STM32L0 devices operating at 1.8V (1.65V at power down) to 3.6V, the BOR can be
disabled by option bytes..
• On STM32L0 devices operating at 1.65V to 3.6V: there is no BOR.
Extended battery lifetime down to 1.65V at power down when BOR disabled

• Programmable Voltage Detection (PVD) - Can be ON/OFF.

The PVD enable/disable is controlled by software via a dedicated bit
(PVDE).

7
 Brown Out Reset (BOR) 8

 During power on, the Brown out reset (BOR) keeps the device
under reset until the supply voltage reaches the specified VBOR
threshold.
 No need for external reset circuit
 The BOR is available only on devices operating from 1.8V to 3.6
V, and unless disabled by option byte it will mask the POR/PDR
threshold. VDD

 When the BOR is disabled by option byte, the reset is asserted

when VDD goes below PDR level VBORH VBORH
VBORL 100mv hysteresis
 BOR have a typical hysteresis of 100mV VBORL

 BOR Levels are configurable by option bytes: Temporization

tRSTTEMPO
 BOR OFF: 1.8 V at power on and VPDR at power down.
A grey zone exists between the VPOR/VPDR thresholds and the
minimum product operating voltage 1.65 V. The start-up time at
power-on can be decreased down to 1ms typically. Reset
 BOR LEVEL 0: 1.8 V at power on and 1.7 V at power down
 BOR LEVEL 1: 2.0 V at power on and 1.9 V at power down
 BOR LEVEL 2: 2.4 V at power on and 2.3 V at power down
 BOR LEVEL 3: 2.6 V at power on and 2.5 V at power down
 BOR LEVEL 4: 2.9 V at power on and 2.8 V at power down

8
 Power On Reset (POR)/Power Down Reset
9
(PDR)

VDD
 Integrated POR / PDR circuitry:
 For devices operating from 1.65 to 3.6 V, VPOR POR
there is no BOR and the reset is released VPDR PDR
when VDD goes above POR level and
Temporization
asserted when VDD goes below PDR level tRSTTEMPO

 POR and PDR have no hysteresis

Reset

VPDR = VPOR = 1.5V

9
 Programmable Voltage Detector (PVD) 10

 Programmable Voltage Detector VDD

 Enabled by software
 Monitor the VDD power supply by comparing it to
a threshold PVD Threshold 100mv hysteresis
 Threshold configurable from 1.9V to 3.1V by
step of 100mV
 Generate interrupt through EXTI Line16 (if
enabled) when VDD < Threshold and/or VDD >
Threshold PVD
Output
 Can be used to generate a warning message
and/or put the MCU into a safe state

10
 Supply monitoring w/ or w/o Brown Out Reset 11
 BOR complies w/ ALL Vdd rise/fall time = No constraints on power supply shape

VDD  BOR can be configured by user through option byte VDD

 BOR can be deactivated in STOP/STANDBY mode by disabling VREFINT

3.6V

Vdd Operating Power

BOR Threshold Supply
VBOR

BOR_LEV0 Threshold
BOR_LEV0 Threshold 1.8V
1.8V
Safe Reset (BOR ON)

Safe Reset release

1.65V 1.65V
w/o BOR = Battery life extension (Grey Zone)
1.5V 1.5V

Safe Reset
NO BOR

POR Threshold PDR Threshold

Reset
Internal Reset
w/ BOR w/ BOR
w/o BOR w/o BOR
BOR not available
BOR activated by user for
BOR LEV0 is always active at power power down detection
on (even BOR is disabled by Option) Time

11
 Standby Circuitry 12
 Standby Circuitry contains
 Low power calendar RTC (Alarm, periodic wakeup from
Stop/Standby)
 20 Bytes Data backup registers
 Separate 32kHz Osc (LSE) for RTC
 RCC CSR register: RTC source clock selection and enable + LSE
Standby Circuitry
config
 Reset only by RTC domain RESET
RCC CSR 32kHz OSC
 2 Wakeup/Tamper/Timestamp pins reg (LSE)
IN 1
 Tamper detection: can resets all RTC user backup registers
Wakeup
 Configurable level: low/high Logic
IWDG

 Configurable interrupt generation

 Configurable reset of backup register RTC_OUT/IN 2 RTC + 20 Bytes Data

 Time Stamp detection: Calendar is saved in the time-stamp registers

 Configurable level: low/high
 Configurable interrupt generation
 On RTC_OUT:
 RTC Alarm Ouput: Alarm A, Alarm B and Wakeup Timer
 RTC Clock calibration Output: RTCCLK/64= 512Hz or 1Hz

12
 13
Low power modes: STM32L0 vs STM32F0
• The STM32L features 5 low power modes
• LP RUN: RUN mode with regulator in low power mode (down to ~10µA)
• Sleep mode (~50µA/MHz)
• LP sleep: Sleep with regulator in low power mode (down to ~4µA)
• STOP and STOP LP (~0.6µA)
• STANDBY (~0.35µA)

• There is no VBAT mode on STM32L0

STM32F0 STM32L0
LP RUN

Sleep Sleep

LP sleep (Regulator in LP mode)

Low Power Mode
STOP and STOP LP STOP and STOP LP

STANDBY STANDBY

VBAT

13
 14
STM32L0 Low power modes features

• The STM32L0 features many options to decrease the consumption

during low power modes
• Dynamic Voltage Scaling
• Peripherals clock stopped automatically during sleep mode
• Flash Power Down mode can be switched off during RUN, LP RUN(only when CPU
is executing from RAM), Sleep mode.

• The internal voltage reference can be OFF in Stop mode and Standby mode with a
fast wakeup mode option ( only for Stop mode).
• The BOR can be OFF also.

14
 Low Power Modes (1/6) 15

• LP RUN Mode: Core running, peripherals kept running

• Entered by
• System Clock is set to multispeed internal (MSI) RC oscillator (131kHz
max)
• Execution from SRAM or Flash memory
• Internal regulator is in low power mode to minimize the regulator's operating
current.
• FLASH can be in Power Down mode (when executing from RAM)
• VREFINT can be OFF
• The system clock frequency and the number of enabled peripherals are
both limited.

15
 Low Power Modes (2/6) 16

• SLEEP Mode: Core stopped, peripherals kept running

• Entered by executing special instructions

• WFI (Wait For Interrupt)
• Exit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller (NVIC)

• WFE (Wait For Event)

• An event can be an interrupt enabled in the peripheral control register but NOT in the NVIC or an EXTI line
configured in event mode
• Exit: as soon as the event occurs  No time wasted in interrupt entry/exit

• Two mechanisms to enter this mode

• Sleep Now: MCU enters SLEEP mode as soon as WFI/WFE instruction are
executed
• Sleep on Exit: MCU enters SLEEP mode as soon as it exits the lowest
priority ISR
• To further reduce power consumption you can save power of unused
peripherals by gating their clock

16
 Low Power Modes (3/6) 17
• LP sleep Mode: Core stopped, peripherals kept running

• Entered by executing special instructions

• WFI (Wait For Interrupt)
• Exit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller (NVIC)

• WFE (Wait For Event)

• An event can be an interrupt enabled in the peripheral control register but NOT in the NVIC or an EXTI line configured
in event mode
• Exit: as soon as the event occurs  No time wasted in interrupt entry/exit

• Internal regulator is in low power mode to minimize the regulator's operating current.
• FLASH can be in Power Down mode
• VREFINT can be OFF
• Two mechanisms to enter this mode
• Sleep Now: MCU enters SLEEP mode as soon as WFI/WFE instruction are
executed
• Sleep on Exit: MCU enters SLEEP mode as soon as it exits the lowest priority ISR
• To further reduce power consumption you can save power of unused
peripherals by gating their clock
17
 Low Power Modes (4/6) 18

• STOP Mode: all periph clocks, PLL, MSI, HSI and HSE are disabled, SRAM and
register contents are preserved.
• If the RTC, LCD and IWDG are running they are not stopped (nor their clock sources)

• To further reduce power consumption the Voltage Regulator can be put in Low Power mode

• VREFINT and BOR can be OFF

• Wake-up sources:
• WFI was used for entry: any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt
vector must be enabled in the NVIC)
• WFE was used for entry: any EXTI Line configured in event mode
• EXTI line source can be: one of the 16 external lines (so any IO), PVD, RTC alarms, RTC Tamper,
RTC Time Stamp, RTC Wakeup, Comparators 1&2 events, USB wake-up
 After resuming from STOP the clock configuration returns to its reset state (MSI, HSI16 or HSI16/4
used as system clock).

Wake-up time from Stop on MSI RC at 4MHz on HSI at 16MHz

wake-up to Flash TBD?? µs 5µs (TBC??)

Wake-up to RAM TBD?? µs 3.5 µs(TBC??)

18
 Low Power Modes (5/6) 19

• STANDBY Mode: Voltage Regulator off, the entire VCORE domain is powered off and VREFINT
can be OFF.
• SRAM and register contents are lost except registers in the STANDBY circuitry

• RTC and IWDG are kept running in STANDBY (if enabled)

• In STANDBY mode all IO pins are high impedance except

• Reset pad (still available)
• RTC_OUT pin if configured for tamper, timestamp, alarmA out, alarmB out, Wakeup timer out or calibration out
• WKUP1, WKUP2 pins if enabled

• Wake-up sources:
• WKUP1, WKUP2 pins rising edge
• RTC alarm A, RTC alarm B, Wakeup Timer, Tamper event, TimeStamp
• External reset in NRST pin
• IWDG reset
 After wake-up from STANDBY mode, program execution will restart in the same way as after a RESET.

Wake-up time from STANDBY mode on MSI RC at 2MHz STM32L0 typ

STANDBY with VREFINT ON 57.2 µs (TBC??)

STANDBY with VREFINT OFF 2.4 ms(TBC??)

19
 Low Power Modes (6/6) 20
• STM32L0 Low Power modes: uses CortexM Sleep modes
• SLEEP, STOP and STANDBY modes
 The reset circuitry, POR/PDR, is active in STANDBY and STOP modes.

STM32L15x
Feature0.9 STM32L0 STM32F10x typ
MD typ
Consumption in RUN mode w/ execute from Flash
140µA/MHz 214µA/MHz -
on Range 3
Consumption in RUN mode w/ execute from RAM on
120µA/MHz 167µA/MHz -
Range 3
Consumption in LP RUN mode w/ execute from RAM
on internal multispeed RC (MSI at 64kHz) 13µA 14µA -

Consumption in SLEEP mode w/ execute from Flash

700µA 900µA -
at 16 MHz and all peripherals clock OFF
Consumption in SLEEP mode w/ execute from Flash
3.5mA -
at 16 MHz and all peripherals clock ON
Consumption in LP sleep mode w/ execute from
Flash at 32kHz, internal regulator in low power mode replaced 17µA -
with one timer running at 32kHz
STOP w/ Voltage Regulator in low power 0.40µA w/o RTC
0.57µA w/o
Low speed and high-speed internal RC oscillators and 0.82µA w/ RTC RTC
high-speed oscillator OFF (no independent watchdog) 0.440 µA w/ 14 µA
1.45µA w/ RTC
LPTIMER
0.87µA w/ LPUART
STANDBY all OFF 0.27µA 0.3µA 2 µA

STANDBY w/ RTC 0.9 µA 1.0 µA -

20
Mode name Entry Wakeup
STM32L Low Power modes Effect on Effect on Voltage IO state Wakeup latency
21

VCORE VDD regulator

domain domain
clocks clocks
Low power LPSDSR and NA. None None In low
run LPRUN bits + power None
Clock setting mode

Sleep WFI Any interrupt CPU CLK None ON None

Sleep now or OFF All I/O pins
sleep on- exit) WFE Wake-up event no effect on keep the
other
same state
clocks or
LP Sleep LPSDSR bits+ Any interrupt analog None In low as in the Regulator wakeup
Sleep now or Clock setting clock sources power Run mode time from low power
sleep on- exit) + WFI mode mode +FLASH
LPSDSR bits Wake-up event wakeup time
+ WFE
Stop Clear PDDS, Any EXTI line (configured ON, in low MSI or HSI RC
LPSDSR in the EXTI registers, power wakeup time +
bits + internal and external lines) mode regulator wakeup
SLEEPDEEP All VCORE HSI and (depending time from Low-power
bit + domain clocks HSE and on
mode +
WFI or WFE OFF MSI PWR_CR)
oscillators
FLASH wakeup time
Standby Set PDDS bit WKUP pin rising edge, OFF OFF all I/O pins Reset phase
+ RTC alarm (Alarm A or are high
SLEEPDEEP Alarm B), RTC Wakeup impedance
bit + event, RTC tamper event, (1)
WFI or WFE RTC timestamp event,
external reset in NRST
pin, Note
IWDG (1):reset
Standby mode: all I/O pins are high impedance except:
- Reset pad (still available)
- RTC_OUT pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, time-stamp, RTC Alarm out, or RTC clock calibration out.
- WKUP pin 1 (PA0) WKUP pin 2 (PC13) if enabled.
21
 STM32L Low Power new feature 22

Mode name New Low power feature to further reduce Comments

power consumption
Low power -Flash power down when code is executed -System clock must be reduced : switch to MSI
run from RAM clock frequency

Sleep -Peripherals clock stopped automatically -All disabled peripherals will be automatically re-
Sleep now or sleep on- during sleep mode enabled.
exit)

LP Sleep - Flash power down - FLASH wakeup time

Sleep now or sleep on-
exit) - Peripherals clock stopped automatically -All disabled peripherals will be automatically re-
during sleep mode enabled.

- BOR OFF - Supply is monitored by the POR/PDR. The PVD

can be also used.
Stop -VREF OFF + Fast wakeup (FWU bit set) - Reduce the wakeup time without waiting for
internal voltage reference startup time .

- BOR OFF - Power supply monitored by the POR/PDR. The

PVD can be also used.
Standby - VREF OFF - If VREF is disabled, a longer wake-up phase
2.3ms instead of 50us

- BOR OFF -Supply is monitored only by the POR/PDR

22
Typ current
STM32 L05* - Power consumption 23

Vdd Range

210µA/MHz 85°C
25°C
• Wake up time
• 5μs (flash)
Range1 @ 32MHz
175µA/MHz1 • 3.5 μs (ram)
8µA
139µA/MHz1 • 50μs

4.2 µA

87/MHz 6 µA
1 μA
While {1}
290 nA
3.2 µA 9502 nA
8003 nA 670 nA
4004 nA 270 nA
Dynamic Run Low-Power Run Low-Power Sleep Stop Standby w/ RTC
From Flash @ 32KHz + 1 timer @ 32KHz Standby w/o RTC

1. Dhrystone power consumption value executed from Flash with VDD=3V (Prefetch on and Prefetch off)
2. STOP mode consumption with : Full Ram retention + RTC + Low-power Pulse counter
3. STOP mode consumption with : Full Ram retention + RTC
4. STOP mode consumption with : Full Ram retention
STM32L152 ultra-low-power consumption 24

CPU ON
Peripherals activated
RAM & context preserved

Backup registers preserved

238µA/MHz 85°C
25°C
Startup time:
From Stop: 5 µs
From Standby: 60 µs
300µA/MHz 12µA
Range1 @ 32MHz

6- µA
214µA/MHz
Range 3 @ 4MHz 9 µA
4.8 μA
4.4 µA 1 µA
1.4 µA
570 nA
300 nA
Dynamic Run Low-Power Run Low-Power Sleep Stop w/ RTC Standby
From Flash @ 32kHz @ 32kHz or w/o RTC

24
 Quiz 25

• How many power supply domains are available?

____________

• What is the content of the Standby Circuitry?

____________

• What is the difference between “Sleep Now” and “Sleep on Exit” modes?

____________

• What are the wake-up sources from STOP mode?

____________
25
 26

System Peripherals

RESET AND CLOCK CONTROL (RCC)

 RESET Sources 27

VDD /VDDA
 System RESET
 Resets all registers except some RCC
registers and RTC RPU
 Sources External
RESET Filter
SYSTEM RESET

 NRST pin (External Reset)

NRST

WWDG RESET
 WWDG/IWDG end of count PULSE IWDG RESET
POR/PDR
GENERATOR Software RESET
 A software reset (through NVIC) (min 20µs) Power RESET RESET
Low power BOR
 Low power management Reset management RESET
RESET
Option Byte loader
 Option byte loader Reset RESET

 Power RESET  RTC domain RESET

 Resets all registers  Resets all RTC domain: RTC registers +
 Sources RTC Backup Registers + RCC CSR
 Power On/Power down Reset register
(POR/PDR)  Sources
 BOR  Setting RTCRST bit in RCC CSR
 When exiting STANDBY mode register
 POWER Reset
 Enhancement (versus L1)
 Pull-up is disabled when pin forced low
 Internal reset is not delayed by reset pad

27
 On Chip Oscillators: overview 28

 Multiple clock sources for full flexibility in RUN/Low Power modes

 HSE (High Speed External oscillator):
 1MHz to 24MHz oscillator or up to 32MHz external clock
 HSI16 (High Speed Internal RC):
 16MHz
 HSI48 (High Speed Internal RC):
 48MHz (for USB and RNG)
 MSI(Multispeed internal RC oscillator): 7 possible frequencies:
 65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz
 LSI (Low Speed Internal RC):
 37kHz Low consumption Low precision
 LSE (Low Speed External oscillator):
 32.768kHz oscillator or external clock (1 kHz to 1MHz)

28
 On Chip Oscillators LSE 29

 LSE feeds the RTC, optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY
 New compared to STM32L1
 LSE oscillator has several drive level to fit quartz requirement with adapted consumption
 Drive level can be changed from high level (for quick start) to lowest level for
consumption (depending on quartz used)

Drive level Low drive Medium L Medium H High

Simulation config, RM, 50kΩ, 80kΩ, 50kΩ, 80kΩ,
C0,CL 1.2pF, 6pF 1.2pF, 6pF 1.2pF, 1.2pF,
12.5pF 12.5pF
consumption@1.8V, nA 180 220 390 490

29
 On Chip Oscillators: usage 30

 HSE, HSI16, MSI and PLL can feed system clock

 MSI is the backup clock in case of HSE failure
 HSI16 and MSI are factory trimmed and user trimmable
 HSI48 can be trimmed through USB (SOF) or LSE
 MSI, HSI or HSI/4 feeds System clock after exit from STOP
 LSI feeds IWDG and optionally the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode
 The clock used for baud rate/communication frequency for USART and I2C is independent
from APB clock
 Clock-independent system clock sources for TIM2/TIM21/TIM22: LSE clock is internally
redirected to the 3 timers’ ETR inputs.
 It is possible to indirectly measure the frequency of all on-board clock source generators
(LSI/LSE/MSI/HSE) by means of the TIM21 channel 1 input capture.

30
 Clock Scheme 31

 System Clock (SYSCLK) sources  RTC Clock (RTCCLK) and LCD Clock USB/SDIO Clock (USBCLK) provided from
(LCDCLK) sources HSI48 or the internal PLL (PLLVCO/2)
 MSI
 HSI16  LSE
 LSI  Clock-out capability on the MCO pin
 HSE
 HSE clock divided by 2, 4, 8 or 16 (PA08/PA09).
 PLL
 Configurable dividers provides AHB,  Clock Security System (CSS) to backup clock in case of HSE clock failure (MSI feeds
the system clock)
APB1/2 and TIM clocks
 Enabled by SW w/ interrupt capability linked to Cortex NMI
64kHz, …, 4MHz
MSI RC ADCCLK

HCLK up
16MHz to 32MHz
HSI16 RC
PCLK1 up
1 -24 to 32MHz
MHz
OSC_OUT PLL Mul PLL Div SYSCLK AHB APB1 If (APB1 pres
HSE Osc X3..x48 /2, /3, /4 Prescaler Prescaler =1) x1 TIMxCLK
OSC_IN PLLCLK up to 32 /1,2…512 /1,2,4,8,16 Else x2
MHz TIM2,6

/2
PCLK2 up
to 32MHz
SYSCLK
HSI16 CSS APB2 If (APB2 pres
/1,/2,/4,/8,/ HSE Prescaler =1) x1 TIMxCLK
MCO
16 /1,2,4,8,16 Else x2
PLLCLK TIM21,22
MSI
/2, 4, USBCLK
LSE
8,16
LSI RBGCLK
48MHz
32.768kHz
OSC32_IN RTCCLK
LSE OSc LSE
OSC32_OUT HSI USART clock
CSS LCDCLK Sys
~37kHz LSI Apb
LSI RC IWDGCLK HSI
LSE
LPTIM Sys
HSI I2C clock
Apb
Apb
HSI48 RC
CRS TIM2/21/22 ETRs 31
 Peripheral gating
• The clock tree toward each register increase consumption

• So clock toward each peripheral register group can be gated (Default

is gated) range 1 range 2 range 3
LP Sleep and
run

Condition: 32MHz 16MHz 4MHz 65kHz

• Consumption (data L1): GPIOA 7 6 5 6

GPIOB 7 6 5 6

CRC 0.5 0.5 0.5 1

DMA1 18 15 13 18
SYSCFG &
RI 3 2 2 3 µA/MHZ
TIM2 13 11 9 11

TIM6 4 4 4 4

LCD 4 3 3 4

WWDG 3 2.5 2.5 3

USB 15 7 7 7

PWR 3 3 3 3

DAC 6 5 4.5 5

………..

ALL 279 221 219 215

 Quiz 33

• How many types of Reset are available?

____________

• What are the different MSI ranges?

____________

• What is the maximum AHB, APB1 and APB2 clock frequencies ?

____________

• What are the clock sources that can feed the PLL input?

____________

• What is the purpose of the CSS?

____________

33
Universal Synchronous Asynchronous
Receiver Transmitter (USART)
 USART Features (1/3) 35

• Fully-programmable serial interface characteristics:

• Data can be 7 or 8 or 9 bits
• Even, odd or no-parity bit generation and detection
• 1, 1.5 or 2 stop bit generation
• Programmable baud rate generator
• Configurable oversampling method by 16 or by 8
• Up to 4 Mbps when the clock frequency is 32 MHz and oversampling by 8 is selected.

• Programmable data order with MSB or LSB first.

• Swappable Tx/Rx pin configuration
• Tx/Rx pins active level inversion & Binary data inversion
• Support hardware flow control (CTS and RTS)

• Dual clock domain allowing

• UART functionality and wakeup from Stop mode
• Convenient baud rate programming independent from the PCLK reprogramming

• Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability
 USART Features (2/3) 36

• Support for DMA

• Receive DMA request

• Transmit DMA request

• LIN Master compatible

• Synchronous Mode: Master mode only
• IrDA SIR Encoder Decoder
• Smartcard Capability T = 0, T = 1 (using the Address/character match,
End of block, receiver timeout etc…)
• Basic support for Modbus communication (using Address/character
match and Receiver timeout features).
• Single wire Half Duplex Communication
 USART Features (3/3) 37

• Multi-Processor communication
• USART can enter Mute mode

• Wake up from mute mode (by idle line detection or address mark detection)

• Auto-baudrate detection using various character patterns.

• Driver enable (for RS485) signal sharing the same pin as nRTS.
 STM32L0 USART Implementation
38

• 2 USART interfaces are available, full features.

USART features USART1/2

Hardware Flow Control YES
Continous communication using DMA YES
Multiprocessor communication YES
Synchronous mode YES
Smartcard mode YES
Single wire half duplex mode YES
IrDA YES
LIN YES
Dual clock domain and wake up from STOP mode YES
Receiver timeout YES
Modbus Communication YES
Autobaudrate detection YES
Driver enable YES
 Wakeup from STOP 39

 When USART_CLK clock is HSI or LSE, the USART is able to wakeup the
MCU from STOP mode.

 Wakeup from STOP is enabled by setting UESM bit in the USART_CR1.

 The sources of wake up from STOP mode can be the standard RXNE interrupt
(the RXNEIE bit must be set before entering Stop mode). Or, a specific
interrupt may be selected through the WUS bit fields in the USART_CR3:

 Wake up on address match

 Wake up on Start bit detection

 Wake up on RXNE
 DMA Capability 40

• Each USART has DMA Tx and Rx requests

 Synchronous Mode 41

• USART supports Full duplex synchronous communication mode

• Full-duplex, three-wire synchronous transfer
• USART Master mode only
• Programmable clock polarity (CPOL) and phase (CPHA)
• Programmable Last Bit Clock Pulse (LBCL) generation
• Transmitter Clock output (SCLK)

Master Slave
SCLK SCK

Rx MISO

Tx MOSI

USART NSS
SPI

Full Duplex
 Smart Card mode (1/2) 42

• USART supports Smart Card Emulation ISO 7816-3

• Half-Duplex, Clock Output (SCLK)
• 9Bits data, 1.5 Stop Bits in transmit and receive.
• T=0, T = 1 support
• Programmable Clock Prescaler to guarantee a wide range clock input

USART
Tx

SCLK
Smart Card mode (2/2) STM32L0 vs
STM32L1 43

Features STM32L0 STM32L1

T=0 In case of transmission error, according
to the protocol specification, the
USART should send the character.
In case of reception error , according to
the protocol specification, the smartcard
must resend the same character.
The USART can handle automatic re- The data retry
sending of data. The number of retries is should be
programmable (8 max). done by
software.
The number of maximum retries is
programmable (8 max).
If the received character is still erroneous
after the programmed number of retries,
the USART will stop transmitting the NACK
and will signal the error as a parity error.

A programmable guardtime is Yes. No.

automaticaly inserted between two
consecutive characters in transmission.

T=1 Character Wait Time (CWT) All T = 1

features
should be
Block Wait Time (BWT) Implemented using the new timeout feature. implemented
by software.
New
Block length and end of block detection

Direct/Inverse convention Implemented using some new features:

MSB/LSBFIRST, Binary data inversion
etc…
 Single Wire Half Duplex mode 44

• USART supports Half duplex synchronous communication mode

• Only Tx pin is used (Rx is no longer used)

• Used to follow a single wire Half duplex protocol.

VDD

USART1 USART2

R = 10 KΩ
Tx Tx

Half Duplex
 IrDA SIR Encoder Decoder 45

• USART supports the IrDA Specifications

• Half-duplex, NRZ modulation,
• Max bit rate 115200 bps
• The pulse width is 3/16 bit duration in normal mode
 Modbus communication 46

• Basic support for the implementation of Modbus/RTU and Modbus/ASCII

protocols.
• Modbus/RTU: In this mode, the end of one block is recognized by a “silence” (idle line)
for more than 2 character times. This function is implemented through the programmable
timeout function.
• Modbus/ASCII: In this mode, the end of a block is recognized by a specific (CR/LF)
character sequence. The USART manages this mechanism using the character match
function.
 Auto-baudrate detection 47

 4 patterns for auto-baudrate detection:

 Any character starting with a bit at 1  the USART will measure the duration of the START bit
(Falling edge to rising edge).
 Any character starting with a 10xx bit pattern  the USART will measure the duration of the START
bit and of the first data bit (Falling edge to Falling edge).
 A 0x7F character frame (it may be a 0x7F character in LSB first mode or a 0xFE in MSB first mode).
In this case, the USART measures the duration of the start bit and the duration of bit 6.
 A 0x55 character frame. In this case, the USART measures the duration of the start bit, the duration
of bit 0 and the duration of bit 6. In parallel, another check is performed for each intermediate
transition of RX line.

 Once the automatic baudrate detection is activated, the USART will wait for the first character on the RX
line. The auto-baudrate completion is indicated by the setting of ABRF flag.

 The clock source frequency must be compatible with the expected communication speed : When
oversampling by 16, the baud rate is between fCK/65535 and fCK/16. When oversampling by 8, the
baudrate is between fCK/65535 and fCK/8).

 If the line is noisy, the correct baudrate detection is not guaranteed (BRR content may be corrupted))
 USART Interrupts 48

Interrupt event Interrupt flag

Transmit Data Register Empty TXE
Transmission Complete TC
CTS CTSIF
Receive Data Register Not Emptyy RXNE
Overrun Error ORE
Idle line detection IDLE
Parity Error PE
LIN break LBDF
Noise Flag, Overrun error and Framing Error in NE, ORE, FE
multibuffer communication.
Character Match CMF
Receiver timeout error RTOF
End of Block EOBF
Wakeup from STOP mode WUF
 STM32L1 USART vs STM32L0 USART
Main features (1/2) 49

Feature STM32L0 STM32L1

Programmable data length (8 or 9 bits) Yes Yes
Configurable stop bits 1, 1.5, 2 0.5, 1, 1.5, 2
Synchronous mode (Master only) Yes Yes
Single wire Half duplex Yes Yes
Programmable parity Yes Yes
Hardware flow control (nCTS/nRTS) Yes Yes
Driver Enable (for RS485) Yes No
Swappable Tx/Rx pin Yes No
IrDA Yes Yes
Basic support for Modbus Yes No
LIN Yes Yes
Smartcard Yes (T = 0, T=1) Yes (T = 0)
Dual Clock domain and wake up from STOP mode Yes No

Programmable data order with MSB first or LSB Yes No

first
 STM32L1 USART vs STM32L0 USART
Main features (2/2) 50

Feature STM32L0 STM32L1

Receiver timeout Yes No
Auto-baudrate detection Yes No
Continous communication using DMA Yes Yes
Address/character match interrupt Yes No
End of Block interrupt Yes No
Multiprocessor communication Yes Yes
Low Power Universal Asynchronous
Receiver Transmitter (LPUART)
 LPUART Features 52

• LPUART includes all necessary hardware support to make

asynchronous serial communications possible with minimum power
consumption.
• Only LSE 32.768 is required to allow UART communication at up to
9600 baud  For this purpose, the baudrate generation has been
changed comparing to the USART peripheral.
• Higher baudrates can be reached when the LPUART is clocked by
clock sources different from the LSE clock.
• Baudrate generation and Implementation are summarized in the next
slides.
 LPUART baudrate generation 53

• Tx/Rx baud = 256 x fck/LPUARTDIV

• Where:
• Tx/Rx baud: desired baudrate
• fck: LPUART clock source frequency
• LPUARTDIV: coded on the the BRR register, with considering
the following:
• fck must be in the range [3 x baudrate ...4096 x baudrate]
• It is forbidden to write values less than 0x300 in the BRR
register.
 LPUART Implementation
54

USART features LPUART

Hardware Flow Control YES
Continous communication using DMA YES
Multiprocessor communication YES
Synchronous mode NO
Smartcard mode NO
Single wire half duplex mode YES
IrDA NO
LIN NO
Dual clock domain and wake up from STOP YES
mode
Receiver timeout NO
Modbus Communication NO
Autobaudrate detection NO
Driver enable YES
 55
• The LPUART is able to wake up the MCU from Stop mode when the UESM bit is set and the
LPUART clock is set to HSI or LSE (refer to the Reset and clock control (RCC) section.

• The MCU wakeup from STOP mode can be done using the standard RXNE interrupt.
In this case, the RXNEIE bit must be set before entering Stop mode.

• In order to be able to wake up the MCU from Stop mode, the UESM bit in the
LPUARTx_CR1 control register must be set prior to entering Stop mode.
When the wakeup event is detected, the WUF flag is set by hardware and a wakeup
interrupt is generated if the WUFIE bit is set.
 Quiz 56

• How many USART interfaces are in the STM32L0 microcontrollers ?

____________

• What is the maximum USART Baudrate?

____________

• What are the features that are not supported by the LPUART comparing to the USART?

____________

• What are the different LPUART/USART DMA requests ?

____________
 Low Power Timer
LPTIM
Microcontrollers Division – Application Support Solutions Team

March 2013
 Features Summary 58

• Asynchronous running capability

• Ultra low power-consumption

• Timeout function for wakeup from

low power modes
 LPTIM Features (1/3) 59

• Up to 5 clock sources to achieve lowest power consumption

• APB clock
• LP oscillators: LSE, LSI, HSI
• External clock
• With configurable active edge: Rising edge, Falling edge and Both edges
• When both edges configuration is chosen, an auxiliary clock source is needed with a
frequency 4 times bigger, at least, than the external signal

• Up to 8 external triggers
• With configurable active edges: Rising edge, Falling edge and Both edges
• With digital glitch filter to avoid spurious triggers

• Up to 2 operation modes
• Continuous mode: free running mode; many counter overruns are possible
• One Shot mode: Counter stops counting when the overrun value is reached
 LPTIM Features (2/3) 60

• Up to 3 configurable waveforms
• PWM waveform
• One Pulse waveform
• Set Once waveform POL = 0
LPTIMx_ARR

LPTIMx_CMP

PWM

OnePulse

SetOnce
 LPTIM Features (3/3) 61

• Encoder mode
• Same operation as Encoder mode on General Purpose Timers
• Only available when LPTimer runs in Continuous mode

• Up to 6 interrupt sources
• Compare match interrupt
• Auto-reload match interrupt
• External trigger event interrupt
• Auto-reload register write completed interrupt Useful when LPTIM is clocked by a
clock source different from APB
• Compare register write completed interrupt
• Direction change interrupt; used by Encoder mode
 62

Reactive peripheral

Confidential
 Comparator as source 63

PA0, PA6, PA11

PA1 +
COMP 1 COMP Interrupt
PA0
- TIM21_ IC1
PA4/DAC1
Edge TIM21_ETR
PA5 selection LPTIM_CH1
Band Gap LPTIM_ETR
TIM2_IC4
TIM2_ETR
Window mode TIM22_IC1
TIM22_ETR
selection
PA2, PA7, PA12
PA3 +
COMP 2 COMP Interrupt
PA2 -
PA4/DAC1 TIM21_IC2
Edge TIM21_ETR
PA5
selection
PB3 LPTIM_CH2
Band Gap LPTIM_ETR
¾ Band Gap
TIM2_IC4
½ Band Gap
TIM2_ETR
¼ Band Gap
TIM22_IC1
TIM22_ETR
 TIMER as Source 64

• Timer Trigger other timer (see next slide)

• Any timer an trigger the ADC conversion

• TIM2, TIM6, TIM21 trigger the DAC conversion

• TIM2 and TIM6 can trigger the DMA

 TIMER as destination 65
timer External Internal trigger CH1 CH2 CH3 CH4
Trigger (TRGO)
• Slave
2 TIM ITR0 (TS
GPIOs = 000) ITR1
TIM21 (TS = 001) GPIOs
GPIOs GPIOs GPIOs

COMP1/2 TIM22 COMP1/2

• TIM2 TIM21 TIM22
LSE/HSI
21 GPIOs TIM2 GPIOs GPIOs

COMP1/2 TIM21 COMP1 COMP2

LSE LSI/LSE/MSI

HSE_RTC

Auto-wakeup int

MCO

22 GPIOs TIM21 GPIOs GPIOs

COMP1/2 TIM2 COMP1/2

LSE
LP GPIOs GPIOs GPIOs

COMP1/2 COMP1 COMP2

ALARMA/B

TAMP1/2 MMS-MCD OR - Application

 RTC as source 66

• Auto-wakeup interrupt triggers TIM21

• RTC ALARMA/B and RTC TAMP1/2 trigger LPTIM

 USB as source 67

• Start Of Frame triggers the Clock recovery System to trim HSI48

 GPIO as source 68

• TIM2/21/22 and LPTIMER can be triggered by GPIOs

• ADC conversion

• DAC conversion
 Thank you

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