Mandalam Anusha

Email : anusha.mandalam9@gmail.com
Mobile : 7989906993

Career Objective:

Seeking a challenging position as Physical Design Engineer to utilize my skills and knowledge in the field
of ASIC Design Implementation which offers professional growth while being innovative and resourceful.

Professional Experience Summary (Experience in Physical Design):

• Worked as Physical Design Trainee with Aricent Technologies, Bangalore from Mar 2018 to Feb 2019.
• Working as Physical Design Engineer with Altran Technologies, Bangalore from Mar 2019 to till date.

ASIC Skills:

● Hands on experience on complete Physical Design flow (Floorplan to GDS-II) that includes Inputs valida-
tion, Floor Planning, Placement, CTS and Routing stages.
● Hands on experience on block level implementation of Always-On and ON-OFF blocks.
● Hands on experience and well versed with Tools such as ICC, ICC2, PrimeTime, DC Compiler.
● Sound technical knowledge of Physical Design, CMOS Basics and MOSFET Physics.
● Understanding in analysis of timing reports for different timing paths in STA.
● Worked on low technology nodes like 10nm and 7nm.

Experience and Project Details:

Project # 1:
Role : Physical Design Trainee

Employer : Aricent Technology Holdings Ltd.

Client : AMD

Technology/Layers : 7nm/12 Metal Layers

Tools Used : ICC2, PrimeTime
Hard Macro Count : 84
Inst. Count : 800k+
Frequency : 1.8GHz
Roles and Responsibilities:
● Implemented PnR on two Always-On block designs which included Floorplan, Placement, CTS, Routing and
Timing closure.
● Running STA using PrimeTime and analyzing the reports causing the design issues.
● Analyzing timing/congestion issues in designs and fixing them through iterations.
● Reviewing missing constraints like clock definitions, IO constraints in SDC and giving feedback to FE Team.
● Implemented timing ECOs to fix timing and DRV violations by placing buffer and resizing the cells.
Project # 2:

Role : Physical Design Engineer

Employer : Altran Technologies

Client : NVIDIA
Technology : 10nm/14 Metal Layers
Tools : ICC2
BLOCK #1:
Hard Macro Count : 51

Inst. Count : 2.2M

Frequency : 800MHz
BLOCK #2:
Hard Macro Count : 55

Inst. Count : 2.4M

Frequency : 800MHz

Roles and Responsibilities:

● Responsible for all the aspects of PnR Flow for blocks covering Design setup, Floorplan, Placement, CTS
and Routing.
● Experimenting with different floorplan recipes to obtain designs with better optimizations and lesser DRC
violations.
● Collaborating with IR team to achieve a better optimized design while considering the power requirements.
● Debugging the issues to achieve better timing optimizations and DRVs in the design through different ap-
proaches.

Education:

• Advanced Diploma in ASIC Design – Physical Design in “RV-VLSI Design Center, Bangalore”, 2018.
• B.Tech in “Electronics and Communication Engineering”, 2017; JNTUA College of Engineering, Kalikiri.

Personal Details:

Date of Birth : 07/08/1996

Gender : Female
Marital Status : Unmarried
Nationality : Indian
Father’s name : M. Raja Sekhar
Languages Known : English, Telugu and Hindi
Declaration:

I do hereby declare that the particulars of information and facts stated herein above are true, correct and complete to
the best of my knowledge and belief.
Date:
Place: (M. ANUSHA)