Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

Digital Learning Handout

Course Title RECONFIGURABLE COMPUTING

Course No(s) ES ZG554 / MEL ZG554
Credit Units 5
Credit Model Theory + Laboratory Component
Content Author Pawan Sharma
Instructor-In-Charge Pawan Sharma

Course Description: The course covers introduction to various computing platforms. A detailed
study on reconfigurable architecture and programming reconfigurable systems; Mapping designs
to reconfigurable platforms; High level synthesis of reconfigurable systems; Reconfigurable
management; system case studies.

COURSE OBJECTIVES

CO1 Introduce various computing platforms

CO2 Introduce Reconfigurable Computing Architecture with emphasis on Field

Programmable Gate Array (FPGA)

CO3 Introduce design and implementation of algorithms in Reconfigurable hardware

CO4 Introduce reconfigurable computing system synthesis

CO5 Introduce Reconfiguration Management.

Text Book(s):
T1 Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications.
Christophe Bobda, Springer, 2007
T2 Scott Hauck, André DeHon, Reconfigurable Computing - The Theory and Practice of
FPGA Based Computation, The Morgan Kaufmann Series in Systems on Silicon, 2007.
Reference Book(s) & other resources:
R1 Wolf Wayne, FPGA Based System Design, Pearson Edu, 2004.
R2 Verilog HDL, Samir Palnitkar, Prentice Hall, 2003.
R3 R Vaidyanathan, Trahan Jerry, Dynamic Reconfiguration: Architectures and Algorithms, L,
Kluwer Academic, 2003.
R4 Xilinx, Altera and Microsemi Architecture reference manual
R5 Giovanni De Micheli, synthesis and optimization of digital circuits, Tata McGraw-Hill,
2003
R6 R. Druyer, L. Torres, P. Benoit, P. V. Bonzom and P. Le-Quere, "A survey on security features in
modern FPGAs," Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015 10th
International Symposium on, Bremen, 2015, pp. 1-8. doi: 10.1109/ReCoSoC.2015.7238102
https://www.altera.com/en_US/pdfs/literature/wp/wp-01111-anti-tamper.pdf
http://www.xilinx.com/support/documentation/white_papers/wp365_Solving_Security_Concerns.p
df
http://www.microsemi.com/document-portal/doc_view/132850-secure-architecture-in-
microsemi-fpgas-and-soc-fpgas-an-overview

COURSE OUTCOMES

NO Learning Outcomes. Knowledge in the following areas

LO1 Understand various computing platform, fundamentals of the reconfigurable computing

and reconfigurable architectures

LO2 Understand the state of the art reconfigurable computing architectures spanning fine
grained (look up table based processing elements) to coarse grained (arithmetic logic unit
level processing
elements) architectures.

LO3 Test Reconfigurable systems using HDL, CAD tool and FPGA boards and realize the
importance of the trade-offs involved in designing a reconfigurable computing platform
with a specific focus on the architecture of a configurable logic block and the
programmable interconnect

LO4 Read and present technical papers

Experiential Learning Components:

The Course would involve use of Xilinx Vivado software for carrying out the assignments. The software
may be accessed using the online lab resources provided by BITS, Pilani. The details would be shared
during the contact hours.

Content Structure:

Contact Hour List of Topic Title Sub-Topics Reference

 General Purpose Computing T1 Ch1
 Domain specific computing
Introduction
1-2  Application Specific Computing
 Reconfigurable Computing

An overview of programmable logic

 PLA T1 Ch1
Reconfigurable
3-4  PAL
Computing Hardware R3
 SPLD
 CPLD
 Modeling with HDLs R3
Hardware Description
Verilog
Languages and Logic
5-6  Combinational Network Delay,
Design
 Power and Energy Optimization

7-11 Reconfigurable FPGA Architecture, FPGA Fabrics T1 Ch2

Computing Architecture  SRAM Based-FPGAs R1 Ch3
 Permanently Programmed
FPGAs
 Programmable I/O
Circuit Design of FPGA Fabrics
Architecture of FPGA Fabrics, Case
Studies, Xilinx R5
Fine - Grained and Course - Grained
 Reconfigurable Architecture T1 Ch2

Logic Design Process T1 Ch3

 Design
 Integration
Programming  FPGA Design Flow
12-15 Reconfigurable Systems Implementation Approaches
 Run Time Reconfiguration
(RTR)
 Partial Reconfiguration (PR)

Logic Implementation for FPGAs, R1 Ch4

Syntax-Directed Translation
Logic Synthesis
Mapping Designs to  Two-Level Logic Synthesis
16-22 Reconfigurable Platform R5
 Multi-Level Logic Synthesis
 Technology Mapping R5 Ch10
 LUT-Based Technology T1 Ch3
Mapping
Modeling T1 Ch3
 DFG, CFG
Introduction to Binding, Scheduling and T1 Ch4
High-Level Synthesis Allocation, Temporal Partitioning
for Reconfigurable Temporal Partitioning Algorithms
23-27  ASAP
Devices
 ALAP
 List Scheduling
 Integer Linear Programming

Offline and Online Temporal Placement T1 Ch5

Temporal Placement
Routing Cost, Routing-Conscious
28-29 and Routing
Placement

Communication at run-time between T1 Ch6

Online Communication
30 modules on the Reconfigurable Device

31-32 Reconfiguration Configuration Architectures R2 Ch4

Management  Single Context
 Multi-Context FPGAs
 Pipeline and Block
Reconfigurable
Managing the Reconfiguration Process
 Configuration Grouping,
Caching and Scheduling
 Relocation and Defragmentation
 Context Switching
Reducing configuration Transfer Time
  Architectural Approach
 Configuration Compression
 Configuration Data Reuse

Laboratory Component:

Exp No. Experiment Title Reference to handout

module/section

1. Tutorial is to get familiar with Verilog and Xilinx

CAD tool introduction
Vivado tool.

2. Simple HDL design targeting the Zed Board Programming

using Vivado IDE reconfigurable systems

3. Demonstration of IP Integrator Mapping Designs to

Reconfigurable Platform
4. Using VIO (Virtual Input/Output) IP for Programming
debugging reconfigurable systems

5. Using ILA (Integrated Logic Analyzer) IP for Programming

debugging reconfigurable systems

6. Creating a MAC Using the Xilinx System

Mapping Designs to
Generator and Implementation on Hardware Reconfigurable Platform
7. Vivado HLS High-Level Synthesis for
Reconfigurable Devices
8. Programming
FPGA-based System Design using FSM
reconfigurable systems

9. Designing FIR filter using the Vivado System Mapping Designs to

Generator’s FIR and FDA Tool blocks. Reconfigurable Platform
Evaluation Scheme:

Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session

Evaluation Name Type Weight Duration Day, Date, Session, Time
Component
EC-1 Assignment 1 Online 10% - August 16-30, 2021
Assignment-II Online 15% - October 16-30, 2021
Mid-Semester Open 30% 2 hours Saturday, 25/09/2021 (AN)
EC-2 Test Book 2 PM – 4 PM
Comprehensive Open 45% 2 hours Saturday, 13/11/2021 (AN)
EC-3 Exam Book 2 PM – 4 PM

Syllabus for Mid-Semester Test (Open Book): Topics in Session Nos. 1 to 15

Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 32
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the
latest announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the
Elearn portal.

Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Students will attempt them
through the course pages on the Elearn portal. Announcements will be made on the
portal, in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: Use of books and any printed / written reference material (filed or
bound) is permitted. However, loose sheets of paper will not be allowed. Use of
calculators is permitted in all exams. Laptops/Mobiles of any kind are not allowed.
Exchange of any material is not allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam which will be
made available on the Elearn portal. The Make-Up Test/Exam will be conducted only at
selected exam centres on the dates to be announced later.

It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the online lectures, and take all the prescribed
evaluation components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam
according to the evaluation scheme provided in the handout.