INTERFACE

interface intif();

logic i0;

logic i1;

logic s;

logic y;

modport mux_dut(input i0,i1,s,output y);

endinterface

/////DUT/////

module mux_dut(intif inf);

assign inf.y=((inf.s==0)?inf.i0:inf.i1);

endmodule

////SEQUENCE ITEM

`ifndef _seqit_

`define _seqit_

class mux_seq_item extends uvm_sequence_item;

`uvm_object_utils(mux_seq_item)

rand bit i0;

rand bit i1;

rand bit s;

bit y;

function new(string name="mux_seq_item");

super.new(name);

endfunction

endclass

`endif
////SEQUENCE

`ifndef _seq_

`define _seq_

class mux_seq extends uvm_sequence #(mux_seq_item);

`uvm_object_utils(mux_seq)

mux_seq_item pkt;

function new(string name="mux_seq");

super.new(name);

endfunction

task body();

pkt=mux_seq_item::type_id::create("pkt"); //memory creating through factory

repeat(10)

begin

start_item(pkt); //stimulus generating

assert(pkt.randomize());

//pkt.print();//stimulus randomizing

finish_item(pkt);// stimulus completed

`uvm_info("seq","seq TRANSACTIONS",UVM_NONE);

$display("pkt=%d",pkt);

end

endtask

endclass
`endif

//////SEQUENCER/////

`ifndef _seqr_

`define _seqr_

class mux_seqr extends uvm_sequencer #(mux_seq_item);

`uvm_component_utils(mux_seqr) //registering with factory

function new(string name="mux_seqr",uvm_component parent); //constructor

super.new(name,parent);

endfunction

`endif

/////DRIVER

`ifndef _drv_

`define _drv_

class mux_driver extends uvm_driver#(mux_seq_item);

`uvm_component_utils(mux_driver)

mux_seq_item pkt;

virtual intif inf;

function new(string name="mux_driver",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase (uvm_phase phase);

super.build_phase(phase);

uvm_config_db #(virtual intif )::get(this,"","inf",inf);

endfunction

task run_phase(uvm_phase phase);

forever
 begin

pkt = mux_seq_item::type_id::create("seq");

seq_item_port.get_next_item(pkt);

inf.a=pkt.a;

inf.b=pkt.b;

inf.s=pkt.s;

#5;

//$display("drv::pkt=%d",pkt);

//`uvm_info("DRV","DRV TRANSACTION TO DUT",UVM_NONE);

seq_item_port.item_done();

end

endtask

endclass

`endif

////MONITOR 1

`ifndef _mon1_

`define _mon1_

class mux_mon1 extends uvm_monitor;

`uvm_component_utils(mux_mon1)

mux_seq_item pkt;

virtual intif inf;

uvm_analysis_port #(mux_seq_item)item_collected_port;

function new(string name="mux_mon1",uvm_component parent);

super.new(name,parent);
item_collected_port=new("item_collected_port",this);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db #(virtual intif)::get(this,"","inf",inf);

endfunction

task run_phase(uvm_phase phase);

pkt=mux_seq_item::type_id::create("pkt");

forever

begin

#2;

pkt.i0=inf.i0;

pkt.i1=inf.i1;

pkt.s=inf.s;

`uvm_info("MON1","MON1 TRANSACTIONS",UVM_NONE);

item_collected_port.write(pkt);

end

endtask

endclass

`endif

///MONITOR 2
`ifndef _mon2_

`define _mon2_

class mux_mon2 extends uvm_monitor;

`uvm_component_utils(mux_mon2)

mux_seq_item pkt1;

virtual intif inf;

uvm_analysis_port #(mux_seq_item)item_collected_port1;

function new(string name="mon2",uvm_component parent);

super.new(name,parent);

item_collected_port1=new("item_collected_port1",this);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

uvm_config_db #(virtual intif)::get(this,"","inf",inf);

endfunction

task run_phase(uvm_phase phase);

pkt1=mux_seq_item::type_id::create("pkt1");

forever

begin

#2;
pkt1.y=inf.y;

//$display($time,"mon2::::::::pkt1=%d",pkt1);

//`uvm_info("MON2","MON2 TRANSACTIONS",UVM_NONE);

item_collected_port1.write(pkt1);

end

endtask

endclass

`endif

////AGENT1

`ifndef _ag1_

`define _ag1_

class mux_agent1 extends uvm_agent;

`uvm_component_utils(mux_agent1)

mux_seqr seqr;

mux_driver drv;

mux_mon1 mon1;

function new(string name="mux_agent1",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

seqr=mux_seqr::type_id::create("seqr",this);

drv=mux_driver::type_id::create("drv",this);
mon1=mux_mon1::type_id::create("mon1",this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

drv.seq_item_port.connect(seqr.seq_item_export);

endfunction

endclass

`endif

//////AGENT2//////

`ifndef _ag2_

`define _ag2_

class mux_agent2 extends uvm_agent;

`uvm_component_utils(mux_agent2)

mux_mon2 mon2;

function new(string name="mux_agent2",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

mon2=mux_mon2::type_id::create("mon2",this);

endfunction

endclass
`endif

////SCOREBOARD

`ifndef _sb_

`define _sb_

class mux_sb extends uvm_scoreboard;

`uvm_component_utils(mux_sb);

mux_seq_item pkt,pkt1;

uvm_tlm_analysis_fifo #(mux_seq_item)ip_fifo;

uvm_tlm_analysis_fifo #(mux_seq_item)op_fifo;

function new(string name="mux_sb",uvm_component parent);

super.new(name,parent);

ip_fifo=new("ip_fifo",this);

op_fifo=new("op_fifo",this);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

pkt=mux_seq_item::type_id::create("pkt",this);

pkt1=mux_seq_item::type_id::create("pkt1",this);

endfunction

task run_phase(uvm_phase phase);

forever

begin
fork

ip_fifo.get(pkt);

// `uvm_info("SB","PKT TRANSACTIONS FROM MONITOR 1",UVM_NONE);

op_fifo.get(pkt1);

// `uvm_info("SB","PKT TRANSACTIONS FROM MONITOR 2",UVM_NONE);

join

if(pkt1.y==((pkt.s==0)?pkt.i0:pkt.i1))

begin

`uvm_info("SB",$sformatf (" DATA MATCHED OUTPUT_ y=%d, input_pkt.i0=%d, input_pkt.i1=%d,pkt.s=

%d",pkt1.y, pkt.i0, pkt.i1,pkt.s),UVM_NONE);

end

else

begin

`uvm_info("SB",$sformatf (" DATA NOT MATCHED OUTPUT_ y=%d, input_pkt.i0=%d, input_pkt.i1=

%d,pkt.s=%d",pkt1.y, pkt.i0, pkt.i1.pkt.s),UVM_NONE);

end

end

endtask

endclass

`endif
////////ENVIRONMENT/////

`ifndef _env_

`define _env_

class mux_env extends uvm_env;

`uvm_component_utils(mux_env)

mux_agent1 agent1;

mux_agent2 agent2;

mux_sb sb;

function new(string name="mux_env",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

agent1=mux_agent1::type_id::create("agent1",this);

agent2=mux_agent2::type_id::create("agent2",this);

sb=mux_sb::type_id::create("sb",this);

endfunction

virtual function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

agent1.mon1.item_collected_port.connect(sb.ip_fifo.analysis_export);

agent2.mon2.item_collected_port1.connect(sb.op_fifo.analysis_export);

endfunction

endclass
`endif

////TEST///

`ifndef _test_

`define _test_

class mux_test extends uvm_test;

`uvm_component_utils(mux_test)

mux_env env;

function new(string name="mux_test",uvm_component parent);

super.new(name,parent);

endfunction

virtual function void build_phase(uvm_phase phase);

super.build_phase(phase);

env=mux_env::type_id::create("env",this);

endfunction

task run_phase(uvm_phase phase);

mux_seq seq;

seq=mux_seq::type_id::create("seq",this);

phase.raise_objection(this);

seq.start(env.agent1.seqr);

#1000;

phase.drop_objection(this);

endtask

endclass
`endif

//////////TOP////////////

import uvm_pkg::*;

`include "uvm_macros.svh"

`include "MUX_interface.sv"

//`include "DESIGN.sv"

`include "MUX_dut.sv"

`include "MUX_sequence_item.sv"

`include "mux_sequence.sv"

`include "MUX_sequencer.sv"

`include "MUX_driver.sv"

`include "MUX_monitor1.sv"

`include "MUX_monitor2.sv"

`include "MUX_agent1.sv"

`include "MUX_agent2.sv"

`include "MUX_sb.sv"

`include "MUX_envmt.sv"

`include "MUX_test.sv"

module mux_top();

intif inf();

mux_dut dut(inf);

initial

begin

uvm_config_db#(virtual intif) :: set(uvm_root::get(),"*","inf",inf);

run_test();

end

endmodule