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STF5N52U
N-channel 525 V, 1.28 Ω, 4.4 A, DPAK, TO-220FP
UltraFASTmesh™ Power MOSFET
Features
RDS(on)
Type VDSS ID Pw
max
STD5N52U 525 V < 1.5 Ω 4.4 A 70 W
STF5N52U 525 V < 1.5 Ω 4.4 A 25 W
3 3
■ 100% avalanche tested 1 1
2
Description G(1)
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ......................... 6
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Electrical ratings
2 Electrical characteristics
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0 525 V
breakdown voltage
Zero gate voltage VDS = Max rating 10 µA
IDSS
drain current (VGS = 0) VDS = Max rating, TC=125 °C 500 µA
Gate-body leakage
IGSS VGS = ± 20 V 10 µA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
Static drain-source on
RDS(on) VGS = 10 V, ID = 2.2 A 1.28 1.5 Ω
resistance
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Ciss 529 pF
Output capacitance VDS = 25 V, f = 1 MHz,
Coss - 71 - pF
Reverse transfer VGS = 0
Crss 13.4 pF
capacitance
Equivalent
Co(tr)(1) capacitance time VDS = 0 to 420 V, VGS = 0 - 11 - pF
related
Rg Gate input resistance f=1 MHz open drain - 6 - Ω
Qg Total gate charge VDD = 416 V, ID = 4.4 A, 16.9 nC
Qgs Gate-source charge VGS = 10 V - 4.2 - nC
Qgd Gate-drain charge (see Figure 17) 8.4 nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
Gate-source breakdown
BVGSO Igs=± 1 mA (open drain) 30 - - V
voltage
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Figure 4. Safe operating area for DPAK Figure 5. Thermal impedance for DPAK
Figure 12. Normalized gate threshold voltage Figure 13. Normalized on resistance vs
vs temperature temperature
Figure 14. Source-drain diode forward Figure 15. Maximum avalanche energy vs
characteristics temperature
3 Test circuits
Figure 16. Switching times test circuit for Figure 17. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
µF µF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. µF 2.7kΩ VG
PW
47kΩ
PW 1kΩ
AM01468v1 AM01469v1
Figure 18. Test circuit for inductive load Figure 19. Unclamped inductive load test
switching and diode recovery times circuit
L
A A A
D
FAST L=100µH VD
G D.U.T. DIODE 2200 3.3
µF µF VDD
S B 3.3 1000
B B µF µF
25 Ω VDD ID
D
RG S
Vi D.U.T.
Pw
AM01470v1 AM01471v1
Figure 20. Unclamped inductive waveform Figure 21. Switching time waveform
90% 90%
IDM
10%
ID 10% VDS
0
mm.
DIM.
min. ty p ma x .
A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.64 0.90
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 5.10
E 6.40 6.60
E1 4. 70
e 2.28
e1 4.40 4.60
H 9.35 10.10
L 1
L1 2.80
L2 0.80
L4 0.60 1
R 0.20
V2 0o 8o
0068772_G
mm
Dim.
Min. Typ. Max.
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
F1 1.15 1.70
F2 1.15 1.5
G 4.95 5.2
G1 2.4 2.7
H 10 10.4
L2 16
L3 28.6 30.6
L4 9.8 10.6
L5 2.9 3.6
L6 15.9 16.4
L7 9 9.3
Dia 3 3.2
L7
E
A
B
D
Dia
L6 L5
F1 F2
F
H G
G1
L2 L4
L3
7012510_Rev_J
DPAK FOOTPRINT
6 Revision history
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