Fig. 8.

1 Definition of gm using transfer characteristic

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.2 Calculating gm at various bias points

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.3 Plot of gm versus VGS.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.4 Plot of gm versus VGS for a JFET with IDSS = 8 mA and VP = -4 V.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.5 Plot of gm versus ID for a JFET with IDSS = 8 mA and VGS = -4 V.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.6 Definition of rd using FET drain characteristics.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.7 Drain characteristics used to calculate rd in Example 8.5.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.8 FET ac equivalent circuit.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.9 FET ac equivalent model for Example 8.6

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.10 JFET fixed-bias configuration.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.11 Substituting the JFET ac equivalent circuit unit into the network of Fig. 8.10

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.12 Redrawn network of Fig. 8.11

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.13 Determining Zo

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.14 JFET configuration for Example 8.7

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.15 Self-bias JFET configuration.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.16 Network of Fig. 8.15 following the substitution of the JFET ac
equivalent circuit.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.17 Redrawn network of Fig. 8.16.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.18 Self-bias JFET configuration including the effects of RS with rd = ∞ Ω.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.19 Including the effects of rd in the self-bias JFET configuration.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.20 Network for Example 8.8.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.22 JFET voltage-divider configuration.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.23 Network of Fig. 8.22 under ac conditions.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.24 Redrawn network of Fig. 8.23.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.25 JFET source-follower configuration.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.26 Network of Fig. 8.25 following the substitution of the JFET ac
equivalent model.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.27 Network of Fig. 8.26 redrawn.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.28 Determining Zo for the network of Fig. 8.25.

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Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.29 Network to be analyzed in Example 8.9.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.30 JFET common-gate configuration.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
Fig. 8.31 Network of Fig. 8.30 following substitution of JFET ac equivalent model.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.32 Determining Z'i for the network of Fig. 8.30.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.33 Network for Example 8.10.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.34 D-MOSFET ac equivalent model

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.35 Network for Example 8.11.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.36 AC equivalent circuit for Fig. 8.35.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.37 Enhancement MOSFET ac small-signal model.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.38 E-MOSFET drain-feedback configuration.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.39 AC equivalent of the network of Fig. 8.38.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.40 Determining Zo for the network of Fig. 8.38.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.41 Drain-feedback amplifier from Example 8.11.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.42 E-MOSFET voltage-divider configuration.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.43 AC equivalent network for the configuration of Fig. 8.42.

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Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.44 Circuit for desired voltage gain in Example 8.13.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.45 Network for desired voltage gain in Example 8.14.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.46 JFET amplifier with Rsig and RL.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.
 Fig. 8.47 Network of Fig. 8.46 following the substitution of the ac equivalent
circuit for the JFET.

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Robert L. Boylestad
Upper Saddle River, New Jersey 07458
Electronic Devices and Circuit Theory, 9e All rights reserved.