FET Biasing: Dr. Talal Skaik

Islamic University of Gaza
Chapter 7:
FET Biasing Dr. Talal Skaik
Basic Current Relationships
For all FETs:

I G  0A
I D  IS
For JFETS and D-Type MOSFETs:

2
 VGS 

I D  I DSS  1  
 VP 
For E-Type MOSFETs:
I D  k ( VGS  VT ) 2
Electronic Devices and Circuit Theory, 10/e 2 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
Fixed-Bias Configuration
I G  0A
V DS V DD  I D R D
V S  0, V D V DS , V GS  V GG
2
 V GS 
I D  I DSS 1   Network for dc analysis.
 Vp 
Fixed-Bias Configuration –Graphical Solution
2
 V GS 
I D  I DSS 1  
 Vp 
Finding the solution for the

Plotting Shockley’s equation. fixed-bias configuration.
Example 7.1
Find VGSQ, IDQ, VDS, VD, VG, VS.
Example 7.1 - graphical solution
Self-Bias Configuration
DC analysis of the self-bias

configuration.
Self-Bias Configuration
V GS  I D R S
2
 V GS 
I D  I DSS 1  
 Vp 
2
 I D R S 
I D  I DSS 1  
 Vp 
2
 I D RS 
I D  I DSS 1  
 Vp 

By squaring and rearranging, I D has the form:
I D2  k 1I D  k 2  0 [Solve for I D ] DC analysis of the self-bias
configuration.
Self-Bias Configuration – graphical solution
•Sketch the transfer curve.
•Draw the line:
VGS  I D R S
•The Q-point is located where

the line intersects the transfer
curve.
•Use the value of ID at the Q-
point (IDQ) to solve for the
other voltages:
V DS V DD  I D (R S  R D )
V S  I D RS
V D V DS V S
Example 7.2
Find VGSQ, IDQ, VDS, VD, VG, VS.
Solution
Draw the line: VGS  I D R S
Example 7.2 - solution
Sketching the device Determining the Q-point

characteristics for the JFET for the network.
Voltage-Divider Bias
IG = 0 A
IR1=IR2 Redrawn network for dc analysis.
VG is equal to the voltage across
divider resistor R2:
R 2 VDD
VG 
R1  R 2
Using Kirchhoff’s Law:

VGS  VG  I D R S
The Q point is established by

plotting a line that intersects the
transfer curve.
Step 1 VGS  VG  I D R S
Plot the line by plotting two
points:
•VGS = VG, ID = 0 A
•VGS = 0 V, ID = VG / RS
Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values
of ID
Step 3
The Q-point is located where the
line intersects the transfer curve
Effect of RS on the resulting Q-point.

Using the value of ID at the Q-point, solve for the other variables in
the voltage-divider bias circuit:
VDS  VDD  I D (R D  R S )
VD  VDD  I D R D
VS  I D R S
VDD
I R1  I R2 
R1  R 2
Example 7.5 Find VGSQ, IDQ, VDS, VD, VG, VS.
D-Type MOSFET Bias Circuits
Depletion-type MOSFET
bias circuits are similar to
those used to bias JFETs.
The only difference is that
depletion-type MOSFETs
can operate with positive
values of VGS and with ID
values that exceed IDSS.
Example 7.7 Find VGSQ, IDQ, VDS
Step 1
Plot the line for
•VGS = VG, ID = 0 A
•ID = VG/RS, VGS = 0 V
Step 2
Plot the transfer curve using IDSS, VP and
calculated values of ID.
Step 3
The Q-point is located where the line
intersects the transfer curve is. Use the ID at R 2 VDD
the Q-point to solve for the other variables in VG 
R1  R 2
the voltage-divider bias circuit.
These are the same steps used to VGS  VG  I D R S

analyze JFET voltage-divider bias
circuits.
Example 7.7 - Solution
For V GS  1V
2
 V GS   1 
2
I D  I DSS 1  =6mA 1    10.67mA

 V p   3 
 
10M (18V )
VG   1.5V V GS  1.5V  I D (750)
10M  110M
R 2 VDD
VG  VGS  VG  I D R S
R1  R 2
Example 7.9 Find VGSQ, IDQ, VD
To plot line V GS  I D R S :
I D  V GS / R S
For V GS  6, I D  (6) / 2.4k  2.5mA
To plot transfer curve for VGS =+2V:
2
 V GS   2 
2
I D  I DSS 1   =8m 1    12.5mA

 Vp   8 
E-Type MOSFET Bias Circuits
The transfer characteristic for

the e-type MOSFET is very
different from that of a simple
JFET or the d-type MOSFET.
I D  k V GS V GS (Th ) 
2
Feedback Bias Circuit
IG = 0 A
VRG = 0 V
VDS = VGS DC equivalent of the network
VGS = VDD – IDRD
Feedback Bias Q-Point
Step 1
Plot the line using
•VGS = VDD, ID = 0 A
•ID = VDD / RD , VGS = 0 V
Step 2
Using values from the specification
sheet, plot the transfer curve with
•VGSTh , ID = 0 A
•VGS(on), ID(on)
Step 3
The Q-point is located where the VGS = VDD – IDRD
line and the transfer curve intersect
Step 4
Using the value of ID at the Q-
point, solve for the other variables
in the bias circuit.
Example 7.11 Find VGSQ, IDQ
Plot Transfer Curve:
I D  k V GS V GS (Th )   0.24 10 V GS  3
2 3 2
I D (on )
k 
V V GS (Th ) 
2
GS (on )
6mA
k   0.24 103
 8  3
2
Example 7.11 - solution
Plot the line : VGS = VDD – IDRD
VGS = 12 – ID(2k)
Voltage-Divider Biasing
Plot the line and the transfer curve to find

the Q-point. Use these equations:
R 2 VDD
VG 
R1  R 2
VDS  VDD  I D ( R S  R D )
Example 7.12 Find VGSQ, IDQ
I D (on )
k 
V V GS (Th ) 
2
GS (on )
3mA
k   0.12 103
10  5
2
I D  k V GS V GS (Th ) 
2
I D  0.12 10 V GS  5 3 2
18M (40V )
VG   18V
22M  18M
V GS V G  I D R S
V GS  18V  I D (0.82k )
Example 7.12 - Solution
I D  0.12 10 V GS  5 3 2
V GS  18V  I D (0.82k )

FET Biasing: Dr. Talal Skaik

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FET Biasing: Dr. Talal Skaik

Uploaded by

Copyright:

Available Formats

Islamic University of Gaza

For all FETs:

For JFETS and D-Type MOSFETs:

For E-Type MOSFETs:

Finding the solution for the

DC analysis of the self-bias

•The Q-point is located where

Sketching the device Determining the Q-point

Using Kirchhoff’s Law:

The Q point is established by

Effect of RS on the resulting Q-point.

These are the same steps used to VGS  VG  I D R S

I D  I DSS 1  =6mA 1    10.67mA

I D  I DSS 1   =8m 1    12.5mA

The transfer characteristic for

Plot the line and the transfer curve to find

You might also like