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A1126 Datasheet
A1126 Datasheet
VCC VOUT
Omnipolar
Dynamic Offset Cancellation
Control
Switchpoints
Signal Current
Amplifier
Recovery Limit
GND
DESCRIPTION (CONTINUED)
manufacturers to orient their magnets. These devices allow simple a miniature low-profile surface-mount package, while package
on/off switching in industrial, consumer, and automotive applications. UA is a three-lead ultra-mini SIP for through-hole mounting. Each
package is lead (Pb) free, with 100% matte-tin-plated leadframe.
The A1126 is rated for operation between the ambient temperatures
–40°C to 150°C. The available package styles provide magnetically
optimized solutions for most applications. Package LH is an SOT23W,
SELECTION GUIDE
Part Number Packing [1] Package
A1126LLHLT-T [2] 3,000 pieces per reel 3-pin SOT-23W surface mount
A1126LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount
A1126LUA-T [3] 500 pieces per bag 3-pin ultramini SIP through-hole mount
1 Contact Allegro™ for additional packing options
2 Available
through authorized Allegro distributors only.
3 The chopper-style UA package is not for new design; the matrix HD style UA package is recommended for new designs.
Pinout Diagrams
3 Terminal List Table
Number
Name Function
LH UA
VCC 1 1 Connects power supply to chip
GND 3 2 Ground
1 2 1 2 3
LH Package UA Package
3-Pin SOT23W 3-Pin SIP
OPERATING CHARACTERISTICS: Valid through TA and VCC ranges, TJ < TJ(max), CBYP = 0.1 µF, unless otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Unit [1]
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC Operating, TJ < 165°C 3 – 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRPS – – 10 µA
Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 185 500 mV
Output Current Limit IOM B > BOP 30 – 60 mA
Power-On Time [2][3] tPO – – 25 µs
Chopping Frequency fC – 800 – kHz
Output Rise Time [3][4] tr RLOAD = 820 Ω, CS = 20 pF – 0.2 2 µs
Output Fall Time [3][4] tf RLOAD = 820 Ω, CS = 20 pF – 0.1 2 µs
ICC(ON) B > BOP , VCC = 12 V – – 4 mA
Supply Current
ICC(OFF) B < BRP , VCC = 12 V – – 4 mA
Supply Zener Clamp Voltage VZ ICC = 6.5 mA; TA = 25°C 28 – – V
Supply Zener Current IZSUPPLY VS = 28 V – – 6.5 mA
MAGNETIC CHARACTERISTICS
BOPS South pole adjacent to branded face 15 38 55 G
Operate Point
BOPN North pole adjacent to branded face –55 –38 –15 G
BRPS South pole adjacent to branded face 5 20 50 G
Release Point
BRPN North pole adjacent to branded face –50 –20 –5 G
Hysteresis BHYS | BOPS – BRPS |, | BOPN – BRPN | 5 – 30 G
Characteristic Performance
Average Supply Current (On) versus Temperature Average Supply Current (On) versus Supply Voltage
4.0 4.0
Supply Current, ICC(ON) (mA)
2.5 2.5
VCC = 3.0 V TA = 25°C
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Supply Current (Off) versus Temperature Average Supply Current (Off) versus Supply Voltage
4.0 4.0
Supply Current, ICC(OFF) (mA)
3.5 3.5
3.0 3.0
TA = 150°C
VCC = 24 V TA = –40°C
2.5 2.5
2.0 2.0
VCC = 3.0 V
TA = 25°C
1.5 1.5
1.0 1.0
0.5 0.5
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Operate Point (South) versus Temperature Average Operate Point (South) versus Supply Voltage
55 55
50 50
Applied Flux Density (G)
40 40
TA = –40°C TA = 150°C
35 35
VCC = 3.0 V
30 30
VCC = 24 V TA = 25°C
25 25
20 20
15 15
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Release Point (South) versus Temperature Average Release Point (South) versus Supply Voltage
50 50
45 45
Applied Flux Density (G)
40 40
Release Point (BRP)
35 35
30 30
25 25 TA = 150°C
TA = –40°C
VCC = 3.0 V
20 20
15 VCC = 24 V 15
TA = 25°C
10 10
5 5
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Operate Point (North) versus Temperature Average Operate Point (North) versus Supply Voltage
–15 –15
–20 –20
Applied Flux Density (G)
–45 –45
–50 –50
–55 –55
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Release Point (North) versus Temperature Average Release Point (North) versus Supply Voltage
–5 –5
–10 –10
Applied Flux Density (G)
TA = –40°C
–15 –15
Release Point (BRP)
VCC = 24 V
–20 –20 TA = 25°C
VCC = 3.0 V
–25 –25
TA = 150°C
–30 –30
–35 –35
–40 –40
–45 –45
–50 –50
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Hysteresis (South) versus Temperature Average Hysteresis (South) versus Supply Voltage
30 30
Switchpoint Hysteresis (BHYS)
20 20
TA = –40°C TA = 25°C
15 15
VCC = 3.0 V
VCC = 24 V
10 10
TA = 150°C
5 5
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
Average Hysteresis (North) versus Temperature Average Hysteresis (North) versus Supply Voltage
30 30
Switchpoint Hysteresis (BHYS)
25 25
20 20
TA = –40°C
15 VCC = 24 V 15
5 5
-60 -40 -20 0 20 40 60 80 100 120 140 160 0 5 10 15 20 25
400
VOUT(SAT), (mV)
350
300
250
200
150
100
50
0
-60 -40 -20 0 20 40 60 80 100 120 140 160
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side con-
Package Thermal Resistance RθJA 110 °C/W
nected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
25
24 VCC(max)
23
22
Maximum Allowable VCC (V)
21
20
19
18
17
16
15
14
13
12
2-layer PCB, Package LH
11 (RθJA = 110 ºC/W)
10
9 1-layer PCB, Package UA
8 (RθJA = 165 ºC/W)
7
6 1-layer PCB, Package LH
5 (RθJA = 228 ºC/W)
4 VCC(min)
3
2
20 40 60 80 100 120 140 160 180
Temperature (ºC)
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (m W)
1200 2-
l
1100 (R aye
θJ rP
A = C
1000 11 B, P
1-la 0 º ac
900 y C/ ka
(R er PC W
) ge L
800 θJA = B H
165 , Pac
700 ºC/ k a
W) ge U
600 A
500 1-lay
400 er P
(R CB,
300 θJA =
228 Packag
ºC/W e LH
200 )
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)
FUNCTIONAL DESCRIPTION
The output of these devices switches low (turns on) when a ing of the output even in the presence of external mechanical
magnetic field perpendicular to the Hall sensor chip exceeds the vibration and electrical noise.
operate point threshold, BOPx . After turn-on, the output voltage
In the case of omnipolar switch devices, removal of the magnetic
is VOUT(SAT) . The output transistor is capable of sinking current
field results in the device output high (off).
up to the short circuit current limit, IOM , which is a minimum
of 30 mA. When the magnetic field is reduced below the release Powering-on the device in the hysteresis range (less than BOPx
point, BRPx , the device output goes high (turns off). The differ- and greater than BRPx ) will allow an indeterminate output state.
ence in the magnetic operate and release points is the hysteresis, The correct state is attained after the first excursion beyond BOPx
BHYS , of the device. This built-in hysteresis allows clean switch- or BRPx .
V+
VS
Switch to High
Switch to High
Switch to Low
Switch to Low
VOUT
VOUT(SAT)
0
B– 0 B+
BOPN
BRPN
BOPS
BRPS
BHYS BHYS
APPLICATION INFORMATION
V+
VCC RLOAD
A1126
CBYPASS VOUT
0.1 µF
GND
When using Hall-effect technology, a limiting factor for baseband, while the DC offset becomes a high-frequency signal.
switchpoint accuracy is the small signal voltage developed across The magnetic-sourced signal then can pass through a low-pass
the Hall element. This voltage is disproportionally small relative filter, while the modulated DC offset is suppressed. The chop-
to the offset that can be produced at the output of the Hall sensor per stabilization technique uses a 400 kHz high frequency clock.
chip. This makes it difficult to process the signal while main- For demodulation process, a sample-and-hold technique is used,
taining an accurate, reliable output over the specified operating where the sampling is performed at twice the chopper frequency.
temperature and voltage ranges. Chopper stabilization is a unique
This high-frequency operation allows a greater sampling rate,
approach used to minimize Hall offset on the chip. The Allegro
which results in higher accuracy and faster signal-processing
technique, namely Dynamic Quadrature Offset Cancellation,
capability. This approach desensitizes the chip to the effects
removes key sources of the output drift induced by thermal and
mechanical stresses. This offset reduction technique is based on of thermal and mechanical stresses, and produces devices that
a signal modulation-demodulation process. The undesired offset have extremely stable quiescent Hall output voltages and precise
signal is separated from the magnetic field-induced signal in the recoverability after temperature cycling. This technique is made
frequency domain, through modulation. The subsequent demodu- possible through the use of a BiCMOS process, which allows the
lation acts as a modulation process for the offset, causing the use of low-offset, low-noise amplifiers in combination with high-
magnetic field-induced signal to recover its original spectrum at density logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold
Amp
Power Derating
The device must be operated below the maximum junction Example: Reliability for VCC at TA = 150°C, package UA, using a
temperature of the device, TJ(max) . Under certain combina- single-layer PCB.
tions of peak conditions, reliable operation may require derating
Observe the worst-case ratings for the device, specifically:
supplied power or improving the heat dissipation properties of
RθJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V, and
the application. This section presents a procedure for correlating
ICC(max) = 4 mA.
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.) Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
heat from the junction (die), through all paths to the ambient air.
This provides the allowable increase to TJ resulting from internal
Its primary component is the Effective Thermal Conductivity,
power dissipation. Then, invert equation 2:
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RθJC, is PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by Finally, invert equation 1 with respect to voltage:
overmolding. VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 4 mA = 23 V
The effect of varying power levels (Power Dissipation, PD), can The result indicates that, at TA, the application and device can
be estimated. The following formulas represent the fundamental dissipate adequate amounts of heat at voltages ≤VCC(est) .
relationships used to estimate TJ, at PD. Compare VCC(est) to VCC(max) . If VCC(est) ≤ VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
PD = VIN × IIN (1) enhanced RθJA. If VCC(est) ≥ VCC(max) , then operation
ΔT = PD × RθJA (2) between VCC(est) and VCC(max) is reliable under these condi-
tions.
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RθJA = 140°C/W, then:
PD = VIN × IIN = 12 V × 4 mA = 48 mW
+0.12
2.98 –0.08
1.49 D
4°±4°
3 A
+0.020
0.180–0.053
0.96 D
1.00
1 2
1.00 ±0.13
NNN
+0.10 1
0.05 –0.05
0.95 BSC C Standard Branding Reference View
0.40 ±0.10
N = Last three digits of device part number
For Reference Only; not for tooling use (reference DWG-2840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Active Area Depth, 0.28 mm REF
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
+0.08
4.09 –0.05
45°
B
E C
2.04
1.52 ±0.05
10°
E 1.44 Mold Ejector
E
+0.08 Pin Indent
3.02 –0.05
Branded 45°
Face
0.79 REF
A NNN
1.02
MAX
1
1 2 3 D Standard Branding Reference View
= Supplier emblem
N = Last three digits of device part number
1.27 NOM
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
+0.08 Pin Indent NNN
3.02 –0.05
E
Branded 45°
Face 1
2.16 D Standard Branding Reference View
MAX
= Supplier emblem
0.79 REF N = Last three digits of device part number
NOT FOR
A
0.51
REF
NEW DESIGN
1 2 3
Revision History
Number Date Description
1 September 16, 2013 Update UA package drawing
2 September 21, 2015 Added AEC-Q100 qualification under Features and Benefits
3 October 28, 2016 Chopper-style UA package designated as not for new design