Silterra 18 RVT

Titlepage
Silterra Malaysia Sdn. Bhd. 0.18 µm Process

1.8-Volt SAGE-X TM v1.0
Standard Cell Library
Databook
March 2004
Release 3.0
Copyright  1993-2004 Artisan Components, Inc. All rights reserved.
Printed in the United States of America.
Part Number DB-SX-SLT004-3.0/18
Artisan Components, Artisan, and Process-Perfect are registered trademarks of Artisan Components,
Inc., in the United States. Accelerated Retention Test, ArtNuvo, ElectroArt, Extra Margin Adjustment,
Flex-Repair, SAGE, SAGE-HS, SAGE-X, and SAGE-Modeler, are trademarks of Artisan Components,
Inc. Artisan acknowledges the trademarks of other organizations for their respective products or services
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Unpublished – rights reserved under the copyright laws of the United States.
Table of Contents
Preface
Revision History ........................................................................................................................................ ix

Customer Support ...................................................................................................................................... ix
Introduction
How This Book Is Organized ....................................................................................................................11

Global Parameters......................................................................................................................................11
Physical Specifications .....................................................................................................12
Propagation Delay and Transition Time ...........................................................................13
Derating Factors ................................................................................................................14
Delay Calculation ..............................................................................................................14
Timing Constraints ...........................................................................................................15
Setup Time ........................................................................................................................15
Hold Time .........................................................................................................................16
Recovery Time ..................................................................................................................17
Minimum Pulse Width ......................................................................................................17
Power Dissipation .............................................................................................................18
Power Calculation .............................................................................................................18
Power-Rail Strapping ........................................................................................................21
Adding Routing Channels .................................................................................................22
Special Cells...............................................................................................................................................23
Antenna-Fix Cell ...............................................................................................................23
Fill Cells ............................................................................................................................23
Low-Power (XL) Cells .....................................................................................................24
TIEHI/LO Cells ................................................................................................................24
Delay Cells ........................................................................................................................24
Reading the Standard Cell Datasheet.........................................................................................................24
1. Base Cell Name .............................................................................................................24
2. Cell Description ............................................................................................................25
3. Functions .......................................................................................................................25
4. Logic Symbol ................................................................................................................25
5. Cell Size ........................................................................................................................25
Silterra Malaysia Sdn. Bhd. 0.18um Process SAGE-X v1.0 Standard Cell Library Databook
iii
Table of Contents
6. Functional Schematic ....................................................................................................25

7. Drive Strength ...............................................................................................................25
8. AC Power ......................................................................................................................26
9. Delay .............................................................................................................................26
10. Timing Constraints .....................................................................................................26
11. Pin Capacitance ...........................................................................................................26
Base Cells
ADDF ............................................................................................................................................30
ADDFH .........................................................................................................................................32
ADDH ...........................................................................................................................................34
AND2 ............................................................................................................................................36
AND3 ............................................................................................................................................38
AND4 ............................................................................................................................................40
AOI21 ...........................................................................................................................................42
AOI211 .........................................................................................................................................44
AOI22 ...........................................................................................................................................46
AOI221 .........................................................................................................................................48
AOI222 .........................................................................................................................................50
AOI2BB1 ......................................................................................................................................52
AOI2BB2 ......................................................................................................................................54
AOI31 ...........................................................................................................................................56
AOI32 ...........................................................................................................................................58
AOI33 ...........................................................................................................................................60
BUF ...............................................................................................................................................62
CLKBUF .......................................................................................................................................64
CLKINV .......................................................................................................................................66
DFF ...............................................................................................................................................69
DFFHQ .........................................................................................................................................71
DFFN ............................................................................................................................................73
DFFNR ..........................................................................................................................................75
DFFNS ..........................................................................................................................................77
DFFNSR .......................................................................................................................................79
DFFR ............................................................................................................................................82
DFFRHQ .......................................................................................................................................84
iv
Table of Contents
DFFS .............................................................................................................................................86
DFFSHQ .......................................................................................................................................88
DFFSR ..........................................................................................................................................90
DFFSRHQ ....................................................................................................................................93
DFFTR ..........................................................................................................................................95
DLY1 ............................................................................................................................................97
DLY2 ............................................................................................................................................99
DLY3 ..........................................................................................................................................101
DLY4 ..........................................................................................................................................103
EDFF ...........................................................................................................................................105
EDFFTR ......................................................................................................................................107
HOLD .........................................................................................................................................109
INV .............................................................................................................................................111
JKFF ............................................................................................................................................114
JKFFR .........................................................................................................................................116
JKFFS .........................................................................................................................................118
JKFFSR .......................................................................................................................................120
MX2 ............................................................................................................................................123
MX4 ............................................................................................................................................125
MXI2 ...........................................................................................................................................127
MXI4 ...........................................................................................................................................129
NAND2 .......................................................................................................................................131
NAND2B ....................................................................................................................................133
NAND3 .......................................................................................................................................135
NAND3B ....................................................................................................................................137
NAND4 .......................................................................................................................................139
NAND4B ....................................................................................................................................141
NAND4BB ..................................................................................................................................143
NOR2 ..........................................................................................................................................145
NOR2B .......................................................................................................................................147
NOR3 ..........................................................................................................................................149
NOR3B .......................................................................................................................................151
NOR4 ..........................................................................................................................................153
NOR4B .......................................................................................................................................155
NOR4BB .....................................................................................................................................157
v
Table of Contents
OAI21 .........................................................................................................................................159
OAI211 .......................................................................................................................................161
OAI22 .........................................................................................................................................163
OAI221 .......................................................................................................................................165
OAI222 .......................................................................................................................................167
OAI2BB1 ....................................................................................................................................169
OAI2BB2 ....................................................................................................................................171
OAI31 .........................................................................................................................................173
OAI32 .........................................................................................................................................175
OAI33 .........................................................................................................................................177
OR2 .............................................................................................................................................179
OR3 .............................................................................................................................................181
OR4 .............................................................................................................................................183
RSLAT ........................................................................................................................................185
RSLATN .....................................................................................................................................187
SDFF ...........................................................................................................................................189
SDFFHQ .....................................................................................................................................191
SDFFN ........................................................................................................................................193
SDFFNR .....................................................................................................................................195
SDFFNS ......................................................................................................................................198
SDFFNSR ...................................................................................................................................201
SDFFR ........................................................................................................................................204
SDFFRHQ ..................................................................................................................................207
SDFFS .........................................................................................................................................210
SDFFSHQ ...................................................................................................................................213
SDFFSR ......................................................................................................................................216
SDFFSRHQ ................................................................................................................................219
SDFFTR ......................................................................................................................................222
SEDFF ........................................................................................................................................225
SEDFFHQ ...................................................................................................................................228
SEDFFTR ...................................................................................................................................231
TBUF ..........................................................................................................................................234
TBUFI .........................................................................................................................................236
TIEHI ..........................................................................................................................................238
TIELO .........................................................................................................................................239
vi
Table of Contents
TLAT ..........................................................................................................................................240
TLATN .......................................................................................................................................242
TLATNR .....................................................................................................................................244
TLATNS .....................................................................................................................................246
TLATNSR ...................................................................................................................................248
TLATR ........................................................................................................................................251
TLATS ........................................................................................................................................253
TLATSR .....................................................................................................................................255
TTLAT ........................................................................................................................................258
XNOR2 .......................................................................................................................................260
XOR2 ..........................................................................................................................................262
Synthesis Optimized Arithmetic Cells
AFCSHCIN .................................................................................................................................265
AFCSHCON ...............................................................................................................................268
AFHCIN ......................................................................................................................................271
AFHCON ....................................................................................................................................273
AHHCIN .....................................................................................................................................275
AHHCON ...................................................................................................................................277
BENC ..........................................................................................................................................279
BMX ...........................................................................................................................................282
CMPR22 .....................................................................................................................................285
CMPR32 ...................................................................................................................................7287
XNOR3 .......................................................................................................................................289
XOR3 ..........................................................................................................................................291
Advanced Arithmetic Cells
CMPR42 .....................................................................................................................................294
Register File Cells
RF1R1W .....................................................................................................................................299
RF2R1W .....................................................................................................................................301
RFRD ..........................................................................................................................................303
vii
Table of Contents
viii
Preface
Revision History
This document contains the release history for the Silterra Malaysia Sdn. Bhd. 0.18um Process
SAGE-X v1.0 Standard Cell Library Databook.
Release
Part Number Number Date of Release Updates
DB-SX-SLT001-1.0/18 1.0 August 2002 • Initial release
DB-SX-SLT001-2.0/18 2.0 February 2003 • Characterization update
DB-SX-SLT004-3.0/18 3.0 March 2004 • Characterization update
Customer Support
For all customer service or technical support questions, please visit the Artisan Components
Web site at www.artisan.com and click on Customer Support.
You may also contact Artisan by telephone or email, using the following information:
■ United States and North America 877-ARTILIB (877-278-4542)

■ International 408-548-3298
■ Email support@artisan.com
ix
x
Introduction
Artisan’s SAGE-XTM standard cell library builds upon our SAGE architecture,
producing the optimum combination of high-density with high-performance.
The cell line-up is derived from extensive customer design, synthesis, and place-
and-route benchmark analysis. Library optimization is achieved by carefully
matching the library functions and drive strengths to leading synthesis and
place-and-route tools, producing superior RTL-to-GDSII results.
How This Book This introduction is organized into three sections:

Is Organized
• Global Parameters provides an overview of parameters specific to your
SAGE-X library.
• Special Cells details the types of special cells included in the library.
• Reading the Standard Cell Datasheet describes the components of each
datasheet.
Datasheets for each cell in this library are provided after the introduction. The
datasheets are included in alphabetical order within the following categories:
• Base Cells
• Advanced Arithmetic Cells
• Register File Cells
• Synthesis Optimized Arithmetic Cells
Global This section specifies global parameters for the Silterra Malaysia Sdn. Bhd.
Parameters 0.18um Process SAGE-X Standard Cell Library. It covers physical
specifications, electrical specifications, derating factors, propagation delay
calculation, timing constraints, power calculation, and power-rail strapping.
11
Introduction
Physical Specifications
Table 1 shows the physical design specifications of this library.

Table 1. Physical Specifications
Drawn Gate Length (µm) 0.18

Layers of Metal 4, 5, or 6
Layout Grid (µm) 0.005
Vertical Pin Grid (µm) 0.56
Horizontal Pin Grid (µm) 0.66
Cell Power and Ground Rail Width (µm) 0.8
Cell Height (µm) 5.04
In this library, all pins are located on the vertical and horizontal pin grids. Most
place-and-route tools work more efficiently with all pins on grids, and some tools
even require it.
The SAGE-X library also supports designs with four, five, or six layers of metal.
You may need to change the design rules in the technology file, because the top-
level metal has a greater minimum width and greater minimum spacing
requirement. See "Design Rule 0.18um LOGIC Salicide 1.8V/3.3V Process"
design rule manual. You must define these rules correctly for the place-and-
route tool.
Table 2 describes the electrical specifications for this library.

Table 2. Electrical Specifications
Parameter Minimum Typical Maximum
DC Supply Voltage (Vdd) 1.62V 1.8V 1.98V

Junction Temperature 0oC 25oC 125oC
Table 3 shows the derating factors for this SAGE-X Standard Cell Library.
Table 3. Derating Factors
KProcess (slow) 1.293

KProcess (typical) 1.000 (by definition)
KProcess (fast) 0.771
12
Introduction
Table 3. Derating Factors
KVolt (1.8V to 1.62V) -0.694/V

KVolt (1.8V to 1.98V) -0.484/V
o o
KTemp (25 C to 0 C) 0.00129/˚C
KTemp (25 oC to 125oC) 0.0013/˚C
Propagation Delay and Transition Time
The propagation delay through a cell is the sum of the intrinsic delay, the load-
dependent delay, and the input-slew dependent delay. Delays are defined as the
time interval between the input stimulus crossing 10% of Vdd and the output
crossing 90% of Vdd. Figure 1 illustrates the propagation delay.
Figure 1. Propagation Delay
Input 50% Vdd
delay
Output 50% Vdd
The transition times (slews) on input and output pins are defined as the time
interval between the signal crossing 10% of Vdd and 90% of Vdd. Figure 2
illustrates transition time measurements for rising and falling signals.
Figure 2. Transition Time
90% Vdd
10% Vdd 10%Vdd
Rising TIme Falling TIme
13
Introduction
Factors that affect propagation delays and transition time include: temperature,
supply voltage, process variations, fanout loading, interconnect loading, input-
transition time, input-signal polarity, and timing constraints. The timing models
provided with this library include the effects of input-transition time on
propagation delays. Also, all timing models use a table lookup method to
calculate accurate timing. To simplify calculations, the standard cell datasheets
provide all timing numbers for an input slew of 0.03ns and a linearized load
factor, Kload, which is not as accurate as the timing models. All cells have been
characterized with a fully populated metal2 (0.66µm horizontal pitch) and
metal3 (0.56µm vertical pitch) routing grid across the entire cell layout.
The SAGE-X Standard Cell Library may contain negative propagation delays.
Although most third-party verification tools can handle negative propagation
delays, some tools will turn negative delays into a zero value.
Derating Factors
Derating factors are coefficients that the typical process characterization data is
multiplied by to arrive at timing data that reflects appropriate operating
conditions. Table 3 on page 12 provides derating factors for variations in process
case, temperature, and voltage.
Derating factors are derived by averaging the performance of many different

cells in the library. A particular combination of cells may perform better or
worse than indicated by these derating factors.
Delay Calculation
Using the delay data in the datasheets (tintrinsic, Kload, and Cload) and the delay
derating factors, the estimated total propagation delay is calculated as such:
tTPD = (KProcess) • [1+(KVolt • ∆Vdd)] • [1+(KTemp • ∆T)] • ttypical
ttypical= tintrinsic + (Kload • Cload)
where:
tTPD = total propagation delay (ns);
ttypical = delay at typical corner—1.8V, 25oC, typical process (ns);
tintrinsic = delay through the cell when there is no output load (ns);
Kload = load delay multiplier (ns/pF);
Cload = total output load capacitance (pF);
14
Introduction
KProcess = process derating factor, where process is slow, typical, or fast;

KVolt = voltage derating factor (/V);
∆Vdd = Vdd - 1.8V;
KTemp = temperature derating factor (/oC);
∆T = junction temperature - 25 oC.
Timing Constraints
Timing constraints define minimum time intervals during which specific signals
must be held steady in order to ensure the correct functioning of any given cell.
Timing constraints include: setup time, hold time, recovery time, and minimum
pulse width.
The sequential-cell timing models provided with this library include the effects
of input-transition time and data-signal and clock-signal polarity on timing
constraints. To simplify calculations, the datasheets specify timing constraint
values for 0.03ns data slew and 0.03ns clock slew. Other factors that affect
timing constraints include temperature, supply voltage, and process case
variations. All cells have been characterized with a fully populated metal2
(0.66µm horizontal pitch) and metal3 (0.56µm vertical pitch) routing grid across
the entire cell layout.
Timing constraints can affect propagation delays. The intrinsic delays given in
the datasheets are measured with relaxed timing constraints (longer than
necessary setup times, hold times, recovery times, and pulse widths). The use
of shorter timing constraint intervals may increase delay. Each cell is considered
functional as long as the actual delay does not exceed the delay given in the
datasheets by more than 10%.
Setup Time
The setup time for a sequential cell is the minimum length of time the data-input
signal must remain stable before the active edge of the clock (or other specified
signal) to ensure correct functioning of the cell. The cell is considered functional
as long as the delay for the output reaching its expected value does not exceed
the reference delay (measured with a large setup time) by more than 10%. Setup-
constraint values are measured as the interval between the data signal crossing
10% of Vdd and the clock signal crossing 90% of Vdd. For the measurement of
setup time, the data input signal is kept stable after the active clock edge for an
infinite hold time. Figure 3 illustrates setup time for a positive-edge-triggered
sequential cell.
15
Introduction
Figure 3. Setup Time
Input 50% Vdd
setup
Clock 50% Vdd
Hold Time
The hold time for a sequential cell is the minimum length of time the data-input
signal must remain stable after the active edge of the clock (or other specified
signal) to ensure correct functioning of the cell. The cell is considered functional
as long as the delay for the output reaching its expected value does not exceed
the reference delay (measured with a large hold time) by more than 10%.
Hold-constraint values are measured as the interval between the data signal
crossing 10% of Vdd and the clock signal crossing 90% of Vdd. For the
measurement of hold time, the data input signal is held stable before the active
clock edge for an infinite setup time. Figure 4 illustrates hold time for a
positive-edge-triggered sequential cell.
NOTE: Artisan does not incorporate any hold time margins in the Synopsys,
TLF, StarDC, or any other timing models. Chip designers should develop a
timing methodology to account for chip-level timing inaccuracies inherent
to extraction and timing analysis tools.
Figure 4. Hold Time
Input 50% Vdd
hold
Clock 50% Vdd
16
Introduction
Recovery Time
Recovery time for sequential cells is the minimum length of time that the active-
low set or reset signal must remain high before the active edge of the clock to
ensure correct functioning of the cell. The cell is considered functional as long
as the delay for the output reaching its expected value does not exceed the
reference delay (measured with a large recovery time) by more than 10%.
Recovery constraint values are measured as the interval between the set or reset
signal crossing 10% of Vdd and the clock signal crossing 90% of Vdd. For the
measurement of recovery time, the set or reset signal is held stable after the
active clock edge for an infinite hold time.
Figure 5 illustrates recovery time.
Figure 5. Recovery Time
Set or
50% Vdd
Reset
recovery
Clock 50% Vdd
Minimum Pulse Width
Minimum pulse width is the minimum length of time between the leading and
trailing edges of a pulse waveform. Minimum pulse width high (minpwh) is
measured as the interval between the rising edge of the signal crossing 10% of
Vdd and the falling edge of the signal crossing 90% of Vdd. Minimum pulse
width low (minpwl) is measured as the interval between the falling edge of the
signal crossing 90% of Vdd and the rising edge of the signal crossing 10% of
Vdd. Figure 6 illustrates minimum pulse width.
Figure 6. Minimum Pulse Width
minpwh
Signal 50% Vdd 50% Vdd
minpwl
17
Introduction
Minimum pulse width is defined as 0.4536ns for all set/reset pins (SN, RN) and
0.6429ns for all clock pins (G, GN, CK, CKN). These are the largest minimum
pulse widths measured from all the cells in the library. An input pulse of shorter
duration will produce unpredictable results.
Power Dissipation
The SAGE-X Standard Cell Library is designed to dissipate only AC power,

except for the small reverse-bias leakage currents which are normally present in
all CMOS circuits.
The power dissipation internal to a cell when a given input switches is primarily
dependent upon the cell design itself. The power dissipation of a complete
design, or part of a design, using cells from the library is primarily a function of
the switching frequency of the design’s internal nets. These nets include the
inputs and outputs of each cell and the capacitive load associated with the
outputs of each cell.
The SAGE-X library datasheets contain both an AC power table which

documents the internal energy consumption of each cell and a pin capacitance
table which gives input-pin capacitance data used to compute output loading.
This information, coupled with design-specific information, can be used to
estimate the total power dissipation of a cell within a design.
The AC power tables specify the amount of energy consumed within a cell
(µW/MHz) when the corresponding pin changes state at 25oC, 1.8V, and typical
process. The energy data in the tables were measured for an input slew of 0.03ns
and no loading at the outputs.
For combinatorial cells, energy values are provided for only input pins. The
energy value for each input pin is the average of energies associated with the
input transitions which result in an output transition.
For sequential cells, the energy associated with each input pin is the average
energy of those input transitions which do not result in an output transition. The
energy associated with the output pin of a sequential cell is the average energy
of all cases where an output transition is the result of a clock-input transition,
minus the energy associated with the clock input pin. In the event that a
sequential cell has multiple outputs, all output energy data will be associated
with only one output pin.
Power Calculation
Power dissipation is dependent upon the power-supply voltage, frequency of

operation, internal capacitance, and output load. The power dissipated by each
cell is:
18
Introduction
x y
Pavg= ∑ ( E in • f in ) + ∑  C on • Vdd • --- f on + E os • f o1
2 1
2 
n=1 n=1
where:
Pavg = average power (µW);
x = number of input pins;
Ein = energy associated with the nth input pin (µW/MHz);
fin = frequency at which the nth input pin changes state during the
normal operation of the design (MHz);
y = number of output pins;
Con = external capacitive loading on the nth output pin, including the
capacitance of each input pin connected to the output driver, plus
the route wire capacitance, actual or estimated (pF);
Vdd = operating voltage = 1.8V;
fon = frequency at which the nth output pin changes state during the
normal operation of the design (MHz);
Eos = energy associated with the output pin for sequential cells only
(µW/MHz).
The switching frequency of inputs and outputs of a particular cell in a design

can be obtained from a gate-level logic simulator (e.g. Verilog) by applying
typical input stimuli and measuring the activity on each node of interest. The
total average power for the design can be computed by adding the average power
for each cell.
EXAMPLE: Calculating Power for a DFFXL Cell
For this exercise, assume that a DFFXL cell has clock switching at 133MHz
(clock frequency = 66.5MHz), input and output pins switching at 20MHz, and
an external capacitive loading on the output pin of 0.02pF. Using the AC Power
table provided in the sample DFF datasheet on page 27, the power dissipated by
the DFFXL can be calculated by using the following equation:
x y
∑ ∑  C on • Vdd • --- f on + E os • f o1

1
( E in • f in ) +
2
Pavg =
2 
n=1 n=1
Given:
x = 2;
Ei1 = 0.0056 µW/MHz;
19
Introduction
Ei2 = 0.0063 µW/MHz;

fi1 = 20 MHz;
fi2 = 133 MHz;
y = 2;
Co1 = 0.02 pF;
Co2 = 0.02 pF;
Vdd= 1.0V;
fo1 = 20 MHz;
fo2 = 20 MHz;
Eos = 0.0060 µW/MHz,
we have:
2 2
∑ ∑  C on • Vdd • --- f on + E os • f o1

1
( E in • f in ) +
2
Pavg =
2 
n=1 n=1
Pavg = ( E i1 • f i1 ) + ( E i2 • f i2 )
--- f o1 +  C o2 • VDD • --- f o2

 C • VDD 2 • 1 2 1
 o1 2   2 
+ ( E os • f o1 )
Pavg = ( 0.0056 • 20 ) + ( 0.0063 • 133 )
+  0.02 • 1.0 • --- ( 20 ) +  0.02 • 1.0 • --- ( 20 )

1 1
 2   2 
+ ( 0.0060 • 20 )
Pavg = 1.46 µW
20
Introduction
Power-Rail Strapping
You must determine the required amount of vertical power-rail strapping to

satisfy all requirements imposed by the design methodology for a given design.
Power-rail strapping should be sized small enough to optimize standard cell
height and maximize router efficiency, yet it must be large enough to provide
sufficient power to the cells.
The guidelines below provide a rough estimate with many simplifying

assumptions. For a given module design, you can estimate the amount of vertical
power-rail strapping that is required to fulfill electromigration requirements.
Given:
Iavg = total average current for the module, calculated from previous
section (mA);
wm1 = VSS/VDD metal1 wire width (µm), see Physical Specifications;
r = number of rows in module;
dm1 = maximum metal1 current density allowed for the process
(mA/µm);
dm2 = maximum metal2 current density allowed for the process
(mA/µm);
Im1 = maximum current that can be supported by all horizontal metal1
wires (mA);
Istrap = total current that must be supported by the vertical metal2
strapping (mA);
wm2 = metal2 wire width required for vertical strapping (µm);
c = minimum number of metal2 straps;
we have:
Im1 = w m1 • r • 2 • d m1 ,
where multiplying by 2 assumes metal1 wires are supplied from both ends;
( I avg – I m1 )
Istrap = ----------------------------- ,
2
21
Introduction
where dividing by 2 assumes the metal2 vertical strap wires are supplied from
both ends;
I strap
wm2 = ------------
-,
d m2
It is recommended that the metal2 wire width, wm2, be divided into c equal
portions which are spaced equidistant across the module, where
I avg
c = ---------
- , rounded up to the next integer.
I m1
The same consideration must be given to the number of vias used to connect the
metal1 and metal2 straps.
Adding Routing Channels
In the SAGE-X Standard Cell Library, each cell is designed with a uniform cell
height of 5.04µm (i.e., 9 tracks tall with 0.56µm per track). The cell layouts
allow neighboring rows of cells to share common power or ground rails when
cells abut each other at the top and bottom edges of the cell bounding box. The
sea-of-cells layout with no channels between rows will usually yield the
minimum area. In case of extremely congested areas, you may want to separate
some rows of cells to increase the number of routing channels within a particular
layout region. Because geometries must overlap cell boundaries, a particular
spacing between the rows may result in DRC violations for layer spacing. It is
recommended that you do not use spacings that cause DRC violations. If these
spacings must be used, the DRC violations must be fixed manually by filling the
void between the rows with the appropriate layer(s).
22
Introduction
Table 4 indicates which DRC violations to expect and how to correct them for
a separation between rows of cells.
Table 4. Correcting DRC Violations
Row Separation in Action to Correct

Expected DRC Violations
Number of Grids DRC Violations
0 (Rows Abut) None None

Draw NWELL layer
between rows to merge
1 NP/PP space < 0.4µm
NWELL regions above and
below row separation.
Draw NWELL layer
2 NWELL space < 0.6µm
Draw NWELL layer
3 NWELL space < 0.6µm
4 None None
5 or more None None
Special Cells This section discusses special cells in the SAGE-X Standard Cell Library.
Antenna-Fix Cell
The library contains an antenna-fix cell which must be inserted manually.

However, most place and route tools will indicate which nets require the
antenna-fix cell. The Silterra Malaysia Sdn. Bhd. antenna effect prevention
guideline, "Design Rule 0.18um LOGIC Salicide 1.8V/3.3V Process," specifies
a maximum wire length. During place and route, the router may connect wires
to the input gates of cells that are longer than the maximum length allowable by
the guideline. The antenna cell can be used in this case to add an optional diode
on the net close to the input gates which do not meet the guideline. Pin A on the
antenna cell connects to a diode, reverse biased to ground. A diode can be added
to either P or N.
Fill Cells
The library contains several FILL cells: FILL1, FILL2, FILL4, FILL8, FILL16,
FILL32, FILL64. The number appended to "FILL" in the cell name denotes the
width of the cell in tracks.
23
Introduction
During place and route, the FILL cells are used to connect power and ground
rails across an area containing no cells. The FILL cells are also used to ensure
gaps do not occur between well or implant layers which could cause design rule
violations. Using wider cells where appropriate reduces the size of the layout
database.
Low-Power (XL) Cells
The library contains a wide variety of cells, denoted by an "XL" suffix in the
cell name, that are designed specifically for low-power applications. Input
capacitance for the XL cells is much lower than that for corresponding X1
(1x drive strength) cells. Because XL cells have been designed for the sole
purpose of reducing power consumption, output rise and fall times for these cells
may not be equal, and due to the low-drive capability of the XL cells, these cells
are not intended for use in critical timing paths, or to drive heavily loaded nets.
TIEHI/LO Cells
The library contains a TIEHI cell and a TIELO cell. The outputs of the TIEHI
and TIELO cells are driven through diffusion to provide isolation from the
power and ground rails for better ESD protection. The standard cell abstract
methodology assumes that the TIEHI and TIELO cells are used to tie off any
inputs to power and ground. If these cells are not used and the router is allowed
to drop vias on the power rail, DRC errors or shorts may result.
Delay Cells
The library contains delay cells that have the same width. These delay cells allow
you to adjust a given delay path with a simple cell substitution after place and
route.
Reading the Please refer to the sample datasheet for DFF on pages 27 and 28 for the
Standard Cell arrangement of each of the following datasheet sections. Datasheet titles
Datasheet reference standard Artisan cell names. Cell names for your specific library are
reflected in the cell size table on each datasheet.
NOTE: This datasheet contains sample characterization values.
1. Base Cell Name
The cell name field contains the cell name. The datasheets are presented
alphabetically by cell name. The cell name presented here is the base cell name.
The Cell Size table displays cell names for your specific library.
24
Introduction
2. Cell Description
The cell description gives the function of the cell. When applicable, the
equation(s) for the output pins are provided.
3. Functions
The function table gives all possible combinations of input and output signals
for the cell. Table 5 defines the symbols used in datasheet function tables.
Table 5. Functions Key
Symbol Description
0 Logic Low
1 Logic High
High to Low Transition
Low to High Transition
x Don’t Care
IL Illegal/Undefined
Z High Impedance
4. Logic Symbol
The logic symbol is a graphical representation of the cell, similar to the view in
the schematic editor when the cell is instantiated. The symbol shows the name
and location of the input and output pins.
5. Cell Size
This cell size table gives the height and width (um) for each drive strength of
the cell.
6. Functional Schematic
The functional schematic provides a functional representation of the cell.
7. Drive Strength
The drive strength of each cell is indicated by an “X” followed by the unit
strength.
25
Introduction
8. AC Power
The AC power table shows the amount of energy consumed (µW/MHz) within
the cell when the corresponding pin changes state. The energy data for each drive
strength of the cell in the sample DFF datasheet are calculated at 25oC, 1.0V,
typical process, input slew of 0.03ns, and no external load at the output pins.
9. Delay
The delay table shows the intrinsic delay (ns) which is the delay through the cell
when there is no load on the output, and the load multiplier for load dependent
delay, Kload (ns/pF). The delays and load multiplier for each drive strength of
the cell in the sample DFF datasheet are calculated at 25oC, 1.0V, typical
process, and input slew of 0.03ns.
10. Timing Constraints
The timing constraints table in the sample DFF datasheet shows the timing
conditions (ns) required at 25oC, 1.0V, and typical process to maintain proper
functionality. Setup constraint values are measured for 0.03ns data slew and
0.03ns clock slew. Hold constraint values are measured for 0.03ns data slew and
0.03ns clock slew. Minimum pulse width is defined to be 0.4536ns for all set/
reset pins and 0.6429ns for all clock pins. These are the largest minimum pulse
widths measured from all the cells in the library.
11. Pin Capacitance
The pin capacitance table shows the typical loading at the input pins of the cell
(pF) for each drive strength of the cell.
26
Introduction
▼ This datasheet contains sample characterization values. ▼
DFF 1
Your logo here
4
2 Cell Description Logic Symbol
The DFF cell is a positive-edge-triggered,

static D-type flip-flop.
D Q
3 Function CK QN
D CK Q[n+1] QN[n+1]
5
0 0 1
1 1 0 Cell Size
x Q[n] QN[n]
Drive Strength Height (um) Width (um)
DFFXL 3.69 7.36

DFFX1 3.69 7.36
DFFX2 3.69 8.74
DFFX4 3.69 11.50
7
6 Functional Schematic
cn c
c cn
c cn
D QN
cn c
Q
cn
CK c
Artisan SAGE-X Standard Cell Library Databook

79
27
Introduction
▼ This datasheet contains sample characterization values. ▼
DFF
Your logo here
11
8 AC Power Pin Capacitance
Power (µW/MHz) Capacitance (pF)

7 Pin Pin
XL X1 X2 X4 XL X1 X2 X4
D 0.0056 0.0063 0.0081 0.0133 D 0.0013 0.0013 0.0015 0.0023

CK 0.0063 0.0068 0.0087 0.0128 CK 0.0015 0.0019 0.0022 0.0035
Q 0.0060 0.0080 0.0124 0.0223
9 Delays at 25 oC, 1.0V, Typical Process
Intrinsic Delay (ns) Kload (ns/pF)

Description
CK → Q↑ 0.1662 0.1427 0.1287 0.1105 7.8830 4.2853 1.9344 0.9666

CK → Q↓ 0.1357 0.1098 0.0983 0.0920 4.3787 2.4148 1.1764 0.5884
CK → QN↑ 0.1828 0.1515 0.1342 0.1292 7.8631 4.2693 1.9226 0.9616
CK → QN↓ 0.2156 0.1947 0.1789 0.1547 3.9375 2.1923 1.1262 0.5569
10 Timing Constraints at 25oC, 1.0V, Typical Process
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0469 0.0547 0.0391 0.0391
setup↓ → CK 0.1094 0.1250 0.1094 0.1016
D
hold↑ → CK -0.0312 -0.0312 -0.0234 -0.0234
hold↓ → CK -0.0312 -0.0469 -0.0312 -0.0312
minpwh 0.0933 0.0835 0.0738 0.0641
CK
minpwl 0.1418 0.1224 0.1127 0.0835
Artisan SAGE-X Standard Cell Library Databook

80
28
Base Cells
29
Process Technology:
ADDF
Silterra Malaysia Sdn. Bhd. 0.18um
Cell Description Logic Symbol

The ADDF cell provides the arithmetic sum (S) and
carry out (CO) of two operands (A, B) with carry in A
(CI). The two outputs (S, CO) are represented by the S
logic equations: B
CO
S = ( A ⊕ B ⊕ CI ) CI
CO = ( A ⊕ B ) • CI + ( A • B )
Functions Cell Size
CI A B S CO Drive Strength Height (um) Width (um)

0 0 0 0 0 ADDFXL 5.04 13.86
0 0 1 1 0 ADDFX1 5.04 13.86
0 1 0 1 0 ADDFX2 5.04 13.86
0 1 1 0 1 ADDFX4 5.04 15.18
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Functional Schematic
A
S
CI
CO
Silterra Malaysia Sdn. Bhd. 0.18um Process SAGE-X Standard Cell Library Databook
30
Process Technology:
ADDF
AC Power Pin Capacitance

Pin Pin
A 0.1190 0.1190 0.1423 0.2163 A 0.0071 0.0071 0.0071 0.0071
B 0.1520 0.1520 0.1915 0.2728 B 0.0068 0.0068 0.0068 0.0068
CI 0.0656 0.0656 0.0927 0.1719 CI 0.0065 0.0065 0.0065 0.0065
Delays at 25 oC, 1.8V, Typical Process

Description
A → S↑ 0.2132 0.2149 0.2345 0.2885 4.5958 4.5561 2.2182 1.1010
A → S↓ 0.2760 0.2886 0.3201 0.3878 2.8836 2.6191 1.3944 0.7189
B → S↑ 0.2456 0.2476 0.2634 0.3069 4.6089 4.5609 2.2213 1.1045
B → S↓ 0.3146 0.3272 0.3590 0.4267 2.8843 2.6191 1.3944 0.7190
CI → S↑ 0.1725 0.1742 0.2026 0.2697 4.5959 4.5562 2.2194 1.1029
CI → S↓ 0.1386 0.1518 0.1825 0.2474 2.9077 2.6327 1.4101 0.7337
A → CO↑ 0.2646 0.2645 0.2929 0.3573 4.5400 4.5332 2.2066 1.0933
A → CO↓ 0.2581 0.2662 0.2984 0.3568 2.7180 2.5457 1.3619 0.7025
B → CO↑ 0.3027 0.3026 0.3311 0.3954 4.5391 4.5329 2.2064 1.0932
B → CO↓ 0.2777 0.2822 0.3092 0.3588 2.5891 2.4916 1.3250 0.6717
CI → CO↑ 0.1378 0.1388 0.1672 0.2345 4.5756 4.5473 2.2152 1.0993
CI → CO↓ 0.1767 0.1863 0.2187 0.2803 2.7703 2.5670 1.3718 0.7072
31
Process Technology:
ADDFH

The ADDFH cell is a high-speed cell providing the
arithmetic sum (S) and carry out (CO) of two A
operands (A, B) with carry in (CI). The two outputs S
(S, CO) are represented by the logic equations: B
CO
S = ( A ⊕ B ⊕ CI ) CI
CO = ( A ⊕ B ) • CI + ( A • B )
Functions Cell Size
CI A B S CO Drive Strength Height (um) Width (um)

0 0 0 0 0 ADDFHXL 5.04 14.52
0 0 1 1 0 ADDFHX1 5.04 15.18
0 1 0 1 0 ADDFHX2 5.04 22.44
0 1 1 0 1 ADDFHX4 5.04 23.10
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A
S
CI
CO
32
Process Technology:
ADDFH

Pin Pin
A 0.1223 0.1404 0.2604 0.3012 A 0.0040 0.0062 0.0111 0.0111
B 0.1097 0.1284 0.2311 0.2760 B 0.0089 0.0144 0.0255 0.0256
CI 0.0635 0.0716 0.1204 0.1639 CI 0.0023 0.0043 0.0078 0.0079

Description
A → S↑ 0.3675 0.2302 0.2226 0.2390 6.4709 4.5403 2.2365 1.0921
A → S↓ 0.3444 0.2657 0.2449 0.2707 3.5709 2.5134 1.2918 0.6545
B → S↑ 0.2645 0.1713 0.1534 0.1742 6.5056 4.5441 2.2384 1.0930
B → S↓ 0.3380 0.2091 0.1848 0.2140 3.5842 2.5124 1.2918 0.6545
CI → S↑ 0.3146 0.1837 0.1594 0.1845 6.4924 4.5441 2.2380 1.0931
CI → S↓ 0.2727 0.1869 0.1568 0.1882 3.6134 2.5188 1.2943 0.6559
A → CO↑ 0.3732 0.2314 0.2232 0.2390 6.4808 4.5399 2.2372 1.0922
A → CO↓ 0.3647 0.2632 0.2461 0.2702 3.7060 2.5074 1.2922 0.6543
B → CO↑ 0.2204 0.1522 0.1401 0.1572 6.5118 4.5406 2.2378 1.0925
B → CO↓ 0.3582 0.1977 0.1775 0.2012 3.7354 2.4893 1.2869 0.6495
CI → CO↑ 0.1357 0.1035 0.0893 0.1018 6.5094 4.5441 2.2385 1.0931
CI → CO↓ 0.2368 0.1504 0.1311 0.1536 3.8335 2.5319 1.3012 0.6581
33
Process Technology:
ADDH

The ADDH cell provides the arithmetic sum (S) and
carry out (CO) of two operands (A, B). The two
outputs (S, CO) are represented by the logic A S
equations:
B CO
S = ( A • B) + ( A • B)
CO = A • B
Functions Cell Size
A B S CO Drive Strength Height (um) Width (um)

0 0 0 0 ADDHXL 5.04 7.26
0 1 1 0 ADDHX1 5.04 7.92
1 0 1 0 ADDHX2 5.04 11.88
1 1 0 1 ADDHX4 5.04 18.48
A S
B
CO
34
Process Technology:
ADDH

Pin Pin
A 0.0588 0.1032 0.1889 0.3602 A 0.0047 0.0103 0.0211 0.0407
B 0.0452 0.0611 0.1071 0.1968 B 0.0065 0.0088 0.0128 0.0245

Description
A → S↑ 0.1296 0.0796 0.0694 0.0667 7.2721 2.7733 1.3439 0.6676
A → S↓ 0.1390 0.0874 0.0789 0.0748 4.0066 1.7329 0.8466 0.4183
B → S↑ 0.0655 0.0548 0.0501 0.0455 7.2102 2.7608 1.3348 0.6627
B → S↓ 0.0866 0.0764 0.0688 0.0630 3.7757 1.6539 0.8118 0.4027
A → CO↑ 0.0743 0.0857 0.0771 0.0748 6.4758 4.5443 2.1828 1.0915
A → CO↓ 0.1041 0.1335 0.1111 0.1039 3.3588 2.6357 1.2799 0.6395
B → CO↑ 0.0720 0.0866 0.0753 0.0713 6.4758 4.5433 2.1822 1.0915
B → CO↓ 0.0937 0.1274 0.1030 0.0941 3.3536 2.6311 1.2785 0.6388
35
Process Technology:
AND2

The AND2 cell provides the logical AND of two inputs
(A, B). The output (Y) is represented by the logic A
Y
equation: B
Y = ( A • B)
Functions Cell Size
A B Y Drive Strength Height (um) Width (um)
0 x 0 AND2XL 5.04 2.64

x 0 0 AND2X1 5.04 2.64
1 1 1 AND2X2 5.04 2.64
AND2X4 5.04 3.30
A
Y
B
36
Process Technology:
AND2
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X4
A 0.0188 0.0213 0.0305 0.0569
B 0.0217 0.0244 0.0357 0.0678
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X4
A 0.0021 0.0020 0.0032 0.0056
B 0.0021 0.0020 0.0034 0.0063
Intrinsic Delay (ns)

Description
XL X1 X2 X4
A → Y↑ 0.0819 0.0853 0.0712 0.0651
A → Y↓ 0.1022 0.1253 0.0948 0.0999
B → Y↑ 0.0873 0.0907 0.0757 0.0705
B → Y↓ 0.1150 0.1402 0.1073 0.1151
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4839 4.5445 2.3203 1.0886
A → Y↓ 3.3706 2.4845 1.2784 0.6530
B → Y↑ 6.4847 4.5454 2.3203 1.0886
B → Y↓ 3.3778 2.4878 1.2799 0.6538
37
Process Technology:
AND3

The AND3 cell provides the logical AND of three
inputs (A, B, C). The output (Y) is represented by the A
logic equation: B Y
C
Y = ( A • B • C)
Functions Cell Size
A B C Y Drive Strength Height (um) Width (um)

0 x x 0 AND3XL 5.04 3.30
x 0 x 0 AND3X1 5.04 3.30
x x 0 0 AND3X2 5.04 3.30
1 1 1 1 AND3X4 5.04 3.96
A
B Y
C
38
Process Technology:
AND3

Pin Pin
A 0.0211 0.0229 0.0354 0.0611 A 0.0026 0.0024 0.0036 0.0060
B 0.0246 0.0263 0.0414 0.0706 B 0.0026 0.0024 0.0037 0.0060
C 0.0282 0.0296 0.0476 0.0802 C 0.0025 0.0023 0.0040 0.0063

Description
XL X1 X2 X4
A → Y↑ 0.0997 0.1088 0.0914 0.0912
A → Y↓ 0.1219 0.1417 0.1121 0.0962
B → Y↑ 0.1077 0.1169 0.0994 0.0989
B → Y↓ 0.1378 0.1576 0.1266 0.1075
C → Y↑ 0.1128 0.1223 0.1052 0.1038
C → Y↓ 0.1525 0.1728 0.1412 0.1182
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4968 4.5538 2.1868 1.1103
A → Y↓ 3.1795 2.6480 1.2852 0.6292
B → Y↑ 6.4969 4.5539 2.1867 1.1102
B → Y↓ 3.1897 2.6521 1.2868 0.6300
C → Y↑ 6.4971 4.5542 2.1868 1.1102
C → Y↓ 3.2064 2.6592 1.2899 0.6312
39
Process Technology:
AND4

The AND4 cell provides the logical AND of four inputs
A
(A, B, C, D). The output (Y) is represented by the logic B
equation: C Y
D
Y = ( A • B • C • D)
Functions Cell Size
A B C D Y Drive Strength Height (um) Width (um)

0 x x x 0 AND4XL 5.04 3.96
x 0 x x 0 AND4X1 5.04 3.96
x x 0 x 0 AND4X2 5.04 3.96
x x x 0 0 AND4X4 5.04 7.26
1 1 1 1 1
A
B
Y
C
D
40
Process Technology:
AND4

Pin Pin
A 0.0200 0.0229 0.0375 0.0658 A 0.0026 0.0023 0.0037 0.0067
B 0.0238 0.0265 0.0439 0.0787 B 0.0025 0.0023 0.0037 0.0072
C 0.0277 0.0299 0.0502 0.0916 C 0.0026 0.0023 0.0037 0.0080
D 0.0316 0.0335 0.0566 0.1050 D 0.0026 0.0024 0.0039 0.0088

Description
XL X1 X2 X4
A → Y↑ 0.1038 0.1234 0.1054 0.0947
A → Y↓ 0.1174 0.1381 0.1141 0.1093
B → Y↑ 0.1158 0.1360 0.1169 0.1063
B → Y↓ 0.1352 0.1554 0.1299 0.1261
C → Y↑ 0.1251 0.1445 0.1249 0.1149
C → Y↓ 0.1523 0.1708 0.1441 0.1419
D → Y↑ 0.1302 0.1503 0.1301 0.1209
D → Y↓ 0.1666 0.1856 0.1573 0.1569
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.5145 4.5665 2.2747 1.1172
A → Y↓ 3.4030 2.4971 1.2851 0.6427
B → Y↑ 6.5146 4.5666 2.2749 1.1172
B → Y↓ 3.4149 2.5022 1.2872 0.6440
C → Y↑ 6.5145 4.5664 2.2750 1.1173
C → Y↓ 3.4321 2.5096 1.2905 0.6457
D → Y↑ 6.5128 4.5656 2.2750 1.1173
D → Y↓ 3.4530 2.5187 1.2948 0.6480
41
Process Technology:
AOI21

The AOI21 cell provides the logical inverted OR of
one AND group and an additional input. The output A0
A1
(Y) is represented by the logic equation:
Y = ( A0 • A1 ) + B0 Y
B0
Functions
Cell Size
A0 A1 B0 Y
0 x 0 1 Drive Strength Height (um) Width (um)
x 0 0 1 AOI21XL 5.04 2.64
x x 1 0 AOI21X1 5.04 2.64
1 1 x 0 AOI21X2 5.04 4.62
AOI21X4 5.04 6.60
A0
A1
B0
42
Process Technology:
AOI21

Pin Pin
A0 0.0153 0.0216 0.0443 0.0827 A0 0.0034 0.0048 0.0097 0.0176
A1 0.0195 0.0273 0.0556 0.1047 A1 0.0033 0.0045 0.0089 0.0177
B0 0.0154 0.0214 0.0431 0.0800 B0 0.0032 0.0044 0.0081 0.0150

Description
XL X1 X2 X4
A0 → Y↑ 0.0620 0.0561 0.0564 0.0516
A0 → Y↓ 0.0330 0.0324 0.0321 0.0302
A1 → Y↑ 0.0769 0.0699 0.0693 0.0656
A1 → Y↓ 0.0369 0.0361 0.0355 0.0341
B0 → Y↑ 0.0557 0.0544 0.0521 0.0507
B0 → Y↓ 0.0216 0.0222 0.0217 0.0208
Kload (ns/pF)
Description
XL X1 X2 X4
A0 → Y↑ 9.5888 6.5578 3.2936 1.6710
A0 → Y↓ 4.0529 2.9041 1.4524 0.7385
A1 → Y↑ 9.5740 6.5512 3.2907 1.6697
A1 → Y↓ 4.0521 2.9037 1.4520 0.7385
B0 → Y↑ 9.5865 6.5577 3.2923 1.6709
B0 → Y↓ 3.3011 2.4367 1.2654 0.6312
43
Process Technology:
AOI211

one AND group and two additional inputs. The output A0
A1
Y = ( A0 • A1 ) + B0 + C0 B0 Y
C0
Functions
A0 A1 B0 C0 Y
Cell Size
0 x 0 0 1
x 0 0 0 1 Drive Strength Height (um) Width (um)
x x x 1 0 AOI211XL 5.04 3.30
x x 1 x 0 AOI211X1 5.04 3.30
1 1 x x 0 AOI211X2 5.04 5.94
AOI211X4 5.04 6.60
A0
A1
B0 Y
C0
44
Process Technology:
AOI211

Pin Pin
A0 0.0236 0.0334 0.0698 0.0842 A0 0.0036 0.0050 0.0102 0.0034
A1 0.0278 0.0392 0.0811 0.0891 A1 0.0036 0.0049 0.0095 0.0034
B0 0.0190 0.0267 0.0549 0.0816 B0 0.0036 0.0049 0.0088 0.0035
C0 0.0226 0.0318 0.0662 0.0846 C0 0.0034 0.0046 0.0095 0.0032

Description
A0 → Y↑ 0.1006 0.0962 0.0979 0.2765 12.2338 8.3432 4.1937 1.0899
A0 → Y↓ 0.0421 0.0438 0.0439 0.1713 4.0897 2.9248 1.4629 0.6390
A1 → Y↑ 0.1197 0.1139 0.1149 0.2981 12.2167 8.3359 4.1894 1.0899
A1 → Y↓ 0.0462 0.0478 0.0474 0.1751 4.0899 2.9247 1.4628 0.6390
B0 → Y↑ 0.0811 0.0780 0.0767 0.2618 12.2356 8.3434 4.1925 1.0899
B0 → Y↓ 0.0261 0.0270 0.0270 0.1432 3.3013 2.4360 1.2653 0.6388
C0 → Y↑ 0.1026 0.0985 0.1010 0.2817 12.2245 8.3377 4.1912 1.0899
C0 → Y↓ 0.0320 0.0334 0.0349 0.1496 3.3082 2.4393 1.2672 0.6388
45
Process Technology:
AOI22

two AND groups. The output (Y) is represented by A0
A1
the logic equation:
Y = ( A0 • A1 ) + ( B0 • B1 ) Y
Functions B0
B1
A0 A1 B0 B1 Y
0 x 0 x 1 Cell Size
0 x x 0 1
x 0 0 x 1 Drive Strength Height (um) Width (um)
x 0 x 0 1 AOI22XL 5.04 3.30
x x 1 1 0 AOI22X1 5.04 3.30
1 1 x x 0 AOI22X2 5.04 5.94
AOI22X4 5.04 9.24
A0
A1
B0
B1
46
Process Technology:
AOI22

Pin Pin
A0 0.0177 0.0242 0.0473 0.0940 A0 0.0036 0.0048 0.0090 0.0176
A1 0.0217 0.0298 0.0587 0.1164 A1 0.0035 0.0048 0.0098 0.0181
B0 0.0229 0.0313 0.0615 0.1234 B0 0.0034 0.0045 0.0087 0.0175
B1 0.0269 0.0370 0.0731 0.1453 B1 0.0033 0.0044 0.0093 0.0177

Description
A0 → Y↑ 0.0634 0.0608 0.0605 0.0612 9.5912 6.5679 3.2939 1.6559
A0 → Y↓ 0.0277 0.0272 0.0268 0.0269 4.0354 2.8995 1.4497 0.7376
A1 → Y↑ 0.0788 0.0753 0.0757 0.0733 9.5812 6.5637 3.2917 1.6122
A1 → Y↓ 0.0319 0.0314 0.0313 0.0311 4.0360 2.8998 1.4499 0.7376
B0 → Y↑ 0.0949 0.0842 0.0816 0.0790 9.5861 6.5658 3.2928 1.6129
B0 → Y↓ 0.0460 0.0438 0.0423 0.0423 4.0557 2.9052 1.4519 0.7385
B1 → Y↑ 0.1094 0.0981 0.0960 0.0924 9.5753 6.5605 3.2903 1.6117
B1 → Y↓ 0.0498 0.0477 0.0465 0.0463 4.0554 2.9053 1.4519 0.7383
47
Process Technology:
AOI221

two AND groups and a third input. The output (Y) is A0
A1
represented by the logic equation:
Y = ( A0 • A1 ) + ( B0 • B1 ) + C0 B0
B1
Functions Y
C0
A0 A1 B0 B1 C0 Y
0 x 0 x 0 1
Cell Size
0 x x 0 0 1
x 0 0 x 0 1 Drive Strength Height (um) Width (um)
x 0 x 0 0 1 AOI221XL 5.04 4.62
x x x x 1 0 AOI221X1 5.04 4.62
x x 1 1 x 0 AOI221X2 5.04 7.92
1 1 x x x 0 AOI221X4 5.04 7.26
A0
A1
B0
Y
B1
C0
48
Process Technology:
AOI221

Pin Pin
A0 0.0253 0.0343 0.0659 0.0834 A0 0.0038 0.0052 0.0096 0.0034
A1 0.0294 0.0399 0.0776 0.0883 A1 0.0038 0.0052 0.0102 0.0034
B0 0.0316 0.0428 0.0830 0.0887 B0 0.0038 0.0050 0.0096 0.0034
B1 0.0356 0.0482 0.0947 0.0935 B1 0.0036 0.0048 0.0100 0.0032
C0 0.0245 0.0329 0.0633 0.0843 C0 0.0035 0.0048 0.0090 0.0034

Description
A0 → Y↑ 0.1262 0.1135 0.1070 0.2964 11.9782 8.3639 4.1819 1.1313
A0 → Y↓ 0.0453 0.0428 0.0403 0.1712 4.0637 2.9085 1.4548 0.6385
A1 → Y↑ 0.1451 0.1312 0.1247 0.3177 11.9642 8.3570 4.1791 1.1312
A1 → Y↓ 0.0495 0.0467 0.0442 0.1751 4.0637 2.9085 1.4548 0.6385
B0 → Y↑ 0.1459 0.1302 0.1243 0.3165 11.9769 8.3628 4.1820 1.1313
B0 → Y↓ 0.0515 0.0504 0.0476 0.1807 4.1442 2.9447 1.4736 0.6387
B1 → Y↑ 0.1638 0.1474 0.1424 0.3373 11.9628 8.3562 4.1788 1.1312
B1 → Y↓ 0.0552 0.0539 0.0518 0.1842 4.1432 2.9444 1.4735 0.6387
C0 → Y↑ 0.0963 0.0943 0.0874 0.2728 11.9816 8.3651 4.1830 1.1312
C0 → Y↓ 0.0280 0.0281 0.0268 0.1438 3.3141 2.4419 1.2687 0.6382
49
Process Technology:
AOI222

A0
three AND groups. The output (Y) is represented by A1
the logic equation:
Y = ( A0 • A1 ) + ( B0 • B1 ) + ( C0 • C1 ) B0
B1 Y
Functions
C0
A0 A1 B0 B1 C0 C1 Y C1
0 x 0 x 0 x 1
0 x 0 x x 0 1 Cell Size
0 x x 0 0 x 1
0 x x 0 x 0 1 Drive Strength Height (um) Width (um)
x 0 0 x 0 x 1 AOI222XL 5.04 5.28
x 0 0 x x 0 1 AOI222X1 5.04 5.28
x 0 x 0 0 x 1 AOI222X2 5.04 9.24
x 0 x 0 x 0 1 AOI222X4 5.04 7.92
x x x x 1 1 0
x x 1 1 x x 0
1 1 x x x x 0
A0
A1
B0
Y
B1
C0
C1
50
Process Technology:
AOI222

Pin Pin
A0 0.0282 0.0369 0.0701 0.0869 A0 0.0037 0.0052 0.0100 0.0035
A1 0.0322 0.0427 0.0812 0.0920 A1 0.0037 0.0051 0.0105 0.0036
B0 0.0336 0.0457 0.0864 0.0921 B0 0.0036 0.0050 0.0096 0.0033
B1 0.0379 0.0513 0.0979 0.0971 B1 0.0036 0.0050 0.0101 0.0033
C0 0.0397 0.0541 0.1038 0.0974 C0 0.0035 0.0049 0.0095 0.0034
C1 0.0438 0.0598 0.1154 0.1023 C1 0.0036 0.0050 0.0100 0.0032

Description
A0 → Y↑ 0.1133 0.1033 0.1003 0.2749 12.5076 8.4012 4.2002 1.1092
A0 → Y↓ 0.0370 0.0354 0.0340 0.1672 4.0493 2.9053 1.4530 0.6400
A1 → Y↑ 0.1340 0.1232 0.1188 0.2982 12.4985 8.3949 4.1979 1.1091
A1 → Y↓ 0.0415 0.0401 0.0381 0.1719 4.0500 2.9055 1.4532 0.6401
B0 → Y↑ 0.1803 0.1556 0.1455 0.3449 12.5016 8.3938 4.1970 1.1092
B0 → Y↓ 0.0579 0.0541 0.0510 0.1901 4.0597 2.9073 1.4528 0.6401
B1 → Y↑ 0.2007 0.1730 0.1644 0.3660 12.4923 8.3883 4.1943 1.1092
B1 → Y↓ 0.0623 0.0580 0.0555 0.1940 4.0597 2.9072 1.4527 0.6402
C0 → Y↑ 0.2011 0.1727 0.1637 0.3647 12.5031 8.3942 4.1974 1.1092
C0 → Y↓ 0.0698 0.0674 0.0646 0.2002 4.1151 2.9333 1.4665 0.6401
C1 → Y↑ 0.2203 0.1907 0.1815 0.3850 12.4903 8.3885 4.1942 1.1092
C1 → Y↓ 0.0741 0.0716 0.0689 0.2038 4.1148 2.9333 1.4663 0.6401
51
Process Technology:
AOI2BB1

The AOI2BB1 cell provides the logical inverted OR
A0N
of one AND group of two inverted inputs (A0N, A1N) A1N
and an additional non-inverted input (B0). The output
(Y) is represented by the logic equation: Y
B0
Y = ( A0N • A1N ) + B0
Functions Cell Size
A0N A1N B0 Y Drive Strength Height (um) Width (um)

1 x 0 1 AOI2BB1XL 5.04 3.30
x 1 0 1 AOI2BB1X1 5.04 3.30
x x 1 0 AOI2BB1X2 5.04 4.62
0 0 x 0 AOI2BB1X4 5.04 7.26
A0N
A1N
B0
52
Process Technology:
AOI2BB1

Pin Pin
A0N 0.0223 0.0256 0.0399 0.0801 A0N 0.0026 0.0025 0.0043 0.0078
A1N 0.0242 0.0277 0.0444 0.0892 A1N 0.0024 0.0026 0.0044 0.0081
B0 0.0143 0.0186 0.0370 0.0715 B0 0.0032 0.0042 0.0085 0.0155

Description
A0N → Y↑ 0.0826 0.0804 0.0744 0.0738 9.5981 6.6952 3.2876 1.6134
A0N → Y↓ 0.1511 0.1708 0.1361 0.1344 3.2460 2.5976 1.2941 0.6466
A1N → Y↑ 0.0868 0.0855 0.0808 0.0799 9.5997 6.6961 3.2880 1.6138
A1N → Y↓ 0.1605 0.1820 0.1465 0.1438 3.2462 2.5976 1.2941 0.6466
B0 → Y↑ 0.0504 0.0460 0.0440 0.0412 9.5786 6.6875 3.2858 1.6122
B0 → Y↓ 0.0237 0.0252 0.0248 0.0239 3.0650 2.5099 1.2653 0.6326
53
Process Technology:
AOI2BB2

The AOI2BB2 cell provides the logical inverted OR
A0N
of one AND group of two inverted inputs (A0N, A1N) A1N
and one AND group of two non-inverted inputs (B0,
B1). The output (Y) is represented by the logic Y
equation:
Y = ( A0N • A1N ) + ( B0 • B1 ) B0
B1
Functions
Cell Size
A0N A1N B0 B1 Y
1 x 0 x 1 Drive Strength Height (um) Width (um)
1 x x 0 1 AOI2BB2XL 5.04 4.62
x 1 0 x 1 AOI2BB2X1 5.04 4.62
x 1 x 0 1 AOI2BB2X2 5.04 5.94
x x 1 1 0 AOI2BB2X4 5.04 9.90
0 0 x x 0
A0N
A1N
B0
B1
54
Process Technology:
AOI2BB2

Pin Pin
A0N 0.0221 0.0245 0.0395 0.0725 A0N 0.0026 0.0024 0.0043 0.0075
A1N 0.0238 0.0263 0.0439 0.0824 A1N 0.0024 0.0021 0.0042 0.0083
B0 0.0164 0.0220 0.0437 0.0852 B0 0.0034 0.0047 0.0096 0.0171
B1 0.0208 0.0279 0.0555 0.1082 B1 0.0033 0.0047 0.0100 0.0182

Description
A0N → Y↑ 0.0756 0.0731 0.0718 0.0697 7.1459 4.9053 2.4521 1.2009
A0N → Y↓ 0.1561 0.1654 0.1391 0.1269 3.4718 2.5142 1.3341 0.6441
A1N → Y↑ 0.0792 0.0770 0.0777 0.0770 7.1478 4.9065 2.4527 1.2013
A1N → Y↓ 0.1633 0.1730 0.1482 0.1374 3.4713 2.5141 1.3341 0.6440
B0 → Y↑ 0.0641 0.0585 0.0550 0.0532 9.5887 6.5867 3.2937 1.6132
B0 → Y↓ 0.0335 0.0327 0.0308 0.0308 4.0463 2.9046 1.4516 0.7387
B1 → Y↑ 0.0793 0.0729 0.0691 0.0673 9.5744 6.5806 3.2905 1.6119
B1 → Y↓ 0.0374 0.0366 0.0346 0.0351 4.0474 2.9058 1.4521 0.7387
55
Process Technology:
AOI31

A0
one AND group and an additional input. The output A1
(Y) is represented by the logic equation: A2
Y = ( A0 • A1 • A2 ) + B0 Y
B0
Functions
Cell Size
A0 A1 A2 B0 Y
0 x x 0 1 Drive Strength Height (um) Width (um)
x 0 x 0 1 AOI31XL 5.04 3.30
x x 0 0 1 AOI31X1 5.04 3.30
x x x 1 0 AOI31X2 5.04 5.94
1 1 1 x 0 AOI31X4 5.04 5.94
A0
A1
A2
B0
56
Process Technology:
AOI31

Pin Pin
A0 0.0168 0.0230 0.0505 0.0734 A0 0.0037 0.0049 0.0111 0.0034
A1 0.0217 0.0301 0.0630 0.0787 A1 0.0036 0.0049 0.0101 0.0034
A2 0.0262 0.0364 0.0762 0.0837 A2 0.0034 0.0047 0.0096 0.0032
B0 0.0214 0.0296 0.0606 0.0797 B0 0.0032 0.0044 0.0081 0.0033

Description
A0 → Y↑ 0.0659 0.0606 0.0651 0.2108 9.5939 6.5889 3.2951 1.0898
A0 → Y↓ 0.0374 0.0357 0.0380 0.1693 4.7194 3.2998 1.6523 0.6375
A1 → Y↑ 0.0842 0.0789 0.0815 0.2323 9.5793 6.5830 3.2918 1.0899
A1 → Y↓ 0.0450 0.0436 0.0445 0.1770 4.7186 3.2998 1.6517 0.6375
A2 → Y↑ 0.1000 0.0942 0.0977 0.2506 9.5861 6.5860 3.2932 1.0899
A2 → Y↓ 0.0488 0.0474 0.0488 0.1807 4.7180 3.2992 1.6517 0.6375
B0 → Y↑ 0.0797 0.0766 0.0747 0.2325 9.5987 6.5919 3.2957 1.0899
B0 → Y↓ 0.0219 0.0223 0.0224 0.1417 3.3180 2.4479 1.2717 0.6371
57
Process Technology:
AOI32

A0
the logic equation: A2
Y = ( A0 • A1 • A2 ) + ( B0 • B1 ) Y
Functions B0
B1
A0 A1 A2 B0 B1 Y
0 x x 0 x 1
Cell Size
0 x x x 0 1
x 0 x 0 x 1 Drive Strength Height (um) Width (um)
x 0 x x 0 1 AOI32XL 5.04 4.62
x x 0 0 x 1 AOI32X1 5.04 4.62
x x 0 x 0 1 AOI32X2 5.04 7.26
x x x 1 1 0 AOI32X4 5.04 6.60
1 1 1 x x 0
A0
A1
A2
B0
B1
58
Process Technology:
AOI32

Pin Pin
A0 0.0248 0.0333 0.0661 0.0807 A0 0.0037 0.0049 0.0095 0.0034
A1 0.0297 0.0402 0.0798 0.0861 A1 0.0037 0.0048 0.0102 0.0034
A2 0.0342 0.0465 0.0933 0.0912 A2 0.0035 0.0047 0.0105 0.0032
B0 0.0241 0.0328 0.0645 0.0812 B0 0.0036 0.0047 0.0091 0.0034
B1 0.0281 0.0383 0.0757 0.0859 B1 0.0036 0.0047 0.0096 0.0035

Description
A0 → Y↑ 0.0987 0.0913 0.0892 0.2431 9.5887 6.5760 3.2939 1.0898
A0 → Y↓ 0.0525 0.0505 0.0492 0.1847 4.7211 3.3009 1.6506 0.6227
A1 → Y↑ 0.1173 0.1092 0.1072 0.2645 9.5776 6.5709 3.2915 1.0899
A1 → Y↓ 0.0605 0.0582 0.0570 0.1925 4.7209 3.3012 1.6505 0.6227
A2 → Y↑ 0.1332 0.1248 0.1237 0.2828 9.5838 6.5730 3.2928 1.0898
A2 → Y↓ 0.0642 0.0621 0.0616 0.1963 4.7211 3.3011 1.6504 0.6228
B0 → Y↑ 0.0890 0.0841 0.0826 0.2365 9.6006 6.5815 3.2965 1.0899
B0 → Y↓ 0.0288 0.0282 0.0274 0.1604 4.0607 2.9143 1.4571 0.6226
B1 → Y↑ 0.1051 0.0987 0.0975 0.2547 9.5912 6.5764 3.2942 1.0898
B1 → Y↓ 0.0334 0.0324 0.0317 0.1649 4.0614 2.9146 1.4573 0.6227
59
Process Technology:
AOI33

A0
the logic equation: A2
Y = ( A0 • A1 • A2 ) + ( B0 • B1 • B2 ) Y
B0
Functions B1
B2
A0 A1 A2 B0 B1 B2 Y
0 x x 0 x x 1
0 x x x 0 x 1 Cell Size
0 x x x x 0 1
x 0 x 0 x x 1
AOI33XL 5.04 5.28
x 0 x x 0 x 1
AOI33X1 5.04 5.28
x 0 x x x 0 1
AOI33X2 5.04 8.58
x x 0 0 x x 1
AOI33X4 5.04 7.26
x x 0 x 0 x 1
x x 0 x x 0 1
x x x 1 1 1 0
1 1 1 x x x 0
A0
A1
A2
B0
B1
B2
60
Process Technology:
AOI33

Pin Pin
A0 0.0259 0.0358 0.0705 0.0843 A0 0.0037 0.0051 0.0097 0.0035
A1 0.0306 0.0424 0.0833 0.0897 A1 0.0037 0.0052 0.0104 0.0036
A2 0.0350 0.0485 0.0965 0.0951 A2 0.0037 0.0050 0.0112 0.0037
B0 0.0323 0.0449 0.0901 0.0905 B0 0.0036 0.0049 0.0093 0.0033
B1 0.0372 0.0517 0.1032 0.0960 B1 0.0036 0.0049 0.0101 0.0034
B2 0.0415 0.0580 0.1169 0.1010 B2 0.0034 0.0047 0.0106 0.0031

Description
A0 → Y↑ 0.1012 0.0961 0.0914 0.2515 9.5989 6.5815 3.2966 1.0899
A0 → Y↓ 0.0366 0.0356 0.0341 0.1820 4.7344 3.3096 1.6885 0.6379
A1 → Y↑ 0.1204 0.1149 0.1090 0.2731 9.5915 6.5769 3.2942 1.0897
A1 → Y↓ 0.0449 0.0438 0.0418 0.1901 4.7346 3.3097 1.6885 0.6379
A2 → Y↑ 0.1377 0.1310 0.1275 0.2941 9.5937 6.5782 3.2953 1.0897
A2 → Y↓ 0.0494 0.0478 0.0472 0.1953 4.7350 3.3098 1.6888 0.6379
B0 → Y↑ 0.1317 0.1256 0.1225 0.2868 9.5956 6.5799 3.2956 1.0899
B0 → Y↓ 0.0651 0.0641 0.0638 0.2059 4.7141 3.2993 1.6840 0.6380
B1 → Y↑ 0.1504 0.1435 0.1401 0.3080 9.5871 6.5758 3.2938 1.0898
B1 → Y↓ 0.0732 0.0720 0.0716 0.2138 4.7139 3.2988 1.6838 0.6381
B2 → Y↑ 0.1666 0.1594 0.1571 0.3261 9.5888 6.5765 3.2942 1.0897
B2 → Y↓ 0.0770 0.0759 0.0769 0.2174 4.7135 3.2982 1.6836 0.6380
61
Process Technology:
BUF

The BUF cell provides the logical buffer of a single
input (A). The output (Y) is represented by the logic
A Y
equation:
Y = A
Cell Size
Functions
A Y
BUFXL 5.04 2.64
0 0
BUFX1 5.04 2.64
1 1
BUFX2 5.04 2.64
BUFX3 5.04 2.64
BUFX4 5.04 3.30
BUFX8 5.04 5.94
BUFX12 5.04 6.60
BUFX16 5.04 8.58
BUFX20 5.04 10.56
A Y
62
Process Technology:
BUF
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0155 0.0183 0.0296 0.0420 0.0540 0.1016 0.1517 0.2052 0.2527
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0023 0.0023 0.0033 0.0045 0.0058 0.0107 0.0159 0.0207 0.0260

Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑
0.0547 0.0578 0.0592 0.0571 0.0567 0.0528 0.0532 0.0541 0.0531
A → Y↓
0.0855 0.0966 0.0901 0.0855 0.0823 0.0779 0.0780 0.0780 0.0762
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑
6.4641 4.5346 2.2345 1.4676 1.1176 0.5447 0.3632 0.2724 0.2179
A → Y↓
3.3425 2.4618 1.2769 0.8436 0.6383 0.3181 0.2121 0.1584 0.1277
63
Process Technology:
CLKBUF

The CLKBUF cell provides the logical buffer of a
single input (A), with balanced delays for clock
A Y
signals. The output (Y) is represented by the logic
equation:
Y = A
Cell Size
Functions Drive Strength Height (um) Width (um)
A Y CLKBUFXL 5.04 2.64

CLKBUFX1 5.04 2.64
0 0
CLKBUFX2 5.04 2.64
1 1
CLKBUFX3 5.04 2.64
CLKBUFX4 5.04 3.30
CLKBUFX8 5.04 4.62
CLKBUFX12 5.04 10.56
CLKBUFX16 5.04 12.54
CLKBUFX20 5.04 15.84
A Y
64
Process Technology:
CLKBUF
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0158 0.0200 0.0247 0.0325 0.0402 0.0781 0.1916 0.2525 0.3144
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0021 0.0035 0.0030 0.0034 0.0041 0.0077 0.0187 0.0224 0.0307

Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑
0.0506 0.0575 0.0652 0.0741 0.0753 0.0714 0.0703 0.0745 0.0693
A → Y↓
0.1236 0.0622 0.0836 0.0903 0.0877 0.0820 0.0793 0.0839 0.0779
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑
4.0645 4.1450 2.2348 1.5158 1.1187 0.5453 0.2186 0.1683 0.1366
A → Y↓
4.2584 4.1860 2.3009 1.4084 1.0903 0.5215 0.2118 0.1635 0.1276
65
Process Technology:
CLKINV

The CLKINV cell provides the logical inversion of a
single input A, with balanced delays for clock signals.
A Y
The output Y is represented by the logic equation:
Y = A
Cell Size
Functions
A Y
CLKINVXL 5.04 1.98
0 1
CLKINVX1 5.04 1.98
1 0
CLKINVX2 5.04 1.98
CLKINVX3 5.04 1.98
CLKINVX4 5.04 2.64
CLKINVX8 5.04 3.96
CLKINVX12 5.04 12.54
CLKINVX16 5.04 16.50
CLKINVX20 5.04 19.14
A Y
66
Process Technology:
CLKINV
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8
A 0.0086 0.0104 0.0179 0.0251 0.0334 0.0700
Power (µW/MHz)
Pin
X12 X16 X20
A 0.2364 0.3150 0.3918
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8
A 0.0026 0.0031 0.0056 0.0082 0.0106 0.0219
Capacitance (pF)
Pin
X12 X16 X20
A 0.0065 0.0083 0.0102

Description
XL X1 X2 X3 X4 X8
A → Y↑ 0.0241 0.0221 0.0180 0.0165 0.0164 0.0169
A → Y↓ 0.0211 0.0207 0.0196 0.0175 0.0177 0.0178

Description
X12 X16 X20
A → Y↑ 0.1384 0.1402 0.1372
A → Y↓ 0.1403 0.1399 0.1394
67
Process Technology:
CLKINV
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8
A → Y↑ 5.8873 4.5292 2.2645 1.4763 1.1092 0.5462
A → Y↓ 4.3565 3.6900 2.2916 1.4001 1.0844 0.5223
Kload (ns/pF)
Description
X12 X16 X20
A → Y↑ 0.2195 0.1648 0.1318
A → Y↓ 0.2121 0.1591 0.1273
68
Process Technology:
DFF

The DFF cell is a positive-edge triggered, static
D-type flip-flop.
D Q
Function Table
CK QN
D CK Q[n+1] QN[n+1]
0 0 1
1 1 0 Cell Size
x Q[n] QN[n]
DFFXL 5.04 11.22
DFFX1 5.04 11.22
DFFX2 5.04 13.86
DFFX4 5.04 16.50
cn c
c cn
c cn
D QN
cn c
Q
cn
CK c
69
Process Technology:
DFF

Pin Pin
D 0.0342 0.0296 0.0396 0.0626 D 0.0034 0.0021 0.0026 0.0039
CK 0.0615 0.0593 0.0768 0.1143 CK 0.0021 0.0027 0.0038 0.0059
Q 0.0360 0.0398 0.0687 0.1144

Description
CK → Q↑ 0.2440 0.2157 0.1950 0.1665 6.3863 4.6243 2.2730 1.1329
CK → Q↓ 0.1963 0.1748 0.1644 0.1429 3.4897 2.5064 1.2530 0.6462
CK → QN↑ 0.2612 0.2319 0.2118 0.1888 6.4748 4.5396 2.2685 1.1314
CK → QN↓ 0.3415 0.3065 0.2784 0.2371 3.4085 2.4775 1.2357 0.6392
Timing Constraints at 25 oC, 1.8V, Typical Process
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0391 0.0625 0.0625 0.0547
setup↓ → CK 0.0977 0.1680 0.1641 0.1406
D
hold↑ → CK -0.0273 -0.0391 -0.0391 -0.0352
hold↓ → CK 0.0156 -0.0547 -0.0508 -0.0352
minpwh 0.1238 0.1140 0.1092 0.0946
CK
minpwl 0.1868 0.1674 0.1529 0.1238
70
Process Technology:
DFFHQ

The DFFHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop. The cell has a single
output (Q) and fast clock-to-out path. D Q
CK
Functions
D CK Q[n+1]
0 0
Cell Size
1 1
x Q[n] Drive Strength Height (um) Width (um)
DFFHQXL 5.04 10.56
DFFHQX1 5.04 10.56
DFFHQX2 5.04 13.20
DFFHQX4 5.04 14.52
cn c
c cn
c cn
cn c
Q
cn
CK c
71
Process Technology:
DFFHQ

Pin Pin
D 0.0386 0.0392 0.0552 0.0763 D 0.0036 0.0023 0.0024 0.0032
CK 0.0660 0.0697 0.0919 0.1230 CK 0.0022 0.0030 0.0037 0.0052
Q 0.0260 0.0282 0.0443 0.0605

Description
CK → Q↑ 0.2205 0.1845 0.1800 0.1577 6.4814 4.6185 2.2709 1.1116
CK → Q↓ 0.2276 0.1668 0.1662 0.1422 3.6182 2.6093 1.3075 0.6451
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0508 0.0938 0.0938 0.0781
setup↓ → CK 0.1445 0.2070 0.2148 0.1875
D
hold↑ → CK -0.0195 -0.0430 -0.0391 -0.0391
hold↓ → CK 0.0117 -0.0547 -0.0508 -0.0391
minpwh 0.1383 0.1043 0.1043 0.0946
CK
minpwl 0.1723 0.1626 0.1529 0.1238
72
Process Technology:
DFFN

The DFFN cell is a negative-edge triggered, static
D-type flip-flop.
D Q
Functions
CKN QN
D CKN Q[n+1] QN[n+1]
0 0 1
1 1 0 Cell Size
x Q[n] QN[n]
DFFNXL 5.04 11.22
DFFNX1 5.04 11.22
DFFNX2 5.04 13.86
DFFNX4 5.04 15.84
cn c
c cn
c cn
D QN
cn c
Q
CKN cn
73
Process Technology:
DFFN

Pin Pin
D 0.0342 0.0303 0.0400 0.0586 D 0.0030 0.0019 0.0023 0.0028
CKN 0.0537 0.0523 0.0652 0.0889 CKN 0.0021 0.0029 0.0037 0.0061
Q 0.0365 0.0423 0.0723 0.1188

Description
CKN → Q↑ 0.1980 0.1549 0.1386 0.1166 6.3944 4.6255 2.2735 1.1699
CKN → Q↓ 0.3422 0.2847 0.2606 0.2180 3.4975 2.5765 1.2883 0.6475
CKN → QN↑ 0.3971 0.3410 0.3073 0.2696 6.4775 4.5399 2.2686 1.1684
CKN → QN↓ 0.2876 0.2466 0.2222 0.1884 3.4012 2.4775 1.2356 0.6406
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.0391 0.0781 0.0820 0.0781
setup↓ → CKN 0.0586 0.1445 0.1367 0.1289
D
hold↑ → CKN 0.0977 0.0469 0.0391 0.0234
hold↓ → CKN -0.0430 -0.1094 -0.1016 -0.0977
minpwl 0.2159 0.1723 0.1577 0.1286
CKN
minpwh 0.1335 0.1626 0.1432 0.1189
74
Process Technology:
DFFNR

The DFFNR cell is a negative-edge triggered, static
D-type flip-flop with asynchronous active-low reset
(RN). D Q
CKN QN
Functions
RN D CKN Q[n+1] QN[n+1]

0 x x 0 1 RN
1 0 0 1
1 1 1 0
Cell Size
1 x Q[n] QN[n]
DFFNRXL 5.04 15.84
DFFNRX1 5.04 15.18
DFFNRX2 5.04 17.16
DFFNRX4 5.04 20.46
cn c
c cn
c cn
D Q
cn c
QN
RN
CKN cn
75
Process Technology:
DFFNR

Pin Pin
D 0.0364 0.0287 0.0330 0.0430 D 0.0034 0.0022 0.0021 0.0029
CKN 0.0622 0.0554 0.0627 0.0748 CKN 0.0024 0.0028 0.0029 0.0038
RN 0.0181 0.0197 0.0238 0.0361 RN 0.0022 0.0025 0.0032 0.0057
Q 0.0449 0.0520 0.0829 0.1385

Description
CKN → Q↑ 0.4063 0.3440 0.3306 0.2969 6.4716 4.5373 2.1886 1.1160
CKN → Q↓ 0.4778 0.4582 0.4546 0.3931 3.3504 2.4657 1.2773 0.6425
RN → Q↓ 0.2692 0.2665 0.2446 0.2175 3.3502 2.4651 1.2770 0.6424
CKN → QN↑ 0.4197 0.3852 0.3769 0.3229 6.4699 4.5378 2.1896 1.1166
CKN → QN↓ 0.3780 0.3081 0.2816 0.2481 3.6198 2.5291 1.3013 0.6538
RN → QN↑ 0.2113 0.1941 0.1675 0.1479 6.4784 4.5400 2.1909 1.1174
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.0391 0.0820 0.1172 0.0938
setup↓ → CKN 0.0664 0.1484 0.1680 0.1289
D
hold↑ → CKN 0.1094 0.0469 0.0430 0.0391
hold↓ → CKN -0.0391 -0.1055 -0.1094 -0.0898
minpwl 0.2353 0.2111 0.2014 0.1674
CKN
minpwh 0.1432 0.1626 0.1868 0.1529
minpwl 0.2062 0.2111 0.2450 0.3664
RN
recovery 0.0312 0.0742 0.1055 0.0781
76
Process Technology:
DFFNS

The DFFNS cell is a negative-edge triggered, static
SN
D-type flip-flop with asynchronous active-low set
(SN).
Functions D Q
SN D CKN Q[n+1] QN[n+1] CKN QN
0 x x 1 0
1 0 0 1
1 1 1 0 Cell Size
1 x Q[n] QN[n]
DFFNSXL 5.04 13.86
DFFNSX1 5.04 13.86
DFFNSX2 5.04 13.86
DFFNSX4 5.04 19.14
cn c
c cn
c cn
D Q
cn c
QN
SN
c
CKN cn
77
Process Technology:
DFFNS

Pin Pin
D 0.0349 0.0265 0.0297 0.0380 D 0.0029 0.0018 0.0019 0.0021
CKN 0.0561 0.0488 0.0524 0.0651 CKN 0.0020 0.0026 0.0028 0.0033
SN 0.0063 0.0071 0.0103 0.0173 SN 0.0051 0.0055 0.0072 0.0123
Q 0.0417 0.0494 0.0771 0.1383

Description
CKN → Q↑ 0.3255 0.2876 0.2804 0.2692 6.4706 4.5365 2.2617 1.1127
CKN → Q↓ 0.4516 0.4328 0.4118 0.3942 3.3453 2.4610 1.2777 0.6388
SN → Q↑ 0.1763 0.1564 0.1565 0.1497 6.4705 4.5367 2.2620 1.1125
CKN → QN↑ 0.4001 0.3672 0.3381 0.3243 6.4874 4.5429 2.2666 1.1149
CKN → QN↓ 0.2982 0.2525 0.2318 0.2207 3.4347 2.4719 1.2820 0.6410
SN → QN↓ 0.1488 0.1212 0.1080 0.1016 3.4093 2.4705 1.2841 0.6433
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.0156 0.0625 0.0625 0.0625
setup↓ → CKN 0.0664 0.1406 0.1523 0.1367
D
hold↑ → CKN 0.1055 0.0469 0.0469 0.0430
hold↓ → CKN -0.0508 -0.1094 -0.1211 -0.1094
minpwl 0.2159 0.1965 0.1723 0.1674
CKN
minpwh 0.1286 0.1480 0.1529 0.1432
minpwl 0.1383 0.1189 0.1189 0.1480
SN
recovery -0.1055 -0.0547 -0.0508 -0.0469
78
Process Technology:
DFFNSR

SN
The DFFNSR cell is a negative-edge triggered, static
(RN) and set (SN), and set dominating reset.
D Q
Functions
CKN QN
RN SN D CKN Q[n+1] QN[n+1]
0 1 x x 0 1
1 0 x x 1 0 RN
0 0 x x 1 0
1 1 0 0 1
Cell Size
1 1 1 1 0
1 1 x Q[n] QN[n] Drive Strength Height (um) Width (um)
DFFNSRXL 5.04 17.16
DFFNSRX1 5.04 16.50
DFFNSRX2 5.04 17.16
DFFNSRX4 5.04 23.10
cn c
c cn
c cn
D Q
cn c
QN
RN
SN
c
CKN cn
79
Process Technology:
DFFNSR

Pin Pin
D 0.0416 0.0330 0.0368 0.0524 D 0.0033 0.0022 0.0020 0.0032
CKN 0.0634 0.0560 0.0602 0.0813 CKN 0.0022 0.0027 0.0029 0.0041
SN 0.0084 0.0088 0.0122 0.0183 SN 0.0065 0.0068 0.0090 0.0152
RN 0.0198 0.0216 0.0268 0.0444 RN 0.0025 0.0028 0.0038 0.0058
Q 0.0469 0.0528 0.0824 0.1507

Description
CKN → Q↑ 0.4063 0.3474 0.3273 0.3083 6.4679 4.5358 2.2621 1.1193
CKN → Q↓ 0.4861 0.4662 0.4287 0.3985 3.1385 2.4685 1.2786 0.6375
SN → Q↑ 0.2073 0.1868 0.1752 0.1676 6.4688 4.5357 2.2619 1.1192
SN → Q↓ 0.2035 0.1925 0.1762 0.1661 3.1391 2.4683 1.2783 0.6374
RN → Q↓ 0.3031 0.2877 0.2519 0.2361 3.1390 2.4683 1.2783 0.6373
CKN → QN↑ 0.4171 0.3842 0.3543 0.3284 6.4997 4.5468 2.2670 1.1224
CKN → QN↓ 0.3685 0.3051 0.2755 0.2607 3.6910 2.5394 1.3040 0.6528
SN → QN↑ 0.1350 0.1114 0.1024 0.0963 6.5242 4.5580 2.2726 1.1260
SN → QN↓ 0.1667 0.1415 0.1230 0.1201 3.4629 2.4909 1.2894 0.6478
RN → QN↑ 0.2344 0.2063 0.1779 0.1662 6.5216 4.5573 2.2724 1.1258
80
Process Technology:
DFFNSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.0664 0.1523 0.1289 0.1055
setup↓ → CKN 0.1016 0.1836 0.1992 0.1445
D
hold↑ → CKN 0.0820 0.0195 0.0273 0.0352
hold↓ → CKN -0.0703 -0.1211 -0.1445 -0.1055
minpwl 0.2159 0.2062 0.1820 0.1626
CKN
minpwh 0.1383 0.1723 0.1723 0.1383
minpwl 0.1626 0.1432 0.1383 0.1771
SN recovery -0.0820 -0.0430 -0.0391 -0.0391
removal 0.0898 0.0508 0.0469 0.0508
minpwl 0.2208 0.2111 0.2353 0.3858
RN recovery 0.0586 0.1289 0.0938 0.0938
removal 0.1055 0.0273 0.0586 0.0586
81
Process Technology:
DFFR

The DFFR cell is a positive-edge triggered, static
D-type flip-flop with asynchronous active-low
reset (RN). D Q
CK QN
Functions
RN D CK Q[n+1] QN[n+1]
0 x x 0 1 RN
1 0 0 1
1 1 1 0
Cell Size
1 x Q[n] QN[n]
DFFRXL 5.04 15.18
DFFRX1 5.04 15.18
DFFRX2 5.04 17.16
DFFRX4 5.04 19.80
cn c
c cn
c cn
D Q
cn c
QN
RN
cn
CK c
82
Process Technology:
DFFR

Pin Pin
D 0.0357 0.0286 0.0321 0.0426 D 0.0033 0.0022 0.0020 0.0029
CK 0.0653 0.0604 0.0717 0.0829 CK 0.0022 0.0027 0.0028 0.0039
RN 0.0171 0.0193 0.0234 0.0356 RN 0.0020 0.0025 0.0032 0.0057
Q 0.0461 0.0523 0.0823 0.1394

Description
CK → Q↑ 0.4606 0.4169 0.4050 0.3565 6.4746 4.5374 2.1883 1.1159
CK → Q↓ 0.3130 0.3372 0.3167 0.2828 3.3500 2.4659 1.2381 0.6426
RN → Q↓ 0.2645 0.2655 0.2440 0.2171 3.3498 2.4653 1.2379 0.6424
CK → QN↑ 0.2575 0.2641 0.2398 0.2127 6.4720 4.5375 2.1896 1.1166
CK → QN↓ 0.4348 0.3811 0.3551 0.3077 3.6196 2.5298 1.2621 0.6538
RN → QN↑ 0.2093 0.1932 0.1678 0.1475 6.4792 4.5400 2.1907 1.1174
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0508 0.0703 0.0938 0.0703
setup↓ → CK 0.0938 0.1641 0.1953 0.1523
D
hold↑ → CK -0.0352 -0.0508 -0.0625 -0.0469
hold↓ → CK 0.0352 -0.0508 -0.0391 -0.0352
minpwh 0.1383 0.1480 0.1335 0.1140
CK
minpwl 0.2111 0.1917 0.2111 0.1577
minpwl 0.2062 0.2062 0.2450 0.3664
RN recovery 0.0430 0.0508 0.0781 0.0508
removal -0.0234 -0.0352 -0.0469 -0.0117
83
Process Technology:
DFFRHQ

The DFFRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with asynchronous
active-low reset (RN). The cell has a single output D Q
(Q) and fast clock-to-out path.
CK
Functions
RN D CK Q[n+1] RN
0 x x 0
1 0 0
1 1 1 Cell Size
1 x Q[n]
DFFRHQXL 5.04 13.86
DFFRHQX1 5.04 13.86
DFFRHQX2 5.04 17.16
DFFRHQX4 5.04 21.12
cn c
c cn
c cn
D Q
cn c
RN
cn
CK c
84
Process Technology:
DFFRHQ

Pin Pin
D 0.0368 0.0420 0.0650 0.1002 D 0.0032 0.0020 0.0027 0.0044
CK 0.0659 0.0771 0.1069 0.1565 CK 0.0020 0.0031 0.0041 0.0062
RN 0.0219 0.0275 0.0379 0.0589 RN 0.0026 0.0041 0.0056 0.0093
Q 0.0345 0.0365 0.0493 0.0762

Description
CK → Q↑ 0.2533 0.2074 0.1821 0.1661 9.6066 6.5771 3.2881 1.8061
CK → Q↓ 0.2738 0.1791 0.1585 0.1444 3.7511 2.4986 1.2909 0.7102
RN → Q↓ 0.1978 0.1413 0.1209 0.1026 3.1138 2.0833 1.1794 0.6918
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0781 0.1250 0.1250 0.1133
setup↓ → CK 0.1523 0.2227 0.2109 0.1797
D
hold↑ → CK -0.0234 -0.0508 -0.0469 -0.0391
hold↓ → CK 0.0234 -0.0430 -0.0273 -0.0156
minpwh 0.1723 0.1189 0.1043 0.0946
CK
minpwl 0.1868 0.1723 0.1480 0.1238
minpwl 0.2984 0.2936 0.4003 0.6284
RN recovery 0.0977 0.1172 0.1172 0.1055
removal -0.0273 -0.0391 -0.0234 -0.0078
85
Process Technology:
DFFS

The DFFS cell is a positive-edge triggered, static D-
SN
type flip-flop with asynchronous active-low set (SN).
Functions
D Q
SN D CK Q[n+1] QN[n+1]
CK QN
0 x x 1 0
1 0 0 1
1 1 1 0
1 x Q[n] QN[n] Cell Size

DFFSXL 5.04 12.54
DFFSX1 5.04 12.54
DFFSX2 5.04 13.86
DFFSX4 5.04 18.48
cn c
c cn
c cn
D Q
cn c
QN
SN
cn
CK c
86
Process Technology:
DFFS

Pin Pin
D 0.0337 0.0255 0.0294 0.0360 D 0.0033 0.0020 0.0020 0.0023
CK 0.0595 0.0532 0.0603 0.0752 CK 0.0022 0.0029 0.0030 0.0034
SN 0.0065 0.0073 0.0117 0.0178 SN 0.0055 0.0058 0.0078 0.0128
Q 0.0402 0.0466 0.0780 0.1337

Description
CK → Q↑ 0.3753 0.3421 0.3485 0.3268 6.4710 4.5372 2.1828 1.1177
CK → Q↓ 0.2987 0.3116 0.3074 0.2814 3.3486 2.4628 1.2782 0.6383
SN → Q↑ 0.1767 0.1536 0.1586 0.1485 6.4720 4.5372 2.1829 1.1176
CK → QN↑ 0.2461 0.2465 0.2321 0.2139 6.4873 4.7621 2.1879 1.0939
CK → QN↓ 0.3474 0.3081 0.3001 0.2800 3.4385 2.6227 1.2828 0.6407
SN → QN↓ 0.1490 0.1197 0.1105 0.1023 3.4181 2.6213 1.2850 0.6432
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0352 0.0586 0.0586 0.0547
setup↓ → CK 0.0977 0.1641 0.1719 0.1602
D
hold↑ → CK -0.0273 -0.0430 -0.0430 -0.0391
hold↓ → CK 0.0078 -0.0664 -0.0664 -0.0508
minpwh 0.1189 0.1335 0.1189 0.1092
CK
minpwl 0.1771 0.1626 0.1674 0.1577
minpwl 0.1432 0.1189 0.1238 0.1480
SN recovery -0.0156 -0.0039 0.0000 0.0078
removal 0.1523 0.1094 0.1133 0.1055
87
Process Technology:
DFFSHQ

The DFFSHQ cell is a high-speed, positive-edge
SN
active-low set (SN). The cell has a single output (Q)
and fast clock-to-out path.
D Q
Functions
CK
SN D CK Q[n+1]
0 x x 1
1 0 0
Cell Size
1 1 1
1 x Q[n] Drive Strength Height (um) Width (um)
DFFSHQXL 5.04 13.20
DFFSHQX1 5.04 13.20
DFFSHQX2 5.04 15.84
DFFSHQX4 5.04 18.48
cn c
c cn
c cn
D Q
cn c
SN
cn
CK c
88
Process Technology:
DFFSHQ

Pin Pin
D 0.0380 0.0419 0.0590 0.0907 D 0.0035 0.0020 0.0026 0.0039
CK 0.0661 0.0743 0.0972 0.1436 CK 0.0022 0.0029 0.0037 0.0056
SN 0.0103 0.0112 0.0197 0.0315 SN 0.0086 0.0092 0.0145 0.0221
Q 0.0335 0.0335 0.0488 0.0778

Description
CK → Q↑ 0.2498 0.2127 0.1904 0.1648 6.5120 4.5437 2.2382 1.1187
CK → Q↓ 0.2648 0.1806 0.1581 0.1436 4.4128 2.9533 1.4720 0.7458
SN → Q↑ 0.0774 0.0865 0.0872 0.0907 3.6146 2.4641 1.2649 0.6731
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0469 0.0938 0.0859 0.0820
setup↓ → CK 0.1719 0.2539 0.2148 0.1875
D
hold↑ → CK -0.0195 -0.0469 -0.0391 -0.0352
hold↓ → CK 0.0117 -0.0742 -0.0430 -0.0312
minpwh 0.1723 0.1238 0.1140 0.0946
CK
minpwl 0.1771 0.1674 0.1432 0.1238
minpwl 0.1189 0.1383 0.1674 0.2305
SN recovery 0.0547 0.0586 0.0664 0.0625
removal 0.1562 0.1172 0.1172 0.1133
89
Process Technology:
DFFSR

The DFFSR cell is a positive-edge triggered, static
SN
Functions D Q
RN SN D CK Q[n+1] QN[n+1] CK QN
0 1 x x 0 1
1 0 x x 1 0
0 0 x x 1 0 RN
1 1 0 0 1
1 1 1 1 0
Cell Size
1 1 x Q[n] QN[n]
DFFSRXL 5.04 17.16
DFFSRX1 5.04 17.16
DFFSRX2 5.04 17.16
DFFSRX4 5.04 23.76
cn c
c cn
c cn
D Q
cn c
QN
RN
SN
cn
CK c
90
Process Technology:
DFFSR

Pin Pin
D 0.0408 0.0329 0.0373 0.0512 D 0.0032 0.0020 0.0020 0.0032
CK 0.0685 0.0631 0.0687 0.0926 CK 0.0024 0.0029 0.0031 0.0041
SN 0.0094 0.0098 0.0134 0.0193 SN 0.0065 0.0069 0.0091 0.0153
RN 0.0194 0.0208 0.0259 0.0440 RN 0.0024 0.0027 0.0038 0.0059
Q 0.0483 0.0544 0.0837 0.1492

Description
CK → Q↑ 0.4485 0.4007 0.3794 0.3641 6.4700 4.5364 2.2621 1.1194
CK → Q↓ 0.3403 0.3490 0.3090 0.2979 3.3704 2.4709 1.2786 0.6376
SN → Q↑ 0.2087 0.1877 0.1752 0.1682 6.4696 4.5365 2.2620 1.1193
SN → Q↓ 0.2062 0.1947 0.1761 0.1671 3.3710 2.4706 1.2783 0.6374
RN → Q↓ 0.3172 0.2914 0.2517 0.2371 3.3709 2.4705 1.2784 0.6374
CK → QN↑ 0.2692 0.2659 0.2345 0.2268 6.5014 4.5470 2.2670 1.1223
CK → QN↓ 0.4104 0.3584 0.3274 0.3155 3.7040 2.5434 1.3041 0.6526
SN → QN↑ 0.1357 0.1126 0.1021 0.0962 6.5273 4.5579 2.2726 1.1259
SN → QN↓ 0.1678 0.1426 0.1229 0.1198 3.4694 2.4923 1.2895 0.6476
RN → QN↑ 0.2463 0.2091 0.1776 0.1661 6.5244 4.5572 2.2724 1.1258
91
Process Technology:
DFFSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0781 0.1484 0.1211 0.0859
setup↓ → CK 0.1328 0.2070 0.2227 0.1719
D
hold↑ → CK -0.0547 -0.0938 -0.0781 -0.0508
hold↓ → CK 0.0078 -0.0312 -0.0664 -0.0352
minpwh 0.1189 0.1432 0.1140 0.1140
CK
minpwl 0.2062 0.2256 0.2062 0.1577
minpwl 0.1626 0.1432 0.1383 0.1771
SN recovery 0.0000 0.0117 0.0195 0.0156
removal 0.1367 0.1055 0.1055 0.1055
minpwl 0.2353 0.2111 0.2353 0.3906
RN recovery 0.0664 0.1250 0.0898 0.0664
removal -0.0430 -0.0859 -0.0586 -0.0234
92
Process Technology:
DFFSRHQ

The DFFSRHQ cell is a high-speed, positive-edge
SN
active-low reset (RN) and set (SN), and set
dominating reset. The cell has a single output (Q)
and fast clock-to-out path. D Q
Functions CK
RN SN D CK Q[n+1]
0 1 x x 0 RN
1 0 x x 1
0 0 x x 1
1 1 0 0 Cell Size
1 1 1 1
1 1 x Q[n]
DFFSRHQXL 5.04 15.84
DFFSRHQX1 5.04 15.84
cn c
c cn
c cn
D Q
cn c
RN
SN
cn
CK c
93
Process Technology:
DFFSRHQ

Pin Pin
D 0.0394 0.0444 0.0672 0.1088 D 0.0035 0.0024 0.0032 0.0050
CK 0.0681 0.0792 0.1140 0.1792 CK 0.0022 0.0032 0.0044 0.0065
SN 0.0132 0.0145 0.0201 0.0338 SN 0.0114 0.0123 0.0175 0.0287
RN 0.0269 0.0321 0.0474 0.0756 RN 0.0027 0.0040 0.0059 0.0102
Q 0.0353 0.0368 0.0573 0.0949

Description
CK → Q↑ 0.2645 0.2162 0.1999 0.1861 9.6061 6.5783 3.2892 1.6444
CK → Q↓ 0.2655 0.1730 0.1636 0.1514 4.3621 2.9385 1.4841 0.7491
SN → Q↑ 0.0853 0.0916 0.0967 0.0954 4.1295 2.8462 1.4615 0.7697
SN → Q↓ 0.0514 0.0548 0.0494 0.0428 3.9368 2.6938 1.4404 0.7469
RN → Q↓ 0.2063 0.1418 0.1196 0.1064 4.0011 2.6947 1.4402 0.7474
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0938 0.1367 0.1328 0.1211
setup↓ → CK 0.1680 0.2227 0.2070 0.1914
D
hold↑ → CK -0.0234 -0.0508 -0.0430 -0.0352
hold↓ → CK 0.0273 -0.0156 -0.0078 -0.0039
minpwh 0.1674 0.1238 0.1092 0.0995
CK
minpwl 0.1917 0.1771 0.1480 0.1286
minpwl 0.1383 0.1674 0.2014 0.2742
SN recovery 0.0625 0.0664 0.0742 0.0781
removal 0.1484 0.1055 0.1094 0.1133
minpwl 0.3081 0.2208 0.3372 0.5750
RN recovery 0.1055 0.1328 0.1250 0.1133
removal -0.0273 -0.0547 -0.0312 -0.0078
94
Process Technology:
DFFTR

The DFFTR cell is a positive-edge triggered,
static D-type flip-flop with synchronous active-low
reset (RN). D Q
CK QN
Functions
RN D CK Q[n+1] QN[n+1]
0 x 0 1 RN
x x Q[n] QN[n]
1 0 0 1
Cell Size
1 1 1 0
DFFTRXL 5.04 11.22
DFFTRX1 5.04 11.22
DFFTRX2 5.04 13.86
DFFTRX4 5.04 16.50
cn c
c cn
c cn
D
Q
RN
cn c
QN
cn
CK c
95
Process Technology:
DFFTR

Pin Pin
D 0.0311 0.0297 0.0377 0.0587 D 0.0030 0.0023 0.0024 0.0034
CK 0.0610 0.0631 0.0785 0.1152 CK 0.0023 0.0031 0.0040 0.0063
RN 0.0338 0.0318 0.0400 0.0620 RN 0.0026 0.0019 0.0019 0.0030
Q 0.0307 0.0371 0.0674 0.1128

Description
CK → Q↑ 0.2393 0.2213 0.2141 0.1708 6.4748 4.5395 2.2383 1.1192
CK → Q↓ 0.1831 0.1643 0.1573 0.1434 3.4621 2.4947 1.2972 0.6463
CK → QN↑ 0.2293 0.2132 0.2124 0.1917 6.4786 4.5401 2.2358 1.1179
CK → QN↓ 0.3169 0.3019 0.2961 0.2395 3.3900 2.4743 1.2811 0.6388
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0703 0.0938 0.1016 0.0898
setup↓ → CK 0.1523 0.2539 0.2500 0.1953
D
hold↑ → CK -0.0547 -0.0664 -0.0742 -0.0625
hold↓ → CK -0.0430 -0.1406 -0.1328 -0.0977
minpwh 0.1189 0.1189 0.1189 0.0946
CK
minpwl 0.2208 0.1965 0.1868 0.1529
setup↑ → CK 0.0742 0.0938 0.1016 0.0938
setup↓ → CK 0.1719 0.2773 0.2695 0.2148
RN
hold↑ → CK -0.0586 -0.0703 -0.0781 -0.0664
hold↓ → CK -0.0508 -0.1562 -0.1445 -0.1094
96
Process Technology:
DLY1

The DLY1 cell provides the logical delay of a single
input (A). The output (Y) is represented by the logic A Y
equation:
Y = A
Cell Size
Functions
A Y DLY1X1 5.04 3.96
0 0
1 1
A Y
97
Process Technology:
DLY1

Pin Pin
X1 X1
A 0.0321 A 0.0020
Intrinsic Delay Kload

Description (ns) (ns/pF)
X1 X1
A → Y↑ 0.1464 4.5369
A → Y↓ 0.1822 2.4673
98
Process Technology:
DLY2

equation:
Y = A
Cell Size
Functions
A Y DLY2X1 5.04 3.96
0 0
1 1
A Y
99
Process Technology:
DLY2

Pin Pin
X1 X1
A 0.0383 A 0.0020

X1 X1
A → Y↑ 0.2847 4.5455
A → Y↓ 0.3242 2.5452
100
Process Technology:
DLY3

equation:
Y = A
Cell Size
Functions
A Y DLY3X1 5.04 4.62
0 0
1 1
A Y
101
Process Technology:
DLY3

Pin Pin
X1 X1
A 0.0453 A 0.0020

X1 X1
A → Y↑ 0.4638 4.5585
A → Y↓ 0.4839 2.6657
102
Process Technology:
DLY4

equation:
Y = A
Cell Size
Functions
A Y DLY4X1 5.04 4.62
0 0
1 1
A Y
103
Process Technology:
DLY4

Pin Pin
X1 X1
A 0.0532 A 0.0020

X1 X1
A → Y↑ 0.6887 4.5815
A → Y↓ 0.6655 2.8129
104
Process Technology:
EDFF

The EDFF cell is a positive-edge triggered, static D-
type flip-flop with synchronous active-high enable
D
(E). Q
E
QN
Functions CK
E D CK Q[n+1] QN[n+1]
0 x x Q[n] QN[n]
Cell Size
1 0 0 1
1 1 1 0 Drive Strength Height (um) Width (um)
1 x Q[n] QN[n]
EDFFXL 5.04 15.18
EDFFX1 5.04 15.18
EDFFX2 5.04 17.82
EDFFX4 5.04 20.46
cn c
c cn
D c cn
E
QN
cn c
Q
cn
CK c
105
Process Technology:
EDFF

Pin Pin
D 0.0374 0.0365 0.0483 0.0737 D 0.0030 0.0020 0.0025 0.0038
CK 0.0660 0.0688 0.0876 0.1288 CK 0.0022 0.0030 0.0041 0.0066
E 0.0542 0.0501 0.0627 0.0908 E 0.0056 0.0047 0.0049 0.0061
Q 0.0417 0.0461 0.0764 0.1307

Description
CK → Q↑ 0.2529 0.2274 0.1974 0.1750 6.4709 5.1316 2.2021 1.1177
CK → Q↓ 0.1965 0.1684 0.1580 0.1455 3.4749 2.7296 1.3231 0.6460
CK → QN↑ 0.2790 0.2342 0.2208 0.2021 6.4861 4.5422 2.2001 1.1167
CK → QN↓ 0.3847 0.3287 0.2899 0.2567 3.5290 2.4951 1.3142 0.6400
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.0938 0.1094 0.1289 0.1172
setup↓ → CK 0.2539 0.4844 0.3984 0.3164
D
hold↑ → CK -0.0742 -0.0859 -0.0938 -0.0898
hold↓ → CK -0.1211 -0.3320 -0.2578 -0.1953
minpwh 0.1335 0.1238 0.1092 0.0946
CK
minpwl 0.2305 0.2014 0.1965 0.1723
setup↑ → CK 0.2930 0.5195 0.4336 0.3594
setup↓ → CK 0.1641 0.3906 0.3086 0.2305
E
hold↑ → CK -0.0898 -0.0977 -0.1133 -0.1016
hold↓ → CK -0.1133 -0.1484 -0.1602 -0.1641
106
Process Technology:
EDFFTR

The EDFFTR cell is a positive-edge triggered, static
D-type flip-flop with synchronous active-high enable
D
(E) and synchronous active-low reset (RN). Q
E
QN
Functions CK
RN E D CK Q[n+1] QN[n+1]
0 x x 0 1 RN
x x x Q[n] QN[n]
1 0 x Q[n] QN[n]
Cell Size
1 1 0 0 1
1 1 1 1 0 Drive Strength Height (um) Width (um)
EDFFTRXL 5.04 16.50
EDFFTRX1 5.04 16.50
EDFFTRX2 5.04 17.82
EDFFTRX4 5.04 21.12
cn c
RN
c cn
c cn
D
QN
E
cn c
Q
cn
CK c
107
Process Technology:
EDFFTR

Pin Pin
D 0.0414 0.0392 0.0520 0.0798 D 0.0031 0.0020 0.0024 0.0039
CK 0.0839 0.0824 0.1022 0.1505 CK 0.0023 0.0032 0.0043 0.0064
E 0.0599 0.0537 0.0677 0.0987 E 0.0062 0.0050 0.0055 0.0068
RN 0.0490 0.0449 0.0575 0.0879 RN 0.0028 0.0020 0.0023 0.0037
Q 0.0433 0.0481 0.0750 0.1278

Description
CK → Q↑ 0.2658 0.2373 0.2093 0.1815 6.4868 4.5427 2.3617 1.1176
CK → Q↓ 0.2101 0.1805 0.1582 0.1444 3.2897 2.5079 1.2959 0.6459
CK → QN↑ 0.3071 0.2559 0.2211 0.2013 6.4926 4.5439 2.3601 1.1166
CK → QN↓ 0.3985 0.3483 0.2965 0.2626 3.5231 2.4998 1.2857 0.6399
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1289 0.1562 0.1680 0.1445
setup↓ → CK 0.2852 0.5312 0.4258 0.3320
D
hold↑ → CK -0.1055 -0.1211 -0.1289 -0.1133
hold↓ → CK -0.1406 -0.3672 -0.2852 -0.2109
minpwh 0.1432 0.1286 0.1092 0.0995
CK
minpwl 0.2887 0.2499 0.2353 0.1917
setup↑ → CK 0.3164 0.5508 0.4531 0.3672
setup↓ → CK 0.2031 0.4492 0.3516 0.2539
E
hold↑ → CK -0.1250 -0.1484 -0.1562 -0.1289
hold↓ → CK -0.1445 -0.1914 -0.2070 -0.2031
setup↑ → CK 0.1445 0.1758 0.1836 0.1602
setup↓ → CK 0.2617 0.4336 0.3672 0.2891
RN
hold↑ → CK -0.1250 -0.1445 -0.1523 -0.1289
hold↓ → CK -0.0820 -0.2656 -0.2188 -0.1523
108
Process Technology:
HOLD

The HOLD cell holds data at a known value. This cell
is often used for holding data on a tri-state bus.
Cell Size

HOLDX1 5.04 2.64
109
Process Technology:
HOLD
Power Capacitance
Pin (µW/MHz) Pin (pF)
X1 X1
Y 0.0252 Y 0.1277
110
Process Technology:
INV

The INV cell provides the logical inversion of a single
input (A). The output (Y) is represented by the logic
A Y
equation:
Y = A
Cell Size
Functions
A Y
INVXL 5.04 1.32
0 1
INVX1 5.04 1.32
1 0
INVX2 5.04 1.98
INVX3 5.04 2.64
INVX4 5.04 2.64
INVX8 5.04 3.96
INVX12 5.04 8.58
INVX16 5.04 11.22
INVX20 5.04 12.54
A Y
111
Process Technology:
INV
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8 X12
A 0.0084 0.0113 0.0219 0.0330 0.0383 0.0783 0.1743
Power (µW/MHz)
Pin
X16 X20
A 0.2257 0.2818
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8 X12
A 0.0026 0.0034 0.0066 0.0099 0.0127 0.0258 0.0066
Capacitance (pF)
Pin
X16 X20
A 0.0085 0.0105

Description
XL X1 X2 X3 X4 X8 X12
A → Y↑ 0.0244 0.0232 0.0214 0.0222 0.0190 0.0186 0.1220
A → Y↓ 0.0165 0.0162 0.0153 0.0161 0.0140 0.0141 0.1170

Description
X16 X20
A → Y↑ 0.1199 0.1189
A → Y↓ 0.1153 0.1127
112
Process Technology:
INV
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8 X12
A → Y↑ 6.4613 4.5318 2.2655 1.4771 1.1299 0.5464 0.3634
A → Y↓ 3.2848 2.4285 1.2619 0.8330 0.6311 0.3152 0.2122
Kload (ns/pF)
Description
X16 X20
A → Y↑ 0.2734 0.2188
A → Y↓ 0.1593 0.1273
113
Process Technology:
JKFF

The JKFF cell is a positive-edge triggered JK-type
flip-flop.
J
Q
K
Functions
QN
CK
J K CK Q[n+1] QN[n+1]
x x Q[n] QN[n]
0 0 Q[n] QN[n] Cell Size
0 1 0 1
1 1 QN[n] Q[n] JKFFXL 5.04 13.86
JKFFX1 5.04 13.86
JKFFX2 5.04 16.50
JKFFX4 5.04 19.80
cn c
c cn
K c cn
J cn c
QN
cn
CK c
114
Process Technology:
JKFF

Pin Pin
J 0.0302 0.0291 0.0397 0.0643 J 0.0022 0.0019 0.0020 0.0023
K 0.0270 0.0265 0.0373 0.0550 K 0.0026 0.0017 0.0021 0.0031
CK 0.0623 0.0624 0.0831 0.1189 CK 0.0020 0.0029 0.0037 0.0066
Q 0.0516 0.0537 0.0897 0.1453

Description
CK → Q↑ 0.2822 0.2304 0.2298 0.1931 6.4958 4.5443 2.1809 1.0899
CK → Q↓ 0.3931 0.3322 0.3050 0.2525 3.5741 2.5046 1.2839 0.6389
CK → QN↑ 0.2449 0.2201 0.2173 0.1737 6.4768 5.0018 2.1829 1.0911
CK → QN↓ 0.1847 0.1591 0.1672 0.1385 3.4703 2.9065 1.2977 0.6448
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1680 0.2695 0.2461 0.2305
setup↓ → CK 0.1289 0.1523 0.1641 0.1836
J
hold↑ → CK -0.0938 -0.2109 -0.1758 -0.1562
hold↓ → CK -0.1211 -0.1406 -0.1523 -0.1758
setup↑ → CK 0.0859 0.1016 0.1133 0.1094
setup↓ → CK 0.1445 0.3867 0.2852 0.2109
K
hold↑ → CK -0.0781 -0.0898 -0.1016 -0.0938
hold↓ → CK -0.1250 -0.3477 -0.2461 -0.1836
minpwh 0.0316 0.0316 0.0316 0.0316
CK
minpwl 0.2208 0.2693 0.2402 0.1868
115
Process Technology:
JKFFR

The JKFFR cell is a positive-edge triggered JK-type
flip-flop with asynchronous active-low reset (RN).
J
Q
K
Functions
QN
CK
RN J K CK Q[n+1] QN[n+1]
1 x x Q[n] QN[n]
0 x x x 0 1 RN
1 0 0 Q[n] QN[n]
1 0 1 0 1
Cell Size
1 1 0 1 0
1 1 1 QN[n] Q[n] Drive Strength Height (um) Width (um)
JKFFRXL 5.04 17.16
JKFFRX1 5.04 18.48
JKFFRX2 5.04 18.48
JKFFRX4 5.04 23.10
cn c
c cn
J c cn
K cn c
QN
RN
cn
CK c
116
Process Technology:
JKFFR

Pin Pin
J 0.0282 0.0255 0.0273 0.0398 J 0.0029 0.0020 0.0020 0.0024
K 0.0361 0.0322 0.0349 0.0468 K 0.0026 0.0024 0.0024 0.0025
CK 0.0666 0.0651 0.0702 0.0897 CK 0.0021 0.0026 0.0029 0.0040
RN 0.0185 0.0210 0.0248 0.0396 RN 0.0023 0.0028 0.0035 0.0058
Q 0.0735 0.0784 0.1129 0.1721

Description
CK → Q↑ 0.5230 0.4666 0.4344 0.3741 6.4903 4.5467 2.1824 1.0910
CK → Q↓ 0.4040 0.4045 0.3487 0.2996 3.5818 2.5382 1.2947 0.6308
RN → Q↓ 0.3718 0.3401 0.2845 0.2498 3.5695 2.5337 1.2931 0.6299
CK → QN↑ 0.2424 0.2540 0.2373 0.2110 6.4660 4.5364 2.1815 1.0911
CK → QN↓ 0.4081 0.3670 0.3557 0.3068 3.6125 2.6308 1.3082 0.6388
RN → QN↑ 0.2064 0.1869 0.1717 0.1602 6.4700 4.5379 2.1834 1.0918
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1172 0.1250 0.1406 0.1445
setup↓ → CK 0.1211 0.3203 0.3320 0.2383
J
hold↑ → CK -0.1055 -0.1133 -0.1250 -0.1250
hold↓ → CK -0.0820 -0.2695 -0.2695 -0.1797
setup↑ → CK 0.1719 0.2969 0.3164 0.2656
setup↓ → CK 0.1758 0.1641 0.1758 0.1875
K
hold↑ → CK -0.0898 -0.2383 -0.2461 -0.1836
hold↓ → CK -0.1680 -0.1523 -0.1641 -0.1758
minpwh 0.1286 0.1383 0.1335 0.1140
CK
minpwl 0.2596 0.2305 0.2353 0.2111
minpwl 0.2062 0.2014 0.2499 0.3518
RN
recovery 0.0508 0.0625 0.0820 0.0703
117
Process Technology:
JKFFS

The JKFFS cell is a positive-edge triggered JK-type
SN
flip-flop with asynchronous active-low set (SN).
Functions J
Q
SN J K CK Q[n+1] QN[n+1] K
QN
1 x x Q[n] QN[n] CK
0 x x x 1 0
1 0 0 Q[n] QN[n]
1 0 1 0 1 Cell Size
1 1 0 1 0
1 1 1 QN[n] Q[n] Drive Strength Height (um) Width (um)
JKFFSXL 5.04 16.50
JKFFSX1 5.04 17.16
JKFFSX2 5.04 17.82
JKFFSX4 5.04 20.46
cn c
c cn
J c cn
K cn c
QN
SN
cn
CK c
118
Process Technology:
JKFFS

Pin Pin
J 0.0266 0.0231 0.0256 0.0294 J 0.0028 0.0018 0.0018 0.0021
K 0.0413 0.0348 0.0385 0.0445 K 0.0024 0.0024 0.0025 0.0024
CK 0.0715 0.0672 0.0725 0.0831 CK 0.0022 0.0026 0.0029 0.0036
SN 0.0051 0.0064 0.0092 0.0161 SN 0.0056 0.0065 0.0085 0.0129
Q 0.0685 0.0780 0.1033 0.1593

Description
CK → Q↑ 0.4660 0.4098 0.3889 0.3545 6.4920 4.5430 2.2755 1.0900
CK → Q↓ 0.4274 0.3804 0.3423 0.2977 3.5876 2.5016 1.2959 0.6394
SN → Q↑ 0.2545 0.1998 0.1872 0.1613 6.4879 4.5420 2.2751 1.0898
CK → QN↑ 0.2575 0.2612 0.2285 0.2136 6.4996 4.7687 2.2772 1.0917
CK → QN↓ 0.3587 0.3294 0.3098 0.2947 3.4687 2.5571 1.2860 0.6396
SN → QN↓ 0.1501 0.1203 0.1090 0.1024 3.4371 2.5547 1.2879 0.6419
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1094 0.1289 0.1289 0.1328
setup↓ → CK 0.1562 0.3945 0.4141 0.2852
J
hold↑ → CK -0.1016 -0.1172 -0.1172 -0.1250
hold↓ → CK -0.1328 -0.3594 -0.3750 -0.2500
setup↑ → CK 0.2070 0.3711 0.3945 0.3008
setup↓ → CK 0.1680 0.1641 0.1641 0.1719
K
hold↑ → CK -0.1172 -0.3008 -0.3164 -0.2188
hold↓ → CK -0.1641 -0.1523 -0.1562 -0.1641
minpwh 0.1286 0.1383 0.1286 0.1238
CK
minpwl 0.2353 0.2208 0.2111 0.2014
minpwl 0.1626 0.1335 0.1335 0.1480
SN
recovery -0.0312 -0.0156 -0.0039 -0.0039
119
Process Technology:
JKFFSR

The JKFFSR cell is a positive-edge triggered
SN
JK-type flip-flop with asynchronous active-low reset
J
Functions Q
K
RN SN J K CK Q[n+1] QN[n+1] QN
CK
1 1 x x Q[n] QN[n]
1 0 x x x 1 0
0 1 x x x 0 1 RN
0 0 x x x 1 0
Cell Size
1 1 0 0 Q[n] QN[n]
1 1 0 1 0 1 Drive Strength Height (um) Width (um)
1 1 1 0 1 0
JKFFSRXL 5.04 19.80
1 1 1 1 QN[n] Q[n]
JKFFSRX1 5.04 19.80
JKFFSRX2 5.04 20.46
JKFFSRX4 5.04 21.78
cn c
c cn
J c cn
K cn c
QN
RN
SN
cn
CK c
120
Process Technology:
JKFFSR

Pin Pin
J 0.0321 0.0286 0.0317 0.0316 J 0.0028 0.0018 0.0020 0.0020
K 0.0392 0.0332 0.0386 0.0384 K 0.0027 0.0027 0.0027 0.0027
CK 0.0732 0.0695 0.0764 0.0765 CK 0.0020 0.0024 0.0029 0.0029
SN 0.0047 0.0055 0.0092 0.0092 SN 0.0047 0.0052 0.0072 0.0072
RN 0.0162 0.0182 0.0242 0.0241 RN 0.0025 0.0029 0.0040 0.0041
Q 0.0769 0.0823 0.1164 0.1689

Description
CK → Q↑ 0.5828 0.4860 0.4624 0.5085 6.4981 4.5447 2.2376 1.1008
CK → Q↓ 0.4655 0.3983 0.3693 0.4022 3.6120 2.5024 1.2879 0.6245
SN → Q↑ 0.2699 0.2206 0.1910 0.2219 6.4946 4.5432 2.2369 1.1005
SN → Q↓ 0.3091 0.2319 0.2190 0.2501 3.5877 2.4937 1.2849 0.6236
RN → Q↓ 0.3970 0.3110 0.2874 0.3188 3.5879 2.4939 1.2850 0.6236
CK → QN↑ 0.2994 0.2869 0.2699 0.2940 6.4981 5.1377 2.2426 1.1063
CK → QN↓ 0.4694 0.4104 0.3913 0.4318 3.6904 2.8079 1.3098 0.6470
SN → QN↑ 0.1419 0.1197 0.1190 0.1418 6.5207 5.1469 2.2475 1.1085
SN → QN↓ 0.1724 0.1485 0.1234 0.1499 3.4570 2.7659 1.2900 0.6298
RN → QN↑ 0.2297 0.1986 0.1873 0.2104 6.5192 5.1465 2.2472 1.1084
121
Process Technology:
JKFFSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1328 0.1875 0.1562 0.1562
setup↓ → CK 0.1172 0.3320 0.2695 0.2656
J
hold↑ → CK -0.1211 -0.1641 -0.1406 -0.1406
hold↓ → CK -0.0625 -0.2539 -0.2109 -0.2070
setup↑ → CK 0.1914 0.3398 0.2969 0.2930
setup↓ → CK 0.1914 0.2188 0.1914 0.1914
K
hold↑ → CK -0.0859 -0.2461 -0.2031 -0.1992
hold↓ → CK -0.1836 -0.1953 -0.1758 -0.1797
minpwh 0.1529 0.1529 0.1529 0.1577
CK
minpwl 0.2839 0.2887 0.2450 0.2450
minpwl 0.1820 0.1529 0.1383 0.1674
SN recovery -0.0195 0.0039 0.0039 0.0000
removal 0.1602 0.1211 0.1211 0.1250
RN minpwl 0.2256 0.2062 0.2353 0.2499
122
Process Technology:
MX2

The MX2 cell is a 2-to-1 multiplexer. The state of the
select input (S0) determines which data input (A, B) A
is presented to the output (Y).The output (Y) is Y
represented by the logic equation: B
Y = ( S0 • A ) + ( S0 • B )
S0
Functions
S0 A B Y Cell Size
0 0 x 0
0 1 x 1
1 x 0 0 MX2XL 5.04 5.28
1 x 1 1 MX2X1 5.04 5.28
MX2X2 5.04 5.94
MX2X4 5.04 6.60
A
s0n
B
s0
s0n
S0 s0
123
Process Technology:
MX2

Pin Pin
S0 0.0349 0.0360 0.0615 0.0886 S0 0.0063 0.0059 0.0088 0.0102
A 0.0269 0.0306 0.0539 0.0835 A 0.0023 0.0033 0.0056 0.0070
B 0.0309 0.0342 0.0601 0.0914 B 0.0023 0.0033 0.0052 0.0059
Delay Tables at 25 oC, 1.8V, Typical Process

Description
XL X1 X2 X4
S0 → Y↑ 0.1350 0.1296 0.1310 0.1371
S0 → Y↓ 0.1422 0.1247 0.1151 0.1353
A → Y↑ 0.0998 0.0888 0.0828 0.0935
A → Y↓ 0.1655 0.1265 0.1155 0.1283
B → Y↑ 0.0996 0.0868 0.0838 0.0922
B → Y↓ 0.1706 0.1310 0.1203 0.1425
Kload (ns/pF)
Description
XL X1 X2 X4
S0 → Y↑ 6.4797 4.5399 2.2237 1.1198
S0 → Y↓ 3.5858 2.5026 1.2964 0.6562
A → Y↑ 6.4828 4.5402 2.2239 1.1203
A → Y↓ 3.5780 2.5092 1.2961 0.6524
B → Y↑ 6.4835 4.5411 2.2248 1.1204
B → Y↓ 3.5903 2.5115 1.2964 0.6563
124
Process Technology:
MX4

The MX4 cell is a 4-to-1 multiplexer. The state of the
select inputs (S1, S0) determines which data input A
(A, B, C, D) is presented to the output (Y). The output B
Y
C
(Y) is represented by the logic equation: D
Y = ( S0 • S1 • A )+( S0 • S1 • B )+( S0 • S1 • C )+( S0 • S1 • D )
S1 S0
Functions
S1 S0 A B C D Y Cell Size
0 0 0 x x x 0
0 0 1 x x x 1
0 1 x 0 x x 0 MX4XL 5.04 13.20
0 1 x 1 x x 1 MX4X1 5.04 13.20
1 0 x x 0 x 0 MX4X2 5.04 15.18
1 0 x x 1 x 1 MX4X4 5.04 15.84
1 1 x x x 0 0
1 1 x x x 1 1
A
s0n
s1n
s0n
B
S0 s0 s0
s1n
Y
C
s1n s0n
s1
S1 s1
D
s0
s1
125
Process Technology:
MX4

Pin Pin
S0 0.0671 0.0808 0.1297 0.1615 S0 0.0109 0.0140 0.0227 0.0227
S1 0.0348 0.0430 0.0660 0.0858 S1 0.0063 0.0071 0.0108 0.0108
A 0.0425 0.0542 0.0878 0.1181 A 0.0021 0.0043 0.0067 0.0067
B 0.0466 0.0591 0.0982 0.1287 B 0.0021 0.0042 0.0065 0.0065
C 0.0488 0.0612 0.1018 0.1335 C 0.0020 0.0041 0.0066 0.0066
D 0.0541 0.0675 0.1123 0.1442 D 0.0022 0.0044 0.0066 0.0066

Description
S0 → Y↑ 0.2488 0.1817 0.1660 0.1805 6.5339 4.5540 2.2304 1.0972
S0 → Y↓ 0.2841 0.2012 0.1945 0.2213 4.0885 2.6157 1.3461 0.6866
S1 → Y↑ 0.1476 0.1454 0.1284 0.1423 6.5241 4.5492 2.2284 1.0964
S1 → Y↓ 0.1352 0.1292 0.1242 0.1529 3.9832 2.6010 1.3393 0.6806
A → Y↑ 0.1681 0.1326 0.1257 0.1419 6.5283 4.5516 2.2290 1.0967
A → Y↓ 0.2694 0.1800 0.1709 0.1971 4.0357 2.6044 1.3390 0.6829
B → Y↑ 0.1674 0.1314 0.1257 0.1418 6.5285 4.5515 2.2291 1.0967
B → Y↓ 0.2743 0.1840 0.1760 0.2023 4.0453 2.6063 1.3392 0.6829
C → Y↑ 0.1775 0.1368 0.1311 0.1462 6.5397 4.5541 2.2307 1.0974
C → Y↓ 0.2871 0.1915 0.1843 0.2104 4.1063 2.6182 1.3470 0.6868
D → Y↑ 0.1765 0.1350 0.1311 0.1463 6.5387 4.5536 2.2309 1.0975
D → Y↓ 0.2931 0.1957 0.1893 0.2153 4.1142 2.6194 1.3470 0.6867
126
Process Technology:
MXI2

The MXI2 cell is a 2-to-1 multiplexer with inverted
output. The state of the select input (S0) determines A
which data input (A, B) is presented to the output (Y). Y
The output (Y) is represented by the logic equation: B
Y = ( S0 • A ) + ( S0 • B )
S0
Functions
S0 A B Y Cell Size
0 0 x 1
0 1 x 0
1 x 0 1 MXI2XL 5.04 4.62
1 x 1 0 MXI2X1 5.04 4.62
MXI2X2 5.04 5.28
MXI2X4 5.04 9.24
A
s0n
B
s0
s0n
S0 s0
127
Process Technology:
MXI2

Pin Pin
S0 0.0262 0.0309 0.0521 0.0935 S0 0.0064 0.0070 0.0098 0.0204
A 0.0171 0.0222 0.0372 0.0812 A 0.0027 0.0038 0.0066 0.0130
B 0.0187 0.0263 0.0445 0.0965 B 0.0020 0.0039 0.0060 0.0131
Delay Tables at 25 oC, 1.8V, Typical Process

Description
XL X1 X2 X4
S0 → Y↑ 0.0556 0.0571 0.0569 0.0509
S0 → Y↓ 0.0660 0.0769 0.0649 0.0655
A → Y↑ 0.0607 0.0489 0.0474 0.0471
A → Y↓ 0.0421 0.0384 0.0398 0.0391
B → Y↑ 0.0852 0.0523 0.0503 0.0516
B → Y↓ 0.0451 0.0352 0.0391 0.0354
Kload (ns/pF)
Description
XL X1 X2 X4
S0 → Y↑ 10.3129 4.8605 2.7530 1.3241
S0 → Y↓ 4.3887 2.8766 1.8548 0.8145
A → Y↑ 7.2524 4.8828 2.7598 1.3288
A → Y↓ 3.9762 2.9476 1.7178 0.8299
B → Y↑ 10.4863 4.8834 2.8055 1.3267
B → Y↓ 4.7460 2.9447 1.9365 0.8272
128
Process Technology:
MXI4

The MXI4 cell is a 4-to-1 multiplexer with inverted
output. The state of the select inputs (S1, S0) A
determines which data input (A, B, C, D) is presented B
Y
C
to the output (Y). The output (Y) is represented by D
the logic equation:
Y = ( S0 • S1 • A )+( S0 • S1 • B )+( S0 • S1 • C )+( S0 • S1 • D ) S1 S0
Functions
Cell Size
S1 S0 A B C D Y
0 0 0 x x x 1
0 0 1 x x x 0 MXI4XL 5.04 15.18
0 1 x 0 x x 1 MXI4X1 5.04 15.18
0 1 x 1 x x 0 MXI4X2 5.04 15.84
1 0 x x 0 x 1 MXI4X4 5.04 16.50
1 0 x x 1 x 0
1 1 x x x 0 1
1 1 x x x 1 0
A
s0n
s1n
s0n
B
S0 s0 s0
s1n
Y
C
s1n s0n
s1
S1 s1
D
s0
s1
129
Process Technology:
MXI4

Pin Pin
S0 0.0730 0.0688 0.1179 0.1554 S0 0.0108 0.0091 0.0144 0.0170
S1 0.0376 0.0388 0.0612 0.0846 S1 0.0047 0.0046 0.0054 0.0064
A 0.0450 0.0481 0.0843 0.1159 A 0.0022 0.0026 0.0044 0.0054
B 0.0490 0.0509 0.0910 0.1212 B 0.0022 0.0026 0.0046 0.0056
C 0.0431 0.0439 0.0729 0.1022 C 0.0024 0.0028 0.0048 0.0057
D 0.0409 0.0433 0.0746 0.1034 D 0.0021 0.0025 0.0045 0.0053

Description
S0 → Y↑ 0.2830 0.2472 0.2117 0.2117 6.4911 4.5441 2.2928 1.1139
S0 → Y↓ 0.3435 0.2860 0.2454 0.2471 3.6296 2.5241 1.2988 0.6545
S1 → Y↑ 0.1510 0.1444 0.1331 0.1339 6.4855 4.5415 2.2921 1.1133
S1 → Y↓ 0.1595 0.1292 0.1137 0.1270 3.6179 2.5188 1.2944 0.6524
A → Y↑ 0.2920 0.2407 0.2104 0.2119 6.4903 4.5438 2.2928 1.1137
A → Y↓ 0.2708 0.2213 0.1989 0.2073 3.6292 2.5238 1.2988 0.6544
B → Y↑ 0.2938 0.2428 0.2160 0.2161 6.4909 4.5439 2.2930 1.1138
B → Y↓ 0.2688 0.2184 0.1984 0.2045 3.6288 2.5237 1.2987 0.6544
C → Y↑ 0.2630 0.2173 0.1847 0.1826 6.4874 4.5437 2.2925 1.1133
C → Y↓ 0.2540 0.2080 0.1813 0.1918 3.6194 2.5222 1.2948 0.6539
D → Y↑ 0.2652 0.2195 0.1864 0.1876 6.4876 4.5433 2.2923 1.1133
D → Y↓ 0.2524 0.2059 0.1823 0.1900 3.6192 2.5222 1.2948 0.6539
130
Process Technology:
NAND2

The NAND2 cell provides the logical NAND of two
inputs (A, B). The output (Y) is represented by the A
Y
logic equation: B
Y = ( A • B)
Functions Cell Size
0 x 1 NAND2XL 5.04 1.98

x 0 1 NAND2X1 5.04 1.98
1 1 0 NAND2X2 5.04 3.30
NAND2X4 5.04 4.62
A
Y
B
131
Process Technology:
NAND2

Pin Pin
A 0.0101 0.0137 0.0258 0.0515 A 0.0031 0.0041 0.0079 0.0157
B 0.0139 0.0188 0.0369 0.0726 B 0.0029 0.0038 0.0084 0.0154
Delay at 25 oC, 1.8V, Typical Process

Description
XL X1 X2 X4
A → Y↑ 0.0303 0.0288 0.0263 0.0270
A → Y↓ 0.0209 0.0206 0.0193 0.0194
B → Y↑ 0.0390 0.0372 0.0359 0.0360
B → Y↓ 0.0239 0.0238 0.0235 0.0230
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4684 4.5344 2.1921 1.1332
A → Y↓ 4.0195 2.9627 1.4461 0.7349
B → Y↑ 6.4594 4.5312 2.1908 1.1325
B → Y↓ 4.0208 2.9639 1.4471 0.7352
132
Process Technology:
NAND2B

The NAND2B cell provides the logical NAND of one
inverted input (AN) and one non-inverted input (B). AN
Y
The output (Y) is represented by the logic equation: B
Y = ( AN • B )
Functions Cell Size
AN B Y Drive Strength Height (um) Width (um)
1 x 1 NAND2BXL 5.04 2.64

x 0 1 NAND2BX1 5.04 2.64
0 1 0 NAND2BX2 5.04 3.96
NAND2BX4 5.04 5.28
AN
Y
B
133
Process Technology:
NAND2B
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X4
AN 0.0171 0.0201 0.0360 0.0683
B 0.0118 0.0155 0.0293 0.0577
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X4
AN 0.0022 0.0022 0.0035 0.0062
B 0.0031 0.0041 0.0085 0.0156

Description
XL X1 X2 X4
AN → Y↑ 0.0629 0.0651 0.0673 0.0677
AN → Y↓ 0.0915 0.1014 0.0947 0.0874
B → Y↑ 0.0396 0.0371 0.0355 0.0352
B → Y↓ 0.0269 0.0268 0.0265 0.0264
Kload (ns/pF)
Description
XL X1 X2 X4
AN → Y↑ 6.4721 4.5375 2.2214 1.1341
AN → Y↓ 4.0632 2.9182 1.4581 0.7401
B → Y↑ 6.4648 4.5343 2.2512 1.1333
B → Y↓ 4.0336 2.9022 1.4506 0.7373
134
Process Technology:
NAND3

The NAND3 cell provides the logical NAND of three
A
inputs (A, B, C). The output (Y) is represented by the
B Y
logic equation:
C
Y = ( A • B • C)
Functions Cell Size
0 x x 1 NAND3XL 5.04 2.64

x 0 x 1 NAND3X1 5.04 2.64
x x 0 1 NAND3X2 5.04 4.62
1 1 1 0 NAND3X4 5.04 6.60
A
B Y
C
135
Process Technology:
NAND3

Pin Pin
A 0.0118 0.0172 0.0301 0.0520 A 0.0034 0.0048 0.0084 0.0147
B 0.0163 0.0236 0.0433 0.0716 B 0.0032 0.0047 0.0090 0.0142
C 0.0207 0.0298 0.0570 0.0925 C 0.0032 0.0044 0.0098 0.0146

Description
XL X1 X2 X4
A → Y↑ 0.0411 0.0338 0.0316 0.0342
A → Y↓ 0.0293 0.0261 0.0229 0.0246
B → Y↑ 0.0523 0.0441 0.0435 0.0449
B → Y↓ 0.0361 0.0334 0.0308 0.0314
C → Y↑ 0.0624 0.0527 0.0542 0.0556
C → Y↓ 0.0400 0.0370 0.0355 0.0360
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4693 4.0140 2.1622 1.3948
A → Y↓ 4.6863 3.2866 1.6431 1.0529
B → Y↑ 6.4618 4.0115 2.1612 1.3940
B → Y↓ 4.6860 3.2865 1.6432 1.0529
C → Y↑ 6.4689 4.0155 2.1634 1.3951
C → Y↓ 4.6874 3.2887 1.6441 1.0534
136
Process Technology:
NAND3B

The NAND3B cell provides the logical NAND of one
AN
inverted input (AN) and two non-inverted inputs (B,
B Y
C). The output (Y) is represented by the logic
C
equation:
Y = ( AN • B • C )
Cell Size
Functions
AN B C Y NAND3BXL 5.04 3.30
1 x x 1 NAND3BX1 5.04 3.30
x 0 x 1 NAND3BX2 5.04 5.28
x x 0 1 NAND3BX4 5.04 7.26
0 1 1 0
AN
B Y
C
137
Process Technology:
NAND3B

Pin Pin
AN 0.0225 0.0267 0.0411 0.0682 AN 0.0023 0.0024 0.0038 0.0064
B 0.0141 0.0192 0.0349 0.0559 B 0.0034 0.0046 0.0091 0.0141
C 0.0179 0.0253 0.0481 0.0763 C 0.0033 0.0046 0.0099 0.0148

Description
AN → Y↑ 0.0792 0.0799 0.0725 0.0708 6.4737 4.0636 2.1636 1.3577
AN → Y↓ 0.1113 0.1196 0.0943 0.0866 4.7210 3.3061 1.6504 1.0625
B → Y↑ 0.0519 0.0454 0.0427 0.0429 6.4681 4.0610 2.1629 1.3570
B → Y↓ 0.0379 0.0382 0.0340 0.0344 4.6963 3.2934 1.6460 1.0610
C → Y↑ 0.0628 0.0554 0.0538 0.0534 6.4720 4.0637 2.1641 1.3602
C → Y↓ 0.0432 0.0434 0.0392 0.0391 4.6994 3.2960 1.6479 1.0614
138
Process Technology:
NAND4

The NAND4 cell provides a logical NAND of four
A
inputs (A, B, C, D). The output (Y) is represented by B
C Y
the logic equation:
D
Y = ( A • B • C • D)
Functions Cell Size

0 x x x 1 NAND4XL 5.04 3.30
x 0 x x 1 NAND4X1 5.04 3.30
x x 0 x 1 NAND4X2 5.04 5.94
x x x 0 1 NAND4X4 5.04 11.22
1 1 1 1 0
A
B
Y
C
D
139
Process Technology:
NAND4

Pin Pin
A 0.0135 0.0187 0.0352 0.0719 A 0.0033 0.0048 0.0089 0.0189
B 0.0189 0.0257 0.0493 0.0998 B 0.0036 0.0048 0.0093 0.0194
C 0.0236 0.0326 0.0631 0.1273 C 0.0035 0.0048 0.0098 0.0199
D 0.0281 0.0391 0.0771 0.1563 D 0.0032 0.0045 0.0103 0.0212

Description
XL X1 X2 X4
A → Y↑ 0.0416 0.0378 0.0370 0.0377
A → Y↓ 0.0293 0.0280 0.0272 0.0279
B → Y↑ 0.0570 0.0506 0.0499 0.0502
B → Y↓ 0.0422 0.0393 0.0384 0.0387
C → Y↑ 0.0685 0.0616 0.0614 0.0617
C → Y↓ 0.0494 0.0468 0.0462 0.0465
D → Y↑ 0.0774 0.0708 0.0725 0.0737
D → Y↓ 0.0523 0.0505 0.0514 0.0525
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4673 4.2524 2.1622 1.0812
A → Y↓ 5.4481 3.8335 1.9166 0.9583
B → Y↑ 6.4650 4.2499 2.1609 1.0804
B → Y↓ 5.4504 3.8334 1.9167 0.9583
C → Y↑ 6.4717 4.2542 2.1631 1.0815
C → Y↓ 5.4501 3.8341 1.9174 0.9585
D → Y↑ 6.4904 4.2633 2.1680 1.0841
D → Y↓ 5.4530 3.8362 1.9176 0.9588
140
Process Technology:
NAND4B

The NAND4B cell provides a logical NAND of one
AN
inverted input (AN) and three non-inverted inputs (B, B
C Y
C, D). The output (Y) is represented by the logic
D
equation:
Y = ( AN • B • C • D )
Cell Size
Functions
AN B C D Y
NAND4BXL 5.04 3.96
1 x x x 1 NAND4BX1 5.04 4.62
x 0 x x 1 NAND4BX2 5.04 6.60
x x 0 x 1 NAND4BX4 5.04 11.88
x x x 0 1
0 1 1 1 0
AN
B
Y
C
D
141
Process Technology:
NAND4B

Pin Pin
AN 0.0213 0.0252 0.0446 0.0890 AN 0.0025 0.0022 0.0038 0.0068
B 0.0148 0.0222 0.0401 0.0813 B 0.0034 0.0048 0.0093 0.0194
C 0.0192 0.0285 0.0530 0.1058 C 0.0034 0.0047 0.0098 0.0199
D 0.0239 0.0351 0.0674 0.1350 D 0.0032 0.0045 0.0105 0.0214

Description
AN → Y↑ 0.0807 0.0835 0.0781 0.0800 6.4769 4.2553 2.1635 1.0820
AN → Y↓ 0.1102 0.1184 0.0987 0.0964 5.4730 3.8451 1.9212 0.9604
B → Y↑ 0.0554 0.0522 0.0488 0.0489 6.4725 4.2543 2.1629 1.0815
B → Y↓ 0.0446 0.0455 0.0412 0.0411 5.4599 3.8396 1.9191 0.9595
C → Y↑ 0.0682 0.0639 0.0609 0.0610 6.4760 4.2565 2.1639 1.0821
C → Y↓ 0.0531 0.0540 0.0498 0.0500 5.4599 3.8404 1.9190 0.9595
D → Y↑ 0.0781 0.0736 0.0723 0.0732 6.4915 4.2643 2.1684 1.0842
D → Y↓ 0.0567 0.0579 0.0550 0.0560 5.4592 3.8402 1.9194 0.9602
142
Process Technology:
NAND4BB

The NAND4BB cell provides a logical NAND of two
AN
inverted inputs (AN, BN) and two non-inverted inputs BN
C Y
(C, D). The output (Y) is represented by the logic
D
equation:
Y = ( AN • BN • C • D )
Cell Size
Functions
AN BN C D Y
NAND4BBXL 5.04 5.28
1 x x x 1 NAND4BBX1 5.04 5.28
x 1 x x 1 NAND4BBX2 5.04 7.26
x x 0 x 1 NAND4BBX4 5.04 12.54
x x x 0 1
0 0 1 1 0
AN
BN
Y
C
D
143
Process Technology:
NAND4BB

Pin Pin
AN 0.0213 0.0256 0.0466 0.0907 AN 0.0022 0.0022 0.0039 0.0068
BN 0.0252 0.0308 0.0561 0.1091 BN 0.0023 0.0023 0.0037 0.0071
C 0.0182 0.0244 0.0458 0.0920 C 0.0035 0.0048 0.0098 0.0199
D 0.0226 0.0306 0.0587 0.1176 D 0.0034 0.0046 0.0106 0.0212

Description
AN → Y↑ 0.0829 0.0837 0.0795 0.0809 6.4721 4.2551 2.1636 1.0819
AN → Y↓ 0.1104 0.1182 0.0995 0.0967 5.4654 3.8445 1.9209 0.9603
BN → Y↑ 0.0960 0.0969 0.0945 0.0934 6.4727 4.2558 2.1638 1.0818
BN → Y↓ 0.1226 0.1318 0.1139 0.1087 5.4796 3.8531 1.9241 0.9618
C → Y↑ 0.0707 0.0630 0.0608 0.0607 6.4797 4.2594 2.1657 1.0829
C → Y↓ 0.0569 0.0556 0.0521 0.0519 5.4636 3.8432 1.9206 0.9604
D → Y↑ 0.0814 0.0730 0.0727 0.0731 6.4936 4.2664 2.1696 1.0848
D → Y↓ 0.0611 0.0599 0.0582 0.0584 5.4624 3.8434 1.9209 0.9611
144
Process Technology:
NOR2

The NOR2 cell provides a logical NOR of two inputs
Y
equation: B
Y = ( A + B)
Functions Cell Size
0 0 1 NOR2XL 5.04 1.98

x 1 0 NOR2X1 5.04 1.98
1 x 0 NOR2X2 5.04 3.30
NOR2X4 5.04 4.62
A
Y
B
145
Process Technology:
NOR2

Pin Pin
A 0.0109 0.0146 0.0277 0.0559 A 0.0032 0.0043 0.0080 0.0164
B 0.0136 0.0187 0.0363 0.0726 B 0.0029 0.0040 0.0084 0.0156

Description
XL X1 X2 X4
A → Y↑ 0.0400 0.0369 0.0324 0.0333
A → Y↓ 0.0211 0.0203 0.0189 0.0195
B → Y↑ 0.0475 0.0446 0.0419 0.0416
B → Y↓ 0.0252 0.0249 0.0246 0.0246
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 9.5851 6.5738 3.2863 1.6312
A → Y↓ 3.4151 2.4306 1.2626 0.6313
B → Y↑ 9.5753 6.5703 3.2859 1.6305
B → Y↓ 3.4225 2.4337 1.2645 0.6322
146
Process Technology:
NOR2B

The NOR2B cell provides a logical NOR of
one inverted input (AN) and one non-inverted input AN
Y
(B). The output (Y) is represented by the logic B
equation:
Y = ( AN + B )
Cell Size
Functions
AN B Y NOR2BXL 5.04 2.64
1 0 1 NOR2BX1 5.04 2.64
x 1 0 NOR2BX2 5.04 3.96
0 x 0 NOR2BX4 5.04 5.28
AN
Y
B
147
Process Technology:
NOR2B
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X4
AN 0.0178 0.0211 0.0343 0.0683
B 0.0136 0.0188 0.0361 0.0731
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X4
AN 0.0022 0.0022 0.0037 0.0064
B 0.0032 0.0043 0.0085 0.0159

Description
XL X1 X2 X4
AN → Y↑ 0.0715 0.0731 0.0686 0.0702
AN → Y↓ 0.0988 0.1124 0.0935 0.0928
B → Y↑ 0.0487 0.0467 0.0437 0.0439
B → Y↓ 0.0244 0.0247 0.0241 0.0242
Kload (ns/pF)
Description
XL X1 X2 X4
AN → Y↑ 9.5892 6.5760 3.2872 1.6228
AN → Y↓ 3.3534 2.4673 1.2763 0.6379
B → Y↑ 9.5797 6.5712 3.2861 1.6217
B → Y↓ 3.2982 2.4359 1.2653 0.6328
148
Process Technology:
NOR3

The NOR3 cell provides a logical NOR of three inputs
(A, B, C). The output (Y) is represented by the logic A
B Y
equation:
C
Y = ( A + B + C)
Functions Cell Size
0 0 0 1 NOR3XL 5.04 2.64

x x 1 0 NOR3X1 5.04 2.64
x 1 x 0 NOR3X2 5.04 4.62
1 x x 0 NOR3X4 5.04 6.60
A
B Y
C
149
Process Technology:
NOR3

Pin Pin
A 0.0146 0.0194 0.0378 0.0601 A 0.0036 0.0047 0.0090 0.0160
B 0.0180 0.0245 0.0482 0.0763 B 0.0034 0.0046 0.0096 0.0153
C 0.0217 0.0299 0.0596 0.0947 C 0.0032 0.0043 0.0096 0.0150

Description
XL X1 X2 X4
A → Y↑ 0.0583 0.0530 0.0483 0.0485
A → Y↓ 0.0248 0.0245 0.0237 0.0232
B → Y↑ 0.0808 0.0751 0.0711 0.0697
B → Y↓ 0.0309 0.0312 0.0310 0.0297
C → Y↑ 0.0879 0.0823 0.0802 0.0785
C → Y↓ 0.0332 0.0344 0.0350 0.0334
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 12.2390 8.3835 4.1905 2.5613
A → Y↓ 3.2882 2.4306 1.2624 0.7392
B → Y↑ 12.2249 8.3772 4.1886 2.5592
B → Y↓ 3.2970 2.4341 1.2647 0.7402
C → Y↑ 12.2226 8.3763 4.1899 2.5593
C → Y↓ 3.3287 2.4500 1.2727 0.7439
150
Process Technology:
NOR3B

one inverted input (AN) and two non-inverted inputs AN
B Y
(B, C). The output (Y) is represented by the logic
C
equation:
Y = ( AN + B + C )
Cell Size
Functions
AN B C Y NOR3BXL 5.04 3.96
1 0 0 1 NOR3BX1 5.04 3.96
x x 1 0 NOR3BX2 5.04 5.28
x 1 x 0 NOR3BX4 5.04 7.26
0 x x 0
AN
B Y
C
151
Process Technology:
NOR3B

Pin Pin
AN 0.0194 0.0233 0.0381 0.0700 AN 0.0020 0.0022 0.0039 0.0062
B 0.0187 0.0252 0.0478 0.0798 B 0.0035 0.0046 0.0091 0.0157
C 0.0223 0.0305 0.0591 0.0991 C 0.0033 0.0044 0.0097 0.0160

Description
AN → Y↑ 0.0950 0.0920 0.0831 0.0849 12.2389 8.3835 4.1910 2.4258
AN → Y↓ 0.1111 0.1152 0.0996 0.1024 3.3515 2.4606 1.2744 0.7455
B → Y↑ 0.0853 0.0791 0.0721 0.0704 12.2269 8.3789 4.1888 2.4243
B → Y↓ 0.0316 0.0316 0.0303 0.0301 3.2987 2.4358 1.2655 0.7410
C → Y↑ 0.0917 0.0858 0.0817 0.0796 12.2226 8.3770 4.1896 2.4246
C → Y↓ 0.0339 0.0348 0.0347 0.0348 3.3270 2.4501 1.2730 0.7443
152
Process Technology:
NOR4

The NOR4 cell provides a logical NOR of four inputs A
C Y
equation:
D
Y = ( A + B + C + D)
Functions Cell Size

0 0 0 0 1 NOR4XL 5.04 3.96
x x x 1 0 NOR4X1 5.04 3.96
x x 1 x 0 NOR4X2 5.04 5.94
x 1 x x 0 NOR4X4 5.04 11.22
1 x x x 0
A
B
Y
C
D
153
Process Technology:
NOR4

Pin Pin
A 0.0174 0.0229 0.0436 0.0805 A 0.0040 0.0053 0.0098 0.0185
B 0.0217 0.0292 0.0563 0.1033 B 0.0039 0.0052 0.0102 0.0199
C 0.0261 0.0355 0.0693 0.1250 C 0.0038 0.0050 0.0108 0.0197
D 0.0306 0.0419 0.0831 0.1491 D 0.0036 0.0048 0.0112 0.0200

Description
XL X1 X2 X4
A → Y↑ 0.0657 0.0577 0.0507 0.0554
A → Y↓ 0.0283 0.0275 0.0262 0.0268
B → Y↑ 0.1022 0.0950 0.0885 0.0953
B → Y↓ 0.0360 0.0361 0.0355 0.0363
C → Y↑ 0.1237 0.1159 0.1095 0.1140
C → Y↓ 0.0402 0.0412 0.0408 0.0409
D → Y↑ 0.1305 0.1228 0.1199 0.1250
D → Y↓ 0.0407 0.0426 0.0435 0.0438
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 13.6994 9.4892 4.7432 2.7205
A → Y↓ 3.2895 2.4313 1.2628 0.6995
B → Y↑ 13.6811 9.4793 4.7398 2.7188
B → Y↓ 3.2974 2.4352 1.2651 0.7005
C → Y↑ 13.6803 9.4795 4.7401 2.7182
C → Y↓ 3.3332 2.4526 1.2740 0.7048
D → Y↑ 13.6770 9.4808 4.7408 2.7188
D → Y↓ 3.3808 2.4774 1.2870 0.7111
154
Process Technology:
NOR4B

AN
one inverted input (AN) and three non-inverted B
inputs (B, C, D). The output (Y) is represented by the C Y
logic equation: D
Y = ( AN + B + C + D )
Cell Size
Functions
AN B C D Y
NOR4BXL 5.04 3.96
1 0 0 0 1 NOR4BX1 5.04 3.96
x x x 1 0 NOR4BX2 5.04 6.60
x x 1 x 0 NOR4BX4 5.04 11.88
x 1 x x 0
0 x x x 0
AN
B
Y
C
D
155
Process Technology:
NOR4B

Pin Pin
AN 0.0216 0.0260 0.0438 0.0790 AN 0.0023 0.0027 0.0044 0.0068
B 0.0210 0.0275 0.0564 0.1029 B 0.0040 0.0051 0.0101 0.0196
C 0.0255 0.0335 0.0696 0.1249 C 0.0039 0.0050 0.0109 0.0197
D 0.0299 0.0395 0.0828 0.1490 D 0.0038 0.0049 0.0108 0.0202

Description
AN → Y↑ 0.0991 0.0976 0.0870 0.0928 13.6946 10.1395 4.7423 2.7203
AN → Y↓ 0.1241 0.1170 0.1047 0.1083 3.3617 2.4597 1.2950 0.7051
B → Y↑ 0.1001 0.0972 0.0880 0.0960 13.6883 10.1313 4.7394 2.7190
B → Y↓ 0.0349 0.0340 0.0350 0.0356 3.3005 2.4370 1.2869 0.7012
C → Y↑ 0.1211 0.1177 0.1116 0.1155 13.6816 10.1310 4.7417 2.7184
C → Y↓ 0.0393 0.0389 0.0417 0.0408 3.3327 2.4515 1.2953 0.7049
D → Y↑ 0.1279 0.1247 0.1200 0.1265 13.6805 10.1300 4.7403 2.7192
D → Y↓ 0.0399 0.0402 0.0439 0.0439 3.3790 2.4739 1.3079 0.7109
156
Process Technology:
NOR4BB

The NOR4BB cell provides a logical NOR of two
AN
inverted inputs (AN, BN) and two non-inverted inputs BN
(C, D). The output (Y) is represented by the logic C Y
equation: D
Y = ( AN + BN + C + D )
Cell Size
Functions
AN BN C D Y
NOR4BBXL 5.04 5.28
1 1 0 0 1 NOR4BBX1 5.04 5.28
x x x 1 0 NOR4BBX2 5.04 7.26
x x 1 x 0 NOR4BBX4 5.04 13.20
x 0 x x 0
0 x x x 0
AN
BN
Y
C
D
157
Process Technology:
NOR4BB

Pin Pin
AN 0.0212 0.0262 0.0448 0.0797 AN 0.0022 0.0026 0.0045 0.0068
BN 0.0248 0.0321 0.0585 0.1049 BN 0.0025 0.0028 0.0046 0.0067
C 0.0283 0.0375 0.0720 0.1274 C 0.0039 0.0052 0.0106 0.0197
D 0.0327 0.0439 0.0857 0.1513 D 0.0038 0.0051 0.0112 0.0201

Description
AN → Y↑ 0.1080 0.1007 0.0912 0.0943 13.6930 9.4845 4.7437 2.7196
AN → Y↓ 0.1248 0.1204 0.1051 0.1086 3.3496 2.4569 1.2737 0.7050
BN → Y↑ 0.1530 0.1428 0.1309 0.1386 13.6878 9.4816 4.7402 2.7201
BN → Y↓ 0.1358 0.1315 0.1183 0.1253 3.3470 2.4557 1.2730 0.7054
C → Y↑ 0.1354 0.1244 0.1159 0.1186 13.6833 9.4826 4.7403 2.7194
C → Y↓ 0.0422 0.0423 0.0412 0.0408 3.3338 2.4534 1.2750 0.7053
D → Y↑ 0.1426 0.1320 0.1257 0.1296 13.6814 9.4814 4.7422 2.7193
D → Y↓ 0.0433 0.0443 0.0441 0.0440 3.3787 2.4767 1.2868 0.7112
158
Process Technology:
OAI21

The OAI21 cell provides the logical inverted AND of
A0
one OR group and an additional input. The output A1
Y = ( A0 + A1 ) • B0 B0 Y
Functions
Cell Size
A0 A1 B0 Y
0 0 x 1
x x 0 1 OAI21XL 5.04 2.64
x 1 1 0 OAI21X1 5.04 3.30
1 x 1 0 OAI21X2 5.04 5.28
OAI21X4 5.04 7.26
A0
A1
B0
159
Process Technology:
OAI21

Pin Pin
A0 0.0196 0.0254 0.0491 0.0899 A0 0.0035 0.0046 0.0098 0.0184
A1 0.0226 0.0299 0.0578 0.1080 A1 0.0034 0.0044 0.0088 0.0177
B0 0.0150 0.0190 0.0357 0.0694 B0 0.0030 0.0040 0.0079 0.0150

Description
XL X1 X2 X4
A0 → Y↑ 0.0744 0.0670 0.0679 0.0585
A0 → Y↓ 0.0345 0.0315 0.0326 0.0288
A1 → Y↑ 0.0832 0.0763 0.0758 0.0669
A1 → Y↓ 0.0409 0.0381 0.0387 0.0353
B0 → Y↑ 0.0353 0.0314 0.0309 0.0276
B0 → Y↓ 0.0322 0.0288 0.0289 0.0271
Kload (ns/pF)
Description
XL X1 X2 X4
A0 → Y↑ 9.5844 6.5741 3.2875 1.6163
A0 → Y↓ 4.3004 2.8944 1.4645 0.7328
A1 → Y↑ 9.5803 6.5725 3.2864 1.6158
A1 → Y↓ 4.3068 2.8973 1.4662 0.7334
B0 → Y↑ 6.4860 4.5464 2.2727 1.1209
B0 → Y↓ 4.3089 2.8981 1.4662 0.7334
160
Process Technology:
OAI211

The OAI211 cell provides the logical inverted OR of
A0
one OR group and two additional inputs. The output A1
Y = ( A0 + A1 ) • B0 • C0 B0 Y
C0
Functions
A0 A1 B0 C0 Y Cell Size
0 0 x x 1
x x 0 x 1 Drive Strength Height (um) Width (um)
x x x 0 1 OAI211XL 5.04 3.96
x 1 1 1 0 OAI211X1 5.04 3.96
1 x 1 1 0 OAI211X2 5.04 6.60
OAI211X4 5.04 5.94
A0
A1
B0 Y
C0
161
Process Technology:
OAI211

Pin Pin
A0 0.0268 0.0362 0.0699 0.0858 A0 0.0036 0.0049 0.0104 0.0034
A1 0.0300 0.0409 0.0788 0.0887 A1 0.0035 0.0047 0.0093 0.0034
B0 0.0158 0.0216 0.0401 0.0719 B0 0.0032 0.0043 0.0083 0.0035
C0 0.0209 0.0285 0.0535 0.0764 C0 0.0033 0.0044 0.0088 0.0029

Description
A0 → Y↑ 0.1069 0.1004 0.0978 0.2641 9.6021 6.5819 3.2915 1.0899
A0 → Y↓ 0.0474 0.0457 0.0447 0.1813 4.6891 3.3140 1.6491 0.6401
A1 → Y↑ 0.1166 0.1095 0.1055 0.2731 9.5985 6.5803 3.2909 1.0899
A1 → Y↓ 0.0550 0.0535 0.0520 0.1902 4.6971 3.3174 1.6567 0.6401
B0 → Y↑ 0.0414 0.0395 0.0377 0.1696 6.4893 4.5469 2.3234 1.0899
B0 → Y↓ 0.0369 0.0362 0.0342 0.1739 4.6974 3.3156 1.6557 0.6400
C0 → Y↑ 0.0548 0.0525 0.0508 0.1823 6.4837 4.5440 2.3221 1.0899
C0 → Y↓ 0.0454 0.0444 0.0425 0.1801 4.6973 3.3163 1.6560 0.6400
162
Process Technology:
OAI22

A0
two OR groups. The output (Y) is represented by the A1
logic equation:
Y = ( A0 + A1 ) • ( B0 + B1 ) Y
B0
Functions B1
A0 A1 B0 B1 Y
0 0 x x 1 Cell Size
x x 0 0 1
x 1 x 1 0 Drive Strength Height (um) Width (um)
x 1 1 x 0 OAI22XL 5.04 3.96
1 x x 1 0 OAI22X1 5.04 3.96
1 x 1 x 0 OAI22X2 5.04 5.94
OAI22X4 5.04 9.24
A0
A1
B0
B1
163
Process Technology:
OAI22

Pin Pin
A0 0.0169 0.0229 0.0457 0.0907 A0 0.0035 0.0047 0.0097 0.0182
A1 0.0200 0.0274 0.0540 0.1078 A1 0.0036 0.0047 0.0087 0.0177
B0 0.0271 0.0361 0.0733 0.1327 B0 0.0035 0.0047 0.0099 0.0184
B1 0.0302 0.0406 0.0820 0.1510 B1 0.0033 0.0044 0.0087 0.0177

Description
A0 → Y↑ 0.0534 0.0495 0.0522 0.0491 9.6242 6.5928 3.2966 1.6206
A0 → Y↓ 0.0330 0.0328 0.0350 0.0347 4.0315 2.8982 1.4841 0.7513
A1 → Y↑ 0.0640 0.0590 0.0599 0.0572 9.6232 6.5916 3.2950 1.6201
A1 → Y↓ 0.0401 0.0398 0.0413 0.0415 4.0367 2.9007 1.4852 0.7518
B0 → Y↑ 0.0995 0.0904 0.0948 0.0819 9.5846 6.5741 3.2870 1.6158
B0 → Y↓ 0.0470 0.0457 0.0487 0.0451 4.0314 2.8983 1.4842 0.7512
B1 → Y↑ 0.1077 0.0986 0.1022 0.0900 9.5809 6.5713 3.2859 1.6153
B1 → Y↓ 0.0530 0.0521 0.0550 0.0520 4.0360 2.9013 1.4853 0.7520
164
Process Technology:
OAI221

The OAI221 cell provides the logical inverted AND
A0
of two OR groups and an additional input. The output A1
Y = ( A0 + A1 ) • ( B0 + B1 ) • C0 B0
B1
Functions Y
C0
A0 A1 B0 B1 C0 Y
0 0 x x x 1 Cell Size
x x 0 0 x 1
x x x x 0 1 Drive Strength Height (um) Width (um)
x 1 x 1 1 0 OAI221XL 5.04 4.62
x 1 1 x 1 0 OAI221X1 5.04 5.28
1 x x 1 1 0 OAI221X2 5.04 8.58
1 x 1 x 1 0 OAI221X4 5.04 7.26
A0
A1
B0
Y
B1
C0
165
Process Technology:
OAI221

Pin Pin
A0 0.0269 0.0349 0.0669 0.0845 A0 0.0038 0.0052 0.0098 0.0035
A1 0.0300 0.0395 0.0758 0.0873 A1 0.0037 0.0050 0.0102 0.0035
B0 0.0361 0.0473 0.0906 0.0958 B0 0.0036 0.0050 0.0098 0.0035
B1 0.0393 0.0519 0.1000 0.0985 B1 0.0034 0.0047 0.0100 0.0031
C0 0.0193 0.0269 0.0496 0.0729 C0 0.0034 0.0044 0.0086 0.0033

Description
A0 → Y↑ 0.1001 0.0883 0.0832 0.2546 9.6202 6.5901 3.2956 1.1592
A0 → Y↓ 0.0556 0.0519 0.0496 0.1841 4.6998 3.2918 1.6511 0.6388
A1 → Y↑ 0.1090 0.0971 0.0917 0.2633 9.6169 6.5884 3.2947 1.1592
A1 → Y↓ 0.0632 0.0597 0.0572 0.1926 4.7030 3.2938 1.6520 0.6388
B0 → Y↑ 0.1381 0.1243 0.1177 0.2943 9.6255 6.5910 3.2958 1.1591
B0 → Y↓ 0.0659 0.0618 0.0589 0.1948 4.7011 3.2926 1.6518 0.6388
B1 → Y↑ 0.1462 0.1323 0.1264 0.3017 9.6213 6.5891 3.2951 1.1591
B1 → Y↓ 0.0733 0.0691 0.0666 0.2030 4.7040 3.2971 1.6530 0.6388
C0 → Y↑ 0.0430 0.0417 0.0370 0.1687 6.5106 4.5587 2.2795 1.1591
C0 → Y↓ 0.0439 0.0445 0.0409 0.1743 4.7045 3.2941 1.6523 0.6388
166
Process Technology:
OAI222

The OAI222 cell provides the logical inverted AND
A0
of three OR groups. The output (Y) is represented A1
by the logic equation:
Y = ( A0 + A1 ) • ( B0 + B1 ) • ( C0 + C1 ) B0
B1 Y
Functions
C0
A0 A1 B0 B1 C0 C1 Y C1
0 0 x x x x 1
x x 0 0 x x 1
Cell Size
x x x x 0 0 1
x 1 x 1 1 x 0 Drive Strength Height (um) Width (um)
x 1 x 1 x 1 0
OAI222XL 5.04 5.28
x 1 1 x 1 x 0
OAI222X1 5.04 5.94
x 1 1 x x 1 0
OAI222X2 5.04 9.90
1 x x 1 1 x 0
OAI222X4 5.04 7.92
1 x x 1 x 1 0
1 x 1 x 1 x 0
1 x 1 x x 1 0
A0
A1
B0
Y
B1
C0
C1
167
Process Technology:
OAI222

Pin Pin
A0 0.0362 0.0464 0.0911 0.0965 A0 0.0038 0.0050 0.0098 0.0034
A1 0.0393 0.0510 0.1002 0.0994 A1 0.0037 0.0050 0.0101 0.0034
B0 0.0452 0.0586 0.1151 0.1074 B0 0.0036 0.0050 0.0097 0.0034
B1 0.0484 0.0632 0.1246 0.1102 B1 0.0034 0.0048 0.0100 0.0031
C0 0.0228 0.0313 0.0611 0.0797 C0 0.0039 0.0051 0.0097 0.0037
C1 0.0255 0.0354 0.0698 0.0820 C1 0.0037 0.0049 0.0103 0.0034

Description
A0 → Y↑ 0.1293 0.1116 0.1074 0.2896 9.6322 6.5968 3.2980 1.1592
A0 → Y↓ 0.0752 0.0697 0.0668 0.2110 4.7048 3.2956 1.6367 0.6389
A1 → Y↑ 0.1379 0.1207 0.1159 0.2988 9.6291 6.5953 3.2971 1.1592
A1 → Y↓ 0.0827 0.0778 0.0745 0.2202 4.7079 3.2965 1.6376 0.6390
B0 → Y↑ 0.1724 0.1525 0.1477 0.3312 9.6061 6.5824 3.2907 1.1590
B0 → Y↓ 0.0853 0.0794 0.0764 0.2214 4.7053 3.2962 1.6372 0.6389
B1 → Y↑ 0.1805 0.1605 0.1564 0.3395 9.6029 6.5805 3.2902 1.1590
B1 → Y↓ 0.0928 0.0870 0.0842 0.2303 4.7081 3.2976 1.6379 0.6390
C0 → Y↑ 0.0721 0.0670 0.0624 0.2258 9.6638 6.6124 3.3056 1.1592
C0 → Y↓ 0.0491 0.0494 0.0466 0.1837 4.7051 3.2943 1.6367 0.6390
C1 → Y↑ 0.0792 0.0748 0.0718 0.2322 9.6565 6.6092 3.3051 1.1592
C1 → Y↓ 0.0557 0.0567 0.0549 0.1910 4.7079 3.2959 1.6373 0.6390
168
Process Technology:
OAI2BB1

The OAI2BB1 cell provides the logical inverted AND
A0N
of one OR group of two inverted inputs (A0N, A1N) A1N
and an additional non-inverted input (B0). The output
(Y) is represented by the logic equation: Y
B0
Y = ( A0N + A1N ) • B0
Functions Cell Size
A0N A1N B0 Y Drive Strength Height (um) Width (um)

1 1 x 1 OAI2BB1XL 5.04 3.30
x x 0 1 OAI2BB1X1 5.04 3.30
x 0 1 0 OAI2BB1X2 5.04 4.62
0 x 1 0 OAI2BB1X4 5.04 6.60
A0N
A1N
B0
169
Process Technology:
OAI2BB1

Pin Pin
A0N 0.0223 0.0254 0.0429 0.0790 A0N 0.0021 0.0020 0.0034 0.0055
A1N 0.0194 0.0224 0.0375 0.0702 A1N 0.0016 0.0016 0.0027 0.0044
B0 0.0115 0.0153 0.0275 0.0582 B0 0.0027 0.0035 0.0070 0.0125

Description
A0N → Y↑ 0.0869 0.0915 0.0827 0.0883 6.4857 4.5459 2.1832 1.0917
A0N → Y↓ 0.1157 0.1305 0.1096 0.1007 4.0848 2.9301 1.4615 0.7423
A1N → Y↑ 0.0825 0.0872 0.0788 0.0845 6.4866 4.5462 2.1835 1.0917
A1N → Y↓ 0.1031 0.1173 0.0984 0.0917 4.0785 2.9268 1.4601 0.7417
B0 → Y↑ 0.0393 0.0376 0.0329 0.0349 6.4634 4.5337 2.1778 1.0889
B0 → Y↓ 0.0263 0.0272 0.0251 0.0272 4.0356 2.9045 1.4518 0.7389
170
Process Technology:
OAI2BB2

The OAI2BB2 cell provides the logical inverted AND
A0N
of one OR group of two inverted inputs (A0N, A1N) A1N
and one OR group of two non-inverted inputs (B0,
B1). The output (Y) is represented by the logic Y
equation:
Y = ( A0N + A1N ) • ( B0 + B1 ) B0
B1
Functions
Cell Size
A0N A1N B0 B1 Y
1 1 x x 1 Drive Strength Height (um) Width (um)
x x 0 0 1 OAI2BB2XL 5.04 4.62
x 0 x 1 0 OAI2BB2X1 5.04 4.62
x 0 1 x 0 OAI2BB2X2 5.04 6.60
0 x x 1 0 OAI2BB2X4 5.04 9.90
0 x 1 x 0
A0N
A1N
B0
B1
171
Process Technology:
OAI2BB2

Pin Pin
A0N 0.0238 0.0274 0.0500 0.0951 A0N 0.0020 0.0020 0.0036 0.0080
A1N 0.0197 0.0229 0.0413 0.0769 A1N 0.0023 0.0023 0.0039 0.0073
B0 0.0167 0.0214 0.0412 0.0760 B0 0.0036 0.0047 0.0099 0.0190
B1 0.0194 0.0255 0.0505 0.0927 B1 0.0034 0.0046 0.0102 0.0179

Description
A0N → Y↑ 0.0888 0.0930 0.0918 0.0879 6.5056 4.5559 2.2756 1.1117
A0N → Y↓ 0.1247 0.1399 0.1267 0.1225 4.0733 2.9229 1.4753 0.7436
A1N → Y↑ 0.0848 0.0890 0.0874 0.0826 6.4847 4.5448 2.2699 1.1093
A1N → Y↓ 0.1043 0.1183 0.1062 0.1005 4.0733 2.9242 1.4751 0.7438
B0 → Y↑ 0.0752 0.0672 0.0651 0.0601 9.5914 6.5764 3.2884 1.6166
B0 → Y↓ 0.0361 0.0356 0.0353 0.0342 4.0386 2.9049 1.4682 0.7409
B1 → Y↑ 0.0842 0.0758 0.0745 0.0683 9.5864 6.5737 3.2875 1.6161
B1 → Y↓ 0.0427 0.0428 0.0423 0.0413 4.0447 2.9073 1.4696 0.7414
172
Process Technology:
OAI31

A0
one OR group and an additional input. The output A1
(Y) is represented by the logic equation: A2
Y = ( A0 + A1 + A2 ) • B0 Y
B0
Functions
Cell Size
A0 A1 A2 B0 Y
0 0 0 x 1 Drive Strength Height (um) Width (um)
x x x 0 1 OAI31XL 5.04 3.96
x x 1 1 0 OAI31X1 5.04 3.96
x 1 x 1 0 OAI31X2 5.04 5.94
1 x x 1 0 OAI31X4 5.04 5.94
A0
A1
A2
B0
173
Process Technology:
OAI31

Pin Pin
A0 0.0208 0.0276 0.0586 0.0828 A0 0.0038 0.0050 0.0098 0.0037
A1 0.0244 0.0330 0.0697 0.0861 A1 0.0037 0.0049 0.0103 0.0035
A2 0.0281 0.0384 0.0811 0.0897 A2 0.0034 0.0047 0.0105 0.0034
B0 0.0187 0.0256 0.0484 0.0750 B0 0.0032 0.0040 0.0077 0.0029

Description
A0 → Y↑ 0.0935 0.0845 0.0913 0.2788 12.2356 8.3853 4.1933 1.0898
A0 → Y↓ 0.0353 0.0339 0.0356 0.1618 4.0251 2.8961 1.4582 0.6376
A1 → Y↑ 0.1161 0.1073 0.1145 0.3006 12.2275 8.3792 4.1916 1.0898
A1 → Y↓ 0.0434 0.0427 0.0446 0.1712 4.0306 2.8995 1.4597 0.6376
A2 → Y↑ 0.1230 0.1146 0.1235 0.3085 12.2266 8.3790 4.1919 1.0899
A2 → Y↓ 0.0468 0.0469 0.0495 0.1775 4.0659 2.9160 1.4680 0.6376
B0 → Y↑ 0.0346 0.0323 0.0298 0.1655 6.4928 4.5488 2.2745 1.0898
B0 → Y↓ 0.0363 0.0365 0.0347 0.1663 4.0677 2.9164 1.4681 0.6376
174
Process Technology:
OAI32

A0
logic equation: A2
Y = ( A0 + A1 + A2 ) • ( B0 + B1 ) Y
Functions B0
B1
A0 A1 A2 B0 B1 Y
0 0 0 x x 1
Cell Size
x x x 0 0 1
x x 1 x 1 0 Drive Strength Height (um) Width (um)
x x 1 1 x 0 OAI32XL 5.04 4.62
x 1 x 1 x 0 OAI32X1 5.04 4.62
x 1 x x 1 0 OAI32X2 5.04 7.26
1 x x 1 x 0 OAI32X4 5.04 6.60
1 x x x 1 0
A0
A1
A2
B0
B1
175
Process Technology:
OAI32

Pin Pin
A0 0.0295 0.0389 0.0749 0.0952 A0 0.0038 0.0051 0.0093 0.0036
A1 0.0333 0.0444 0.0863 0.0986 A1 0.0038 0.0050 0.0098 0.0036
A2 0.0370 0.0498 0.0975 0.1023 A2 0.0037 0.0048 0.0098 0.0033
B0 0.0217 0.0297 0.0603 0.0805 B0 0.0036 0.0049 0.0085 0.0034
B1 0.0247 0.0340 0.0693 0.0831 B1 0.0036 0.0047 0.0090 0.0031

Description
A0 → Y↑ 0.1304 0.1165 0.1103 0.3221 12.2355 8.3820 4.1904 1.0897
A0 → Y↓ 0.0506 0.0487 0.0531 0.1788 4.0319 2.8993 1.6394 0.6377
A1 → Y↑ 0.1534 0.1389 0.1336 0.3451 12.2280 8.3796 4.1888 1.0897
A1 → Y↓ 0.0591 0.0577 0.0636 0.1887 4.0370 2.9020 1.6403 0.6376
A2 → Y↑ 0.1603 0.1461 0.1412 0.3515 12.2264 8.3785 4.1890 1.0896
A2 → Y↓ 0.0632 0.0625 0.0698 0.1948 4.0665 2.9161 1.6481 0.6378
B0 → Y↑ 0.0555 0.0511 0.0523 0.2138 9.6358 6.6016 3.2993 1.0899
B0 → Y↓ 0.0404 0.0409 0.0468 0.1684 4.0665 2.9156 1.6479 0.6376
B1 → Y↑ 0.0660 0.0605 0.0621 0.2232 9.6345 6.6001 3.2989 1.0899
B1 → Y↓ 0.0480 0.0484 0.0556 0.1764 4.0670 2.9156 1.6477 0.6377
176
Process Technology:
OAI33

A0
logic equation: A2
Y = ( A0 + A1 + A2 ) • ( B0 + B1 + B2 ) Y
B0
Functions B1
B2
A0 A1 A2 B0 B1 B2 Y
0 0 0 x x x 1
x x x 0 0 0 1 Cell Size
x x 1 x x 1 0
x x 1 x 1 x 0
OAI33XL 5.04 5.28
x x 1 1 x x 0
OAI33X1 5.04 5.28
x 1 x x x 1 0
OAI33X2 5.04 8.58
x 1 x x 1 x 0
OAI33X4 5.04 7.26
x 1 x 1 x x 0
1 x x x x 1 0
1 x x x 1 x 0
1 x x 1 x x 0
A0
A1
A2
B0
B1
B2
177
Process Technology:
OAI33

Pin Pin
A0 0.0263 0.0358 0.0683 0.0900 A0 0.0039 0.0052 0.0094 0.0037
A1 0.0299 0.0410 0.0790 0.0929 A1 0.0038 0.0050 0.0099 0.0035
A2 0.0337 0.0466 0.0903 0.0962 A2 0.0038 0.0050 0.0107 0.0033
B0 0.0383 0.0515 0.0996 0.1075 B0 0.0038 0.0051 0.0092 0.0037
B1 0.0421 0.0570 0.1111 0.1109 B1 0.0037 0.0050 0.0099 0.0035
B2 0.0458 0.0624 0.1223 0.1145 B2 0.0035 0.0048 0.0098 0.0034

Description
A0 → Y↑ 0.0828 0.0741 0.0692 0.2675 12.3061 8.4214 4.2094 1.0901
A0 → Y↓ 0.0470 0.0470 0.0507 0.1775 4.0634 2.9142 1.6476 0.6378
A1 → Y↑ 0.1057 0.0985 0.0925 0.2902 12.2997 8.4184 4.2082 1.0901
A1 → Y↓ 0.0560 0.0570 0.0619 0.1876 4.0638 2.9149 1.6474 0.6378
A2 → Y↑ 0.1144 0.1081 0.1021 0.2978 12.3010 8.4191 4.2089 1.0901
A2 → Y↓ 0.0615 0.0634 0.0696 0.1946 4.0871 2.9274 1.6536 0.6379
B0 → Y↑ 0.1589 0.1444 0.1372 0.3560 12.2285 8.3800 4.1898 1.0898
B0 → Y↓ 0.0633 0.0630 0.0686 0.1978 4.0631 2.9170 1.6476 0.6378
B1 → Y↑ 0.1819 0.1667 0.1607 0.3776 12.2231 8.3768 4.1887 1.0898
B1 → Y↓ 0.0723 0.0724 0.0797 0.2075 4.0635 2.9171 1.6475 0.6378
B2 → Y↑ 0.1889 0.1735 0.1681 0.3853 12.2222 8.3768 4.1892 1.0898
B2 → Y↓ 0.0773 0.0780 0.0866 0.2147 4.0868 2.9284 1.6537 0.6379
178
Process Technology:
OR2

The OR2 cell provides the logical OR of two inputs
Y
equation: B
Y = ( A + B)
Functions Cell Size
0 0 0 OR2XL 5.04 2.64

x 1 1 OR2X1 5.04 2.64
1 x 1 OR2X2 5.04 2.64
OR2X4 5.04 3.96
A
Y
B
179
Process Technology:
OR2

Pin Pin
A 0.0194 0.0229 0.0339 0.0639 A 0.0025 0.0025 0.0035 0.0061
B 0.0217 0.0252 0.0379 0.0708 B 0.0026 0.0027 0.0038 0.0061

Description
XL X1 X2 X4
A → Y↑ 0.0614 0.0643 0.0630 0.0602
A → Y↓ 0.1322 0.1491 0.1275 0.1304
B → Y↑ 0.0676 0.0706 0.0703 0.0662
B → Y↓ 0.1458 0.1626 0.1396 0.1399
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4683 4.5357 2.3180 1.0898
A → Y↓ 3.4524 2.5147 1.2948 0.6476
B → Y↑ 6.4716 4.5373 2.3185 1.0899
B → Y↓ 3.4523 2.5146 1.2949 0.6475
180
Process Technology:
OR3

The OR3 cell provides the logical OR of three inputs
(A, B, C). The output (Y) is represented by the logic A
B Y
equation:
C
Y = ( A + B + C)
Functions Cell Size
0 0 0 0 OR3XL 5.04 3.30

x x 1 1 OR3X1 5.04 3.96
x 1 x 1 OR3X2 5.04 3.96
1 x x 1 OR3X4 5.04 5.94
A
B Y
C
181
Process Technology:
OR3

Pin Pin
A 0.0245 0.0267 0.0419 0.0790 A 0.0029 0.0026 0.0039 0.0073
B 0.0266 0.0291 0.0461 0.0877 B 0.0027 0.0026 0.0038 0.0079
C 0.0292 0.0317 0.0506 0.0972 C 0.0026 0.0025 0.0037 0.0081

Description
XL X1 X2 X4
A → Y↑ 0.0673 0.0689 0.0698 0.0663
A → Y↓ 0.1801 0.1939 0.1735 0.1623
B → Y↑ 0.0735 0.0754 0.0778 0.0750
B → Y↓ 0.2034 0.2179 0.1970 0.1862
C → Y↑ 0.0771 0.0789 0.0825 0.0804
C → Y↓ 0.2127 0.2265 0.2054 0.1954
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4686 4.5360 2.2623 1.1109
A → Y↓ 3.6159 2.5839 1.3265 0.6620
B → Y↑ 6.4701 4.5367 2.2629 1.1110
B → Y↓ 3.6160 2.5837 1.3264 0.6619
C → Y↑ 6.4774 4.5399 2.2648 1.1120
C → Y↓ 3.6156 2.5835 1.3264 0.6619
182
Process Technology:
OR4

The OR4 cell provides the logical OR of four inputs
A
equation: C Y
D
Y = ( A + B + C + D)
Functions Cell Size

0 0 0 0 0 OR4XL 5.04 3.96
x x x 1 1 OR4X1 5.04 3.96
x x 1 x 1 OR4X2 5.04 3.96
x 1 x x 1 OR4X4 5.04 7.26
1 x x x 1
A
B
Y
C
D
183
Process Technology:
OR4

Pin Pin
A 0.0277 0.0326 0.0457 0.0903 A 0.0028 0.0028 0.0043 0.0082
B 0.0306 0.0355 0.0508 0.1013 B 0.0027 0.0027 0.0042 0.0086
C 0.0336 0.0385 0.0559 0.1114 C 0.0030 0.0030 0.0041 0.0088
D 0.0369 0.0418 0.0614 0.1231 D 0.0031 0.0031 0.0043 0.0097

Description
XL X1 X2 X4
A → Y↑ 0.0736 0.0766 0.0725 0.0716
A → Y↓ 0.2123 0.2403 0.1902 0.1825
B → Y↑ 0.0812 0.0843 0.0820 0.0825
B → Y↓ 0.2508 0.2788 0.2267 0.2213
C → Y↑ 0.0868 0.0901 0.0886 0.0893
C → Y↓ 0.2756 0.3037 0.2484 0.2417
D → Y↑ 0.0897 0.0935 0.0919 0.0935
D → Y↓ 0.2881 0.3165 0.2578 0.2528
Delay Table at 25 oC, 1.8V, Typical Process
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4709 4.5379 2.2627 1.1347
A → Y↓ 3.8066 2.6904 1.3550 0.6476
B → Y↑ 6.4726 4.5382 2.2631 1.1349
B → Y↓ 3.8061 2.6900 1.3550 0.6476
C → Y↑ 6.4807 4.5424 2.2654 1.1362
C → Y↓ 3.8061 2.6902 1.3550 0.6475
D → Y↑ 6.4930 4.5485 2.2691 1.1381
D → Y↓ 3.8058 2.6902 1.3549 0.6475
184
Process Technology:
RSLAT

The RSLAT cell is an RS-type latch with active-high
set (S) and reset (R).
R Q
Functions
S QN
R S Q[n+1] QN[n+1]
0 0 Q[n] QN[n]
0 1 1 0 Cell Size
1 0 0 1
1 1 IL IL Drive Strength Height (um) Width (um)
RSLATXL 5.04 6.60
RSLATX1 5.04 6.60
RSLATX2 5.04 7.92
RSLATX4 5.04 11.88
QN
S
Q
R
185
Process Technology:
RSLAT

Pin Pin
S 0.0105 0.0116 0.0151 0.0282 S 0.0022 0.0023 0.0026 0.0046
R 0.0110 0.0119 0.0161 0.0287 R 0.0023 0.0024 0.0026 0.0046
Q 0.0416 0.0521 0.0855 0.1533

Description
S → Q↑ 0.2468 0.2227 0.2002 0.1854 6.4943 4.5471 2.2384 1.0916
R → Q↑ 0.1738 0.1688 0.1589 0.1386 6.4928 4.5462 2.2385 1.0915
R → Q↓ 0.1735 0.1552 0.1380 0.1298 3.4239 2.4752 1.2782 0.6383
S → QN↑ 0.1581 0.1579 0.1575 0.1347 6.4907 4.5447 2.2386 1.0914
S → QN↓ 0.1596 0.1468 0.1385 0.1262 3.4190 2.4749 1.2788 0.6379
R → QN↑ 0.2552 0.2260 0.2020 0.1872 6.4925 4.5450 2.2389 1.0915
Interval (ns)
Pin Requirement
XL X1 X2 X4
S minpwh 0.1335 0.1092 0.0946 0.0946
R minpwh 0.1286 0.1092 0.0995 0.0946
186
Process Technology:
RSLATN

The RSLATN cell is an RS-type latch with active-low
set (SN) and reset (RN).
RN Q
Function
SN QN
RN SN Q[n+1] QN[n+1]
0 0 IL IL
0 1 0 1 Cell Size
1 0 1 0
1 1 Q[n] QN[n] Drive Strength Height (um) Width (um)
RSLATNXL 5.04 6.60
RSLATNX1 5.04 7.26
RSLATNX2 5.04 7.26
RSLATNX4 5.04 11.88
Q
SN
QN
RN
187
Process Technology:
RSLATN

Pin Pin
SN 0.0114 0.0131 0.0166 0.0322 SN 0.0022 0.0022 0.0028 0.0049
RN 0.0115 0.0120 0.0184 0.0323 RN 0.0023 0.0024 0.0031 0.0048
Q 0.0440 0.0551 0.0931 0.1672

Description
SN → Q↑ 0.1531 0.1629 0.1471 0.1323 6.4826 4.5418 2.2377 1.1186
SN → Q↓ 0.2134 0.1873 0.1668 0.1567 3.3581 2.5199 1.2967 0.6461
RN → Q↓ 0.3182 0.3023 0.2723 0.2453 3.3581 2.5199 1.2969 0.6462
SN → QN↓ 0.3224 0.3020 0.2660 0.2448 3.3701 2.5232 1.2959 0.6474
RN → QN↑ 0.1570 0.1658 0.1509 0.1332 6.4831 4.5417 2.2372 1.1185
RN → QN↓ 0.2186 0.1907 0.1681 0.1568 3.3703 2.5231 1.2958 0.6473
Interval (ns)
Pin Requirement
XL X1 X2 X4
SN minpwl 0.1432 0.1480 0.1335 0.1189
RN minpwl 0.1480 0.1529 0.1383 0.1238
188
Process Technology:
SDFF

The SDFF cell is a positive-edge triggered, static D-
type flip-flop with scan input (SI) and active-high D Q
scan enable (SE). SI QN
SE
Functions CK
D SI SE CK Q[n+1] QN[n+1]
1 x 0 1 0
Cell Size
0 x 0 0 1
x x x Q[n] QN[n] Drive Strength Height (um) Width (um)
x 1 1 1 0
SDFFXL 5.04 13.20
x 0 1 0 1
SDFFX1 5.04 13.86
SDFFX2 5.04 16.50
SDFFX4 5.04 19.14
cn c
c cn
SI c cn
SE
QN
cn c
D Q
cn
CK c
189
Process Technology:
SDFF

Pin Pin
SI 0.0432 0.0407 0.0511 0.0787 SI 0.0025 0.0023 0.0024 0.0023
SE 0.0509 0.0471 0.0573 0.0816 SE 0.0050 0.0042 0.0045 0.0051
D 0.0372 0.0358 0.0452 0.0674 D 0.0030 0.0019 0.0023 0.0033
CK 0.0685 0.0683 0.0857 0.1291 CK 0.0020 0.0027 0.0038 0.0059
Q 0.0357 0.0396 0.0682 0.1149

Description
CK → Q↑ 0.2544 0.2210 0.2018 0.1679 6.3926 4.6237 2.2729 1.1329
CK → Q↓ 0.2089 0.1796 0.1666 0.1452 3.5017 2.5789 1.2892 0.6463
CK → QN↑ 0.2697 0.2367 0.2130 0.1912 6.4739 4.5394 2.2688 1.1313
CK → QN↓ 0.3506 0.3127 0.2850 0.2384 3.6665 2.4784 1.2356 0.6390
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1250 0.1250 0.1484 0.1719
setup↓ → CK 0.3555 0.4180 0.4219 0.4922
SI
hold↑ → CK -0.1016 -0.0938 -0.1094 -0.1250
hold↓ → CK -0.2305 -0.2969 -0.2930 -0.3594
setup↑ → CK 0.3867 0.4453 0.4453 0.5273
setup↓ → CK 0.2148 0.4297 0.3633 0.2812
SE
hold↑ → CK -0.0898 -0.0781 -0.0938 -0.1172
hold↓ → CK -0.0898 -0.1445 -0.1602 -0.1445
setup↑ → CK 0.0820 0.1094 0.1328 0.1094
setup↓ → CK 0.2188 0.4414 0.3711 0.2852
D
hold↑ → CK -0.0664 -0.0781 -0.0938 -0.0781
hold↓ → CK -0.0938 -0.3281 -0.2461 -0.1719
minpwh 0.1335 0.1189 0.1092 0.0946
CK
minpwl 0.2256 0.2111 0.2062 0.1626
190
Process Technology:
SDFFHQ

The SDFFHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI) D Q
and active-high scan enable (SE). The cell has a SI
single output (Q) and fast clock-to-out path.
SE
CK
Functions
D SI SE CK Q[n+1]
Cell Size
1 x 0 1
0 x 0 0 Drive Strength Height (um) Width (um)
x x x Q[n]
SDFFHQXL 5.04 13.20
x 1 1 1
SDFFHQX1 5.04 13.20
x 0 1 0
SDFFHQX2 5.04 15.84
SDFFHQX4 5.04 17.16
cn c
c cn
SI c cn
SE
cn c
D Q
cn
CK c
191
Process Technology:
SDFFHQ

Pin Pin
SI 0.0476 0.0519 0.0697 0.0952 SI 0.0023 0.0024 0.0024 0.0023
SE 0.0547 0.0590 0.0763 0.0977 SE 0.0047 0.0042 0.0043 0.0048
D 0.0414 0.0472 0.0644 0.0845 D 0.0027 0.0019 0.0022 0.0029
CK 0.0742 0.0807 0.1041 0.1400 CK 0.0021 0.0028 0.0035 0.0050
Q 0.0256 0.0267 0.0444 0.0623

Description
CK → Q↑ 0.2268 0.1925 0.1909 0.1637 6.4840 4.6186 2.2709 1.0905
CK → Q↓ 0.2330 0.1736 0.1749 0.1478 3.6182 2.6090 1.3077 0.6443
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1406 0.1484 0.1562 0.1758
setup↓ → CK 0.4180 0.4688 0.4805 0.5039
SI
hold↑ → CK -0.0938 -0.0977 -0.1016 -0.1211
hold↓ → CK -0.2266 -0.3047 -0.3008 -0.3320
setup↑ → CK 0.4492 0.5000 0.5117 0.5352
setup↓ → CK 0.3086 0.4805 0.4570 0.3516
SE
hold↑ → CK -0.0820 -0.0820 -0.0859 -0.1094
hold↓ → CK -0.1250 -0.1523 -0.1562 -0.1523
setup↑ → CK 0.0977 0.1367 0.1406 0.1367
setup↓ → CK 0.3125 0.4961 0.4688 0.3555
D
hold↑ → CK -0.0586 -0.0820 -0.0859 -0.0859
hold↓ → CK -0.1328 -0.3359 -0.2891 -0.1953
minpwh 0.1432 0.1092 0.1140 0.0995
CK
minpwl 0.2208 0.2111 0.1965 0.1723
192
Process Technology:
SDFFN

The SDFFN cell is a negative-edge triggered, static
D-type flip-flop with scan input (SI) and active-high D Q
scan enable (SE). SI QN
SE
Functions CKN
D SI SE CKN Q[n+1] QN[n+1]

1 x 0 1 0
Cell Size
0 x 0 0 1
x x x Q[n] QN[n] Drive Strength Height (um) Width (um)
x 1 1 1 0
SDFFNXL 5.04 13.86
x 0 1 0 1
SDFFNX1 5.04 13.86
SDFFNX2 5.04 16.50
SDFFNX4 5.04 18.48
cn c
c cn
SI c cn
SE
QN
cn c
D Q
CKN cn
193
Process Technology:
SDFFN

Pin Pin
SI 0.0444 0.0423 0.0524 0.0785 SI 0.0023 0.0021 0.0022 0.0021
SE 0.0522 0.0494 0.0590 0.0820 SE 0.0046 0.0040 0.0043 0.0048
D 0.0383 0.0374 0.0465 0.0677 D 0.0026 0.0018 0.0021 0.0030
CKN 0.0618 0.0602 0.0735 0.1074 CKN 0.0020 0.0027 0.0038 0.0059
Q 0.0365 0.0421 0.0725 0.1185

Description
CKN → Q↑ 0.2015 0.1582 0.1418 0.1178 6.3929 4.6253 2.2733 1.1110
CKN → Q↓ 0.3419 0.2885 0.2625 0.2229 3.4803 2.5765 1.2881 0.6655
CKN → QN↑ 0.4035 0.3446 0.3098 0.2722 6.4746 4.5399 2.2687 1.1094
CKN → QN↓ 0.2984 0.2496 0.2262 0.1896 3.4139 2.4774 1.2358 0.6588
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.1133 0.1367 0.1641 0.1836
setup↓ → CKN 0.3477 0.4062 0.4102 0.4727
SI
hold↑ → CKN 0.0430 0.0117 -0.0117 -0.0391
hold↓ → CKN -0.2969 -0.3438 -0.3398 -0.3945
setup↑ → CKN 0.3711 0.4336 0.4336 0.5039
setup↓ → CKN 0.1953 0.4180 0.3477 0.2578
SE
hold↑ → CKN 0.0547 0.0234 0.0000 -0.0312
hold↓ → CKN -0.0039 -0.0508 -0.0742 -0.0703
setup↑ → CKN 0.0781 0.1250 0.1523 0.1250
setup↓ → CKN 0.1992 0.4258 0.3555 0.2617
D
hold↑ → CKN 0.0586 0.0156 -0.0078 -0.0039
hold↓ → CKN -0.1641 -0.3594 -0.2891 -0.2148
minpwl 0.2208 0.1723 0.1529 0.1335
CKN
minpwh 0.1529 0.1820 0.1868 0.1383
194
Process Technology:
SDFFNR

The SDFFNR cell is a negative-edge triggered,
static D-type flip-flop with scan input (SI), D Q
active-high scan enable (SE), and asynchronous SI QN
active-low reset (RN).
SE
CKN
Functions
RN D SI SE CKN Q[n+1] QN[n+1] RN

1 1 x 0 1 0
1 0 x 0 0 1
1 x x x Q[n] QN[n] Cell Size
1 x 1 1 1 0
1 x 0 1 0 1
SDFFNRXL 5.04 18.48
0 x x x x 0 1
SDFFNRX1 5.04 17.82
SDFFNRX2 5.04 19.80
SDFFNRX4 5.04 23.10
cn c
c cn
SI c cn
SE
Q
cn c
D QN
RN
CKN cn
195
Process Technology:
SDFFNR

Pin Pin
SI 0.0462 0.0419 0.0450 0.0564 SI 0.0021 0.0021 0.0022 0.0022
SE 0.0547 0.0489 0.0542 0.0641 SE 0.0047 0.0041 0.0044 0.0048
D 0.0402 0.0367 0.0402 0.0499 D 0.0027 0.0019 0.0019 0.0024
CKN 0.0696 0.0644 0.0693 0.0847 CKN 0.0023 0.0027 0.0031 0.0037
RN 0.0181 0.0201 0.0238 0.0357 RN 0.0023 0.0028 0.0033 0.0057
Q 0.0449 0.0534 0.0817 0.1383

Description
CKN → Q↑ 0.4173 0.3526 0.3346 0.3011 6.4716 4.5384 2.1881 1.1159
CKN → Q↓ 0.4877 0.4682 0.4614 0.4021 3.3506 2.4645 1.4147 0.6425
RN → Q↓ 0.2692 0.2706 0.2448 0.2210 3.3501 2.4640 1.4143 0.6424
CKN → QN↑ 0.4297 0.3956 0.3825 0.3319 6.4702 4.5400 2.1896 1.1166
CKN → QN↓ 0.3889 0.3172 0.2885 0.2549 3.6197 2.5314 1.4364 0.6539
RN → QN↑ 0.2113 0.1987 0.1665 0.1513 6.4784 4.5427 2.1905 1.1174
196
Process Technology:
SDFFNR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.1133 0.1406 0.1797 0.1758
setup↓ → CKN 0.3594 0.4219 0.4531 0.4375
SI
hold↑ → CKN 0.0547 0.0039 0.0000 -0.0195
hold↓ → CKN -0.3086 -0.3594 -0.3945 -0.3711
setup↑ → CKN 0.3828 0.4492 0.4766 0.4570
setup↓ → CKN 0.1992 0.4180 0.4609 0.3203
SE
hold↑ → CKN 0.0625 0.0195 0.0117 -0.0039
hold↓ → CKN 0.0117 -0.0625 -0.0664 -0.0781
setup↑ → CKN 0.0781 0.1289 0.1680 0.1523
setup↓ → CKN 0.2031 0.4336 0.4688 0.3281
D
hold↑ → CKN 0.0742 0.0117 0.0039 -0.0078
hold↓ → CKN -0.1680 -0.3672 -0.4023 -0.2695
minpwl 0.2450 0.2111 0.2062 0.1771
CKN
minpwh 0.1626 0.1868 0.2111 0.1820
minpwl 0.2062 0.2111 0.2450 0.3712
RN
recovery 0.0234 0.0703 0.0977 0.0742
197
Process Technology:
SDFFNS

The SDFFNS cell is a negative-edge triggered, static
SN
D-type flip-flop with scan input (SI), active-high scan
enable (SE), and asynchronous active-low set (SN).
D Q
Functions SI QN
SE
SN D SI SE CKN Q[n+1] QN[n+1]
CKN
1 1 x 0 1 0
1 0 x 0 0 1
1 x 1 1 1 0
1 x 0 1 0 1 Drive Strength Height (um) Width (um)
0 x x x x 1 0 SDFFNSXL 5.04 15.84
SDFFNSX1 5.04 15.84
SDFFNSX2 5.04 16.50
SDFFNSX4 5.04 21.78
cn c
c cn
SI c cn
SE
Q
cn c
D QN
SN
c
CKN cn
198
Process Technology:
SDFFNS

Pin Pin
SI 0.0444 0.0379 0.0416 0.0504 SI 0.0021 0.0021 0.0021 0.0019
SE 0.0524 0.0447 0.0487 0.0565 SE 0.0048 0.0042 0.0042 0.0044
D 0.0384 0.0327 0.0366 0.0444 D 0.0026 0.0017 0.0017 0.0019
CKN 0.0633 0.0563 0.0607 0.0736 CKN 0.0021 0.0027 0.0027 0.0034
SN 0.0062 0.0070 0.0101 0.0173 SN 0.0050 0.0055 0.0072 0.0123
Q 0.0414 0.0491 0.0775 0.1382

Description
CKN → Q↑ 0.3311 0.2909 0.2913 0.2728 6.4716 4.5377 2.1791 1.1127
CKN → Q↓ 0.4553 0.4382 0.4253 0.3947 3.3490 2.4624 1.2757 0.6388
SN → Q↑ 0.1777 0.1567 0.1570 0.1499 6.4718 4.5375 2.1789 1.1126
CKN → QN↑ 0.4025 0.3723 0.3497 0.3248 6.4868 4.5421 2.1840 1.1149
CKN → QN↓ 0.3031 0.2554 0.2432 0.2242 3.4378 2.4716 1.2793 0.6410
SN → QN↓ 0.1496 0.1212 0.1090 0.1018 3.4135 2.4703 1.2814 0.6434
199
Process Technology:
SDFFNS
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.0898 0.1172 0.1133 0.1328
setup↓ → CKN 0.3516 0.3984 0.4102 0.4141
SI
hold↑ → CKN 0.0469 0.0078 0.0156 -0.0039
hold↓ → CKN -0.3164 -0.3516 -0.3594 -0.3594
setup↑ → CKN 0.3789 0.4297 0.4414 0.4336
setup↓ → CKN 0.1914 0.3984 0.4141 0.3477
SE
hold↑ → CKN 0.0586 0.0234 0.0273 0.0078
hold↓ → CKN 0.0039 -0.0547 -0.0508 -0.0664
setup↑ → CKN 0.0547 0.1055 0.1016 0.1211
setup↓ → CKN 0.1992 0.4180 0.4336 0.3555
D
hold↑ → CKN 0.0664 0.0156 0.0195 0.0000
hold↓ → CKN -0.1758 -0.3672 -0.3789 -0.3086
minpwl 0.2159 0.2014 0.1820 0.1674
CKN
minpwh 0.1480 0.1626 0.1771 0.1723
minpwl 0.1432 0.1189 0.1238 0.1480
SN
recovery -0.1055 -0.0547 -0.0586 -0.0469
200
Process Technology:
SDFFNSR

The SDFFNSR cell is a negative-edge triggered,
SN
static D-type flip-flop with scan input (SI), active-
high scan enable (SE), and asynchronous active-
low reset (RN) and set (SN). Set (SN) dominates
D Q
reset (RN).
SI QN
SE
Functions
CKN
RN SN D SI SE CKN Q[n+1] QN[n+1]
1 1 1 x 0 1 0 RN
1 1 0 x 0 0 1
1 1 x x x Q[n] QN[n]
1 1 x 1 1 1 0 Cell Size
1 1 x 0 1 0 1
0 1 x x x x 0 1
SDFFNSRXL 5.04 19.14
1 0 x x x x 1 0
SDFFNSRX1 5.04 19.14
0 0 x x x x 1 0
cn c
c cn
SI c cn
SE
Q
cn c
D QN
RN
SN
c
CKN cn
201
Process Technology:
SDFFNSR

Pin Pin
SI 0.0465 0.0404 0.0459 0.0596 SI 0.0019 0.0019 0.0019 0.0019
SE 0.0542 0.0468 0.0531 0.0668 SE 0.0045 0.0040 0.0043 0.0047
D 0.0407 0.0353 0.0405 0.0526 D 0.0021 0.0016 0.0017 0.0024
CKN 0.0668 0.0598 0.0663 0.0854 CKN 0.0022 0.0028 0.0028 0.0040
SN 0.0085 0.0089 0.0124 0.0181 SN 0.0065 0.0069 0.0091 0.0149
RN 0.0194 0.0218 0.0265 0.0447 RN 0.0026 0.0029 0.0039 0.0060
Q 0.0462 0.0539 0.0823 0.1510

Description
CKN → Q↑ 0.4042 0.3531 0.3394 0.3099 6.4687 4.5366 2.1796 1.1194
CKN → Q↓ 0.4848 0.4711 0.4305 0.3992 3.3674 2.4715 1.2766 0.6376
SN → Q↑ 0.2068 0.1886 0.1748 0.1684 6.4683 4.5360 2.1795 1.1193
SN → Q↓ 0.2047 0.1957 0.1761 0.1669 3.3676 2.4713 1.2764 0.6374
RN → Q↓ 0.3129 0.2925 0.2499 0.2376 3.3679 2.4712 1.2764 0.6374
CKN → QN↑ 0.4145 0.3879 0.3537 0.3287 6.5033 4.5457 2.1843 1.1224
CKN → QN↓ 0.3669 0.3105 0.2869 0.2620 3.6976 2.5414 1.3074 0.6530
SN → QN↑ 0.1349 0.1134 0.0998 0.0967 6.5282 4.5577 2.1900 1.1260
SN → QN↓ 0.1666 0.1432 0.1224 0.1206 3.4672 2.4910 1.2866 0.6479
RN → QN↑ 0.2428 0.2099 0.1735 0.1673 6.5254 4.5570 2.1897 1.1259
202
Process Technology:
SDFFNSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CKN 0.1484 0.1992 0.1797 0.1875
setup↓ → CKN 0.3594 0.4375 0.4414 0.4219
SI
hold↑ → CKN 0.0195 -0.0195 -0.0117 -0.0234
hold↓ → CKN -0.3125 -0.3711 -0.3711 -0.3516
setup↑ → CKN 0.3906 0.4648 0.4648 0.4492
setup↓ → CKN 0.2773 0.4531 0.4180 0.2930
SE
hold↑ → CKN 0.0312 -0.0078 0.0039 -0.0117
hold↓ → CKN -0.0273 -0.0820 -0.0742 -0.0625
setup↑ → CKN 0.1094 0.1875 0.1680 0.1484
setup↓ → CKN 0.2812 0.4609 0.4219 0.2969
D
hold↑ → CKN 0.0430 -0.0156 -0.0039 0.0000
hold↓ → CKN -0.2344 -0.3867 -0.3516 -0.2383
minpwl 0.2159 0.2062 0.1820 0.1626
CKN
minpwh 0.1674 0.2014 0.2062 0.1674
minpwl 0.1626 0.1432 0.1383 0.1771
SN recovery -0.0781 -0.0391 -0.0391 -0.0391
removal 0.0859 0.0469 0.0469 0.0469
minpwl 0.2305 0.2111 0.2208 0.3906
RN recovery 0.0625 0.1328 0.0977 0.0898
removal 0.0898 0.0234 0.0586 0.0664
203
Process Technology:
SDFFR

The SDFFR cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high D Q
scan enable (SE), and asynchronous active-low SI QN
reset (RN).
SE
CK
Functions
RN D SI SE CK Q[n+1] QN[n+1] RN
1 1 x 0 1 0
1 0 x 0 0 1
1 x 1 1 1 0
1 x 0 1 0 1
SDFFRXL 5.04 18.48
0 x x x x 0 1
SDFFRX1 5.04 18.48
SDFFRX2 5.04 19.80
SDFFRX4 5.04 23.10
cn c
c cn
SI c cn
SE
Q
cn c
D QN
RN
cn
CK c
204
Process Technology:
SDFFR

Pin Pin
SI 0.0453 0.0417 0.0433 0.0559 SI 0.0023 0.0025 0.0025 0.0024
SE 0.0540 0.0486 0.0521 0.0634 SE 0.0050 0.0043 0.0046 0.0051
D 0.0394 0.0365 0.0384 0.0494 D 0.0030 0.0022 0.0021 0.0028
CK 0.0722 0.0701 0.0778 0.0932 CK 0.0023 0.0027 0.0031 0.0037
RN 0.0176 0.0199 0.0234 0.0350 RN 0.0022 0.0027 0.0032 0.0056
Q 0.0455 0.0522 0.0796 0.1394

Description
CK → Q↑ 0.4633 0.4202 0.4040 0.3573 6.4716 4.5371 2.1883 1.1161
CK → Q↓ 0.3203 0.3416 0.3202 0.2851 3.3505 2.4654 1.4145 0.6426
RN → Q↓ 0.2683 0.2676 0.2442 0.2200 3.3501 2.4650 1.4142 0.6424
CK → QN↑ 0.2622 0.2684 0.2407 0.2150 6.4708 4.5378 2.1894 1.1166
CK → QN↓ 0.4349 0.3839 0.3592 0.3085 3.6194 2.5296 1.5425 0.6538
RN → QN↑ 0.2104 0.1951 0.1653 0.1504 6.4786 4.5401 2.1905 1.1174
205
Process Technology:
SDFFR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1484 0.1445 0.1680 0.1680
setup↓ → CK 0.3789 0.4297 0.4609 0.4570
SI
hold↑ → CK -0.1250 -0.1172 -0.1328 -0.1367
hold↓ → CK -0.2383 -0.3047 -0.3164 -0.3281
setup↑ → CK 0.4062 0.4570 0.4844 0.4805
setup↓ → CK 0.2305 0.4297 0.4727 0.3438
SE
hold↑ → CK -0.1133 -0.1016 -0.1172 -0.1211
hold↓ → CK -0.0898 -0.1719 -0.1875 -0.1797
setup↑ → CK 0.1016 0.1289 0.1523 0.1445
setup↓ → CK 0.2344 0.4492 0.4727 0.3555
D
hold↑ → CK -0.0859 -0.1016 -0.1172 -0.1133
hold↓ → CK -0.0938 -0.3242 -0.3320 -0.2305
minpwh 0.1383 0.1480 0.1335 0.1140
CK
minpwl 0.2742 0.2353 0.2548 0.2159
minpwl 0.2062 0.2111 0.2450 0.3664
RN recovery 0.0352 0.0508 0.0742 0.0508
removal -0.0117 -0.0273 -0.0430 -0.0117
206
Process Technology:
SDFFRHQ

The SDFFRHQ cell is a high-speed, positive-edge
triggered, static D-type flip-flop with scan input (SI), D Q
active-high scan enable (SE), and asynchronous SI
active-low reset (RN). The cell has a single output
SE
(Q) and fast clock-to-out path.
CK
Functions
RN
RN D SI SE CK Q[n+1]
1 1 x 0 1
1 0 x 0 0 Cell Size
1 x x x Q[n]
1 x 1 1 1
1 x 0 1 0 SDFFRHQXL 5.04 16.50
0 x x x x 0 SDFFRHQX1 5.04 16.50
SDFFRHQX2 5.04 19.80
SDFFRHQX4 5.04 24.42
cn c
c cn
SI c cn
SE
Q
cn c
D
RN
cn
CK c
207
Process Technology:
SDFFRHQ

Pin Pin
SI 0.0461 0.0560 0.0812 0.1224 SI 0.0023 0.0023 0.0023 0.0022
SE 0.0534 0.0626 0.0860 0.1216 SE 0.0051 0.0046 0.0048 0.0056
D 0.0398 0.0507 0.0735 0.1059 D 0.0028 0.0020 0.0024 0.0038
CK 0.0734 0.0869 0.1204 0.1759 CK 0.0020 0.0029 0.0040 0.0060
RN 0.0218 0.0275 0.0379 0.0585 RN 0.0025 0.0041 0.0056 0.0095
Q 0.0346 0.0362 0.0495 0.0762

Description
CK → Q↑ 0.2573 0.2143 0.1876 0.1697 9.6056 6.5762 3.2876 1.8060
CK → Q↓ 0.2787 0.1829 0.1608 0.1463 3.7476 2.4970 1.2906 0.7103
RN → Q↓ 0.1980 0.1412 0.1208 0.1023 3.1106 2.0779 1.1794 0.6921
208
Process Technology:
SDFFRHQ
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1680 0.1914 0.2188 0.2344
setup↓ → CK 0.4375 0.5000 0.5312 0.5781
SI
hold↑ → CK -0.1094 -0.1211 -0.1367 -0.1484
hold↓ → CK -0.2266 -0.3008 -0.3203 -0.3711
setup↑ → CK 0.4609 0.5234 0.5547 0.6211
setup↓ → CK 0.2891 0.4805 0.4180 0.3281
SE
hold↑ → CK -0.1016 -0.1055 -0.1250 -0.1406
hold↓ → CK -0.0898 -0.1680 -0.1758 -0.1484
setup↑ → CK 0.1289 0.1758 0.1914 0.1602
setup↓ → CK 0.2891 0.4883 0.4219 0.3320
D
hold↑ → CK -0.0703 -0.1055 -0.1133 -0.0859
hold↓ → CK -0.0938 -0.2930 -0.2227 -0.1523
minpwh 0.1723 0.1238 0.1092 0.0946
CK
minpwl 0.2402 0.2208 0.2062 0.1626
minpwl 0.2984 0.2936 0.3955 0.6284
RN recovery 0.0977 0.1094 0.1133 0.1055
removal -0.0273 -0.0352 -0.0234 -0.0078
209
Process Technology:
SDFFS

The SDFFS cell is a positive-edge triggered, static
SN
enable (SE), and asynchronous active-low set (SN).
D Q
Functions SI QN
SE
SN D SI SE CK Q[n+1] QN[n+1]
CK
1 1 x 0 1 0
1 0 x 0 0 1
1 x 1 1 1 0
1 x 0 1 0 1 Drive Strength Height (um) Width (um)
0 x x x x 1 0 SDFFSXL 5.04 15.84
SDFFSX1 5.04 15.84
SDFFSX2 5.04 16.50
SDFFSX4 5.04 21.12
cn c
c cn
SI c cn
SE
Q
cn c
D QN
SN
cn
CK c
210
Process Technology:
SDFFS

Pin Pin
SI 0.0428 0.0362 0.0402 0.0478 SI 0.0021 0.0022 0.0021 0.0022
SE 0.0500 0.0424 0.0463 0.0538 SE 0.0052 0.0045 0.0045 0.0047
D 0.0366 0.0309 0.0351 0.0418 D 0.0027 0.0018 0.0018 0.0021
CK 0.0675 0.0625 0.0703 0.0839 CK 0.0024 0.0029 0.0030 0.0035
SN 0.0065 0.0073 0.0117 0.0181 SN 0.0054 0.0058 0.0078 0.0130
Q 0.0404 0.0479 0.0776 0.1322

Description
CK → Q↑ 0.3779 0.3497 0.3605 0.3306 6.4733 4.5381 2.2350 1.0898
CK → Q↓ 0.3069 0.3237 0.3149 0.2851 3.3501 2.4637 1.2782 0.6370
SN → Q↑ 0.1783 0.1570 0.1584 0.1489 6.4742 4.5377 2.2350 1.0897
CK → QN↑ 0.2531 0.2553 0.2403 0.2160 6.4882 4.7633 2.2400 1.0922
CK → QN↓ 0.3486 0.3136 0.3119 0.2834 3.4363 2.7058 1.2829 0.6396
SN → QN↓ 0.1488 0.1209 0.1100 0.1021 3.4101 2.7045 1.2848 0.6420
211
Process Technology:
SDFFS
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1250 0.1211 0.1211 0.1328
setup↓ → CK 0.3789 0.4141 0.4336 0.4336
SI
hold↑ → CK -0.1094 -0.0977 -0.0977 -0.1055
hold↓ → CK -0.2734 -0.3242 -0.3242 -0.3203
setup↑ → CK 0.4102 0.4492 0.4648 0.4531
setup↓ → CK 0.2266 0.4258 0.4453 0.3711
SE
hold↑ → CK -0.0938 -0.0820 -0.0781 -0.0898
hold↓ → CK -0.1211 -0.1523 -0.1484 -0.1562
setup↑ → CK 0.0820 0.1055 0.1055 0.1172
setup↓ → CK 0.2344 0.4414 0.4609 0.3789
D
hold↑ → CK -0.0703 -0.0859 -0.0820 -0.0898
hold↓ → CK -0.1289 -0.3555 -0.3594 -0.2734
minpwh 0.1189 0.1383 0.1238 0.1140
CK
minpwl 0.2402 0.2111 0.2256 0.2062
minpwl 0.1432 0.1189 0.1238 0.1480
SN recovery -0.0234 -0.0078 -0.0078 0.0078
removal 0.1445 0.1016 0.1094 0.0938
212
Process Technology:
SDFFSHQ

The SDFFSHQ cell is a high-speed, positive-edge
SN
triggered, static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low set (SN). The cell has a single output (Q)
D Q
SI
SE
Functions
CK
SN D SI SE CK Q[n+1]
1 1 x 0 1
Cell Size
1 0 x 0 0
1 x x x Q[n] Drive Strength Height (um) Width (um)
1 x 1 1 1
SDFFSHQXL 5.04 15.84
1 x 0 1 0
SDFFSHQX1 5.04 15.84
0 x x x x 1
cn c
c cn
SI c cn
SE
Q
cn c
D
SN
cn
CK c
213
Process Technology:
SDFFSHQ

Pin Pin
SI 0.0477 0.0543 0.0748 0.1126 SI 0.0023 0.0025 0.0023 0.0023
SE 0.0568 0.0623 0.0800 0.1131 SE 0.0052 0.0046 0.0047 0.0053
D 0.0414 0.0500 0.0677 0.0984 D 0.0029 0.0019 0.0022 0.0032
CK 0.0742 0.0847 0.1108 0.1644 CK 0.0021 0.0028 0.0037 0.0056
SN 0.0102 0.0113 0.0197 0.0315 SN 0.0086 0.0093 0.0145 0.0221
Q 0.0349 0.0333 0.0489 0.0779

Description
CK → Q↑ 0.2619 0.2153 0.1932 0.1677 6.5150 4.5438 2.2382 1.1189
CK → Q↓ 0.3118 0.1836 0.1616 0.1452 4.5246 2.9531 1.4721 0.7458
SN → Q↑ 0.0775 0.0865 0.0872 0.0907 3.6010 2.4627 1.2648 0.6736
214
Process Technology:
SDFFSHQ
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1445 0.1562 0.1758 0.2031
setup↓ → CK 0.3867 0.5273 0.5234 0.5664
SI
hold↑ → CK -0.1094 -0.1055 -0.1172 -0.1328
hold↓ → CK -0.2617 -0.3359 -0.3281 -0.3789
setup↑ → CK 0.4219 0.5508 0.5469 0.5938
setup↓ → CK 0.2344 0.5547 0.4375 0.3516
SE
hold↑ → CK -0.1016 -0.0898 -0.1055 -0.1250
hold↓ → CK -0.1094 -0.1562 -0.1680 -0.1484
setup↑ → CK 0.1016 0.1406 0.1562 0.1406
setup↓ → CK 0.2383 0.5547 0.4453 0.3516
D
hold↑ → CK -0.0742 -0.0898 -0.1016 -0.0820
hold↓ → CK -0.1172 -0.3672 -0.2578 -0.1875
minpwh 0.2062 0.1238 0.1140 0.0946
CK
minpwl 0.2256 0.2111 0.1965 0.1674
minpwl 0.1189 0.1383 0.1674 0.2305
SN recovery -0.0195 0.0547 0.0625 0.0625
removal 0.1445 0.1055 0.1094 0.1055
215
Process Technology:
SDFFSR

The SDFFSR cell is a positive-edge triggered, static
SN
enable (SE), and asynchronous active-low reset
(RN) and set (SN). Set (SN) dominates reset (RN).
D Q
SI QN
Functions SE
CK
RN SN D SI SE CK Q[n+1] QN[n+1]
1 1 1 x 0 1 0
RN
1 1 0 x 0 0 1
1 1 x x x Q[n] QN[n]
1 1 x 1 1 1 0 Cell Size
1 1 x 0 1 0 1
0 1 x x x x 0 1 Drive Strength Height (um) Width (um)
1 0 x x x x 1 0 SDFFSRXL 5.04 19.14
0 0 x x x x 1 0 SDFFSRX1 5.04 19.80
SDFFSRX2 5.04 19.14
SDFFSRX4 5.04 25.74
cn c
c cn
SI c cn
SE
Q
cn c
D QN
RN
SN
cn
CK c
216
Process Technology:
SDFFSR

Pin Pin
SI 0.0462 0.0398 0.0454 0.0588 SI 0.0022 0.0021 0.0021 0.0021
SE 0.0536 0.0468 0.0523 0.0658 SE 0.0047 0.0043 0.0044 0.0049
D 0.0400 0.0344 0.0397 0.0517 D 0.0024 0.0018 0.0019 0.0027
CK 0.0721 0.0672 0.0734 0.0964 CK 0.0025 0.0030 0.0031 0.0040
SN 0.0094 0.0098 0.0132 0.0193 SN 0.0065 0.0069 0.0091 0.0153
RN 0.0192 0.0205 0.0256 0.0444 RN 0.0025 0.0027 0.0038 0.0061
Q 0.0477 0.0553 0.0830 0.1485

Description
CK → Q↑ 0.4498 0.4031 0.3962 0.3672 6.4689 4.5357 2.2653 1.1194
CK → Q↓ 0.3396 0.3515 0.3095 0.2962 3.3686 2.4702 1.3130 0.6376
SN → Q↑ 0.2079 0.1895 0.1759 0.1681 6.4679 4.5350 2.2649 1.1192
SN → Q↓ 0.2057 0.1962 0.1770 0.1668 3.3687 2.4699 1.3127 0.6374
RN → Q↓ 0.3156 0.2913 0.2498 0.2374 3.3688 2.4700 1.3128 0.6374
CK → QN↑ 0.2687 0.2691 0.2322 0.2256 6.5043 4.5452 2.2704 1.1225
CK → QN↓ 0.4120 0.3612 0.3434 0.3192 3.7022 2.5425 1.3444 0.6529
SN → QN↑ 0.1353 0.1146 0.1003 0.0964 6.5289 4.5570 2.2760 1.1261
SN → QN↓ 0.1673 0.1447 0.1229 0.1202 3.4695 2.4910 1.3237 0.6479
RN → QN↑ 0.2449 0.2095 0.1730 0.1669 6.5260 4.5563 2.2758 1.1259
217
Process Technology:
SDFFSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1680 0.1992 0.1797 0.1758
setup↓ → CK 0.3828 0.4414 0.4492 0.4375
SI
hold↑ → CK -0.1367 -0.1445 -0.1367 -0.1367
hold↓ → CK -0.2344 -0.2891 -0.2930 -0.2969
setup↑ → CK 0.4141 0.4688 0.4727 0.4688
setup↓ → CK 0.3047 0.4570 0.4297 0.3164
SE
hold↑ → CK -0.1211 -0.1250 -0.1211 -0.1211
hold↓ → CK -0.1562 -0.1992 -0.1875 -0.1602
setup↑ → CK 0.1211 0.1836 0.1602 0.1328
setup↓ → CK 0.3086 0.4648 0.4336 0.3164
D
hold↑ → CK -0.0938 -0.1250 -0.1172 -0.0977
hold↓ → CK -0.1602 -0.3125 -0.2773 -0.1836
minpwh 0.1238 0.1432 0.1140 0.1140
CK
minpwl 0.2353 0.2450 0.2353 0.1917
minpwl 0.1626 0.1432 0.1383 0.1771
SN recovery 0.0000 0.0117 0.0156 0.0156
removal 0.1328 0.0938 0.1016 0.0977
minpwl 0.2305 0.2111 0.2256 0.3906
RN recovery 0.0625 0.1250 0.0859 0.0625
removal -0.0391 -0.0859 -0.0547 -0.0234
218
Process Technology:
SDFFSRHQ

The SDFFSRHQ cell is a high-speed, positive-edge
SN
triggered, static D-type flip-flop with scan input (SI),
active-high scan enable (SE), and asynchronous
active-low reset (RN) and set (SN), and set
D Q
dominating reset. The cell has a single output (Q)
SI
SE
CK
Functions
RN SN D SI SE CK Q[n+1]
RN
1 1 1 x 0 1
1 1 0 x 0 0
1 1 x x x Q[n] Cell Size
1 1 x 1 1 1
1 1 x 0 1 0
0 1 x x x x 0 SDFFSRHQXL 5.04 19.80
1 0 x x x x 1 SDFFSRHQX1 5.04 19.80
0 0 x x x x 1 SDFFSRHQX2 5.04 25.08
SDFFSRHQX4 5.04 33.66
cn c
c cn
SI c cn
SE
Q
cn c
D
RN
SN
cn
CK c
219
Process Technology:
SDFFSRHQ

Pin Pin
SI 0.0522 0.0585 0.0831 0.1295 SI 0.0021 0.0021 0.0021 0.0022
SE 0.0605 0.0662 0.0884 0.1274 SE 0.0060 0.0054 0.0055 0.0062
D 0.0456 0.0525 0.0743 0.1104 D 0.0029 0.0019 0.0027 0.0045
CK 0.0791 0.0887 0.1228 0.1870 CK 0.0023 0.0029 0.0044 0.0064
SN 0.0130 0.0140 0.0200 0.0333 SN 0.0114 0.0122 0.0174 0.0283
RN 0.0264 0.0310 0.0472 0.0757 RN 0.0025 0.0039 0.0059 0.0102
Q 0.0351 0.0375 0.0568 0.0899

Description
CK → Q↑ 0.2723 0.2258 0.2049 0.1907 9.6066 6.5778 3.2888 1.6441
CK → Q↓ 0.2735 0.1793 0.1681 0.1535 4.3654 2.9376 1.5198 0.7721
SN → Q↑ 0.0854 0.0921 0.0961 0.0948 4.1330 2.8494 1.4621 0.7663
SN → Q↓ 0.0503 0.0550 0.0505 0.0435 3.9355 2.6927 1.4710 0.7689
RN → Q↓ 0.2048 0.1401 0.1206 0.1067 4.0010 2.6928 1.4706 0.7692
220
Process Technology:
SDFFSRHQ
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1875 0.2070 0.2227 0.2656
setup↓ → CK 0.4844 0.4961 0.5352 0.6406
SI
hold↑ → CK -0.1211 -0.1250 -0.1367 -0.1680
hold↓ → CK -0.2578 -0.2930 -0.3281 -0.4375
setup↑ → CK 0.5195 0.5312 0.5664 0.6914
setup↓ → CK 0.3203 0.4531 0.3789 0.3281
SE
hold↑ → CK -0.1055 -0.1094 -0.1211 -0.1602
hold↓ → CK -0.0977 -0.1875 -0.1758 -0.1445
setup↑ → CK 0.1445 0.1875 0.1875 0.1719
setup↓ → CK 0.3242 0.4648 0.3867 0.3320
D
hold↑ → CK -0.0781 -0.1094 -0.1016 -0.0820
hold↓ → CK -0.1016 -0.2656 -0.1914 -0.1523
minpwh 0.1723 0.1238 0.1092 0.0995
CK
minpwl 0.2499 0.2305 0.2062 0.1723
minpwl 0.1383 0.1723 0.2014 0.2693
SN recovery 0.0586 0.0625 0.0703 0.0703
removal 0.1445 0.1055 0.1055 0.1055
minpwl 0.2984 0.2159 0.3324 0.5556
RN recovery 0.1133 0.1250 0.1211 0.1133
removal -0.0312 -0.0430 -0.0234 0.0000
221
Process Technology:
SDFFTR

The SDFFTR cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high scan D Q
enable (SE), and synchronous active-low reset SI QN
(RN). Scan enable (SE) dominates reset (RN).
SE
CK
Functions
RN D SI SE CK Q[n+1] QN[n+1] RN
x x 0 1 0 1
x x 1 1 1 0
0 x x 0 0 1 Cell Size
1 0 x 0 0 1
1 1 x 0 1 0
SDFFTRXL 5.04 14.52
x x x x Q[n] QN[n]
SDFFTRX1 5.04 14.52
SDFFTRX2 5.04 17.16
SDFFTRX4 5.04 19.80
cn c
c cn
SI c cn
SE
QN
cn c
D
RN Q
cn
CK c
222
Process Technology:
SDFFTR

Pin Pin
SI 0.0434 0.0407 0.0523 0.0779 SI 0.0024 0.0024 0.0023 0.0024
SE 0.0524 0.0488 0.0587 0.0812 SE 0.0053 0.0045 0.0046 0.0059
D 0.0369 0.0359 0.0459 0.0648 D 0.0026 0.0019 0.0021 0.0026
CK 0.0661 0.0666 0.0867 0.1275 CK 0.0021 0.0029 0.0039 0.0064
RN 0.0418 0.0398 0.0497 0.0722 RN 0.0029 0.0019 0.0022 0.0042
Q 0.0320 0.0377 0.0674 0.1130

Description
CK → Q↑ 0.2409 0.2130 0.2164 0.1726 6.4752 4.5391 2.2381 1.0917
CK → Q↓ 0.1908 0.1668 0.1609 0.1482 3.2479 2.6466 1.2970 0.6460
CK → QN↑ 0.2389 0.2145 0.2146 0.1980 6.4749 4.5385 2.2355 1.0900
CK → QN↓ 0.3184 0.2942 0.2966 0.2442 3.3877 2.4732 1.2801 0.6377
223
Process Technology:
SDFFTR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1328 0.1250 0.1523 0.1719
setup↓ → CK 0.4180 0.4570 0.4414 0.5312
SI
hold↑ → CK -0.1094 -0.0977 -0.1211 -0.1328
hold↓ → CK -0.2969 -0.3359 -0.3086 -0.4102
setup↑ → CK 0.4453 0.4805 0.4570 0.5391
setup↓ → CK 0.2656 0.4766 0.3867 0.3008
SE
hold↑ → CK -0.1016 -0.0820 -0.1016 -0.1250
hold↓ → CK -0.1484 -0.1914 -0.2031 -0.1641
setup↑ → CK 0.1094 0.1445 0.1719 0.1250
setup↓ → CK 0.2656 0.4805 0.3945 0.2891
D
hold↑ → CK -0.0898 -0.1133 -0.1367 -0.0977
hold↓ → CK -0.1484 -0.3594 -0.2617 -0.1836
minpwh 0.1189 0.1140 0.1189 0.0995
CK
minpwl 0.2450 0.2256 0.2353 0.1674
setup↑ → CK 0.1211 0.1562 0.1797 0.1406
setup↓ → CK 0.3125 0.5469 0.4414 0.3398
RN
hold↑ → CK -0.1016 -0.1250 -0.1445 -0.1094
hold↓ → CK -0.1758 -0.4180 -0.3008 -0.2188
224
Process Technology:
SEDFF

The SEDFF cell is a positive-edge triggered, static
D-type flip-flop with scan input (SI), active-high D Q
scan enable (SE), and synchronous active-high E QN
enable (E). SI
SE
Functions CK
D E SI SE CK Q[n+1] QN[n+1]
x x 1 1 1 0 Cell Size
x x 0 1 0 1
x 0 x 0 Q[n] QN[n] Drive Strength Height (um) Width (um)
0 1 x 0 0 1 SEDFFXL 5.04 17.82
1 1 x 0 1 0 SEDFFX1 5.04 17.82
x x x x Q[n] QN[n] SEDFFX2 5.04 19.80
SEDFFX4 5.04 23.10
cn c
SI c cn
SE c cn
D cn c
QN
E
cn
CK c
225
Process Technology:
SEDFF

Pin Pin
SI 0.0472 0.0488 0.0640 0.0928 SI 0.0021 0.0018 0.0022 0.0034
SE 0.0570 0.0602 0.0745 0.1031 SE 0.0041 0.0040 0.0046 0.0054
D 0.0397 0.0438 0.0558 0.0799 D 0.0021 0.0018 0.0022 0.0033
CK 0.0661 0.0730 0.0917 0.1309 CK 0.0021 0.0029 0.0039 0.0066
E 0.0575 0.0609 0.0734 0.1010 E 0.0051 0.0048 0.0052 0.0061
Q 0.0408 0.0467 0.0770 0.1308

Description
CK → Q↑ 0.2477 0.2266 0.1927 0.1694 6.4741 5.0022 2.2383 1.0921
CK → Q↓ 0.1976 0.1679 0.1546 0.1419 3.4934 2.6528 1.3241 0.6271
CK → QN↑ 0.2807 0.2342 0.2169 0.2020 6.4827 4.5405 2.2367 1.0908
CK → QN↓ 0.3745 0.3279 0.2831 0.2512 3.5069 2.4931 1.3132 0.6203
226
Process Technology:
SEDFF
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1680 0.1562 0.1719 0.1484
setup↓ → CK 0.5156 0.7422 0.5625 0.4414
SI
hold↑ → CK -0.1484 -0.1367 -0.1484 -0.1289
hold↓ → CK -0.4102 -0.6523 -0.4688 -0.3516
setup↑ → CK 0.5273 0.7617 0.5781 0.4648
setup↓ → CK 0.5508 0.7656 0.5781 0.4766
SE
hold↑ → CK -0.1172 -0.1133 -0.1250 -0.1055
hold↓ → CK -0.2422 -0.2344 -0.2461 -0.2305
setup↑ → CK 0.1641 0.1602 0.1719 0.1445
setup↓ → CK 0.5078 0.7188 0.5430 0.4492
D
hold↑ → CK -0.1445 -0.1406 -0.1484 -0.1250
hold↓ → CK -0.4258 -0.6367 -0.4609 -0.3711
minpwh 0.0316 0.0316 0.0316 0.0316
CK
minpwl 0.2839 0.2305 0.2208 0.1820
setup↑ → CK 0.5430 0.7539 0.5820 0.4922
setup↓ → CK 0.4336 0.6406 0.4648 0.3633
E
hold↑ → CK -0.1562 -0.1484 -0.1602 -0.1367
hold↓ → CK -0.2305 -0.2227 -0.2383 -0.2266
227
Process Technology: SEDFFHQ

The SEDFFHQ cell is a positive-edge triggered,
static D-type flip-flop with scan input (SI), active- D Q
high scan enable (SE), and synchronous active- E
high enable (E). The cell has a single output (Q) SI
and fast clock-to-output path. SE
CK
Functions
D E SI SE CK Q[n+1]
Cell Size
x x 1 1 1
x x 0 1 0 Drive Strength Height (um) Width (um)
x 0 x 0 Q[n] SEDFFHQXL 5.04 20.46
0 1 x 0 0 SEDFFHQX1 5.04 20.46
1 1 x 0 1 SEDFFHQX2 5.04 22.44
x x x x Q[n] SEDFFHQX4 5.04 25.08
cn c
SI c cn
SE c cn
D cn c
E
cn
CK c
228

Pin Pin
SI 0.0520 0.0620 0.0798 0.1146 SI 0.0022 0.0021 0.0021 0.0021
SE 0.0724 0.0805 0.0983 0.1331 SE 0.0021 0.0021 0.0021 0.0021
D 0.0728 0.0820 0.1000 0.1348 D 0.0026 0.0029 0.0029 0.0029
CK 0.0606 0.0794 0.1061 0.1597 CK 0.0021 0.0036 0.0046 0.0065
E 0.0957 0.0980 0.1154 0.1471 E 0.0023 0.0023 0.0023 0.0023
Q 0.0343 0.0440 0.0617 0.0879

Description
CK → Q↑ 0.2933 0.1824 0.1727 0.1461 6.4813 4.5365 2.1797 1.0898
CK → Q↓ 0.3527 0.2318 0.2177 0.1960 3.5447 2.4605 1.2788 0.6397
229
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.1016 0.1367 0.1562 0.2031
setup↓ → CK 0.1992 0.2266 0.2305 0.2539
SI
hold↑ → CK -0.0938 -0.1250 -0.1445 -0.1914
hold↓ → CK -0.1875 -0.1953 -0.2031 -0.2188
setup↑ → CK 0.2969 0.3242 0.3477 0.3945
setup↓ → CK 0.3203 0.3203 0.3438 0.3906
SE
hold↑ → CK -0.1641 -0.2031 -0.2227 -0.2500
hold↓ → CK -0.1523 -0.1875 -0.2109 -0.2578
setup↑ → CK 0.1758 0.1836 0.2031 0.2539
setup↓ → CK 0.3242 0.2734 0.2773 0.3008
D
hold↑ → CK -0.1680 -0.1758 -0.1953 -0.2461
hold↓ → CK -0.3047 -0.2383 -0.2461 -0.2656
minpwh 0.0316 0.0316 0.0316 0.0316
CK
minpwl 0.2159 0.1917 0.2014 0.2305
setup↑ → CK 0.3828 0.3828 0.4102 0.4531
setup↓ → CK 0.3477 0.3008 0.3008 0.3281
E
hold↑ → CK -0.2500 -0.2695 -0.2891 -0.3164
hold↓ → CK -0.1211 -0.1484 -0.1836 -0.3008
230
Process Technology:
SEDFFTR

The SEDFFTR cell is a positive-edge triggered,
static D-type flip-flop with scan input (SI), active-high D Q
scan enable (SE), synchronous active-high enable E QN
(E) and synchronous active low reset (RN). Scan SI
enable (SE) dominates reset (RN) and enable (E). SE
CK
Functions
RN D E SI SE CK Q[n+1] QN[n+1] RN
x x x 0 1 0 1
x x x 1 1 1 0
Cell Size
1 x 0 x 0 Q[n] QN[n]
0 x x x 0 0 1 Drive Strength Height (um) Width (um)
1 1 1 x 0 1 0 SEDFFTRXL 5.04 25.08
1 0 1 x 0 0 1 SEDFFTRX1 5.04 25.74
x x x x x Q[n] QN[n] SEDFFTRX2 5.04 26.40
SEDFFTRX4 5.04 27.72
cn c
SI c cn
SE c cn
RN cn c
QN
D
E
cn
CK c
231
Process Technology:
SEDFFTR

Pin Pin
SI 0.0557 0.0691 0.0692 0.0689 SI 0.0023 0.0022 0.0022 0.0022
SE 0.0805 0.0922 0.0923 0.0919 SE 0.0041 0.0041 0.0041 0.0041
D 0.0740 0.0934 0.0935 0.0930 D 0.0020 0.0030 0.0030 0.0030
CK 0.0668 0.0939 0.0939 0.0934 CK 0.0020 0.0037 0.0036 0.0037
E 0.0956 0.1115 0.1114 0.1106 E 0.0021 0.0022 0.0022 0.0022
RN 0.0490 0.0654 0.0655 0.0652 RN 0.0028 0.0028 0.0028 0.0028
Q 0.0464 0.0589 0.0825 0.1396

Description
CK → Q↑ 0.3481 0.2060 0.2268 0.2709 6.4850 4.5376 2.2387 1.0904
CK → Q↓ 0.3845 0.2428 0.2522 0.2730 3.5750 2.4618 1.3167 0.6328
CK → QN↑ 0.2225 0.1734 0.1826 0.2017 6.4920 4.5392 2.2429 1.0953
CK → QN↓ 0.2409 0.1571 0.1797 0.2247 3.7355 2.4972 1.3462 0.6620
232
Process Technology:
SEDFFTR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → CK 0.3008 0.3438 0.3438 0.3164
setup↓ → CK 0.2344 0.2617 0.2617 0.2617
SI
hold↑ → CK -0.1523 -0.2031 -0.2031 -0.1992
hold↓ → CK -0.2148 -0.2266 -0.2266 -0.2266
setup↑ → CK 0.3750 0.4258 0.4219 0.3945
setup↓ → CK 0.4102 0.4180 0.4141 0.3906
SE
hold↑ → CK -0.2266 -0.2695 -0.2656 -0.2656
hold↓ → CK -0.1914 -0.2695 -0.2656 -0.2617
setup↑ → CK 0.3867 0.3789 0.3789 0.3516
setup↓ → CK 0.3516 0.2969 0.2969 0.2969
D
hold↑ → CK -0.2227 -0.2383 -0.2383 -0.2305
hold↓ → CK -0.3281 -0.2617 -0.2578 -0.2578
minpwh 0.1868 0.1043 0.1238 0.1626
CK
minpwl 0.2596 0.2450 0.2499 0.2450
setup↑ → CK 0.4688 0.4688 0.4688 0.4414
setup↓ → CK 0.3711 0.3438 0.3398 0.3320
E
hold↑ → CK -0.3203 -0.3164 -0.3164 -0.3164
hold↓ → CK -0.1172 -0.1406 -0.1641 -0.2812
setup↑ → CK 0.2891 0.3203 0.3164 0.2930
setup↓ → CK 0.2227 0.2500 0.2539 0.2500
RN
hold↑ → CK -0.1250 -0.1719 -0.1719 -0.1680
hold↓ → CK -0.2070 -0.2188 -0.2188 -0.2188
233
Process Technology:
TBUF

The TBUF cell provides the logical buffer of a single
input (A) with an active-high output enable (OE).
A Y
When the enable is high, the output (Y) is
OE
Y = A
Functions Cell Size
OE A Y Drive Strength Height (um) Width (um)

0 x Z TBUFXL 5.04 4.62
1 0 0 TBUFX1 5.04 4.62
1 1 1 TBUFX2 5.04 4.62
TBUFX3 5.04 5.28
TBUFX4 5.04 5.94
TBUFX8 5.04 7.92
TBUFX12 5.04 9.90
TBUFX16 5.04 11.22
TBUFX20 5.04 15.18
A Y
OE
234
Process Technology:
TBUF
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0269 0.0304 0.0401 0.0515 0.0657 0.1152 0.1668 0.2126 0.2733
OE 0.0197 0.0216 0.0284 0.0359 0.0470 0.0817 0.1217 0.1529 0.1988
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0023 0.0024 0.0033 0.0045 0.0059 0.0120 0.0167 0.0200 0.0261
OE 0.0042 0.0044 0.0043 0.0044 0.0048 0.0068 0.0098 0.0123 0.0151
Y 0.0018 0.0023 0.0039 0.0040 0.0054 0.0106 0.0156 0.0203 0.0259

Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑ 0.0960 0.1025 0.1049 0.1029 0.0990 0.0924 0.0840 0.0855 0.0849
A → Y↓ 0.1709 0.1809 0.1567 0.1451 0.1403 0.1260 0.1219 0.1235 0.1215
OE → Y↑ 0.0617 0.0666 0.0747 0.0782 0.0745 0.0733 0.0689 0.0686 0.0689
OE → Y↓ 0.1234 0.1257 0.1188 0.1127 0.1131 0.1053 0.1047 0.1026 0.1034
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑ 6.4822 4.5476 2.3249 1.4934 1.1354 0.5675 0.3643 0.2732 0.2251
A → Y↓ 4.4436 2.5802 1.3442 0.8405 0.6605 0.3446 0.2352 0.1767 0.1366
OE → Y↑ 6.4781 4.5443 2.3241 1.4930 1.1349 0.5673 0.3641 0.2731 0.2250
OE → Y↓ 4.4393 2.5744 1.3398 0.8375 0.6588 0.3438 0.2348 0.1763 0.1363
235
Process Technology:
TBUFI

The TBUFI cell provides the logical inversion of a
single input (A) with an active-high output enable
A Y
(OE). When the enable is high, the output (Y) is
OE
Y = A Cell Size
Functions Drive Strength Height (um) Width (um)

TBUFIXL 5.04 2.64
OE A Y
TBUFIX1 5.04 2.64
0 x Z TBUFIX2 5.04 3.96
1 0 1 TBUFIX3 5.04 6.60
1 1 0 TBUFIX4 5.04 6.60
TBUFIX8 5.04 8.58
TBUFIX12 5.04 11.22
TBUFIX16 5.04 12.54
TBUFIX20 5.04 16.50
A Y
OE
236
Process Technology:
TBUFI
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0244 0.0241 0.0443 0.0532 0.0644 0.1136 0.1715 0.2216 0.2763
OE 0.0155 0.0154 0.0953 0.0371 0.0442 0.0833 0.1246 0.1613 0.2026
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X3 X4 X8 X12 X16 X20
A 0.0047 0.0046 0.0093 0.0022 0.0027 0.0048 0.0066 0.0085 0.0105
OE 0.0030 0.0029 0.0041 0.0044 0.0047 0.0070 0.0098 0.0122 0.0152
Y 0.0029 0.0029 0.0039 0.0041 0.0049 0.0105 0.0159 0.0212 0.0265

Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑ 0.0624 0.0623 0.0569 0.1945 0.1817 0.1599 0.1549 0.1502 0.1510
A → Y↓ 0.0305 0.0313 0.0281 0.1886 0.1752 0.1633 0.1625 0.1598 0.1580
OE → Y↑ 0.0644 0.0649 0.0651 0.0799 0.0801 0.0721 0.0705 0.0700 0.0704
OE → Y↓ 0.0195 0.0201 0.0172 0.1156 0.1090 0.1075 0.1058 0.1042 0.1038
Kload (ns/pF)
Description
XL X1 X2 X3 X4 X8 X12 X16 X20
A → Y↑ 6.5802 6.5689 3.2854 1.4721 1.1556 0.5878 0.3646 0.2734 0.2252
A → Y↓ 2.8431 2.9005 1.4509 0.8434 0.6634 0.3124 0.2231 0.1662 0.1284
OE → Y↑ 6.5955 6.5762 3.2894 1.4706 1.1548 0.5874 0.3643 0.2732 0.2251
OE → Y↓ 2.8411 2.8989 1.4506 0.8401 0.6613 0.3116 0.2226 0.1658 0.1281
237
Process Technology:
TIEHI

The TIEHI cell drives the output (Y) to a logic high.
The output is driven through diffusion and not tied
directly to the power rail to provide some ESD
protection. The output (Y) is represented by the logic
equation:
Y = 1 Y
Function
Cell Size
Y
1
TIEHI 5.04 1.32
X1
238
Process Technology:
TIELO

The TIELO cell drives the output (Y) to a logic low.
Y
The output is driven through diffusion and not tied
directly to the power rail to provide some ESD
protection. The output (Y) is represented by the logic
equation:
Y = 0
Function
Cell Size
Y
0
TIELO 5.04 1.32
X1
239
Process Technology:
TLAT

The TLAT cell is an active-high D-type transparent
latch. When the enable (G) is high, data is transferred
to the outputs (Q, QN). D Q
G QN
Functions
G D Q[n+1] QN[n+1]
1 0 0 1
Cell Size
1 1 1 0
0 x Q[n] QN[n] Drive Strength Height (um) Width (um)
TLATXL 5.04 7.26
TLATX1 5.04 7.26
TLATX2 5.04 7.92
TLATX4 5.04 11.22
g
gn
gn
D QN
g
Q
gn
G g
240
Process Technology:
TLAT

Pin Pin
D 0.0049 0.0060 0.0098 0.0213 D 0.0034 0.0041 0.0061 0.0139
G 0.0226 0.0242 0.0283 0.0474 G 0.0019 0.0025 0.0027 0.0044
Q 0.0341 0.0407 0.0650 0.1115

Description
D → Q↑ 0.0913 0.0901 0.0850 0.0755 6.4803 4.5418 2.2659 1.1311
D → Q↓ 0.1555 0.1554 0.1434 0.1313 3.4687 2.5051 1.2980 0.6459
G → Q↑ 0.1978 0.1884 0.1990 0.1656 6.4798 4.5419 2.2659 1.1310
G → Q↓ 0.1660 0.1637 0.1617 0.1474 3.4661 2.5041 1.2979 0.6456
D → QN↑ 0.2062 0.2099 0.2112 0.2005 6.4781 4.5397 2.2631 1.1302
D → QN↓ 0.1754 0.1786 0.1864 0.1714 3.4000 2.4783 1.2881 0.6422
G → QN↑ 0.2173 0.2188 0.2299 0.2168 6.4778 4.5400 2.2633 1.1303
G → QN↓ 0.2831 0.2780 0.3012 0.2620 3.4004 2.4784 1.2879 0.6421
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → G -0.0273 -0.0117 -0.0273 -0.0234
setup↓ → G 0.0898 0.1016 0.0859 0.0781
D
hold↑ → G 0.0391 0.0273 0.0430 0.0391
hold↓ → G -0.0859 -0.0938 -0.0820 -0.0703
G minpwh 0.1092 0.1140 0.1092 0.0995
241
Process Technology:
TLATN

The TLATN cell is an active-low D-type transparent
latch. When the enable (GN) is low, data is
transferred to the outputs (Q, QN). D Q
GN QN
Functions
GN D Q[n+1] QN[n+1]
0 0 0 1
Cell Size
0 1 1 0
1 x Q[n] QN[n] Drive Strength Height (um) Width (um)
TLATNXL 5.04 7.26
TLATNX1 5.04 7.26
TLATNX2 5.04 7.92
TLATNX4 5.04 11.22
g
gn
gn
D QN
g
Q
GN gn
242
Process Technology:
TLATN

Pin Pin
D 0.0050 0.0061 0.0095 0.0210 D 0.0034 0.0041 0.0062 0.0139
GN 0.0263 0.0294 0.0368 0.0633 GN 0.0020 0.0025 0.0026 0.0043
Q 0.0352 0.0423 0.0689 0.1160

Description
D → Q↑ 0.0903 0.0864 0.0840 0.0735 6.4822 4.5414 2.2394 1.1311
D → Q↓ 0.1555 0.1512 0.1458 0.1326 3.4683 2.5017 1.2991 0.6459
GN → Q↑ 0.1702 0.1448 0.1498 0.1214 6.4845 4.5425 2.2401 1.1313
GN → Q↓ 0.2665 0.2445 0.2477 0.2224 3.4672 2.5015 1.2989 0.6459
D → QN↑ 0.2062 0.2070 0.2145 0.2020 6.4786 4.5388 2.2366 1.1303
D → QN↓ 0.1746 0.1768 0.1873 0.1697 3.3991 2.4791 1.2884 0.6422
GN → QN↑ 0.3176 0.3006 0.3165 0.2917 6.4789 4.5395 2.2365 1.1303
GN → QN↓ 0.2562 0.2368 0.2549 0.2185 3.3997 2.4796 1.2884 0.6422
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → GN 0.0508 0.0547 0.0547 0.0469
setup↓ → GN 0.0547 0.0625 0.0430 0.0352
D
hold↑ → GN -0.0469 -0.0430 -0.0430 -0.0352
hold↓ → GN -0.0430 -0.0430 -0.0312 -0.0234
GN minpwl 0.1723 0.1577 0.1529 0.1335
243
Process Technology:
TLATNR

The TLATNR cell is an active-low D-type transparent
latch with asynchronous active-low reset (RN).
When the enable (GN) is low, data is transferred to D Q
the outputs (Q, QN).
GN QN
Functions
RN GN D Q[n+1] QN[n+1] RN
1 0 0 0 1
1 0 1 1 0
1 1 x Q[n] QN[n] Cell Size
0 x x 0 1
TLATNRXL 5.04 8.58
TLATNRX1 5.04 8.58
TLATNRX2 5.04 9.24
TLATNRX4 5.04 11.88
g
r
gn
D gn
g Q
r
QN
GN gn
RN r
244
Process Technology:
TLATNR

Pin Pin
D 0.0034 0.0042 0.0073 0.0145 D 0.0026 0.0031 0.0053 0.0101
GN 0.0287 0.0308 0.0404 0.0650 GN 0.0020 0.0020 0.0024 0.0038
RN 0.0043 0.0045 0.0050 0.0063 RN 0.0043 0.0045 0.0053 0.0072
Q 0.0405 0.0476 0.0750 0.1309

Description
D → Q↑ 0.1357 0.1294 0.1179 0.1125 6.5181 4.5570 2.2463 1.0957
D → Q↓ 0.2386 0.2300 0.2011 0.1880 3.6660 2.5749 1.3200 0.6565
GN → Q↑ 0.2207 0.2164 0.1894 0.1703 6.5182 4.5571 2.2469 1.0962
GN → Q↓ 0.3546 0.3493 0.3095 0.2928 3.6653 2.5747 1.3200 0.6565
RN → Q↑ 0.1331 0.1255 0.1104 0.1038 6.5183 4.5567 2.2463 1.0958
RN → Q↓ 0.1616 0.1847 0.2713 0.4411 3.5252 2.5622 1.3952 0.7706
D → QN↑ 0.2961 0.2908 0.2717 0.2609 6.4783 4.5410 2.2366 1.0909
D → QN↓ 0.2300 0.2282 0.2240 0.2169 3.4220 2.4888 1.2896 0.6432
GN → QN↑ 0.4127 0.4109 0.3805 0.3659 6.4786 4.5405 2.2366 1.0909
GN → QN↓ 0.3170 0.3172 0.2971 0.2759 3.4255 2.4901 1.2899 0.6433
RN → QN↑ 0.2193 0.2451 0.3454 0.5329 6.4791 4.5408 2.2364 1.0909
RN → QN↓ 0.2280 0.2250 0.2169 0.2085 3.4228 2.4890 1.2896 0.6432
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → GN 0.1016 0.0938 0.0820 0.0781
setup↓ → GN 0.1406 0.1289 0.0859 0.0703
D
hold↑ → GN -0.0898 -0.0820 -0.0703 -0.0664
hold↓ → GN -0.1250 -0.1172 -0.0781 -0.0625
GN minpwl 0.2596 0.2548 0.2014 0.1820
minpwl 0.1577 0.1771 0.2402 0.3664
RN
recovery 0.0977 0.0898 0.0703 0.0664
245
Process Technology:
TLATNS

The TLATNS cell is an active-low D-type transparent
SN
latch with asynchronous active-low set (SN). When
the enable (GN) is low, data is transferred to the
outputs (Q, QN).
D Q
Functions
GN QN
SN GN D Q[n+1] QN[n+1]
1 0 0 0 1
1 0 1 1 0
Cell Size
1 1 x Q[n] QN[n]
TLATNSXL 5.04 10.56
TLATNSX1 5.04 10.56
TLATNSX2 5.04 11.22
TLATNSX4 5.04 13.86
g
sn
gn
D gn
g Q
sn
QN
GN gn
SN sn
246
Process Technology:
TLATNS

Pin Pin
D 0.0039 0.0047 0.0078 0.0140 D 0.0028 0.0033 0.0051 0.0092
GN 0.0271 0.0304 0.0353 0.0511 GN 0.0022 0.0028 0.0029 0.0040
SN 0.0151 0.0154 0.0168 0.0234 SN 0.0019 0.0019 0.0025 0.0036
Q 0.0552 0.0610 0.0913 0.1456

Description
D → Q↑ 0.1425 0.1315 0.1164 0.1100 6.5195 4.5588 2.2446 1.0953
D → Q↓ 0.3195 0.3049 0.2664 0.2463 3.7803 2.7685 1.3634 0.6759
GN → Q↑ 0.2373 0.1973 0.1831 0.1619 6.5175 4.5602 2.2464 1.0963
GN → Q↓ 0.4309 0.3953 0.3614 0.3206 3.7795 2.7686 1.3635 0.6759
SN → Q↑ 0.2123 0.2254 0.2479 0.3233 6.4792 4.5461 2.2472 1.1052
SN → Q↓ 0.3541 0.3390 0.2934 0.2704 3.7805 2.7686 1.3635 0.6759
D → QN↑ 0.4014 0.3766 0.3421 0.3208 6.4737 4.5402 2.2373 1.0910
D → QN↓ 0.2542 0.2578 0.2309 0.2134 3.2208 2.5059 1.2934 0.6431
GN → QN↑ 0.5138 0.4679 0.4376 0.3954 6.4741 4.5404 2.2373 1.0910
GN → QN↓ 0.3512 0.3261 0.3000 0.2672 3.2214 2.5059 1.2935 0.6431
SN → QN↑ 0.4365 0.4111 0.3693 0.3450 6.4740 4.5404 2.2374 1.0910
SN → QN↓ 0.3232 0.3505 0.3655 0.4368 3.2154 2.5046 1.2938 0.6443
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → GN 0.1172 0.1094 0.0859 0.0820
setup↓ → GN 0.2266 0.1953 0.1484 0.1328
D
hold↑ → GN -0.1133 -0.1055 -0.0820 -0.0742
hold↓ → GN -0.1875 -0.1602 -0.1250 -0.1172
GN minpwl 0.3421 0.2936 0.2499 0.2111
minpwl 0.1820 0.1917 0.1965 0.2402
SN
recovery 0.2617 0.2305 0.1758 0.1602
247
Process Technology:
TLATNSR

The TLATNSR cell is an active-low D-type
SN
transparent latch with asynchronous active-low set
(SN) and reset (RN), and set dominating reset. When
the enable (GN) is low, data is transferred to the
outputs (Q, QN). D Q
Functions GN QN
RN SN GN D Q[n+1] QN[n+1]
1 1 0 0 0 1 RN
1 1 0 1 1 0
1 1 1 x Q[n] QN[n]
0 1 x x 0 1 Cell Size
1 0 x x 1 0
0 0 x x 1 0
TLATNSRXL 5.04 11.22
TLATNSRX1 5.04 11.22
g
sn
gn
r
D gn
r Q
sn
QN
RN r
SN sn
g
GN gn
248
Process Technology:
TLATNSR

Pin Pin
D 0.0037 0.0045 0.0077 0.0158 D 0.0029 0.0034 0.0052 0.0111
GN 0.0288 0.0321 0.0400 0.0712 GN 0.0021 0.0027 0.0030 0.0041
SN 0.0168 0.0189 0.0251 0.0464 SN 0.0019 0.0025 0.0038 0.0066
RN 0.0047 0.0055 0.0091 0.0170 RN 0.0041 0.0045 0.0062 0.0111
Q 0.0606 0.0685 0.1053 0.1789

Description
D → Q↑ 0.1830 0.1703 0.1697 0.1544 6.5655 4.5768 2.2550 1.0993
D → Q↓ 0.3674 0.3532 0.3157 0.2932 4.1826 2.8579 1.4112 0.6977
GN → Q↑ 0.2697 0.2252 0.2230 0.1971 6.5648 4.5773 2.2551 1.0996
GN → Q↓ 0.4643 0.4270 0.3968 0.3703 4.1837 2.8580 1.4112 0.6978
SN → Q↑ 0.2434 0.2185 0.1869 0.1811 6.5009 4.5539 2.2433 1.0946
SN → Q↓ 0.4046 0.3857 0.3415 0.3219 4.1706 2.8524 1.4083 0.6962
RN → Q↑ 0.1776 0.1651 0.1647 0.1496 6.5660 4.5765 2.2551 1.0993
RN → Q↓ 0.2737 0.2601 0.2245 0.2049 4.0489 2.8125 1.3872 0.6878
D → QN↑ 0.4492 0.4289 0.3925 0.3680 6.4754 4.5405 2.2370 1.0909
D → QN↓ 0.3013 0.3024 0.2842 0.2602 3.4521 2.5087 1.2923 0.6435
GN → QN↑ 0.5472 0.5038 0.4743 0.4455 6.4757 4.5408 2.2371 1.0910
GN → QN↓ 0.3902 0.3595 0.3390 0.3040 3.4554 2.5099 1.2929 0.6436
SN → QN↑ 0.4862 0.4614 0.4179 0.3961 6.4761 4.5408 2.2372 1.0910
SN → QN↓ 0.3610 0.3482 0.2991 0.2851 3.4425 2.5060 1.2912 0.6430
RN → QN↑ 0.3528 0.3326 0.2968 0.2744 6.4730 4.5413 2.2373 1.0911
RN → QN↓ 0.2966 0.2979 0.2797 0.2556 3.4530 2.5089 1.2925 0.6435
249
Process Technology:
TLATNSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → GN 0.1562 0.1484 0.1367 0.1211
setup↓ → GN 0.2852 0.2578 0.2070 0.1719
D
hold↑ → GN -0.1445 -0.1367 -0.1250 -0.1133
hold↓ → GN -0.2383 -0.2188 -0.1758 -0.1484
GN minpwl 0.3858 0.3372 0.2936 0.2548
minpwl 0.2111 0.1868 0.1480 0.1383
SN recovery 0.3203 0.2891 0.2305 0.1992
removal -0.3164 -0.2852 -0.2266 -0.1953
minpwl 0.2742 0.2450 0.1917 0.1577
RN recovery 0.1523 0.1445 0.1328 0.1133
removal -0.1484 -0.1406 -0.1289 -0.1094
250
Process Technology:
TLATR

The TLATR cell is an active-high D-type transparent
latch with asynchronous active-low reset (RN).
When the enable (G) is high, data is transferred to D Q
the outputs (Q, QN).
G QN
Functions
RN G D Q[n+1] QN[n+1] RN
1 1 0 0 1
1 1 1 1 0
1 0 x Q[n] QN[n] Cell Size
0 x x 0 1
TLATRXL 5.04 8.58
TLATRX1 5.04 8.58
TLATRX2 5.04 9.24
TLATRX4 5.04 11.88
g
r
gn
D gn
g Q
r
QN
gn
G g
RN r
251
Process Technology:
TLATR

Pin Pin
D 0.0033 0.0041 0.0073 0.0145 D 0.0026 0.0031 0.0052 0.0101
G 0.0281 0.0285 0.0329 0.0557 G 0.0020 0.0021 0.0024 0.0040
RN 0.0043 0.0042 0.0052 0.0064 RN 0.0042 0.0043 0.0054 0.0072
Q 0.0383 0.0450 0.0739 0.1282

Description
D → Q↑ 0.1389 0.1316 0.1188 0.1148 6.5188 4.5580 2.2465 1.0958
D → Q↓ 0.2416 0.2318 0.2009 0.1874 3.6767 2.5789 1.3206 0.6567
G → Q↑ 0.2537 0.2405 0.2417 0.2355 6.5176 4.5575 2.2463 1.0958
G → Q↓ 0.2441 0.2379 0.2160 0.1977 3.6732 2.5777 1.3221 0.6582
RN → Q↑ 0.1349 0.1265 0.1113 0.1059 6.5193 4.5579 2.2464 1.0959
RN → Q↓ 0.1630 0.1849 0.2718 0.4415 3.5290 2.5657 1.3962 0.7712
D → QN↑ 0.2985 0.2928 0.2723 0.2604 6.4776 4.5410 2.2367 1.0909
D → QN↓ 0.2328 0.2307 0.2259 0.2191 3.4234 2.4887 1.2899 0.6432
G → QN↑ 0.3023 0.3001 0.2888 0.2724 6.4777 4.5408 2.2367 1.0909
G → QN↓ 0.3496 0.3413 0.3502 0.3408 3.4267 2.4899 1.2903 0.6433
RN → QN↑ 0.2202 0.2455 0.3469 0.5333 6.4770 4.5408 2.2365 1.0910
RN → QN↓ 0.2295 0.2262 0.2189 0.2105 3.4240 2.4889 1.2900 0.6432
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → G 0.0195 0.0195 -0.0078 -0.0078
setup↓ → G 0.1836 0.1758 0.1445 0.1328
D
hold↑ → G 0.0039 0.0078 0.0273 0.0234
hold↓ → G -0.1797 -0.1719 -0.1367 -0.1289
G minpwh 0.1917 0.1868 0.1626 0.1480
minpwl 0.1577 0.1771 0.2402 0.3664
RN
recovery 0.0117 0.0039 -0.0195 -0.0234
252
Process Technology:
TLATS

The TLATS cell is an active-high D-type transparent
SN
latch with asynchronous active-low set (SN). When
the enable (G) is high, data is transferred to the
outputs (Q, QN).
D Q
Functions
G QN
SN G D Q[n+1] QN[n+1]
1 1 0 0 1
1 1 1 1 0
Cell Size
1 0 x Q[n] QN[n]
TLATSXL 5.04 10.56
TLATSX1 5.04 10.56
TLATSX2 5.04 11.22
TLATSX4 5.04 13.86
g
sn
gn
D gn
g Q
sn
QN
gn
G g
SN sn
253
Process Technology:
TLATS

Pin Pin
D 0.0039 0.0048 0.0079 0.0140 D 0.0028 0.0033 0.0052 0.0092
G 0.0285 0.0293 0.0310 0.0402 G 0.0023 0.0028 0.0029 0.0041
SN 0.0151 0.0153 0.0167 0.0232 SN 0.0019 0.0019 0.0025 0.0036
Q 0.0516 0.0563 0.0857 0.1388

Description
D → Q↑ 0.1432 0.1326 0.1189 0.1120 6.5213 4.5597 2.2447 1.0953
D → Q↓ 0.3177 0.3035 0.2658 0.2447 3.7768 2.8420 1.3629 0.6757
G → Q↑ 0.2712 0.2586 0.2450 0.2189 6.5186 4.5589 2.2443 1.0952
G → Q↓ 0.2984 0.2811 0.2561 0.2350 3.7752 2.8409 1.3619 0.6754
SN → Q↑ 0.2121 0.2235 0.2475 0.3230 6.4790 4.5473 2.2473 1.1052
SN → Q↓ 0.3524 0.3371 0.2922 0.2693 3.7768 2.8421 1.3630 0.6757
D → QN↑ 0.4002 0.3739 0.3397 0.3193 6.4744 4.5401 2.2371 1.0910
D → QN↓ 0.2557 0.2593 0.2316 0.2155 3.2207 2.5053 1.2927 0.6431
G → QN↑ 0.3820 0.3525 0.3305 0.3097 6.4745 4.5405 2.2372 1.0910
G → QN↓ 0.3853 0.3871 0.3588 0.3231 3.2208 2.5051 1.2927 0.6430
SN → QN↑ 0.4353 0.4078 0.3664 0.3440 6.4747 4.5406 2.2372 1.0910
SN → QN↓ 0.3241 0.3490 0.3633 0.4366 3.2149 2.5040 1.2931 0.6443
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → G 0.0000 0.0156 -0.0156 -0.0156
setup↓ → G 0.2539 0.2383 0.1953 0.1758
D
hold↑ → G 0.0117 -0.0078 0.0273 0.0234
hold↓ → G -0.2461 -0.2305 -0.1875 -0.1680
G minpwh 0.2402 0.2208 0.1917 0.1723
minpwl 0.1820 0.1917 0.1965 0.2402
SN
recovery 0.2891 0.2734 0.2227 0.2031
254
Process Technology:
TLATSR

The TLATSR cell is an active-high D-type
SN
transparent latch with asynchronous active-low set
(SN) and reset (RN), and set dominating reset. When
the enable (G) is high, data is transferred to the
outputs (Q, QN). D Q
Functions G QN
RN SN G D Q[n+1] QN[n+1]
1 1 1 0 0 1 RN
1 1 1 1 1 0
1 1 0 x Q[n] QN[n]
0 1 x x 0 1 Cell Size
1 0 x x 1 0
0 0 x x 1 0
TLATSRXL 5.04 11.22
TLATSRX1 5.04 11.22
TLATSRX2 5.04 11.88
TLATSRX4 5.04 16.50
g
sn
gn
r
D gn
r Q
sn
QN
RN r
SN sn
gn
G g
255
Process Technology:
TLATSR

Pin Pin
D 0.0037 0.0045 0.0077 0.0158 D 0.0029 0.0034 0.0052 0.0111
G 0.0305 0.0314 0.0337 0.0583 G 0.0021 0.0027 0.0029 0.0041
SN 0.0169 0.0190 0.0252 0.0466 SN 0.0019 0.0025 0.0038 0.0067
RN 0.0045 0.0053 0.0090 0.0170 RN 0.0040 0.0045 0.0062 0.0111
Q 0.0584 0.0661 0.1021 0.1735

Description
D → Q↑ 0.1832 0.1724 0.1709 0.1561 6.5665 4.5776 2.2550 1.0994
D → Q↓ 0.3692 0.3556 0.3154 0.2919 4.1867 2.8620 1.4112 0.6976
G → Q↑ 0.2966 0.2801 0.2764 0.2524 6.5628 4.5765 2.2545 1.0992
G → Q↓ 0.3725 0.3506 0.3124 0.2842 4.1894 2.8627 1.4110 0.6975
SN → Q↑ 0.2440 0.2199 0.1870 0.1789 6.5004 4.5544 2.2433 1.0947
SN → Q↓ 0.4064 0.3882 0.3414 0.3205 4.1747 2.8568 1.4083 0.6961
RN → Q↑ 0.1776 0.1668 0.1657 0.1513 6.5657 4.5774 2.2550 1.0994
RN → Q↓ 0.2746 0.2620 0.2246 0.2048 4.0544 2.8158 1.3873 0.6877
D → QN↑ 0.4506 0.4306 0.3926 0.3667 6.4752 4.5404 2.2369 1.0910
D → QN↓ 0.3012 0.3039 0.2858 0.2619 3.4518 2.5086 1.2925 0.6435
G → QN↑ 0.4553 0.4270 0.3904 0.3594 6.4757 4.5408 2.2372 1.0910
G → QN↓ 0.4165 0.4137 0.3926 0.3590 3.4545 2.5098 1.2928 0.6436
SN → QN↑ 0.4876 0.4632 0.4181 0.3948 6.4758 4.5406 2.2373 1.0910
SN → QN↓ 0.3609 0.3491 0.2995 0.2830 3.4419 2.5058 1.2912 0.6431
RN → QN↑ 0.3534 0.3338 0.2973 0.2745 6.4727 4.5410 2.2374 1.0911
RN → QN↓ 0.2963 0.2990 0.2810 0.2573 3.4523 2.5087 1.2926 0.6435
256
Process Technology:
TLATSR
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → G 0.0508 0.0703 0.0430 0.0234
setup↓ → G 0.2969 0.2891 0.2461 0.2227
D
hold↑ → G -0.0195 -0.0391 -0.0195 -0.0078
hold↓ → G -0.2852 -0.2773 -0.2344 -0.2109
G minpwh 0.3033 0.2887 0.2450 0.2208
minpwl 0.2111 0.1868 0.1480 0.1383
SN recovery 0.3359 0.3203 0.2695 0.2500
removal -0.3320 -0.3164 -0.2656 -0.2461
minpwl 0.2742 0.2450 0.1917 0.1577
RN recovery 0.0391 0.0625 0.0312 0.0117
removal -0.0352 -0.0586 -0.0273 -0.0078
257
Process Technology: TTLAT

The TTLAT cell is an active-high D-type transparent
latch with active-high output enable (OE). When the
enable (G) is high and the output enable (OE) is high, D Q
data is transferred to the output (Q).
G
Functions
OE G D Q[n+1] OE
0 x x Z
Cell Size
1 1 0 0
1 0 x Q[n]
TTLATXL 5.04 8.58
TTLATX1 5.04 8.58
TTLATX2 5.04 12.54
TTLATX4 5.04 15.18
g
gn
gn
g
Q
OE
gn
G g
258
Process Technology: TTLAT

Pin Pin
D 0.0051 0.0096 0.0176 0.0177 D 0.0036 0.0054 0.0113 0.0112
G 0.0263 0.0273 0.0435 0.0568 G 0.0021 0.0026 0.0040 0.0066
OE 0.0355 0.0638 0.1155 0.1854 OE 0.0027 0.0038 0.0058 0.0101
Q 0.0326 0.0576 0.1039 0.1678 Q 0.0019 0.0042 0.0052 0.0099

Description
D → Q↑ 0.1233 0.1082 0.1093 0.1200 8.6321 2.6787 1.4031 0.7204
D → Q↓ 0.1863 0.1566 0.1536 0.1864 5.3520 1.7351 0.8614 0.4832
G → Q↑ 0.2345 0.2177 0.2152 0.1901 8.6389 2.6798 1.4037 0.7206
G → Q↓ 0.2078 0.1747 0.1716 0.1959 5.3462 1.7342 0.8608 0.4828
OE → Q↑ 0.0289 0.0234 0.0172 0.0224 8.5478 2.6371 1.3832 0.7097
OE → Q↓ 0.0183 0.0178 0.0140 0.0165 5.2508 1.6911 0.8401 0.4688
Interval (ns)
Pin Requirement
XL X1 X2 X4
setup↑ → G -0.0312 -0.0312 -0.0312 0.0039
setup↓ → G 0.1055 0.0820 0.0820 0.1211
D
hold↑ → G 0.0469 0.0430 0.0430 0.0078
hold↓ → G -0.0859 -0.0664 -0.0703 -0.1055
G minpwh 0.1286 0.1043 0.1043 0.1335
259
Process Technology:
XNOR2

The XNOR2 cell provides a logical EXCLUSIVE
NOR of two inputs (A, B). The output (Y) is A
Y
represented by the logic equation: B
Y = ( A • B) + ( A • B)
Functions Cell Size
0 0 1 XNOR2XL 5.04 5.28

0 1 0 XNOR2X1 5.04 5.28
1 0 0 XNOR2X2 5.04 7.26
1 1 1 XNOR2X4 5.04 11.22
260
Process Technology:
XNOR2

Pin Pin
A 0.0377 0.0402 0.0701 0.1197 A 0.0062 0.0059 0.0089 0.0153
B 0.0419 0.0551 0.1045 0.1999 B 0.0022 0.0065 0.0137 0.0261

Description
A → Y↑ 0.1435 0.1407 0.1458 0.1235 6.4832 4.5406 2.2368 1.1882
A → Y↓ 0.1382 0.1209 0.1076 0.1071 3.5937 2.5001 1.2894 0.6006
B → Y↑ 0.1980 0.1262 0.1129 0.1126 6.4898 4.5420 2.2372 1.1883
B → Y↓ 0.2109 0.1485 0.1315 0.1296 3.5827 2.5086 1.2937 0.6029
261
Process Technology:
XOR2

The XOR2 cell provides a logical EXCLUSIVE OR
of two inputs (A, B). The output (Y) is represented A
Y
by the logic equation: B
Y = ( A • B) + ( A • B)
Functions Cell Size
0 0 0 XOR2XL 5.04 5.28

0 1 1 XOR2X1 5.04 5.28
1 0 1 XOR2X2 5.04 6.60
1 1 0 XOR2X4 5.04 11.22
262
Process Technology:
XOR2
AC Power
Power (µW/MHz)
Pin
XL X1 X2 X4
A 0.0366 0.0376 0.0652 0.1107
B 0.0399 0.0520 0.0985 0.1885
Pin Capacitance
Capacitance (pF)
Pin
XL X1 X2 X4
A 0.0062 0.0058 0.0088 0.0163
B 0.0023 0.0064 0.0138 0.0261

Description
XL X1 X2 X4
A → Y↑ 0.1436 0.1292 0.1337 0.1089
A → Y↓ 0.1402 0.1214 0.1200 0.1112
B → Y↑ 0.1904 0.1233 0.1119 0.1066
B → Y↓ 0.2001 0.1485 0.1343 0.1305
Kload (ns/pF)
Description
XL X1 X2 X4
A → Y↑ 6.4853 4.5360 2.2348 1.1867
A → Y↓ 3.3273 2.5078 1.2937 0.6021
B → Y↑ 6.4861 4.5420 2.2370 1.1881
B → Y↓ 3.3280 2.5083 1.2934 0.6021
263
Synthesis Optimized Arithmetic Cells
264
Process Technology: AFCSHCIN

The AFCSHCIN cell provides a carry-select adder
function that produces the arithmetic sum (S) and A
carry-outs (CO0, CO1) of the operands (A, B) with
B S
active-low carry-ins (CI0N, CI1N).The three outputs
(S, CO0, CO1) are represented by the logic CI0N CO0
equations:
CI1N CO1
S = CS • ( A ⊕ B ⊕ CI 1N ) + CS • ( A ⊕ B ⊕ CI 0N )
CS
CO0 = ( A • B ) + ( A • CI 0N ) + ( B • CI 0N )
CO1 = ( A • B ) + ( A • CI 1N ) + ( B • CI 1N )
Cell Size

AFCSHCINX2 5.04 33.00
AFCSHCINX4 5.04 38.28
A
B 1
S
0
CS
CO1
CO0
CI1N
CI0N
265

Pin Pin
X2 X4 X2 X4
CS 0.0677 0.0677 CS 0.0058 0.0058
A 0.3302 0.3667 A 0.0073 0.0073
B 0.3040 0.3400 B 0.0170 0.0170
CI0N 0.1343 0.1703 CI0N 0.0084 0.0140
CI1N 0.1363 0.1692 CI1N 0.0082 0.0136
Functions Functions (cont.)
A B CI0N CI1N CS S CO0 CO1 A B CI0N CI1N CS S CO0 CO1

0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0
0 0 0 1 1 0 0 0 1 0 0 1 1 1 1 0
0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1
0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1
0 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0
0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0
0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1
0 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1
0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1
0 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 1 0 1 1 1 1 0 0 0 1 1
0 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1
0 1 1 1 0 1 0 0 1 1 1 1 0 0 1 1
0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1
266

Description
X2 X4 X2 X4
CS → S↑ 0.1458 0.1467 2.2380 2.2334
CS → S↓ 0.1215 0.1245 1.2963 1.2754
A → S↑ 0.4383 0.4681 2.2388 2.2341
A → S↓ 0.4080 0.4323 1.2986 1.2760
B → S↑ 0.3625 0.3879 2.2388 2.2339
B → S↓ 0.3501 0.3765 1.2989 1.2765
CI0N → S↑ 0.2649 0.2720 2.2389 2.2339
CI0N → S↓ 0.2901 0.2959 1.2991 1.2764
CI1N → S↑ 0.2345 0.2309 2.2380 2.2336
CI1N → S↓ 0.2711 0.2659 1.2965 1.2756
A → CO0↑ 0.2091 0.2412 3.0365 2.9807
A → CO0↓ 0.2585 0.3139 1.6674 1.6315
B → CO0↑ 0.1695 0.1995 2.9591 2.9740
B → CO0↓ 0.1979 0.2431 1.6423 1.6225
CI0N → CO0↑ 0.0775 0.0614 3.0628 1.5583
CI0N → CO0↓ 0.0450 0.0383 1.6025 0.8193
A → CO1↑ 0.2052 0.2528 2.9415 2.6878
A → CO1↓ 0.2749 0.3267 1.7003 1.6712
B → CO1↑ 0.1440 0.1850 2.9588 2.6787
B → CO1↓ 0.1972 0.2457 1.6882 1.6637
CI1N → CO1↑ 0.0735 0.0565 3.0003 1.4976
CI1N → CO1↓ 0.0450 0.0371 1.6398 0.8193
267
Process Technology: AFCSHCON

The AFCSHCON cell provides a carry-select adder
function that produces the arithmetic sum (S) and
A
active-low carry-outs (CO0N, CO1N) of two
operands (A, B) with carry-ins (CI0, CI1). The three B S
outputs (S, CO0N, CO1N) are represented by the
CI0 CO0N
logic equations:
S = CS • ( A ⊕ B ⊕ CI 1 ) + CS • ( A ⊕ B ⊕ CI 0 ) CI1 CO1N
CS
CO0N = ( A • B ) + ( A • CI 0 ) + ( B • CI 0 )
CO1N = ( A • B ) + ( A • CI 1 ) + ( B • CI 1 )
Cell Size

AFCSHCONX2 5.04 33.66
AFCSHCONX4 5.04 38.94
Functions
A B CI0 CI1 CS S CO0N CO1N A B CI0 CI1 CS S CO0N CO1N

0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1
0 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1
0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 0
0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0
0 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1
0 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1
0 0 1 1 0 1 1 1 1 0 1 1 0 0 0 0
0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0
0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0
0 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0
0 1 0 1 0 1 1 0 1 1 0 1 0 0 0 0
0 1 0 1 1 0 1 0 1 1 0 1 1 1 0 0
0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0
0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0
0 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0
0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0
268
A
B 1
S
0
CS
CO1N
CO0N
CI1
CI0

Pin Pin
X2 X4 X2 X4
CS 0.0673 0.0674 CS 0.0092 0.0091
A 0.3525 0.3945 A 0.0131 0.0130
B 0.3324 0.3758 B 0.0151 0.0151
CI0 0.1647 0.2114 CI0 0.0125 0.0243
CI1 0.1362 0.1799 CI1 0.0121 0.0242
269

Description
X2 X4 X2 X4
CS → S↑ 0.1462 0.1470 2.2380 2.2336
CS → S↓ 0.1215 0.1248 1.2964 1.2756
A → S↑ 0.4619 0.5086 2.2390 2.2340
A → S↓ 0.4108 0.4513 1.2986 1.2767
B → S↑ 0.4183 0.4622 2.2390 2.2342
B → S↓ 0.3815 0.4092 1.2986 1.2767
CI0 → S↑ 0.2643 0.2586 2.2389 2.2343
CI0 → S↓ 0.2655 0.2517 1.2989 1.2766
CI1 → S↑ 0.2182 0.2090 2.2381 2.2337
CI1 → S↓ 0.2299 0.2173 1.2966 1.2758
A → CO0N↑ 0.2585 0.3173 2.7148 2.6401
A → CO0N↓ 0.2586 0.3191 1.7120 1.6778
B → CO0N↑ 0.2243 0.2867 2.9790 2.6389
B → CO0N↓ 0.2126 0.2663 1.7020 1.6775
CI0 → CO0N↑ 0.0696 0.0581 3.0568 1.6136
CI0 → CO0N↓ 0.0477 0.0388 1.7828 0.9204
A → CO1N↑ 0.2741 0.3235 2.9481 3.0174
A → CO1N↓ 0.2565 0.3200 1.6888 1.6713
B → CO1N↑ 0.2449 0.2933 2.9489 3.0173
B → CO1N↓ 0.2065 0.2679 1.6841 1.6705
CI1 → CO1N↑ 0.0628 0.0506 2.9711 1.5118
CI1 → CO1N↓ 0.0446 0.0342 1.7836 0.8318
270
Process Technology: AFHCIN

The AFHCIN cell is a full adder that provides the
arithmetic sum (S) and carry-out (CO) of two
A S
operands (A, B) with active-low carry-in (CIN). The
outputs (S, CO) are represented by the logic B CO
equations:
CIN
S = A ⊕ B ⊕ CIN
CO = ( A • B ) + ( A • CIN ) + ( B • CIN )
Cell Size
Functions
A B CIN S CO
AFHCINX2 5.04 16.50
0 0 0 1 0
AFHCINX4 5.04 18.48
0 0 1 0 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
A
B
CIN S
CO
271
Process Technology: AFHCIN

Pin Pin
X2 X4 X2 X4
A 0.1719 0.1896 A 0.0068 0.0068
B 0.1789 0.1996 B 0.0174 0.0152
CIN 0.1247 0.1774 CIN 0.0130 0.0256

Description
X2 X4 X2 X4
A → S↑ 0.2296 0.2463 2.8043 2.2334
A → S↓ 0.2740 0.2955 1.4039 1.2746
B → S↑ 0.2096 0.2260 2.8047 2.2337
B → S↓ 0.2099 0.2284 1.4028 1.2742
CIN → S↑ 0.1309 0.1152 2.8042 2.2336
CIN → S↓ 0.1432 0.1426 1.4077 1.2762
A → CO↑ 0.1620 0.1868 2.9499 2.9450
A → CO↓ 0.2021 0.2373 1.9167 1.8913
B → CO↑ 0.1238 0.1448 2.9335 2.9370
B → CO↓ 0.1733 0.2048 1.8960 1.8822
CIN → CO↑ 0.0446 0.0405 2.7097 1.3597
CIN → CO↓ 0.0383 0.0382 1.6670 0.8391
272
Process Technology: AFHCON

The AFHCON cell is a full adder that provides the
arithmetic sum (S) and active-low carry-out (CON)
A S
of two operands (A, B) with carry-in (CI). The outputs
(S, CON) are represented by the logic equations: B CON
S = A ⊕ B ⊕ CI CI
CON = ( A • B ) + ( A • CI ) + ( B • CI )
Functions
Cell Size
A B CI S CON
0 0 0 0 1
AFHCONX2 5.04 15.84
0 0 1 1 1
AFHCONX4 5.04 17.16
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
A
B
CI S
CON
273
Process Technology: AFHCON

Pin Pin
X2 X4 X2 X4
A 0.1751 0.1963 A 0.0068 0.0068
B 0.1678 0.1879 B 0.0207 0.0217
CI 0.1171 0.1703 CI 0.0128 0.0257

Description
X2 X4 X2 X4
A → S↑ 0.2235 0.2383 2.8031 2.8004
A → S↓ 0.2589 0.2715 1.6211 1.6103
B → S↑ 0.1591 0.1653 2.8036 2.7997
B → S↓ 0.1813 0.1987 1.6221 1.6098
CI → S↑ 0.1253 0.1140 2.8023 2.8008
CI → S↓ 0.1379 0.1447 1.6231 1.6107
A → CON↑ 0.2101 0.2319 3.0486 2.9166
A → CON↓ 0.1751 0.2046 1.9582 1.8723
B → CON↑ 0.1413 0.1610 3.0852 2.9345
B → CON↓ 0.1133 0.1392 1.9729 1.8808
CI → CON↑ 0.0588 0.0456 2.7052 1.3287
CI → CON↓ 0.0416 0.0359 1.6622 0.8332
274
Process Technology: AHHCIN

The AHHCIN cell is a half adder that provides the
arithmetic sum (S) and carry-out (CO) of the input
A S
operand (A) with an active-low carry-in (CIN). The
outputs (S, CO) are represented by the logic
equations: CIN CO
S = A ⊕ CIN
CO = A • CIN
Cell Size
Functions
A CIN S CO
AHHCINX2 5.04 7.92
0 0 1 0
AHHCINX4 5.04 9.24
0 1 0 0
1 0 0 1
1 1 1 0
A
CIN S
CO
275
Process Technology: AHHCIN

Pin Pin
X2 X4 X2 X4
A 0.0860 0.1049 A 0.0078 0.0098
CIN 0.0738 0.1001 CIN 0.0156 0.0208

Description
X2 X4 X2 X4
A → S↑ 0.0835 0.0825 3.2153 3.2201
A → S↓ 0.0907 0.0822 1.8966 1.9373
CIN → S↑ 0.0515 0.0509 3.2187 3.2217
CIN → S↓ 0.0711 0.0682 1.9298 1.9500
A → CO↑ 0.0744 0.0710 4.8494 2.4240
A → CO↓ 0.1014 0.0918 1.6812 0.8396
CIN → CO↑ 0.0475 0.0459 4.8471 2.4235
CIN → CO↓ 0.0237 0.0229 1.6690 0.8347
276
Process Technology: AHHCON

The AHHCON cell is a half adder that provides the
arithmetic sum (S) and active-low carry-out (CON)
A S
of the input operand (A) with carry-in (CI). The
outputs (S, CON) are represented by the logic
equations: CI CON
S = A ⊕ CI
CON = A • CI
Cell Size
Functions
A CI S CON
AHHCONX2 5.04 7.26
0 0 0 1
AHHCONX4 5.04 8.58
0 1 1 1
1 0 1 1
1 1 0 0
A
CI S
CON
277
Process Technology: AHHCON

Pin Pin
X2 X4 X2 X4
A 0.0939 0.1193 A 0.0115 0.0176
CI 0.0589 0.0772 CI 0.0167 0.0225

Description
X2 X4 X2 X4
A → S↑ 0.0906 0.0916 3.2288 3.2261
A → S↓ 0.1007 0.1005 1.9711 1.9684
CI → S↑ 0.0541 0.0531 3.2186 3.2236
CI → S↓ 0.0707 0.0666 1.9274 1.9494
A → CON↑ 0.0347 0.0347 2.9302 1.4655
A → CON↓ 0.0248 0.0234 2.1681 1.0031
CI → CON↑ 0.0280 0.0262 2.9317 1.4660
CI → CON↓ 0.0221 0.0198 2.1681 1.0025
278
Process Technology: BENC

The booth encoder block, BENC, cell performs a
2-bit multiplier recoding per a modified Booth’ s
algorithm. Each BENC cell examines 3 bits of the M2 S
multiplier (M0, M1, M2) and generates the M1 A
appropriate control signals to adjust the multiplicand
for subsequent partial product reduction. The M0 X2
outputs (S, A, X2) are represented by the logic
equations:
A = M2 + ( M0 • M1 )
S = M2 + ( M0 • M1 )
Cell Size
X 2 = M1 ⊕ M0
Functions
BENCX1 5.04 20.46
M2 M1 M0 X2 A S BENCX2 5.04 27.06
BENCX4 5.04 40.26
0 0 0 1 1 1
0 0 1 0 0 1
0 1 0 0 0 1
0 1 1 1 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 1 1 1
279
M0
M1 X2
M2 A
AC Power
Power (µW/MHz)
Pin
X1 X2 X4
M2 0.0800 0.1380 0.2499
M1 0.1610 0.2802 0.5414
M0 0.1849 0.3149 0.5714
Pin Capacitance
Capacitance (pF)
Pin
X1 X2 X4
M2 0.0078 0.0101 0.0159
M1 0.0106 0.0173 0.0304
M0 0.0094 0.0153 0.0240
280

Description
X1 X2 X4 X1 X2 X4
M2 → A↑ 0.2317 0.2214 0.2054 1.1013 0.5604 0.2770
M2 → A↓ 0.2052 0.2189 0.2200 0.6919 0.3436 0.1702
M1 → A↑ 0.2491 0.2170 0.1935 1.1011 0.5603 0.2768
M1 → A↓ 0.1742 0.1671 0.1805 0.6926 0.3440 0.1704
M0 → A↑ 0.2435 0.2093 0.1845 1.1011 0.5602 0.2768
M0 → A↓ 0.1683 0.1592 0.1687 0.6923 0.3438 0.1703
M2 → S↑ 0.1767 0.1716 0.1585 1.1694 0.5603 0.2752
M2 → S↓ 0.1338 0.1258 0.1345 0.6886 0.3425 0.1627
M1 → S↑ 0.3043 0.2647 0.2392 1.1689 0.5601 0.2751
M1 → S↓ 0.3073 0.2660 0.2718 0.6896 0.3428 0.1629
M0 → S↑ 0.2831 0.2378 0.2255 1.1690 0.5600 0.2751
M0 → S↓ 0.2380 0.2272 0.2294 0.6890 0.3426 0.1627
M1 → X2↑ 0.2072 0.1732 0.1789 1.1026 0.5507 0.2513
M1 → X2↓ 0.2641 0.2257 0.2115 0.7447 0.4795 0.1811
M0 → X2↑ 0.2534 0.2024 0.2141 1.1026 0.5501 0.2513
M0 → X2↓ 0.2594 0.2440 0.2433 0.7448 0.4797 0.1812
281
Process Technology: BMX

The BMX cell performs the shifting and 2’ s
complement inversion of the multiplicand bits (M1,
M0) based on the recode control signals (X2, A, S)
from the booth encoder block cell. The partial M0
product output (PP) is represented by the logic PP
M1
equation:
PP = X 2 • ( ( M0 • A ) + ( M0 • S ) ) + X 2 • ( ( M1 • A ) + ( M1 • S ) )
A S X2
1
Functions
X2 A S M0 M1 PP Cell Size
0 0 0 x x x
0 0 1 x 0 0
0 0 1 x 1 1 BMXX1 5.04 12.54
0 1 0 x 0 1
0 1 0 x 1 0
0 1 1 x x 0
1 0 0 x x x
1 0 1 0 x 0
1 0 1 1 x 1
1 1 0 0 x 1
1 1 0 1 x 0
1 1 1 x x 0
1 Shaded areas represent illegal conditions.
282
Process Technology:
BMX
M0
A 1
S 0
1
PP
0
1
0
M1
X2

Pin Pin
X1 X1
X2 0.0379 X2 0.0033
M0 0.0607 M0 0.0056
A 0.0575 A 0.0043
S 0.0755 S 0.0043
M1 0.0505 M1 0.0052
283
Process Technology:
BMX
Intrinsic
Kload (ns/pF)
Description Delay (ns)
X1 X1
X2 → PP↑ 0.1408 4.5365
X2 → PP↓ 0.1242 2.5168
M0 → PP↑ 0.1956 4.5412
M0 → PP↓ 0.2465 2.5221
A → PP↑ 0.2090 4.5418
A → PP↓ 0.2109 2.5218
S → PP↑ 0.2274 4.5422
S → PP↓ 0.2244 2.5224
M1 → PP↑ 0.1817 4.5417
M1 → PP↓ 0.2231 2.5133
284
Process Technology:
CMPR22

The CMPR22 cell provides the arithmetic sum (S)
and carry out (CO) of two operands (A, B). The two
outputs (S, CO) are represented by the logic A S
equations:
B CO
S = ( A • B) + ( A • B)
CO = A • B
Functions Cell Size
A B S CO Drive Strength Height (um) Width (um)

0 0 0 0 CMPR22X1 5.04 7.92
0 1 1 0
1 0 1 0
1 1 0 1
A S
B
CO
285
Process Technology:
CMPR22

Pin Pin
X1 X1
A 0.1031 A 0.0104
B 0.0609 B 0.0088
Delays (25 oC, 1.8V, Typical Process)
Intrinsic
Kload (ns/pF)
Description Delay (ns)
X1 X1
A → S↑ 0.0796 2.7733
A → S↓ 0.0874 1.7330
B → S↑ 0.0548 2.7606
B → S↓ 0.0764 1.6539
A → CO↑ 0.0837 4.5426
A → CO↓ 0.1308 2.6335
B → CO↑ 0.0842 4.5426
B → CO↓ 0.1242 2.6289
286
Process Technology: CMPR32

The CMPR32 cell takes in 3 bits of the partial product
(A, B, C) and compresses them into 2-bits of partial
product (S, CO). The two outputs (S, CO) are A S
represented by the logic equations:
B CO
S = A⊕B⊕C
C
CO = ( A • B ) + ( A • C ) + ( B • C )
Functions
Cell Size
A B C S CO
0 0 0 0 0
0 0 1 1 0 CMPR32X1 5.04 13.86
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A
B
C S
CO
287

Pin Pin
X1 X1
A 0.1190 A 0.0071
B 0.1520 B 0.0068
C 0.0656 C 0.0065

Description
X1 X1
A → S↑ 0.2149 4.5561
A → S↓ 0.2886 2.6192
B → S↑ 0.2476 4.5609
B → S↓ 0.3272 2.6191
C → S↑ 0.1742 4.5563
C → S↓ 0.1518 2.6328
A → CO↑ 0.2646 4.5332
A → CO↓ 0.2662 2.5457
B → CO↑ 0.3026 4.5329
B → CO↓ 0.2822 2.4918
C → CO↑ 0.1389 4.5473
C → CO↓ 0.1863 2.5669
288
Process Technology: XNOR3

The XNOR3 cell provides a logical EXCLUSIVE
NOR of three inputs (A, B, C). The output (Y) is
represented by the following equation: A
B Y
Y = A⊕B⊕C C
Functions
A B C Y
0 0 0 1 Cell Size
0 0 1 0
0 1 0 0
0 1 1 1 XNOR3X2 5.04 11.88
1 0 0 0 XNOR3X4 5.04 19.80
1 0 1 1
1 1 0 1
1 1 1 0
A
B Y
C
289
Process Technology: XNOR3

Pin Pin
X2 X4 X2 X4
A 0.1475 0.2819 A 0.0066 0.0131
B 0.1302 0.2405 B 0.0149 0.0280
C 0.0599 0.1099 C 0.0052 0.0093

Description
X2 X4 X2 X4
A → Y↑ 0.2480 0.2347 2.1904 1.0954
A → Y↓ 0.2792 0.2610 1.3647 0.6790
B → Y↑ 0.1674 0.1557 2.1901 1.0953
B → Y↓ 0.2034 0.1916 1.3566 0.6771
C → Y↑ 0.1446 0.1317 2.1887 1.0946
C → Y↓ 0.1395 0.1357 1.3564 0.6760
290
Process Technology: XOR3

The XOR3 cell provides a logical EXCLUSIVE OR
of three inputs (A, B, C). The output (Y) is
represented by the following equation: A
B Y
Y = A⊕B⊕C C
Functions
A B C Y
0 0 0 0 Cell Size
0 0 1 1
0 1 0 1
0 1 1 0 XOR3X2 5.04 11.88
1 0 0 1 XOR3X4 5.04 19.80
1 0 1 0
1 1 0 0
1 1 1 1
A
B Y
C
291
Process Technology: XOR3

Pin Pin
X2 X4 X2 X4
A 0.1493 0.2854 A 0.0066 0.0131
B 0.1347 0.2499 B 0.0149 0.0281
C 0.0596 0.1102 C 0.0085 0.0160

Description
X2 X4 X2 X4
A → Y↑ 0.2493 0.2347 2.1908 1.0954
A → Y↓ 0.2770 0.2579 1.3665 0.6792
B → Y↑ 0.1666 0.1543 2.1903 1.0953
B → Y↓ 0.2059 0.1944 1.3566 0.6770
C → Y↑ 0.1445 0.1322 2.1893 1.0947
C → Y↓ 0.1418 0.1364 1.3529 0.6754
292
Advanced Arithmetic Cells
293

The CMPR42 cell takes in 4 bits of the partial product
(A, B, C, D) and compresses them into
2-bits of partial product (S, CO). The cell requires an A S
intermediate carry-in input (ICI) from the n-1
compressor and an intermediate carry-out output B CO
(CO) to the n+1 compressor. The CMPR42 cell also C ICO
contains an internal sum IS. The internal sum IS,
carry-in output (ICO), and the two outputs (S, CO) D
are represented by the logic equations:
ICI
IS = A ⊕ B ⊕ C
ICO = ( A • B ) + ( A • C ) + ( B • C )
S = IS ⊕ D ⊕ ICI Cell Size
CO = ( IS • D ) + ( IS • ICI ) + ( D • ICI ) Drive Strength Height (um) Width (um)

CMPR42X1 5.04 22.44
CMPR42X2 5.04 26.40
Functions Functions (cont.)
A B C IS ICO IS D ICI S CO
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 1 0
0 1 0 1 0 0 1 0 1 0
0 1 1 0 1 0 1 1 0 1
1 0 0 1 0 1 0 0 1 0
1 0 1 0 1 1 0 1 0 1
1 1 0 0 1 1 1 0 0 1
1 1 1 1 1 1 1 1 1 1
294
A
B
IS
C
ICI S
ICO
CO
295

Pin Pin
X1 X2 X1 X2
A 0.1655 0.2957 A 0.0085 0.0159
B 0.1593 0.2809 B 0.0086 0.0163
C 0.1513 0.2652 C 0.0082 0.0134
D 0.1304 0.2305 D 0.0048 0.0095
ICI 0.0655 0.1129 ICI 0.0028 0.0059
296

Description
X1 X2 X1 X2
A → S↑ 0.5083 0.5106 4.5499 2.2266
A → S↓ 0.6153 0.6105 2.5188 1.3575
B → S↑ 0.4714 0.4246 4.5476 2.2265
B → S↓ 0.5477 0.5246 2.5188 1.3575
C → S↑ 0.4058 0.3820 4.5478 2.2266
C → S↓ 0.5035 0.4853 2.5188 1.3576
D → S↑ 0.4225 0.3278 4.5475 2.2238
D → S↓ 0.4437 0.3940 2.5181 1.3573
ICI → S↑ 0.2380 0.1774 4.5499 2.2256
ICI → S↓ 0.2526 0.1957 2.5210 1.3582
A → ICO↑ 0.1156 0.0868 4.5517 2.2250
A → ICO↓ 0.1960 0.1562 2.5274 1.2947
B → ICO↑ 0.1140 0.0887 4.5516 2.2264
B → ICO↓ 0.1880 0.1532 2.5272 1.2948
C → ICO↑ 0.1000 0.0779 4.5477 2.2249
C → ICO↓ 0.1612 0.1336 2.5235 1.2934
A → CO↑ 0.4960 0.4944 4.5536 2.2254
A → CO↓ 0.5816 0.5815 2.5374 1.2929
B → CO↑ 0.4638 0.4369 4.5449 2.2255
B → CO↓ 0.5205 0.5240 2.5374 1.2929
C → CO↑ 0.4004 0.3764 4.5537 2.2255
C → CO↓ 0.4459 0.4225 2.5379 1.2931
D → CO↑ 0.3741 0.3084 4.5461 2.2236
D → CO↓ 0.3832 0.3110 2.5362 1.2870
ICI → CO↑ 0.1410 0.0967 4.5570 2.2265
ICI → CO↓ 0.1918 0.1488 2.5795 1.3075
297
Register File Cells
298
Process Technology: RF1R1W
The RF1R1W register file cell is an active-high

D-type transparent latch with an active-high tri-state WB RB
output. The output (RB) is inverted.
WW
Functions for Write Operations
WW WB q[n+1] RW
0 0 q[n] RWN
0 1 q[n]
0 0 q[n]
0 1 q[n]
1 0 0 Cell Size
1 1 1
1 0 0
RF1R1WX2 5.04 6.60
1 1 1
AC Power
Functions for Read Operations1
Power (µW/MHz)
RW RWN q RB Pin
X2
0 0 0 1
WW 0.0329
0 0 1 Hi-Z
WB 0.0358
0 1 0 Hi-Z
RW 0.0062
0 1 1 Hi-Z
RB 0.0255
1 0 0 1
1 0 1 0
Pin Capacitance
1 1 0 Hi-Z
1 1 1 0 Capacitance (pF)
1Shaded areas represent operations that are legal only Pin
during RW/RWN transitions. X2
WW 0.0053
WB 0.0023
RW 0.0031
RWN 0.0020
RB 0.0071
299
WW RW
q
WB RB
RWN

Description
X2 X2
WW → RB↑ 0.2786 4.3572
WW → RB↓ 0.1693 1.9633
WB → RB↑ 0.2595 4.3572
WB → RB↓ 0.1827 1.9633
RW → RB↑ 0.0303 4.3530
RW → RB↓ 0.0143 1.9573
Interval (ns)
Pin Requirement
X2
WW minpwh 0.1674
setup↑ → WW 0.0977
setup↓ → WW 0.1445
WB
hold↑ → WW -0.0820
hold↓ → WW -0.1367
300
The RF2R1W register file cell is an active-high

D-type transparent latch with two independently WB R1B
controlled, active-high tri-state outputs. The cell has WW R2B
two read ports and one write port. The outputs (R1B,
R1W
R2B) are inverted.
R2W
Functions for Write Operations
WW WB q[n+1]
0 0 q[n] Cell Size
0 1 q[n]
1 0 0 Drive Strength Height (um) Width (um)
1 1 1 RF2R1WX2 5.04 10.56
Functions for Read Operations
R1W/ R2W q R1B/ R2B

0 0 Hi-Z
0 1 Hi-Z
1 0 1
1 1 0
R1W
R1B
WW
r1wn
q
WB
R2W
wwn wwn
R2B
WW wwn
r2wn
R1W r1wn WW
R2W r2wn
301

Pin Pin
X2 X2
WB 0.0494 WB 0.0024
WW 0.0134 WW 0.0044
R1W 0.0120 R1W 0.0035
R2W 0.0118 R2W 0.0045
R1B 0.0981 R1B 0.0042
R2B 0.0040

Description
X2 X2
WB → R1B↑ 0.3003 4.3584
WB → R1B↓ 0.2210 1.9696
WW → R1B↑ 0.3168 4.3583
WW → R1B↓ 0.2085 1.9696
R1W → R1B↑ 0.0648 4.3523
R1W → R1B↓ 0.0147 1.9559
WB → R2B↑ 0.2995 4.3578
WB → R2B↓ 0.2206 1.9699
WW → R2B↑ 0.3160 4.3582
WW → R2B↓ 0.2081 1.9698
R2W → R2B↑ 0.0639 4.3527
R2W → R2B↓ 0.0145 1.9560
Interval (ns)
Pin Requirement
X2
setup↑ → WW 0.1133
setup↓ → WW 0.1680
WB
hold↑ → WW -0.0977
hold↓ → WW -0.1484
WW minpwh 0.1868
302
Process Technology: RFRD

The RFRD output buffer has a “ keeper” function that
holds the input and output ports at the present level
when the input (RB) is in a state of high-impedance. RB BRB
Functions
RB BRB
0 1
1 0
Hi-Z Keep
Cell Size

RFRDX1 5.04 3.30
RFRDX2 5.04 3.30
RFRDX4 5.04 3.96
RB BRB
303
Process Technology: RFRD

Pin Pin
X1 X2 X4 X1 X2 X4
RB 0.0298 0.0383 0.0543 RB 0.0580 0.0623 0.0704

Description
X1 X2 X4 X1 X2 X4
RB → BRB↑ 0.0477 0.0326 0.0239 4.5364 2.2201 1.1101
RB → BRB↓ 0.0317 0.0233 0.0178 2.4290 1.2616 0.6309
304

Silterra 18 RVT

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Titlepage

Silterra Malaysia Sdn. Bhd. 0.18 µm Process

Part Number DB-SX-SLT004-3.0/18

Artisan Components, Inc., 141 Caspian Court, Sunnyvale, CA 94089, USA

Revision History ........................................................................................................................................ ix

How This Book Is Organized ....................................................................................................................11

6. Functional Schematic ....................................................................................................25

Synthesis Optimized Arithmetic Cells

Advanced Arithmetic Cells

Register File Cells

DB-SX-SLT001-1.0/18 1.0 August 2002 • Initial release

DB-SX-SLT001-2.0/18 2.0 February 2003 • Characterization update

DB-SX-SLT004-3.0/18 3.0 March 2004 • Characterization update

■ United States and North America 877-ARTILIB (877-278-4542)

How This Book This introduction is organized into three sections:

Table 1 shows the physical design specifications of this library.

Drawn Gate Length (µm) 0.18

Table 2 describes the electrical specifications for this library.

Parameter Minimum Typical Maximum

DC Supply Voltage (Vdd) 1.62V 1.8V 1.98V

KProcess (slow) 1.293

Table 3. Derating Factors

KVolt (1.8V to 1.62V) -0.694/V

Propagation Delay and Transition Time

Figure 1. Propagation Delay

Input 50% Vdd

Output 50% Vdd

Figure 2. Transition Time

10% Vdd 10%Vdd

Rising TIme Falling TIme

Derating factors are derived by averaging the performance of many different

tTPD = (KProcess) • [1+(KVolt • ∆Vdd)] • [1+(KTemp • ∆T)] • ttypical

ttypical= tintrinsic + (Kload • Cload)

KProcess = process derating factor, where process is slow, typical, or fast;

Figure 3. Setup Time

Input 50% Vdd

Clock 50% Vdd

Figure 4. Hold Time

Input 50% Vdd

Clock 50% Vdd

Figure 5. Recovery Time

Clock 50% Vdd

Minimum Pulse Width

Figure 6. Minimum Pulse Width

Signal 50% Vdd 50% Vdd

The SAGE-X Standard Cell Library is designed to dissipate only AC power,

The SAGE-X library datasheets contain both an AC power table which

Power dissipation is dependent upon the power-supply voltage, frequency of

The switching frequency of inputs and outputs of a particular cell in a design

EXAMPLE: Calculating Power for a DFFXL Cell

∑ ∑  C on • Vdd • --- f on + E os • f o1

Ei2 = 0.0063 µW/MHz;

∑ ∑  C on • Vdd • --- f on + E os • f o1

--- f o1 +  C o2 • VDD • --- f o2

Pavg = ( 0.0056 • 20 ) + ( 0.0063 • 133 )

+  0.02 • 1.0 • --- ( 20 ) +  0.02 • 1.0 • --- ( 20 )

You must determine the required amount of vertical power-rail strapping to

The guidelines below provide a rough estimate with many simplifying

Adding Routing Channels

Row Separation in Action to Correct

0 (Rows Abut) None None

The library contains an antenna-fix cell which must be inserted manually.

Low-Power (XL) Cells