W . Y . M . W W .1 Y .C M.

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. . C .T W . 1 . C . T
W W 00Y O M W W 00Y M
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W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
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W W 00 O M W W 00Y M
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0 W 0
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W Description Y .C O
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W Features
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10
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W 00 . 1 Optional
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W 1 W reliability or manufacturability W 1 O
ANPEC reserves
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W 0
10 Corp..CO W W 0
0www.anpec.com.twO W
Copyright W ANPEC Electronics . .T 1 W . 1 .C .T
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O . T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C . T W . 1 . C .T
W W 00Y O M W W 00Y M
W . 1 .C . T W . 1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y .C . T W . 1 .C . T
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W W Ordering Y Information W WCode 00Y .
W . 100 .COM .TW W
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W Y W W Y .
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W W . 1
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W Handling Code W 0 O M W
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WW W.1 Y M .T W W
W 00Y. 1
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W
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WW W.1 Y . C . T W W
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W W Y M W W Y . M
Copyright W
W
ANPEC Electronics . 100 Corp..CO .T W2 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C .T W . 1 . C .T
W W 00Y O M W W 00Y M
W . 1 .C .T W .1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
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WW Rising C T W 1 O- V.TW
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W
W VIN POR W .1
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Y .C M.T W W
W
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Y .C- O VM.T
Copyright W
W
ANPEC Electronics. 100 Corp..CO .T W3 W W . 1 0
0www.anpec.com.tw
.C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O . T W
W 00Y M W W 00Y . M
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C .T W . 1 . C . T
W W 00Y O M W W 00Y M
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W APL5932A/B/C/D W .
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W . Y .C .T W .1 .C .T
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W 00 .CO W W W 0 0 O W
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Copyright W . 1 Corp..C .T W . 1 C O . T W
ANPEC Electronics
W 00Y M 4 W W 00Y .
www.anpec.com.tw
M
Rev. A.1 - Aug., 2011
W . 1 C O . T W W . 1 C O T W
W W 00Y . M W W 00Y . M .
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
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W W Typical Y Operating M Characteristics W .
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W W 0 0 O M W W
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W Output Current,Y W
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100 Corp..CO 0
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C O T W
Copyright W ANPEC Electronics
W 00Y M 5 W W 00Y . M .
Rev. A.1 - Aug., 2011
W . 1 C O .T W W . 1 C O T W
W W 00Y . M W W 00Y . M .
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C .T W . 1 . C .T
W W 00Y O M W W 00Y M
W . 1 .C .T W .1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y .C . T W .1 . C . T
W W 00 O M W W 00Y M
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W WTypical Y Operating Characteristics W W 00Y .
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Power Supply Rejection Ratio (dB)

Power Supply Rejection Ratio (dB)

W . .C IN
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V =1.2V
W O M
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W
V =1.2V OUT

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W 00. 1
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W . 1 00 .COM .TW W . 1 C O M
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W W Y M W W Y . M
Copyright W
W .
ANPEC Electronics 100 Corp..CO .T W6 W W . 1 0
0www.anpec.com.tw
.C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C .T W . 1 . C .T
W W 00Y O M W W 00Y M
W . 1 .C . T W .1 C O . T W
W APL5932A/B/C/D W .
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W . Y .C .T W . 1 . C . T
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W TIME:W . 1A/Div, DC
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WW W.1 Y . C . T W W
W 00. 1
Y .TW
W . 1 00 .COM .TW W . 1 C O M
.TW
W W Y M W W Y . M
Copyright W
W
ANPEC Electronics . 100 Corp..CO .T W7 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C . T W . 1 .C . T
W W 00Y O M W W 00Y M
W . 1 .C .T W .1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y .C . T W . 1 .C . T
W W 00 O M W W 00Y M
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. Waveforms . T W . 1 C O . T W
W WOperating Y W W 00Y .
W . 1 C OM circuit.
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W V .=5V, 1 C O M
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WL R =0.4Ω
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W W 00Y O M V W W 00Y V OM W 00Y
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, 5V/Div, DC0
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W TIME: W 5µs/Div 0Y
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M W
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W M
00 .CO
TIME: 1ms/Div
0 O W
WW W.1 Y . C . T W W
W 00. 1
Y .TW
W . 1 00 .COM .TW W . 1 C O M
.TW
W W Y M W W Y . M
Copyright W
W
ANPEC Electronics. 100 Corp..CO .T W8 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O .T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C . T W .1 .C . T
W W 00Y O M W W 00Y M
W . 1 .C . T W . 1 C O . T W
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W . Y .C . T W . 1 . C . T
W W 00 O M W W 00Y M
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W W Pin Description Y W W 00Y .
W . 1 00PIN .COM .TW W . 1 C O M
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1
W 2 W.EN/ENB Y.onenable T control pin. Applying andW
C voltage.threshold shuts down the output. . 1
holding the voltage
C below/above the
. T W
Msoft-startW W When re-enabled, the IC
Y
Wan internal00pull-up/down .
undergoes a new
M (3µA W
turn
0 typical)
TW W 0 O O
delay and process. When leave this pin open, current
W . 1 .C M.pulls the T
EN/ENB voltage and enables the
W W
regulator. . 1 .C M.T
W W 0 Y O W W 0 Y
.T W W VIN .10 usually.C Main supply input pin for
. T
voltage conversions. A
Wand improve
decoupling capacitor
. 1
(≥10µF
C O Theis .TW
0transientrecommended)
M
3
W 0voltage
connected near
Y on this O this pin to filter the voltage noise
W .
response.

W W 0 pinMis monitored for Power-On-Reset purpose W

W 0Y M
M . T W W . 1 Bias .
voltage
Y C input pin for .T
internal control circuitry. W
Connect
W this pin to . 1
a
0voltage . C
source
Y
O(+5V . TW
0 noise.A The M capacitor W near0this 0 pin to filterOM
O TW
4 VCNTL
. W recommended).
. 1 0voltage C
decoupling
O . T Wpin(1µF typical) is usually connected
W . 1 C TW
M W W
the
Y . voltage at this is monitored for Power-On-Reset
W W
purpose.
Y . .
CO .TW
5 NC
W . 1 00 .COM .TW
No Connection.
W . 1 0 0
C O M
. T W
W W capacitors (10µF at least).is
M W 0Y and improving M transientWresponse. The output voltageWisW Ythe OM
Output pin of the regulator. Connecting this pin to load and output
O W programmed0by
T VOUT W 0
required for stability
1 O 0 W
Y.C OM. W T 1
6
W During .
resistor-divider
.C
connected to FB pin. .The VOUT can provide 3A
W
(max.) load .
current to loads.
.C . T
W Wshutdown,
1 0 0theYoutput voltage
O Mis quicklyW discharged by an internal pull-lowW
W
MOSFET.
0 0Y O M
.C T
. 7 W voltageW
Voltage .
Feedback Pin. .C M.
Connecting this pinTto an external resistor
W
divider receives the . 1
feedback
.C M.T
0Y M W
FB
of the regulator.Y
0 W 0 Y
Y .CO M.T8 GND
W W
Ground pin of the . 0 All.voltage
1circuitry.
W 00 of the O Y C O levels are . W with respect to this pin.
Tmeasured W W . 10 .C O
100 .CO Exposed T W W
P-Type Substrate connection
1
MConnect this
chip. W pad to system ground plane W
W for good
1 0 0Y O M
Y . Pad -
W
thermal conductivity. . Y . C . T W . .C
0 0 O M W W 0 M W W 0 Y
1
W. 00Y.C Block M .T WW W.1
0
Y .CO M.T W W
W 00. 10
Y .C O
. 1 C O Diagram .T W W . 1 00 .CO T W W .1
W 0 Y . M W W Y M .
VCNTL W W Y .C
W 10 O W W 1 0 0 O W W 0 0
. . C . T W . . C . T W . 1
W W 00Y O M W W 00Y M W 00Y
. 1 C T W 1 O T W
Power -On- W .1
W W Y . M . W Thermal
W . Y .C M. POR
Reset
W W
00 .CO
Shutdown
00 .CO
VCNTL
W (POR)

WW W.1 Y . T W W
W 00 . 1
Y . TW W W .10
00 .COM .TW M W
3µA

W W . 1 EN W
Enable Control Logic
. 1 C O .T W W .1
W Y M
Delay
W W
and
Y . M W W
0 0 O W
Soft-Start
0
WW W.1 W 0 O W W
0.8V
.C . T W . 1 .C . T W
Enable

Y
Soft- Start

W 00 .CO POK M W W 0 0 Y O M VIN

W W
W . 1 .T W . 1 C . T W
W W 00Y. OM W
Enable

W W 00Y O M W
VREF_OK

.1 .C M.T W .1 W W
.C M.T
PWOK

VREF
W W Y 0.8V W W Y
VOUT
W
00 .CO W 00 .CO
WW W.1 W W
Error Amplifier
T 1
ISEN

Y . W . . T W
W 0 0 O M Delay
W W W 00Y
Current-Limit
O M W
W W .1 Y .C M.T 90%
W and
.1 GND
Y .C M.T
0 0 O W
VREF
W
Short Current-Limit

00 .CO
WW W.1 Y . C . T W W
W 00 . 1
Y .TW
W . 1 00 .COM .TW W . 1 C O M
.TW
W W Y M
FB
W W Y . M
Copyright W
W
ANPEC Electronics. 100 Corp..CO . T W 9 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O . T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C . T W .1 .C . T
W W 00Y O M W W 00Y M
W . 1 .C . T W .1 C O .T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y .C . T W .1 . C . T
W W 00 O M W W 00Y M
. 1 . C . T W . 1 C O . T W
W W Block Diagram Y (Cont.) W W 00Y .
W . 1 00 .COM .TW W . 1 C O M
. TW
W W Y W W 00 Y . VCNTL

W . 100 .COM .TW W . 1 C O M

. TW
W W Y M W W Y . M
W . 100 .CO .T W Thermal
W . 1 0 0 POR
C OPower -On-
Reset
. T W
W W 00Y M
Shutdown
W W 00Y . (POR)
W
W W . 1 . C O . T W W . 1 .C OM .TW
W 00Y M Enable
W W 00Y
Control Logic
M
T W W .
ENB
1 C O Delay
T W W and
1 C O T W
W W 00Y 3µA . M . W Soft-Start .
W 00Y . .
0.8V
M
TW W 1 O T W W 1 O W

E nable
. C T

Soft-S tart
M . W W Y . . W . .C VIN
.
POK

00 .COM .TW W 00Y M

. TW W W . 1 Enable
VREF_OK
W W . 1 .C O . TW
M W Y
00 .COM .TW W 00 Y M
O TW W O TW
VREF
P WO K

. W . 1 0.8V
W W . 1 VOUT
. C .
M W Y
00 .COM .TW
Error Amplifier
W 0 Y M

ISEN
CO .TW W W . 1 Delay
W W . 1 0 .C O . T W
O M W W W 00Y O M W
Current-Limit
W 00Y M
.C . T W . 1 .C
90%
. T
and
W .1
GND
C O . T W
Y M W 00Y
VREF
M W
Short Current-Limit
W 00Y . M
C O T W W 1 O T W W 1 O
. . W . .C M. W . .C M.T
0Y M W W 0 Y W 0 Y
.CO M.T W 10 O TW W 10 O
FB

Y W W 00. Y . C . W . .C
Typical W Application Circuit M W 00Y M
100 .CO . T W W . 1 . C O .T W
W W . 1 .C O
0 0 Y O M W W 0 Y M W 0 Y
W
1
W. 00Y.C OM. W
T WW W.1
0
Y .CO M.T W W
W 00. 10
Y .C O
. 1 C .T W . 100 .CO T W V W .1
W 0 Y . M W W Y M . +5V is preferred W
CNTL

W Y .C
W 10 O W C W 10 0 O W W 0 0
. . C . T W . . C . T W . 1
W W 00Y O M W
CNTL
1µF W 00Y M W 00Y
. 1 C T W 1 O T W V IN
W .1
W . . R3 . C .C . +1.8V
4

W Y M W W Y M W W
00 .CO 5.1kΩ 0010µF .CO
IN

W
WW W.1 TW
VCNTL

. T W W . 1 . W .10
Y 1 VIN
W 00
3
Y W
00 .COM .TW M W
POK POK

W W . 1 W 6
. 1 C O . T W W .1
W Y M W VOUT
W Y . M
V OUT
W W
0 0 O W APL5932 0 +1.2V / 3A
WW W.1 W
W 0 C O
.C . T W . 1 . C . T OUT

W W
Y
00 .CO M 2
W
A/B/C/D
7 W 0 Y 10µF (X5R/X7R
M Recommended)
W
W W . 1 EN/ENB
. T
EN/ENB FB
W R1 .1
0 C O . T W W
R2 W W 00Y. OM W
GND

W W 00Y O M W 12kΩ
.1 .C M.T
8
W .1 W W
.C M.T
24kΩ
W W Y W W Y W
00 .CO W 00Recommended)
WW W.1 W O W
C1

Y . T W Optional .
(X5R/X7R1 . C .T W
W 0 0 O M W W W 00Y O M W
W W .1 Y .C M.T W .1 Y .C M.T
0 0 O W W 00 .CO
WW W.1 Y . C . T W W
W 00. 1
Y .TW
W . 1 00 .COM .TW W . 1 C O M
.TW
W W Y M W W Y . M
Copyright W
W .
ANPEC Electronics 100 Corp..CO .T W
10 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O . T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. .C .T W . 1 . C . T
W W 00Y O M W W 00Y M
W . 1 . C . T W . 1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y .C . T W . 1 . C . T
W W 00 O M W W 00Y M
. 1 C
. Description . T W . 1 C O . T W
W W Function Y W W 00Y .
W . 1 00 .COM .TW W . 1 C O M
. TW
W Power-On-Reset
W Y M W W 00
Thermal Shutdown
Y . M
W . 1 00 (POR) .C O . T Wboth of supply A thermal W . 1 C O . TW
W voltages
A Power-On-Reset
W Y
circuit
M
monitors
W shutdown
W
circuit
Y .
limits the junction
M
tempera-

W The.1POR on VCNTL 0 O a soft-start

0 function.Cinitiates W
and VIN pins to prevent wrong logic ture of APL5932A/B/C/D.0When the junction
W 0 sensor Oturns off .the W
temperature
Wcontrols. Y .T process W
exceeds +170 C, a.thermal
o 1 . C T output
W W 0 voltages O
M W POR NMOS, allowing W 0 Y M
WWthresholds
after both
. 10during
of the supply
.C exceed their rising
.T W W the device . 1 0 to cool .down. C O The regulator. T W
voltage W 00Y powering on.M The POR func- regulates the output W 00Y
again through initiation of
Mby 50 C,W
a new soft-
TW tion alsoW
W pulls low .the1 POK voltage O regardless T W
.C M.falls below resulting inW
of the start process W
after the junction 1
. during Y
temperature O
.C M.T
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W output status when W one of the 0 Ysupply voltages a pulsed output W 0 continuous thermal
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W 10
POR voltage .threshold.
Y .C O . TW overload conditions. W WThe thermal . 10shutdown.CisOdesigned.TW
M W 00 .COM .TWwith a 50 C hysteresis W W the average 0Y junctionOtem- M
TW W 0 TW
o
to lower
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M W Y
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W 00 overload conditions,
Y M
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W the current . 1
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W W . 1 O
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M put voltage to limit W surge during
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0 Y
CO .TWtypical soft-start interval W W 1
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. T
be Wexternally limited so thatW
W . 1 0
junction temperatures
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.C . T Output Voltage Regulation
W . 1 . C . T W .1 CO . T W
Y W .
O M AnW error amplifier working with aW
W 0 0Y
temperature-compen-
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W W W 00Y O M
.C T
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C The APL5932A/B/C/D W enable 1
. pin (EN/Y.C .T
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an output NMOS
M W W 0 M has a dedicated
W 0 M
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put to the preset voltage. The error
with high bandwidth and DC W
Wamplifier.1is0designed.CO
W 00 Y
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W W 00Y .10
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. T W and less load regulation. W . 1 C O T W W 1 O
0 Y M withWthe feedback voltage
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the
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M .
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W
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W .1load W 0 O
W. 00Y.C ference M
drive the output NMOSW which provides
W Y . Tby an internal currentW
M normalWoperation. It’s not necessary source (3µA.1
W Y .C
. 1 C O from VIN
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.T Wto VOUT. W . 100typical).CtoOenable T W to
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W 0 Y . M W W useY
M .
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W 10 O
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. . C . T W . . C . T W . 1
W W 00Y The M
APL5932A/B/C/D
O
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W
the current flowing throughW 00Y Power-OK and Delay
M W 00Y
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W W Y . and APL5932A/B/C/D
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M . limits the maximum current
W to pre-
W .The .C M.
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Y
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W W
00 .COconditions..TW
vent load from damages during cur-
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Y W pin..1As the V .rises

Y C .
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W 00Current-Limit O M W W W 0 0 (V O), M
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an internal W
W
W . 1
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voltage threshold
. 1 C
.of the delayMtime,
THPOK
T delay function starts
. the IC turns off the W W .1
W 0 Y
0 current-limit M
O function.Treduces W the current-limit W W At the end
0 Y W
WW W The 1
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. C
M W .
internal NMOS
the V W
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Y . C O to indicate T
M . theW output is ok. As
W W
W
W 1
0.9A (typical)
00.2V (typical) when the voltage on FB pin
Oduring current Woverload or short- threshold, W FB
1 0 0
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W
W falls .
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Y . C . T W the . IC turns on . C
the NMOS of . T
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W
W Wconditions. 0 0 O M W W 0 Ytypical ). OM
circuit
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debounce time of 10µs
.1 0 W W
W The short W .current-limit Y .function M W Y .C M.T W
00soft-start.Cinterval.
O W 00 .CO
WW W.1 W W
ful start-up during
Y . T W . 1 .T W
W 0 0 O M W W W 00Y O M W
W W .1 Y .C M.T W .1 Y .C M.T
0 0 O W W 00 .CO
WW W.1 Y .C .T W W
W 00 . 1
Y . TW
W . 1 00 .COM .TW W . 1 C O M
.TW
W W Y M W W Y . M
Copyright W
W
ANPEC Electronics . 100 Corp..CO .T W
11 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 . C .T W . 1 C O .T W
W 00Y M W W 00Y . M
W . 1 C O . T W W . 1 C O T W
W . W . .
W 0Y M W 0Y M
Free Datasheet http://www.datasheetlist.com/
 W . Y . M . W W .1 Y .C M.
W 10 0 O W W 0 0 O W
. . C . T W . 1 .C . T
W W 00Y O M W W 00Y M
W . 1 .C . T W . 1 C O . T W
W APL5932A/B/C/D W .
W 1 0 0Y O M W W W 00Y O M W
W . Y . C . T W . 1 . C . T
W W 00 O M W W 00Y M
. 1 C
. Information . T W . 1 C O . T W
W W Application Y W W 00Y .
W . 1 00 .COM .TW W . 1 C O M
. W
Tless
W Power W Sequencing Y M W W
is not cared, the input capacitance
Y . can be
M than 10µF.
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WW 1sequencing.Cof VIN and VCNTL T W 1 0 O Wsupply
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The power . . is not neces-
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W VOUT for a .
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W W Voltage00Y M
Oresistor W
W . . C . T The W
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TW W
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W W 0 Y following equationW 0 M
. T Output Capacitor
W W . 10
Y .C O . TW =W
W 
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M W 00a proper.Coutput OMcapacitor
V OUT
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. TW to maintain W
W
The APL5932A/B/C/D requires
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W W 1 0
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M W 0 Y MESR W where R1 is the risistor
W the0 risistor con- Y M
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W W and R2 is 0
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M (equivalent series W Y
and capacitance out- W Y
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nected from FB to GND. A bypass capacitor(C1)
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operating temperature.
. T W with R1 in parallelWto improve.1load
connected 00 transient . C O . T W
M Ultra-low-ESR capacitors W (such as 0 Y chip M response W W 00Y M
C O . T W W . 1 0 ceramic
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W 1 CO T W
Y . capacitors) and low-ESR
M tantalum, W bulk capacitors
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C O T W POSCap, and Aluminum W 1 0 0capacitors) O M Layout Consideration (See Figure 1) W
W W 1 0 0Y O M
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. solder the Exposed Pad Won the system . groundY.C .T
0Y M W W 0 Y Please
W 0 M
Y .CO M .T load
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W
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Y
pad on the top-layer
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Tconduct W W 00Y
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pending on the stepping amplitude and slew rate of load wide size to heat into the ambient air through the
Wused to reduce the slewWrate . 1 C O T W W 1 O
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W
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Y .2. PleaseM
system ground
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W W . Y .C
0 O W 0 place the input capacitors for VIN and VCNTL
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.10 Y
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1
W. 00Y.C response. M
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mize the .variations of output voltage WforWgoodW transient .Cnear
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Mripples.W W W
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O For.TtheWapplications with large W stepping load00 high-frequency O W
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W 0 Y current, M
O
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M be placed
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W . 10 recommended.
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W W . 1 0
W W 00Y M capacitors
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W W and
Y .
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the imped-
W .4. To
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WW W.1 Input Capacitor O response. TW
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T Wproper input capacitors toWW 1 0
5. The negative 0 pins ofOtheMinput andWoutput capacitors WW
W W .The
Y . .
requires
M W andW .
the GND pinY .Cbe connected
must
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WW W .1
prevent the input Y .Cvoltage
M
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the
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W . Y . C O
M . T W
W W
W
W 00 from
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. W or other bulk 1, W
sources
6. Large current
. 1 0 0
paths, shown
C O by bold lines
.T Won the figure
W
W capacitors W to0the0YVIN pin limit M the slew rate of the surge W
must have wide
WR1, R2,0and
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YC1. (option) M W
W 1 parasitic O W W
7. Place the 0 O W
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W
W currents, W .more Y .Cinductance M .Tneeds more input B/C/D W as close as
W .1to avoidYnoise . C coupling..T W
0 O(such as.Tceramic W M
00the R2 .toCtheOGND pin.TbyW
W 10capacitors
capacitance.
W . . C 8. Connect
W W the ground of
. 1 using
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Wand low-ESR 0 Y M (suchWas solid chip
a dedicated track. W 00Y M W
W
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W POSCap,
tantalum, W 0 Y M Wthe oneW Y . the load M for Kelvin

can all beW

W used as .an 10input capacitor .C Oof VIN..For T Wmost
sensing.
10. Connect W
W
one pin of the C1 . 1 00
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W
applications, the recommended Y
0if 0the drop M of VIN
input capacitance
O W reliable feedback compensation. W 00 Y M
W W . 1 . C .T W . 1 C O .TW
is 10µF at least. However,
W Y of the input
M
voltage
W W Y . M
Copyright W
W
ANPEC Electronics . 100 Corp..CO . T W
12 W W . 1 0
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Copyright W
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ANPEC Electronics . 100 Corp..CO .T W
13 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
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Copyright W
W .
ANPEC Electronics 100 Corp..CO .T W
14 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
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Copyright W
W .
ANPEC Electronics 100 Corp..CO . T W
15 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 . C .T W . 1 C O .T W
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Copyright W
W .
ANPEC Electronics 100 Corp..CO .T W
16 W W . 1 0
0www.anpec.com.tw
. C O .T W
Rev. A.1 - Aug., 2011
W W 00Y O M W W 00Y M
W . 1 .C .T W . 1 C O .T W
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W . 1 C O . T W W . 1 C O T W
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