University of Essex

School of Computer Science and

Electronic Engineering

CE162 Digital Electronic

Systems
Assignment A2
Asynchronous Serial Data Transmission

CONTENTS

Design and simulation using Multisim

Assessment

1
Introduction

The assignment is an open-ended design exercise to implement the Transmit part of the
RS232 serial data transmission process that was formerly the main method of computer
communication, both machine-to-machine and machine-to-user. It is still available in the form
of the COM ports of most PCs, and can be implemented on those where the ports are absent
by inserting a USB interface unit. Unlike more recent developments in serial data transmission
to and from computers, like USB and FireWire, RS232 is relatively uncomplicated, and hence
straightforward to implement in a hardware laboratory or a simulator environment.

The details of the signal format are discussed in the CE162 lecture notes, Section 1 starting at
page 1.27, to which you should refer.

This document is not an instruction manual on how to implement the system, but gives
advice on possible ways of doing it using standard logic devices, like gates, counters and
multiplexers. You should also research the Internet where complete designs are likely to be
found (this is a fairly popular design exercise in university Engineering departments!). However,
these should be treated with extreme caution: past experience suggests that some of the
'designs' are not all they seem, and after detailed examination can be shown not to work as
intended. Any external sources that you do eventually use in your design should, of course, be
acknowledged and referenced in the usual way, and you should explain how it works in your
report.

In weeks 19-21, you are asked to design and implement a system using the CAD package
Multisim. The test characters must, of course, be from the printable ASCII range.

Staff and a postgraduate demonstrator will be available in scheduled laboratory sessions, but
you can, of course, work at any other time. Out-of-session queries can be emailed to Nikolaos
Thomos; where appropriate a response will be copied to all members of the CE162 group.

Taking it a bit further?

1. A possible extension to the basic hardware system is to provide an 'exerciser' in the form of
an 8-bit counter that generates the full 8 bit binary sequence 0000 0000 – 1111 1111. Fed to
the terminal emulator you should at some stages of the count see 'sensible' character
sequences, at other times random graphic characters or nothing. Terminal emulators usually
offer a 'data capture' or 'log' mode which records raw binary input to a serial port; this can
subsequently be examined using a file probing utility like 'od' on a Linux system.

2. Investigate how to do the Receive part of the process, i.e. detect the Start Bit and generate
the appropriate clock waveform to capture the serial input sequence onto a parallel 8 bit
register.
Getting started

Multiplexer

The name 'multiplexer' comes from its original application as a way of transmitting digital data
from a number of sources down a single channel, by enabling each source in turn onto the
channel. A multiplexer is basically a switch, in which one of inputs are routed through to the
output, Y, depending on the state of the Select inputs. A 4 to 1 multiplexer is shown in the
figure below. Input I0-I3 are the data inputs (they contain the information which should be
switched) and Select inputs S0 and S1 (S1 being the most significant bit), which are used to
select data inputs to the output Y. Input G enables or disables the whole device, and can be
used when multiplexers are cascaded to handle more inputs.

Four input Multiplexer

Data inputs
Output, Y
I0

I1
MUX
I2

I3
S1 S0

Select inputs A B Strobe/enable

G

The total expression for the output Y is given by

Y = I0 A B G + I1 A B G + I2 A B G + I3A B G (1)
More details regarding the operation of a multiplexer can be found in Section 3 (page 16 and
onwards) of the module.

Familiarization with multiplexer operation

Use a Word Generator to create a 4 bit data input. Then connect the corresponding outputs of
the Word Generator to the data inputs of the multiplexer (use MUX_4TO1 model or build your
own multiplexer, as shown in slide 17 of Section 3). Connect the output Y of the multiplexer to
a Logic Analyser. Connect the Select inputs S1 and S0 (e.g., A and B) to switches or to a
Word Generator and generate Select inputs S1S0 that correspond to numbers digital numbers
0, 1, 2, and 3. Does the output Y correspond to equation (1)?
Implementation of RS232 protocol - suggested methods

The illustration below reproduces the RS232 signal example from the lecture notes – note that
the output polarity is negative (- 4 V) for a Logic 1.

The system is essentially a parallel to serial converter, and can work in the following
sequence.

1. Capture data byte (ASCII character) to be transmitted onto an 8 bit register

2. Output one start bit.

3. Output data bits 0 to 7 (in that order, i.e. LSB first)

4. Output one (or more) stop bits – this is the RS232 quiescent or 'resting' state.

5. Done.

There are two possible implementations, but you should implement only one of them.
A. Implementation using a multiplexer* (recommended method!)

1. Load data into a parallel-in, parallel-out shift register.

2. A 16 to 1 multiplexer (10 bits are used to implement the RS232 protocol, while the last 6
bits unused) has input 0 connected to logic 0 (start bit), bits 1 to 8 connected to the shift
register and bit 9 connected to logic 1 (stop bit). Remaining (spare) bits also connected
to logic 1. (In your design, you should use 74LS151 or 74LS150N, which is 16 to 1
multiplexer.)

3. Multiplexer output is inverted and level shifted to fit the RS232 format.

4. To transmit a character (ASCII character from the printable range), a trigger pulse resets
a counter to zero, which then generates the output sequence 0000, 0001, 0010,...,1001,
i.e. 0 to 9. It stops counting on 1001, and remains in that state until reset to zero. The
counter clock runs at the selected Baud rate, e.g., 9600 Hz.

5. The counter trigger pulse needs to be synchronous with the main timing clock.

6. Counter outputs feed the multiplexer Select inputs to control the multiplexer.

7. Retiming of the multiplexer output with a D-type flip-flop may be necessary to

eliminate 'glitches' at bit transitions. (Where might these come from?)

B. Implementation using a Shift Register

A 10-bit parallel-in, serial-out shift register is loaded with the data byte in parallel to bits 1 to
8. Bit 0 is always loaded with Logic 0 and bit 9 is always loaded with Logic 1 (by hardwiring
the inputs). You must generate your own parallel-in, serial-out shift register and not use
existing implementations.

The shift register is set to serial output mode, and is assumed to output bit 0 first. A counter
generates a sequence of 10 clock pulses. The shift register's serial output is inverted and
level- shifted to RS232 to form the output signal in the correct format.

In the Multisim implementation you can use any available TTL-family devices.

The 'count to 9 and stop' element (4 above) is probably the heart of the system, followed by
the multiplexer. The counter should be designed and tested first. The multiplexer can be
tested separately, with its Select inputs coming initially from bit patterns stored in the Word
Generator. The Logic Analyser should monitor the serial output to confirm that the bit
sequence is correct.

Assessment

Your CAD work along with a short report explaining the functionality of your CAD design
must be submitted through FASER. The assignment is worth 10% of the marks for the
module.

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