Task 3 - CMOS NAND and NOR

Nikhil Subramanian
18BEC0711
Objectives-
1. NAND and NOR implementation using static CMOS
2. Calculating propagation delay and average power
dissipation
CMOS NAND

Circuit diagram-

Propagation delay-
Fall time Output:100.1315 ns Rise time output:112.71027 ns
Fall time Input:100.0625 ns Rise time Input:112.6781 ns
Difference: 0.069 ns Difference: 0.0231 ns
Propagation Delay=(Rise time+fall time)/2= 4.6 ps

Power Dissipation-

Power dissipated = 444nW

CMOS NOR-

Circuit diagram-
Propagation delay-

Fall time Output:50.078 ns Rise time output:37.6956 ns

Fall time Input:50.0626 ns Rise time Input:37.6875 ns
Difference: 0.0154 ns Difference: 0.0081 ns
Propagation Delay=(Rise time+fall time)/2= 0.01175 ps

Power Dissipated-