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ECEN474/704: (Analog) VLSI Circuit Design Spring 2018: Lecture 5: Layout Techniques
ECEN474/704: (Analog) VLSI Circuit Design Spring 2018: Lecture 5: Layout Techniques
Spring 2018
Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• HW1 is due today
• Exam1 is on 2/13
• 11:10-12:35PM (10 extra minutes)
• Closed book w/ one standard note sheet
• 8.5”x11” front & back
• Bring your calculator
• Covers material through lecture 5
• Previous years’ Exam 1s are posted on the website for
reference
• Reference Material
• Razavi Chapter 18 & 19
2
Agenda
• MOS Fabrication Sequence
• Layout Techniques
• Layout Examples
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P+ N+ P+
N-Well
Substrate is always connected
to the most negative voltage,
and is shared by all N-type
transistors
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MOS Fabrication Sequence
[Razavi]
5
MOS Fabrication Sequence
[Razavi]
6
MOS Fabrication Sequence
[Razavi]
“Front-End”
“Back-End”
• A “silicide” step, where highly
conductive metal is deposited
on the gate and diffusion
regions, reduces transistor
terminal resistance
• To prevent potential gate-
source/drain shorting an “oxide
spacer” is first formed before
silicide deposition
7
Contact and Metal Fabrication
[Razavi]
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Transistor Geometries
• -based design rules allow a process and feature size-
independent way of setting mask dimensions to scale
• Due to complexity of modern processing, not used often today
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Bulk
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X
Design Rule Basics d
X X
Metal
d
n+
n+
Implanted dopants
p, Na p, Na (a) Contact size
(a) Mask definition (b) After annealing Metal
S
n+ n+
Poly gate
Active
W
poly
Poly gate
substrate substrate substrate
W
Gate spacing form an (a) Resist pattern (b) Isotropic etch (c) anisotropic etch
n+ edge
Effect12 of misalignment without overhang
ECEN-474-2009 Jose Silva-Martinez
1 NWELL Nselect
Poly
2 ACTIVE Active
W'
W
3 POLY
L'
4 SELECT Side View
5 POLY CONTACT
6 ACTIVE CONTACT
7 METAL1 n+
L
n+
8 VIA FrontView
9 METAL2
Difference between the drawn and physical
10 PAD
values for channel length and the channel
11 POLY2 width
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n+ n+ p+ Gate Oxide p+
Gate Oxide
n-well Bulk
p substrate p substrate
Bulk Bulk
Gate
(a) Cross section Gate
Bulk Bulk
n+ Poly n+
W
Stick Diagrams
D
Poly
G
Metal 1
N+/P+
Contact S
VDD
VDD VDD
Mp Mp In
Mp
Vin Vout
In Out
Out
Mn Mn
Mn
Gnd Gnd
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Mp Mp In
Mp
Vin Vout
In Out
Out
Mn Mn
Mn
Gnd Gnd
Wp
Lp
N-Well
Metal
Metal VDD VDD p+
n+
Lp pFET
pFET
Wp
Metal Out
p+
nFET Poly In
WN
nFET
LN
Metal GND
n+
WN
LN
B MpB MpA
Vo
MnB
Out
A MnA
n+
CMOS NAND2 logic gate
A B nFET
Metal GND
Metal VDD
MpA pFET
p+
MpB
Vo Out
A B nFET
MnA MnB
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Transistor orientation
• Orientation is important in analog circuits for matching purposes
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Stacked Transistors
Drain
Gate
Source
Matched Transistors
• Simple layouts are prone to process variations, e.g. VT, KP, Cox
• Matched transistors require elaborated layout techniques
M1 M2
Drain M1 Drain M2
Source
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Interdigitized Layout
• Averages the process variations among transistors
• Common terminal is like a serpentine
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Why Interdigitized?
M1 M2 M2 M1 M1 M2 M2 M1
M1: 8 transistors
M2 M1 M2 M1 (0,3) (0,1)
2
(1,2) (1,0)
(2,3) (2,1)
(3,2) (3,0)
1 M1 M2 M1 M2
M2: 8 transistors
(0,2) (0,0)
M2 M1 M2 M1 (1,3) (1,1
0 (2,2) (2,0)
(3,3) (3,1)
0 1 2 3
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Integrated Resistors
• Highly resistive layers (p+, n+, well or polysilicon)
L
• R defines the resistance of a square of the layer R
Wt
• Accuracy less than 30% L
Current flow t
Resistivity (volumetric
measure of material’s
resistive characteristic)
(-cm) W
L
Sheet resistance (measure
of the resistance of a R = /t ( )
uniform film with arbitrary W
thickness t
L
# Squares
W
W R = 2Rcontact + (L/W) R
L
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Diffusion/Well Resistors
Diffused resistance
p-substrate
Diffused resistance
well resistance
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Poly Resistors
First polysilicon resistance
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Special poly sheet resistance for some analog processes might be as high as 1.2 K/
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Large Resistors
In order to implement large resistors :
• Use layers with high sheet resistance (bad performances – see previous table)
•High temperature coefficient and non-linearityt
L L
R R
W W xj
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Well-Diffusion Resistor
• Example shows two long resistors for K range
• Alternatively, “serpentine” shapes can be used
• Noise problems from the body
• Substrate bias surrounding the well
• Substrate bias between the parallel strips
Dummies
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Plastic packages cause a large pressure on the die (= 800 Atm.). It determines a variation of
the resistivity.
For <100> material the variation is unisotropic, so the minimum is obtained if the resistance
have a 45o orientation. compensated
Temperature :
uncompensated
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Etching
Boundary :
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MOS Capacitors
[Razavi]
38
Integrated Capacitors
Poly - Diffusion Poly - Poly Metal1 - Poly
[Razavi]
Vertical Metal “Sandwich” Lateral Metal-Oxide-Metal (MOM)
[Wang]
[Ho]
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Poly 2
Poly 1
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C1 C1,ideal 1 e1
C2 C2,ideal 1 e2
• To minimize the error in the cap ratio, we need to have
e1=e2. This implies that the Perimeter/Area should be equal.
• Generally, we break up both caps C1 and C2 into square unit
caps, Cu
Au xu2
43
Capacitor Matching
• If both C1 and C2 are integer multiples of Cu, then simply
use I1 unit caps for C1 and I2 unit caps for C2
C1 I1Cu
C2 I 2Cu
N1xu2 N 2 xu2
xnu1 xnu 2
ynu1 ynu 2
ynu1 xu N1 N 12 N1
ynu 2 xu N 2 N 22 N 2
Although, generally we have the flexibility to size Cu to set
C1 I1Cu
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Approximate Common Centroid Structure
C1 C2 C3 C4 C5
C2 = C1
C3 = 2C1
C4 = 4C1
C5 = 8C1
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“Floating” Capacitors
Be aware of parasitic capacitors
poly2
Polysilicon-Polysilicon: Bottom plate
CP1 C1 CP2’’
capacitance is comparable (10-30 %) poly1
with the poly-poly capacitance CP2’
substrate
C1
CP1, CP2’’ are very small (1-5 % of C1)
CP1 CP2’ is around 10-50 % of C1
CP2
metal2
Metal1-Metal2: More clean, C1
but the capacitance per
CP1 metal1
micrometer square is smaller. CP2 Thick oxide
Good option for very high
frequency applications ( C~ 0.1- substrate
0.3 pF).
CP2 is very small (1-5 % of C1)
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• Respect symmetries
• Potential for parasitic BJTs (Vertical PNP and Lateral NPN) to form a
positive feedback loop circuit
• If circuit is triggered, due to current injected into substrate, then a
large current can be drawn through the circuit and cause damage
• Important to minimize substrate and well resistance with many
contacts/guard rings
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Transistors with even number of parts have the source (drain) on both
sides of the stack
Transistors with odd number of parts have the source on one end and the
drain on the other. If matching is critical use dummies
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M3 M6 M6 M6 M6 M4
M3 M4
M6 C
M1 M2 M1 M2 M1 M2
M1 M2
M8
M5 M5 M7 M7 M7 M7 M5 M8
M7
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VDD
Vi+
Vi-
Ibias
Vo
VSS
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VDD
D M3 M4x2 M3 D D M8x6 D
D M4 M3x2 M4 D D M8x6 D
D M3 M4x2 M3 D D M8x6 D
M1x2
Vi+ D M1 M2x2 M2x2 M1 Dx7
Vo
VSS
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Capacitive network
Resistive network (Common centroid)
Fully differential
amplifier
From downstairs
Differential pair
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Q-value of Spiral
Inductors in CMOS
Process
Most of the following slides were taken from
TAMU, 2003
68
What is Q?
energy stored
Q
average power dissipated
Ls
Q
Simple Inductor Model: Rs
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Equivalent Circuit & Calculation
Cs
9
Q-factor
Port1 Ls Rs Port2 8
6
Cox1 Cox2 5
2
Csub Rsub Csub Rsub 1
0
0 1 2 3 4 5 6
Frequncy (GHz)
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Layout & Structure
Metal-6
(thickness=2um)
Metal-5
under path
N : # of Turns
Via-5
R : Radius
Oxide
Substrate
S : Space W : Width
(=1.5um) (=14.5um)
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Layout Split 1
Shape & Radius
9
Q-factor
8 NxWxS
square (R=60)
(4.5x15x1.5)
7
5
octagon (R=60)
3
square (R=60)
2 octagon (R=60) square (R=30)
square (R=30)
1
octagon (R=30)
0
0 1 2 3 4 5 6 octagon (R=30)
Frequncy (GHz)
8
Q-factor none
NxRxWxS
(4.5x60x15x1.5)
7
6
nwell
5
3
none poly
2 nwell
poly
1
metal1
0
0 1 2 3 4 5 6
metal 1
Frequncy (GHz)
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poly PGS(wide)
6
4
SGS poly
3
none
2 poly PGS(wide)
nonsal poly SGS
1 nonsal poly PGS nonsal poly SGS
poly PGS
0
0 1 2 3 4 5 6
Frequncy (GHz) poly PGS
• GS : Poly PGS > Poly(nonsal) SGS > Poly(nonsal) PGS > none
PGS = patterned ground shield
SGS = solid ground shield
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Metal Stack
9
8 Q-factor
NxRxWxS
7 (4.5x60x15x1.5)
5
M6
4
3 M 5/6
M6
2 M 5/6
M 4/5/6 M 4/5/6
1
M 3/4/5/6
0
0 1 2 3 4 5 6 M 3/4/5/6
Frequncy (GHz)
76
TAMU Mixed-Signal Research Chip
• A 10 Gb/s Hybrid ADC-Based Receiver w/ Embedded Analog
and Per-Symbol Dynamically Enabled Digital Equalization
• 10GS/s asynchronous SAR
ADC with embedded 3-tap FFE
• Digital equalizer with 4-tap
FFE and 3-tap DFE
• Fabricated in GP 65nm CMOS
BER w/ 36.4dB Loss Channel
A. Shafik et al, “A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm
CMOS,” ISSCC 2015.
A. Shafik et al, “A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization,” JSSC 2016. 77
Next Time
• Current Mirrors
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