Chapter 1

Sequential circuits

A block diagram of a sequential circuit (Mealy model) is shown in Figure 1.1. It

consists of a combinational circuit to which memory elements (flip-flops (FFs)) are
connected to form a feedback path. The memory elements are devices capable of
storing binary information within them. The binary information stored in the
memory elements at any given time defines the state of the sequential circuit. The
sequential circuit receives binary information from external inputs. These inputs,
together with the present state of the memory elements, determine the binary value
at the output terminals. They also determine the condition for changing the state in
the memory elements.
External inputs
outputs
Combinational circuit Next state
Memory
condition
Elements
( FFs)

Clock pulse
Present state

(a)

(b)

Figure 1.1 (a) Block diagram of a synchronous sequential

circuit (Mealy Model) (b) Timing diagram of clock pulses.

There are two main types of sequential circuits:

Synchronous and asynchronous sequential circuits
1. Synchronous sequential circuit, Figure 1.1(a) employs signals that affect the
storage elements only at discrete instants of time. Synchronization is achieved by a
timing device called a clock generator that produces a periodic train of clock pulses,
Figure 1.1(b). The outputs of storage elements can change their value only in the
presence of the clock pulses. Synchronous sequential circuits that use clock pulses as
inputs to storage elements are called clocked sequential circuits. As a result, a
transition from one state to other occurs only at fixed time intervals dictated by the
clock pulses, giving synchronous operation.
2. Asynchronous sequential circuit behavior depends upon the order in which its
input signals change and can be affected at any instant of time and it does not uses
clock pulses.

1
Mealy and Moore models
Mealy and Moore are two models that are used for implementing synchronous
sequential circuits. Sequential circuits, in which the outputs depend on the inputs, as
well as, on the present states, are referred to as Mealy model circuit, Figure 1.1(a).
On the other hand, if the outputs depend only on the present states, the circuits are
referred to as Moore model circuit as shown in Figure 1.2. Each model is named
after its originator.
External
inputs
Combinational circuit
Next state Memory
(CC) outputs
condition Elements CC
(FFs)

Clock pulse
Present state

Figure 1.2 Block diagram of a synchronous sequential circuit (Moore Model)

Memory Elements
Basic latches’ circuits
A latch is a binary storage device that is capable of storing one bit of information. A
latch circuit can be constructed from two NAND gates or two NOR gates, as shown in
Figures 1.3(a) and 1.3(b), respectively. How these two latches operate are shown in
the truth tables 1.1 and 1.2 for NAND and NOR latch, respectively.
The truth table for the NAND latch can be derived as follows. First, as shown
in Table 1.1 assume S (Set) = 1 and R (Reset) = 0. Since, 0 input to NAND gates is
considered a dominant signal, it forces the output of an NAND gate to 1 regardless of

S (set)
Q

Q
R (reset)

Figure 1.3(a) Basic RS latch circuit with NAND gates

S R Q Q
1 0 0 1 (Reset state)
1 1 0 1 (no change)
0 1 1 0 (Set state)
1 1 1 0 (no change)
0 0 1 1 (undefined)
Table 1.1 Truth table for Figure 1.3(a)
2
 R (reset)
Q

Q
S (set)
Figure 1.3(b) Basic RS latch circuit with NOR gates

S R Q Q
1 0 1 0 (set state)
0 0 1 0 (no change)
0 1 0 1 (reset state)
0 0 0 1 (no change)
1 1 0 0 (undefined)
Table 1.2 Truth table for Figure 1.3(b)
the other inputs thus we must first consider the effect of the input R. R = 0 forces the
output Q to be 1. This output is fed back to the NAND gate whose output is Q and
since both inputs to the NAND gate are 1, then the output Q evaluates to 0 (reset
state). When both S and R signals are 1 the output Q of the latch remains
unchanged. On other hand, S = 0 and R = 1 force Q to evaluate to 1 since S = 0 and Q
to 0 giving a set state. When both S and R signals to the latch are 0, the state of the
latch becomes undefined because this input combination requests at the same time
to set and rest the latch which is ambiguous and therefore not acceptable and
should be avoided.
Similarly, the truth table for the NOR latch can be derived by taking the input
with value 1 as the dominant signal when evaluating the latch circuit and its effect
should be considered first.
Figure 1.3(c) gives a timing diagram for the basic latch built with (NOR) gates,
assuming that the propagation delay through the NOR gates is negligible.

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

1
R
0

1
S
0

1
Q ?
0

1
Q ?
0

Figure 1.3(c) Timing diagram for NOR latch

3
Clocked (gated) SR latch
The basic latch as it stands is asynchronous sequential circuit. By adding gates to the
inputs of the basic latches of Figure 1.3, it can be made to respond to input levels
during the occurrence of a clock pulse. Two clocked RS latches, which are obtained
by modifying latches of Figure 1.3, are shown in Figure 1.4. The function table for
both latches is shown in Table 1.3.

S (set)
Q

clk (clock)

Q
R (reset)

Figure 1.4(a) SR latch with control input (clock)

R (reset)

Q
S Q
clk clk (clock)
R Q
Q
SR logic symbol
S (set)

Figure 1.4(b) SR latch with control input ( clock)

clk S R Q(t+1)
0 x x Q(t) (no change)
1 0 0 Q(t) (no change)
1 0 1 0 (reset state)
1 1 0 1 (set state)
1 1 1 (undefined)
Table 1.3 Function table for Figure 1.4

A timing diagram for the clocked SR latch is shown in Figure 1.4(c). It shows
clock as a periodic signal that is equal to 1 at regular time interval and this how the
clock signal usually appears in a real system. The undefined state where S = R = 1
must be avoided in practice since the normal operation of the latch will have the
outputs as complements of each other.

4
 1
clock
0
1
R
0
1
S
0
1
Q ?
0
1
Q ?
0

Timing
Figure 1.4(c) Timing diagram for clocked SR latch

Clocked (Gated) D latch

One way to eliminate the undesirable undefined state in the clocked SR latch of
Figure 1.4 is to ensure that S and R inputs are never equal to 1 at the same time. The
SR latches of Figure 1.4 can be modified as shown in Figure 1.5 to give a new latch
called D latch where the undefined state is eliminated by first inverting the input R
and then combining it with input S to form one input D.

D
Q
D Q
clk
clk
Q Q
D latch logic symbol
Figure 1.5(a) D latch logic diagram (NAND gates)

clk

Figure 1.5(b) D latch logic diagram ( NOR gates)

5
 clk D Q(t+1) next state of Q(t)
0 x Q(t) (No change)
1 0 0 (Reset state)
1 1 1 (Set state)
Table 1.4 D latch function table

Clocked JK latch
A JK latch is a refinement of the clocked RS latches of Figure 1.4 in which the
indeterminate (undefined) state of the RS latch, which occurs when both S and R
inputs are 1, is defined in the JK latch where Q is made to toggle as shown in Figure
1.6. In Figure 1.6, the letters J and K stand for set and reset (clear), respectively.

J
Q
J Q
clk clk
K Q
Q
JK logic symbol K

Figure 1.6(a) JK latch (NAND gates)

K (reset)
Q

clk

Q
J (set)

Figure 1.6(b) JK latch ( NOR gates)

J K Q(t+1)
0 0 Q(t) (No change)
0 1 0 (Reset)
1 0 1 (Set)
1 1 Q (Toggle)
Table 1.5 Function table For JK latch

6
To show that the undefined state of the SR latch is defined in the JK latch we use
Table 1.3. All the entries in Table 1.3 remain unchanged for the JK latch except the
entry where both inputs are high. This condition is undefined in SR Latch and is
defined in the JK Latch. To show that this is true assume the output Q of the JK of
Figure 1.6 (a) is high and both its inputs J and K are high. When a clock pulse is
applied the output of the upper NAND gate, connected to the J input, changes to 1,
whereas the output of the lower NAND gate connected to the K input becomes zero.
This zero forces the output of the JK labeled Q to be 1, that is, it changes its state
from 0 to 1 (which means toggle). Now, since both inputs of the upper NAND gate
connected to the output Q are 1 then Q evaluate to 0 that is changes its state from
1 to 0 (toggle).
Similarly, assume Q is 0 and follow the same steps to show that it changes its
state from 0 to 1 (toggle). Thus, this proves that the undefined state in SR latch is
defined in the JK latch.

T latch
The T latch is a single input version of JK latch. As shown in Figure 1.7, the T latch is
obtained from a JK latch if both inputs are tied together. The designation T comes
from the ability of the latch to "Toggle", or change state.

T
Q
T Q
clk
clk
Q
Q
T logic symbol

Figure 1.7(a) T latch logic digram (NAND gates)

T
Q
T Q(t + 1)
0 Q(t ) clk
1 Q(t )
Function table Q

Figure 1.7(b) T latch logic diagram ( NOR gates)

7
Master-slave and Edge-triggered D flip-flops
All latches we have studied so far are responsive or sensitive to pulse duration of the
clock. That is, in these level-sensitive latches, the state of the latch keeps changing
according to the values of input signals during the period when the clock signal is
active. The result is an unpredictable situation, since the state may keep changing
and continue to change until the clock signal becomes inactive. Because of this
unreliable operation, the output of a latch cannot be applied directly to the input of
another latch when all the latches are triggered by a single clock signal. Thus, there is
a need for storage elements that can change their states no more than once during
one clock cycle. We will next study two types of circuits that exhibit such behavior:
Master-slave D flip-flop and Edge-triggered D flip-flop.

1. Master-slave D flip-flop
Consider the circuit given in Figure 1.8(a), which consists of two gated D latches. The
first, called master, changes its state while clock = 1. The second, called slave,
changes its state while clock = 0. The operation of the circuit is such that when the
clock is high, the master tracks the value of the D input signal and the slave does not
change. Thus the value of Qm follows any changes in D, and the value of Qs remains
constant. When the clock signal changes to 0 the master stage stops following the
changes in the D input. At the same time, the slave stage responds to the value of
the signal Qm and changes state accordingly. Since Qm does not change when clock =
0, the slave stage can undergo at most one change of state during a clock cycle. From
the external observer's point of view, namely, the circuit connected to the output of
the slave stage, the master-slave circuit changes its state at the negative-going edge
of the clock. The negative edge is the edge where the clock signal changes from 1 to
0. Regardless of the number of changes in the D input to the master stage during one
clock cycle, the observer of the Qs signal will see only the change that corresponds
to the D input at the negative edge of the clock.
To obtain a DFF that responses to the “positive edge” of the clock pulse,
connect the inverter of Figure 1.8(a) to the master instead of the slave D latch. This
would allow the master to change its state while the clock = 0 and the slave while
the clock = 1.
The circuit in Figure 1.8 is called a master-slave D flip-flop. The term flip-flop
denotes a storage element that changes its output state at the edge of a controlling
clock signal. The timing diagram for this flip-flop is shown in Figure 1.8(b). A graphical
symbol is given in Figure 1.8(c). In the symbol we use the > mark to denote that the
flip-flop responds to the "positive edge" of the clock whereas a bubble placed on the
clock input indicates that the circuit responds to the negative edge of the clock.

8
 Master slave
D D Q Qm D
Qs Q

clock D Q
clk Q clk Q
clk
Q

(a) circuit (c) Graphical symbol

clock

Qm

Q = Qs

(b) Timing diagram

Figure 1.8 Mater-slave D flip-flop

2. Edge-triggered D flip-flop
The output of the master-slave D flip-flop in Figure 1.8(a) responds on the negative
edge of the clock signal. The circuit can be changed to respond to the positive clock
edge by connecting the slave stage directly to the clock and the master stage to the
complement of the clock. A different circuit that accomplishes the same task is
presented in Figure 1.9(a). It requires only six NAND gates and, hence, fewer
transistors. The operation of the circuit is as follows. When clock = 0, the outputs of
gates 2 and 3 are high. Thus, P1 = P2 = 1, which maintains the output latch,
comprising gates 5 and 6, in its present state. At the same time, the signal P3 is equal
to D, and P4 is equal to its complement D . When clock changes to 1, the following
changes take place. The values of P3 and P4 are transmitted through gates 2 and 3 to
cause P1 = D and P2 = D and that sets Q = D and Q = D . To operate reliably, P3 and
P4 must be stable when clock changes from 0 to 1. For that to occur the data to be
clocked into a flip-flop must be stable t su time before the active clock edge and must
remain stable t h time after the clock edge. Hence, from the figure, the setup time t su
of the flip-flop is equal to the delay from the D input through gates 4 and 1 to P3. The
hold time ( t h ) is given by the delay through gate 3 because once P2 is stable; the
changes in D no longer matter. The delay of the gate 3 is taken as t h because it has
three inputs and that implies its delay is greater than that of gate 2 which has two
inputs.

9
 1 P3

P1
2
5 Q

clk

P2 6 Q
3

D Q

4 P4 clk
D Q

(a) circuit (b) Graphical symbol

Figure 1.9 positive-edge-triggered D flip-flop

For proper operation it is necessary to show that, after clock changes to 1, any
further changes in D will not affect the output latch as long as clock = 1. We have to
consider two cases. Suppose first that D = 0 when the clock is inactive (clock = 0).
Since, clock = 0, P1 = P2 = 1. Then at the positive edge of the clock P2 = 0, which
will keep the output of gate 4 equal to 1 as long as clock = 1, regardless of the value
of the D input. The second case is D = 1 when the clock is inactive (clock = 0). Then
at the positive edge of the clock P1 = 0, which forces the outputs of gate 1 and gate 3
(P2) to remain at 1, regardless of the changes in the D input. That is, the flip-flop
ignores changes in the D input while clock = 1.
Figure 1.9(b) gives a graphical symbol for this flip-flop. The clock input
indicates that the positive edge of the clock is the active edge. A similar circuit,
constructed with (NOR) gates, can be used as a negative-edge-triggered flip-flop.

Clock Clock

D D
t su th t su th
a) Ideal (no clock delay) b) Real (taking into account clock delay)

Setup time and Hold time for DFF

Level-sensitive versus Edge-triggered storage elements

Figure 1.10 shows three different types of storage elements that are driven by the
same data and clock inputs. The first element is a gated D latch, which is level
sensitive. The second one is a positive-edge-triggered D flip-flop, and the third one is
a negative-edge-triggered D flip-flop. To accentuate (illustrate) the differences

10
between these storage elements, the D input changes its values more than once during
\each half of the clock cycle. Observe that the gated D latch follows the D input as
long as the clock is high. The positive-edge-triggered flip-flop responds only to the
value of D when the clock changes from 0 to 1. The negative-edge-triggered flip-flop
responds only to the value of D when the clock changes from 1 to 0.
D Qa
D Q
clk

Q Qa

D Q Qb

Q Qb

D Q Qc

Q Qc

(a) Circuit

clk

Qa

Qb

Qc

(b) Timing diagram

Figure 1.10 Comparison of level-sensitive and edge-

triggered D storage elements.

D flip-flops with clear and preset

Flip-flops often provide special inputs for setting and resetting them asynchronously,
i.e., independently of the clock. The input that asynchronously set the flip-flop is
called set, or preset. The input that asynchronously reset the flip-flop is called reset,
or clear. When power is turned on in a digital system, the states of its flip-flops can be
anything. The reset and preset signals are useful for bringing all flip-flops in a digital
system to an initial state prior to the normal clocked operation.
Figure 1.11(a) shows a Master-slave D flip-flop with Clear and Preset signals
added. Placing a 0 on the Clear input will force the flip-flop into the state Q = 0. If

11
Clear = 1, then this input will have no effect on the flip-flop. Similarly, Preset = 0
forces the flip-flop into the state Q = 1, whereas, Preset = 1 has no effect. To denote
that the Clear and Preset inputs are active when their value is 0, we placed an over
bar on the names in the figure. For proper operation of the flip-flop both Clear and
Preset signals should not be 0 at the same time. A graphical symbol for this flip-flop
is shown in Figure 1.11(b).
To show that the Preset and the Clear signals of the master-slave D FF of
Figure 1.11a function properly, we start by assuming the Clear signal 0 (active) and
the Preset signal 1 (inactive). Since Clear = 0, it will force Q to be 1 and P 4 =1 (the
output of gate 4). Now two inputs of gate 7 are 1, one through Q and the other by the
Preset signal. However, for Q to be 0, the input labeled P5 (the output of gate 5)
which is the third input to gate 7, must be 1. For the above situation, we need to
consider two cases. One when the clock is low and the other when it’s high. The clock
low will cause ( P1 ), the output of gate 1, to be 1. Since, all inputs to gate 3 are now 1,
its output P3 will be 0. That sets ( P5 ), the output of gate 5, to 1. Now all inputs to
gate 7 are 1 and that forces Q to be 0 as require.
Now consider the second case when the clock is high. This will cause the
output of the inverter, which is input to gate 5, to be 0. This is in turn will cause P5 ,
the output of gate 5, to be 1. Now, since all inputs to gate 7 are 1, the output Q will
be 0 as require. Thus, we conclude that Q remains 0 as long as the Clear signal is
active regardless of the position of the clock input (high or low).
preset

D P1 P3 P5
Preset 1 3 5 7 Q

clk
D Q
P6
2 4 6 8 Q
clk
P4
Q
Clear Clear

(b) Graphical symbol (a) Circuit

Figure 1.11 Master-slave D flip-flop with Clear and preset

For the preset case, we set Preset signal 0 (active) and the Clear signal 1
(inactive). The active Preset signal will cause both P3 and Q signals to be 1. Now we
need to show that Q is 0. To show that we need to consider two case when the clock
is high and when it’s low. When the clock is high, the output of the inverter will be 0,
and that will cause P6 , the output of gate 6, to be 1. Now, since all inputs to gate 8 are
1, its output will be 0 as require. Now consider the second case, when the clock is
low. This will cause the output of gate 2 to be 1. Now, since all inputs to gate 4 are 1,
its output P 4 will be 0 and that in turn will cause P6 , the output of gate 6, to be 1. At
this moment, all the three inputs to gate 8 are 1 and that will reset Q signal 0 as

12
require. We conclude that the active Preset signal sets the FF 1 regardless of the clock
positions.
A similar modification is done on the edge-triggered flip-flop of Figure 1.9(a),
as indicated in Figure 1.12(a). Again, both clear and Preset inputs are active low and
at any time only one signal should be active Preset or Clear but not both. For the FF
to operate as a synchronous FF both Preset and Clear should be equal 1 (inactive).
The output Q of the D FF then responds to the changes in D only synchronous with
the clock input and performs its intend function.
Similarly, as we done with the master-slave D FF with Clear and Preset we
need to show that the Preset and the Clear signals of the edge triggered D FF shown
in Figure 1.12 perform their intended function. We begin by assuming the Clear
signal 0 (active) and the Preset signal 1 (inactive) to see that if the FF would be
cleared. Asserting the Clear signal 0 will force Q , the output of gate 6 to be 1, which
also is fed back as an input to gate 5. The active Clear signal will also cause P1 , the
output of gate 2, to be 1. Now, since all the three inputs to gate 5 are 1, its output Q
will be 0. Thus, the Q signal, which reflects the value stored in the FF, remains 0 as
long as the Clear signal is active regardless of the clock positions.

preset
1 P3

P1
2
5 Q

clk

P2 6 Q Preset
3

D Q

clk
D 4 P4 Q

Clear Clear

(a) circuit (b) Graphical symbol

Figure 1.12 Positive-edge-triggered D Flip-flop with Clear and Preset

On the other hand, to show that the Preset signal performs its function
properly, we begin by asserting the Preset signal 0 (active) and the Clear signal 1
(inactive). Asserting the Preset signal low will force Q , the output of gate 5, to 1 (set
state) which also is fed back as input to gate 6. At that moment, the output of gate 6
should be 0. To show that this is the case. We first consider the clock is low.
Asserting the clock signal low forces P 2 , the output of gate 3, to be 1. Now, since all
inputs to gate 6 is high its output Q will be low as require. Second, we consider the
clock is high which is input to gate 2. The active Preset signal causes P3 , the output
of gate 1, to be 1. Since, all inputs to gate 2, are now 1, its output P1 is 0 and that
forces P 2 , the output of gate 3, to be 1. At that moment, all the input to gate 6 are 1

13
which causes its output Q to be 0 as require. Thus, the content of the FF remains 1 as
long as the Preset signal is active, regardless of the clock positions.
The Preset and the Clear signals are asynchronous signals, that is, they change
the content of the FF immediately regardless of the clock pulses when either signal is
activated. For the FF to operate synchronously with the clock both Preset and Clear
signals should be inactive.
JK Flip-flop
The D flip-flop is a versatile storage element that can be used in any sequential circuit
design. Furthermore, by including some logic, the D flip-flop of Figure 1.9(a) can be
converted to JK flip-flop as shown in Figure 1.13(a). JK flip-flop behaves as JK latch
except that its state is affected by the input only at the active edge of the clock.

D Q
K
Q
clock

(a) circuit

J k Q(t + 1) J Q
0 0 Q(t )
0 1 0 clk
1 0 1 k Q
1 1 Q(t )
(b) Truth table (c) Graphical symbol

Figure 1.13 JK flip-flop

T Flip-flop
The T flip-flop is obtained from a JK flip-flop if both inputs are tied together as
shown in Figure 1.14(a). If T = 0, D = Q that is the state remains unchanged, Q (t+1)
= Q (t). Whereas if T = 1, then D = Q and the new state becomes Q (t + 1) = Q . Thus,
the overall operation of the flip-flop is that it retains its present state if T = 0, and
complements its present state if T = 1. The operation of the flip-flop is specified as a
function table in Figure 1.14(b) which is the same as that for T latch except that any
change in the state occurs at the active edge of the clock.

14
 D Q
T
Q
clock

(a) circuit

T Q
T Q(t + 1)
0 Q(t ) clk
Q
1 Q(t )

(b) Truth table (c) Graphical symbol

Clock

(d) Timing diagram

Figure 1.14 T flip-flop

In the previous sections, two types of memory elements are introduced: latches
and flip-flops. Latches are termed pulse or level triggered since during an active clock
pulse any change in the inputs of a latch may cause the state of the latch to change as
well. That is, the state of the latch may change several times during an active clock
pulse. Thus, for a latch to operate properly and avoid ambiguity in its state its inputs
must be set up (stable) prior to the rising edge of the active clock pulse and remain
unchanged until the falling edge of the active clock pulse.
On the other hand, flip-flops are termed edge triggered. An edge-triggered
flip-flop changes its state once either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock pulse. When the triggering occurs on the
positive going edge of the clock, it is called positive edge triggered whereas when the
triggering occurs on the negative edge of the clock it is called negative edge triggered.

15
Flip-flop and latch characteristics and excitation tables
A characteristic (or function) table defines the logical operations of a flip-flop or a
latch by describing its operation in tabular form. The characteristic tables of the four
flip-flops presented in the previous sections are shown Table 1.1. They define the next
state as a function of the inputs and present state. Q(t ) , refers to the present state and
Q(t + 1) to the next state after the occurrence of a clock pulse.

Table 1.1 Flip-Flop characteristic tables

(a) SR Flip-Flop (b) JK Flip-Flop

S R Q (t + 1) Operation J K Q (t + 1) Operation
0 0 Q (t) No change 0 0 Q (t) No change
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 ? Undefined 1 1 Q (t) Complement

(c) D Flip-Flop (d) T Flip-Flop

D Q (t + 1) Operation T Q (t + 1) Operation
0 0 Reset 0 Q (t) No change
1 1 Set 1 Q (t) Complement

The characteristic table is useful for analysis and for defining the operation of
the flip-flop. It specifies the next state when the inputs and present state are known.
During the design process we usually know the transition from present state to next
state and wish to find the flip-flop input conditions that will cause the required
transition. For this reason, we need a table that lists the required inputs for a given
change of state. Such a list is called an excitation table. Table 1.2 presents the
excitation tables for the four types of flip-flops (SR, D, JK, and T).

Table 1.2
Flip-Flop Excitation Tables

(a) SR Flip-Flop (b) JK Flip-Flop

Q (t) Q (t + 1) S R Q (t) Q (t + 1) J K
0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0

16
 (c) D Flip-Flop (d) T Flip-Flop
Q (t) Q (t + 1) D Q (t) Q (t + 1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

Assignment # 1

1.1 The D latch shown in Figure 1.5(a) can be constructed with only four NAND
gates. This can be done by removing the inverter and connecting the output of the
upper NAND gate (NAND connected to input D) to the input of the lower gate.
Show that the new circuit is functionally the same as the original one.

1.2 Given the input waveforms shown in the figure below, sketch the output, Q, of an
SR latch.

1.3 Given the input waveforms shown in the figure below, sketch the output, Q, of a
D latch.

17
1.4 Given the input waveforms shown in problem 1.3 (given below), sketch the
output, Q, of a D flip-flop.

1.5 Consider the timing diagram in the following figure. Assume that the D and Clock
inputs shown are applied to the circuit shown in Figure 1.10(a), draw waveform
for the Qa , Qb and Qc signals.

clock

Qa 0

Qb 0

Qc 0

1.6 Complete the timing diagram for this circuit.

18
 clock

Q 0

1.7 Consider the timing diagram in Figure 1.15(b). Assume that the T and Clock
inputs shown are applied to the circuit shown in Figure 1.15(a), draw waveform
for the Qa , Qb and Qc signals.

T Qa
T Q
clk clock
Q Qa

T
T Q Qb
Qa 0
Q Qb
Qb 0
T Q Qc
Qc 0

Q Qc

(a ) Circuit (b) Timing diagram

Figure 1.15

19