North South University

Department of Electrical & Computer Engineering

LAB REPORT
Course Code: CSE231L
Course Title: Digital logic design
Course Instructor: RSF
Experiment Number: 04
Experiment Name: Combinational Logic Design

Experiment Date: 23/03/2021

Date of Submission: 06/04/2021
Section: 05
Submitted To: Fowzia Shamsunnahar

Submitted By
Student Name and ID:
1. Rezuan Chowdhury Rifat 1931372642
Objecti ves;
- esig Complete minmal comdi national
log ic
m rom
System specdicatiom
omto implemen tatiom.
- Mini mi 2e com bimational logic cincuits usi
using
ng
Kan naugh maps
- heann vani ous Mumenical nepnesen tation Systes
ystems

-Implement cincuits using CAnoncal mnimal-oams.

APpanatus;

r a i nen loand

-mput AND gates

AND ates
IxTe Ao7 3 Trniple-3
OR gates
gateg
Tniple 3-inpat
-1x IC 4075
He Inventeas(NOT ate)
-Ix IC 7404
gates
NAND ates
1xTC 7400 2-input
2-i nput
AND gettes
2 x TC 7408
Cincut Diagnam

Ve

GtND
D
Minlmal Ist camomcal cincui+ s BC).
tigwne :

o Ekcess-3 Convecte
 A

uniVe nsal gate implimeation

Fig urre. Minimal

o BCD to Excess -3 Conveter.

Resus gcD Excess-3

D
Declna
W Y 2 A B C

2
6
3
A

5 6 O

1
9

Namben od inputs 4 Tmput yasnlabes. +

b1ts
Nam ber 5 outpots Otput vanl ables ;
its A
 O

X X x x
X xx
x

0
O
X
X X X X
X
X

Hiqune:k - Maps
 Dis Cussion
hous to enete numberz
Syste
We leanned

We cnected
cneated excess
e -3 nunbe
k-map
using
had to
Convet decimal
Syste.m. We
BCD We CReated tnuth
umber 1sto
A,D,C, D we Cleatted
Hoble andren Son
tnuth trble
-maP We used 9 bit on
used full
but Son KmaP

bi+. We teetted cineuit usina

by using
6
SOP nom k-map
have been Some eqmepment
Thene corld
we
ehecked all TC s
ennon. So, tinst

wwonking ine hen be

Fthe ae

eprmet
proceed o Our
Ansuwens: