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Collins 479s-6A
VOR/ILS Signal Generator
Collins Government
Avionics Division
Avionics Group
Rockwell International
Cedar Rapids, Iowa 52498
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Collins 479s-6A ,
List of EIwtive Pages *The asterisk indicates pages changed. added. or deleted by the current change
\
Record of Revisions .
o h RECEIPT OF REVISIONS INSERT REVISED PAGES IN THE MANUAL .
AN11 ENTER DATE INSERTED AND INITIALS
1 15 Oct 80 1 thru 10
C
Scans by ArtekMedia © 2008
description
I
function, the -003 status incorporates the store/ dBc Decibel below carrier
recall and an IEEE-488/1978 interface function,
and the -004 status incorporates the four IEEE-488/
1978 interface function. Unless noted otherwise, all
information in this instruction book is applicable to DDM Difference in depth of
all four statuses. modulation
PROM Programmable read only Optional growth features add stored programming
memory and/or remote programming (IEEE 488) capabili-
Digital audio waveform synthesizer provides in- VOR radial adjustable in +30, +lo, -10, +0.01, and
creased accuracy, stability, and longer calibration -0.01-degree increments.
intervals.
Preset 1020-Hz audio tone for identification signal.
Synchronous detection and advanced design
modulation loop generates precise, stable modula- Programmable audio signal with a 30-Hz to 14-kHz
tion levels. range.
I
Variable rf output level to check receiver sensitivi- The -002 status contains an A9 store/recall as-
ty. sembly, and the -003 status contains the A9 plus an
A10 IEEE-488/1975 interface assembly.
Variable rf frequency to check receiver selectivity.
Front panel assembly A1 consists of driver board
Variable percent modulation to check receiver assembly A l A l and display board assembly A1A2.
response. Controller/audio assembly A2 consists of CPU board
Variable DDM in 0.001 increments. assembly A2A1, analog board assembly A2A2, and
TDM board assembly A2A3. Rf modulator assembly
Standard localizer and glideslope rf frequency A3 consists of r f strip-line assembly ~ 3 ~ 1 ,
pairings. demodulator/ALC board assembly A3A2, and
counter-I/0 board assembly A3A3. Synthesizer A4
Single key provides switching between localizer and consists of divider board and filter assembly A4A1,
glideslope paired frequencies and vice versa. output amplifier board assembly A4A2, vco assembly
A4A3, and tcxo assembly A4A4. Power supply
Standard marker beacon frequency of 75.000 MHz assembly A5 consists of power supply terminal board
with provisions for simulation of interference-type assembly A5A1, power supply PCB assembly A5A2,
rf frequencies from 74.6 to 75.4 MHz. 'heat sink assembly no 1 A5A3, heat sink assembly
no 2 A5A4, and a blower. Chassis assembly A6 con-
Preset 400-Hz (outer marker), 1300-Hz (middle tains the interconnect wiring harness and a digitally
marker), and 3000-Hz (inner marker) marker controlled attenuator.
beacon audio tones.
The front panel contains the switches, keyboard, dis-
Remote tune output for automatic channel plays, and type N coaxial connector required for
programming of receiver under test. operation of the signal generator and connection of
receivers to be tested.
Mode discrete outputs provide antenna switching
and mode select/disable logic. The rear of the signal generator contains a COMP
BNC coaxial connector, an AUX BNC coaxial connec-
Timing trigger output pulse coincident with any tor; a DEMOD BNC coaxial connector, an EXT MOD
front panel keystroke for making time response BNC coaxial connector; a REMOTE TUNE connector;
measurements. an IEEE-488/1975 PROGRAM I/O connector; fuse
F1; a 115/230-V ac, 50/60-Hz connector, and an input
Vhf-COMM receiver frequencies from 118.000 to power identification plate.
151.975 MHz with 25-kHz spacing.
7. 115/230-VOLT AC, 50160-HZ OPERATION
Functionally grouped controls and displays.
Although the signal generator is shipped from the
115/230-V, 50/60-Hz input power capability. factory wired for 115-V ac, 501'60-Hz input power
operation, the power transformer input wiring can be
changed to provide 230-V ac, 50/60-Hz operation. If it
5. SPECIFICATIONS
is required to change to 230-V ac operation, refer to
the maintenance section for disassembly and wiring
Table 1 is a list of the specifications for the 479s-6A
changes required.
VOR/ILS Signal Generator.
8. BLOCK DIAGRAM THEORY OF OPERATION
6. CIRCUIT CARD AND MODULE ASSEMBLY (Refer to figure 3.)
LOCATION (Refer to figure 2.)
8.1 General
The signal generator major subassemblies are: front
panel assembly A l , controller/audio assembly A2, rf The 479s-6A VOR/ILS Signal Generator is a
modulator assembly A3, synthesizer assembly A4, microprocessor-controlled signal generator t h a t
power supply assembly A5, chassis assembly A6, produces audio-modulated rf signals and ARINC 410
backplane assembly A7, and remote tune assembly 2-of-5 tuning data. The rf output signals are used to
A8. test and troubleshoot VOR, localizer, glideslope,
CHARACTERISTIC
I SPECIFICATION
Dimensions
Connectors
Front panel
R e a r panel
Environmental specifications
Temperature
Operating
Storage
Electrical specifications
Power requirements
Rf outputs
Frequencies
CHARACTERISTIC SPECIFICATION
Frequency accuracy (fixed mode) < 1 2 ppm, (+lo to +40 "C (+50 to +lo4 OF)),
including aging
Output level
Range
Accuracy
pzT
The following parameters apply to
the m a r k e r beacon, VOR/LOC, and
glideslope bands. Performance over
the 118.000- to 151.975-MHz vhf
communication band may be some-
what degraded.
-6 to -60 dB mW +1.5 dB
Vs wr <1.5:1
Spectral purity
pzT
The following parameters apply to
the m a r k e r beacon, VOR/LOC, and
GS bands. Performance over the
118.000- to 151.975-MHz vhf com-
munication band may be somewhat
degraded with respect to the VOR/
LOC band specifications.
R ~ V ~ S 1.5
P IOctober
Z 1980 5
description 523-0768882 Scans by ArtekMedia © 2008
CHARACTERISTIC SPECIFICATION
Harmonics
VOR mode
Modulation tones
Frequencies
Variable
30-Hz v a r i a b l e , 30-Hz r e f e r e n c e ,
I Tones variable simultaneously +50/0. Resolution
9960 Hz of the 30-Hz tones i s 0.1 Hz. The 9960-Hz
signal v a r i e s proportionally.
Distortion (audio)
Aux audio
CHARACTERISTIC SPECIFICATION
30-Hz variable
Aux audio
Radial accuracy
Amplitude modulation
Accuracy
Aux audio
P r e s e t (30% modulation)
30-Hz variable
CHARACTERISTIC SPECIFICATION
1020-Hz ident
30-Hz variable
9960 Hz
Localizer mode
Modulation tones
Frequencies
Variable
Frequency accuracy
Distortion (audio)
Preset mode
Variable mode
90/150-HZ phase
Selectable 6 0 i 2 degrees
Amplitude modulation
90 and 1 5 0 Hz
Preset
Variable
1020-Hz ident
Aux audio
Preset
Variable
Accuracy
90 and 150 Hz
Preset
Variable
1020-Hz ident
Aux audio
Preset
Variable
90 and 150 Hz
Preset
Variable
1020-Hz ident
Aux audio
Preset
Variable
CHARACTERISTIC SPECIFICATION
DDM
Preset 0.000
~ u d i oe r r o r
On c o u r s e 0.0001 DDM
On c o u r s e 0.00056 DDM
Glideslope mode
Modulation tones
Frequencies
Variable
Frecluency a c c u r a c y *0.005%
Distortion (audio)
P r e s e t mode
Fixed 0.0 *1 d e g r e e
Selectable 60 +2 d e g r e e s
CHARACTERISTIC 1 SPECIFICATION
Amplitude modulation
Preset I 40%
Variable
I 1 0 t o 80g, in 0.1-% increments
1I
Aux audio
Preset 30%
Variable
I 10to 60% in 0.1-%increments
Accuracy
I
90 and 150 Hz
I
Preset
I *2.5% of indication
Variable
I 1 5 % of indication
II
Aux audio
Preset 1 5 % of indication
Variable 1 1 7 % of indication
Preset
Variable
Aux audio
Preset
I1 (2.0%
Variable 1 <3.0%
DDM
Preset
Selectable settings
Variable range
I 0.000, 10.045, i0.091, 10.175, and *0.400
i0.800 in 0.001-increments
CHARACTERISTIC SPECIFICATION
Audio e r r o r
On c o u r s e 0.0001 DDM
On c o u r s e 0.00102 DDM
M a r k e r beacon
Modulation tones
Frequencies
Preset
Outer m a r k e r 400 Hz
Middle m a r k e r 1300 Hz
Inner m a r k e r 3000 Hz
Variable
Frequency a c c u r a c y *0.0050/0
Amplitude modulation
Range
Preset 95%
Aux audio
Preset 95%
0
CHARACTERISTIC SPECIFICATION
Accuracy
400, 1300, and 3000 Hz
Preset i 5 % of indication
Variable *6.5% of indication
Aux audio
Preset i5.5% of indication
Variable i 7 % of indication
Tone distortion
P r e s e t 400, 1300, and 3000 Hz < 4%
Aux audio 5% maximum
Vhf COMM
Modulation tones
Preset
Variahle I 30 Hz to 10 kHz (0.1-Hz steps from 30 Hz to
1 kHz, 1.0-Hz steps from 1 to 10 kHz)
Frequency accuracy *0.005%
Distortion (audio) < 2.0%, p r e s e t 1020 Hz a t 3094, variable f r e -
quencies from 5 t o 35%
Amplitude modulation
Range
P r e s e t 1020 Hz 30%
Variable 10 Hz t o 10 kHz 5 t o 35% in 0.1-% increments
External modulation
Input impedance 5 kS2 minimum
Maximum modulation depth 90%
Modulation distortion 4% maximum
Modulation bandwidth
Marker beacon DC - 4 kHz
Localizer DC - 4 kHz
Glideslope DC - 4 kHz
VOR DC - 15 kHz
Vhf COMM DC - 15 kHz
Remote tune
Tuning format I 2-of-5 in accordance with ARINC 410
Selection method, tuning, and mode Spst relay closure with maximum contact rating
of 28 V dc a t 1 0 0 mA
Timing t r i g g e r TTI, level positive pulse, coincident with any
keystroke
PWR SUPPLY
TERM BD
ASSY A5A1 *
CONTROLLER1
AUDIO ASSY A2
CPL' ZSSY
A2A1
TDkS 3L>
42A3
COMP
BNC \ 1 151230 V AC,
CONN
50160 Hz CO NN
AUX
B NC
DEMOD
BNC
EXT MOD
BNC
REMOTE f i " , ~ ~ l - ~~1~
FUSE INPUT PWR
IDENT PLATE
CONN CONN CONN lgE: PROGRAM 110
CONN
I
IEEE-488/1978
1
/
INTERFACE
ASSY A 1 0 C CONT/DATA BUS
0
I
STORE/RECALL
2 OF 5 TUNING DATA
- - - - -- -
FRONT PANEL
-
CONT/DATA BUS
CONTRCLLER/
AUD I 0 ASSY A2
<
ASSY A1
(CPU, AUDIO GEN)
DIGITALLY-CONT
1 RF MOWLATOR ATTENUATOR
/ ASSY A3 P/O CHASSIS ASSY A6
- A \
A ATTEN
CCNT
11 5 / 2 3 0 INTERNAL
POWER SUPPLY OPERATING
ASSY A5 VOLTAGES
I
RF CARRIER S I G
VAR RF TLME VDCTAGE
SYNTHESIZER
RF COLNTER CLK
ASSY A 4
SYNTH CONT S I G rn
NOTES:
marker beacon, and vhf communication receivers. signal produced by the signal generator is applied
Selection of t h e desired rf (carrier) frequency through the RF OUT connector to the receiver under
automatically places the signal generator in the cor- test.
rect mode of operation and preset condition for that
mode of operation. Two-of-five tuning d a t a is Front panel assembly A1 contains a keyboard and
automatically provided a t the rear connector for tun- displays that provide the operator interface with the
ing the receiver under test to the channel correspon- signal generator. All operator instructions a r e
ding with the selected rf frequency. When a entered through the keyboard, and all signal
glideslope frequency is selected, 2-of-5 tuning data generator test parameters are indicated on the dis-
corresponding to the paired localizer channel is plays.
provided.
Controller/audio a s s e m b l y A2 c o n t a i n s a
microprocessor, memory circuits, and an audio
8.2 Overall Operation generator. The microprocessor is interconnected to
the internal signal generator circuits through a
The receiver under test is connected to the RF OUT parallel control bus. The parallel control bus consists
connector on the signal generator front panel. The of an 8-bit data bus, an &bit address bus, and a 2-line
I/O read/write bus. The microprocessor executes the Synthesizer assembly A4 uses the rf frequency con-
instructions stored in the memory circuits to control trol signals to produce the selected rf carrier frequen-
the audio generator and other signal generator func- cy. The rf carrier frequency is applied to rf modulator
tions. assembly A3.
The microprocessor is interrupted with an internally Rf modulator assembly A3 combines the carrier fre-
generated 4-ms interrupt. At each 4-ms interrupt, the quency with the audio modulation signal, either in-
keyboard is scanned to determine if any entries have ternally generated or provided from EXT MOD, to
been made. After valid keystrokes are recognized, the produce a simulated ground station signal. The
microprocessor verifies that the entries are within modulated rf signal is supplied to the digitally con-
the functional capability of the signal generator and/ trolled attenuator on A6.
or program. The microprocessor then transmits
operating instructions over the control bus to the The control signal supplied to the attenuator deter-
signal generator circuits. mines the amount of attenuation required to provide
an rf output signal with the selected output level a t
The audio generator circuits, contained on controller/ the RF OUT connector.
audio assembly A2, produce the required AM audio
tones to modulate the rf carrier signal. Rf modulator assembly A3 counts the frequency of
the rf carrier signal generated by A4 and supplies the
The amplitude of the audio signals is adjusted to information back to the microprocessor over the con-
provide the required modulation percentage. Audio trol bus. The microprocessor supplies the rf carrier
signals are combined, when required, to produce com- frequency and rf output level parameter information
posite audio signals to modulate the rf carrier fre- to front panel assembly A1 over the control bus.
quency. The composite signal produced in the VOR Front panel assembly A1 uses the information from
mode consists of a combined 30-Hz variable AM the microprocessor to indicate the rf carrier frequen-
signal and a 9960-Hz FM (30-Hz reference) signal. The cy in the FREQUENCY display, mode of operation in
composite signal produced in the ILS mode consists of the MODE display, and rf output level in the RF
a combined 90- and 150-Hz AM signal. The relative LEVEL display.
amplitude of the audio signals is adjusted in the ILS
mode to produce the desired difference in depth of Rf modulator assembly A3 and synthesizer assembly
modulation (DDM). Single tones are provided in the A4 produce monitor signals that are transmitted over
marker beacon and VHF COMM modes. In the VOR the control bus to the microprocessor and from the
mode, the phase between the audio signals is adjusted microprocessor over the control bus to front panel
to produce the selected VOR radial. assembly Al. The monitor signals are displayed in
the RF STATUS display and indicate that the syn-
The audio generator decodes instructions received thesizer is locked on the selected frequency, and that
from the microprocessor, via the control bus, and the output of the rf modulator is within specific
produces the required audio signals with the correct limits.
signal amplitude and phase. The audio, or composite
audio modulation signal, is applied to rf modulator The signal is applied from the RF OUT connector to
assembly A3. the receiver under test. Controller/audio assembly
A2 supplies composite and auxiliary signals to con-
Front panel assembly A1 processes the data received
nectors on the rear of the signal generator. The com-
from the microprocessor via the control bus, and
posite signal consists of the generated combined
produces displays in the RDL/DDM/MOD and audio modulation signals and the auxiliary signal is a
AUDIO STATUS displays indicating the audio
30-Hz reference signal (VOR mode only).
modulation parameters produced by the audio
generator. The applicable keys are lit for the audio
tones generated. Rf modulator assembly A3 supplies a demodulation
signal to a connector on the rear of the signal
Rf modulator assembly A3 processes data received generator. The demodulation signal is the detected
from the microprocessor via the control bus, to audio modulation (rf carrier removed).
produce rf frequency control signals that are applied
to synthesizer assembly A4 and attenuation control Remote tune assembly A8 processes the data received
signals that are supplied to the digitally controlled from the microprocessor via the control bus, to
attenuator on chassis assembly A6. produce 2-of-5 tuning data outputs in the ARINC 410
tuning format, mode control outputs, and a scope The RDL/DDM/MOD display and SELF TEST in-
trigger output. The outputs are available a t the dicator flash on and off to alert the operator that a
REMOTE TUNE connector on the rear of the signal memory (ROM) output is incorrect and that the
generator for automatic tuning of the receiver under memory check has stopped. The signal generator is
test. Entry of a glideslope frequency will cause the inoperable and must be repaired before any further
paired localizer frequency to be output on the 2-of-5 operations can be performed.
lines. The 2-of-5 data output remains unchanged
when the selected rf frequency is varied for off- 8.4 Self-Test Mode Operation
channel testing. The output logic for the mode control
signals is listed in table 2. Mode select A and B lines In the self-test mode, the signal generator checks all
are intended for use in switching rf antenna relays. A display segments, indicators, and key lamps, and
scope trigger pulse output is provided, occurring coin- then performs a check of the controller memory
cident with front panel keystrokes. (ROM) outputs. When the SELF TEST switch on the
front panel is initially depressed, a lamp check is per-
8.3 Initial Power-On formed; and when the switch'is released, the memory
output (ROM) check is performed. The displays, in-
On initial signal generator turn-on, the controller dicators, and keys remain lit as long as the SELF
m e m o r i e s ( R A M ' s a n d ROM1s) a r e checked TEST switch is held depressed.
automatically. All displays, except SELF TEST light,
are blank during the memory check, unless a memory During the lamp check, all indicators and key lamps
output is incorrect. If the outputs from the controller under designated key caps are lit and the 7-segment
memories are correct, the signal generator switches displays indicate 0.8 for each digit in the display. The
to the VOR mode preset condition with an rf carrier memory output (ROM) check is indicated by sequen-
frequency of 108.000 MHz and a 50-dB mW rf output tial indications in the RDL/DDM/MOD display. All
level. When the signal generator completes the other displays are blank during the memory output
memory check and switches to the VOR mode preset (ROM) check. If the outputs from the controller
condition, the operator is assured that the signal memories (ROM's) are correct, the signal generator
generator is programmed correctly and is ready for switches to the initial power-on status, checks the
testing or troubleshooting VOR, ILS, marker beacon, RAM'S, rechecks the ROM's, and then switches to the
or communication receivers. If one of the RAM's has VOR mode preset condition with an rf carrier fre-
failed, the R F LEVEL display will indicate the RAM quency of 108.000 MHz and a -50-dB mW rf output
that has failed (...I). The signal generator will begin level. (When the signal generator switches to the VOR
another RAM check and will continue to sequence un- mode preset condition, the operator is assured that
til malfunction is cleared. If an output from one of the the signal generator is programmed correctly and is
controller ROM memories is incorrect, the memory ready for testing or troubleshooting VOR,ILS,
check stops. The RDL/DDM/MOD display will in- marker beacon, or vhf communication receivers.) If a
dicate the number of the ROM that is malfunctioning. memory output is incorrect, the indications are the
MODE COMM
DISABLE
LOC/GS
ENERGIZE
NAV
DISABLE
MOD
SELECT A
(
VOR X
I
LOC X
I
COMM 0
I
same a s described during initial power-on in on test requirements. The desired off-channel rf
paragraph 8.3. During self-test, the rf output is carrier frequency may also be selected via the data
automatically disabled (turned off). entry keyboard in 1-kHz increments.
8.5 VOR Mode Operation The rf output level is adjustable from -6 to -120 dB
mW to allow operator selection of the output level
When a standard VOR rf carrier frequency is initially required to meet test requirements for receiver
selected, the signal generator automatically switches response. The output level can be increased or
to the VOR mode and to the VOR mode preset condi- decreased in either 1- or 10-dB steps as required by
tion. the operator.
The rf output signal from the signal generator VOR radials are selectable from 000.00 to 359.99
simulates a VOR ground station signal and in the degrees in 0.01-degree steps to provide precise and ac-
preset condition, provides an audio modulated, rf out- curate radials for checking or aligning the receiver
put signal with the following parameters. under test. The radial can be set to major headings a t
SIGNAL every 30 degrees and then stepped from that point in
CHARACTERISTIC OUTPUT PARAMETER +30-, +lo-, -10-degree steps or slewed in f0.01-
degree steps, as required to check the receiver.
VOR rf carrier Selected standard VOR
frequency ground station
frequency
Radials are expressed in degrees and are 180
Rf carrier 30-Hz variable degrees out of phase from the aircraft bear-
modulation AM/9960-HZ FM ing to the station. An RMI bearing indicator
(30-Hz reference) will point to a bearing 180 degrees out of
composite audio phase with the selected radial, thus the tail
signal of the bearing pointer should indicate the
selected radial.
Amplitude (%)
modulation The amplitude (%) modulation of the simulated VOR
signal is adjustable from 5.0 to 35.0 percent in 0.1-
VOR radial 000.00 degree percent increments t o check receiver response.
Independent control for modulation adjustments of
TO or FROM status FROM the 30-Hz VAR and 9960-FM tones is also provided.
indicator
The TO/FROM indication is determined by the phase
Output level -50 dB mW (If the relationship of the composite audio VOR signal and is
output level is changed always a FROM signal on initial selection of the VOR
after initial power-on mode. Through keyboard entry, the FROM signal can
or after self-test, the be changed to a TO signal, which phase shifts the
level remains a t the VOR bearing signal by 180 degrees.
selected level.)
A 1020-Hz audio tone, which simulates an identifica-
Rf channel frequencies are normally entered via the tion signal, can be added to the VOR rf output signal
DATA ENTRY keyboard. Use of the RF FREQ key, a t 30 percent modulation by keyboard entry. Ad-
however, allows selection of sequential VOR channels ditionally, a 1020-Hz or a 30-Hz to 14-kHz auxiliary
using a single keystroke. With modulation on, only audio tone is available. (For specialized tests, entries
consecutive VOR channels are selected. With modula- are allowed down to 10-Hz; however, operation is
tion off, sequential localizer carrier frequencies in the only specified over the 30-Hz to 14-kHz range.) The
108.10- to 111.95-MHz range are also selected. operator may add or remove the signal as required
during receiver checks. The auxiliary audio tone
The rf carrier frequency is variable up to fl- amplitude (%) modulation is adjustable in 0.1-percent
channel spacing for checking receiver selectivity. Us- increments from 5 to 35 percent. The 1020-Hz ident
ing the slew keys, the carrier frequency can be varied tone amplitude (%) modulation, when selected, is fix-
in either direction a t a fast or a slow rate depending ed a t 30 percent.
Either or both of the 30-Hz variable or 9960-Hz FM Adjustment of the rf carrier frequency and the rf out-
signals can be removed a s required to perform put level is the same a s described for the VOR mode
receiver flag checks. of operation in paragraph 8.5, except that stepping rf
The frequencies of the 30-Hz variable, 3 0 - ~ z carrier frequencies with modulation on will skip over
reference, and 9960-Hz signals are adjustable h5.0 adjacent 'OR frequencies.
percent. (Entries over a f10-percent range are
A 1020-Hz audio tone, which simulates an identifica-
allowed for specialized testing; however, operation is
tion signal, can be added to the localizer rf output
only specified over the f5-percent range.) Selection in
signal a t 30-percent modulation by keyboard entry.
0.1-Hz increments of the 30-Hz variable signal fre-
Additionally a 30-Hz to 4-kHz auxiliary audio tone is
quency changes the 30-Hz reference the same amount
available. (Entries to 10 Hz and up to 10 kHz are also
and also varies the 9960-Hz signal proportionally.
allowed; however, operation is only specified over the
A n y time information displayed in t h e 30-Hz to 4-kHz range.) The operator may add or
RDL/DDM/MOD and AUDIO STATUS displays is remove the signal a s required during receiver checks.
changed from the preset condition, the rf carrier fre- The amplitude (%) modulation of the auxiliary audio
quency is slewed from the selected rf carrier frequen- is adjustable in 0.1-percent increments from 5.0 to
cy or the rf output is turned off, and it is desired to 30.0 percent. The 1020-Hz ident tone amplitude (5%)
return the signal generator to a preset condition, a modulation, when selected, is fixed a t 30.
single entry using the STD key returns the signal
generator to the preset condition for the selected rf The difference in depth of modulation (DDM) is selec-
carrier frequency. The rf output level is not affected table in standard preset DDM steps of 0.000, f0.046,
by the STD key and remains a t the last selected out- f0.093, f0.155, and f0.200, or in 0.001 increments to
put level. f0.400 through keyboard entry. The DDM can be
slewed in either direction in f0.001 increments. The
For detailed operating procedures and detailed infor- selected DDM's are used to check receiver operation
mation on the controls and indicators, refer to the
and accuracy. The amplitude (9%) modulation of the
operation section. 90/150-Hz tones in the LOC mode is variable from 5.0
to 40.0 percent in 0.1-percent increments to check
8.6 Localizer (LOC) Mode Operation
receiver response. The % modulation can be varied
only a t beam center.
When a standard localizer rf carrier frequency is in-
itially selected, the signal generator a;tomatically
When the signal generator produces an up or left
switches to the LOC mode and to the LOC mode
signal, the 150-Hz portion of the composite signal is
preset condition. The rf output signal from the signal
predominant and when the signal generator produces
generator simulates a localizer ground station signal
a down or right signal, the 90-Hz portion of the com-
and in the preset condition provides an audio
posite signal is predominant. All DDM signals
modulated, rf output signal with the following
produced by the signal generator are up or left signals
parameters.
unless changed to a down or right signal through
keyboard entry. The 90- and 150-Hz signals are
SIGNAL
OUTPUT PARAMETER balanced a t 0.000 DDM and neither signal is predomi-
CHARACTERISTIC
nant; however, the signal generator provides a U/L
Localizer rf Selected standard (150-Hz) indication that indicates the next DDM step
carrier frequency localizer ground will be in the up or left direction. The DDM cannot be
station frequency changed to indicate D/R (90 Hz) a t 0.000 DDM.
Rf carrier 90-Hz/150-Hz AM Either or both of the 90- and/or 150-Hz audio signals
modulation composite audio can be removed a s required to perform receiver flag
signal checks.
Amplitude (%) 20.0% per tone, on
beam center The phase angle between the 90- and 150-Hz tones is
modulation
normally fixed a t 0 degree. I t mag be varied to 60
DDM 0.000 degrees" (referenced to the 150-HZ signal) via
U/L (150-Hz) or U/L (150 Hz) keyboard entry. The 90- and 150-Hz signal frequen-
D/R (90-Hz) status cies are adjustable f5.0 percent. Adjustment of
indicators either causes a corresponding change in the other.
The signal generator can be returned to the preset to the MB mode preset condition. The rf output signal
condition using the STD key the same as described for from the signal generator simulates a marker beacon
the VOR mode in paragraph 8.5. ground station and in the preset condition provides
For detailed operating procedures and detailed infor- an audio modulated, rf output signal with the follow-
mation on the controls and indicators, refer to the ing parameters. \,
Rf carrier 1020-Hz audio signal The 479s-6AVOR/ILS Signal Generators, -002 or -003
modulation status, installed have all the basic 479s-6A features
plus the additional capability of the operator pro-
Amplitude (%) 30.0% gramming up to 100 front panel setups. Refer to
modulation figure 2 for store/recall assembly A9 location and
figure 3 for a block diagram. Once programmed into
Output level -50 dB mW (If the storage, the setups can be recalled upon command
output level is changed from the operator. Setups can be recalled and changed
after initial power-on a s desired. After a setup is placed in storage, power
or after self-test, the can be removed and the data will be retained in-
level remains a t the definitely.
selected level.)
Selection of the store function causes store/recall
assembly A9 to process data received from the
microprocessor via the control bus, and to store it in
The 479s-6A does not provide reverse power the selected location. On a recall command, store/
protection. Do not key a communications recall assembly A9 transfers the selected memory
transceiver when connected to the signal data back to the microprocessor, which in turn
generator or extensive damage will result to reprograms the signal generator as required.
the signal generator.
For detailed operating procedures of the store/recall
Rf carriers from 118.000 to 151.975 MHz can be function, refer to the operation section.
selected in 25-kHz steps.
The rf carrier is variable up to f1-channel spacing 8.11 R e m o t e Bus Progrartzming Function (479.9-
to check receiver selectivity. Using the slew keys, the 6.1 VORIILS Signal Genrators, -003 S t a t u s )
carrier frequency can be varied in either direction a t a
fast or a slow rate depending on test requirements. The 479s-6A VOR/ILS Signal Generators, -003 sta-
Consecutive channel frequencies can be selected with tus, installed have all the basic 479s-6A features, the
a single keystroke by use of the RF FREQ key. Off- store/recall function, plus the capability of being
channel frequencies can be entered via the DATA remotely programmed. For ease of programming, the
ENTRY keyboard in 1-kHz increments. store/recall may be programmed first, either locally
or remotely. Only the step numbers for the stored
The rf output level is adjustable from -6 to -120 dB setups need to be transmitted on the remote bus,
mW to allow operator selection of the output level which will then program a complete front panel
required to meet test requirements for frequency setup. Refer to figure 2 for IEEE-488/1978 interface I
response. The output level can be increased or assembly A10 location and figure 3 for a system block
decreased in either 1- or 10-dB steps as required by diagram.
the operator.
The audio tone may be switched from the preset 1020 IEEE-488/1978 interface assembly A10 connects the I
Hz to an auxiliary signal of 30 Hz to 10 kHz. (Entries signal generator to the IEEE-488 bus. Subminiature
to 10 kHz are allowed, however, operation is only rocker switches are used to preset a 5-bit address for
specified over the 30-Hz to 10-kHz range.) Initial the signal generator. The IEEE-488 interface cir-
selection of the auxiliary frequency function provides cuitry is initialized during the CPU's power-up
a tone of 1 kHz. The amplitude (%) modulation of the routine. Subsequently, when a command is received
auxiliary signal is adjustable from 5.0 to 35.0 percent that agrees with the preselected address of the
in 0.1-percent increments to check receiver response. generator, a nonmaskable interrupt is generated by
the IEEE-488 circuitry, requesting service from the
For detailed operating procedures and detailed infor- CPU. The CPU then processes the remote computer
mation on the controls and indicators, refer to the command, either receiving setup instructions or
operation section. replying with status information.
9. FUNCTIONAL THEORY OF OPERATION bus. The CPU stores the returned data until the same
(Refer to figure 4.) data is returned 12 consecutive times. After the 12th
time, the CPU recognizes the keyboard entry a s valid,
9.1 General
and processes the data. Twelve consecutive d a t a re-
The functional theory of operation is a discussion of turns from the keyboard are required to ensure t h a t
the 479s-6A VOR/ILS Signal Generator a t the circuit the entry is,valid and not a n entry due to key bounce.
card assembly level. This discussion provides Since the keyboard is in a matrix, returned data de-
assistance to the technician in understanding signal notes the, key position in the matrix.
generator operation for maintenance purposes.
9.2.3 Keyboard D.4T.4 E,YTRY Keys
The signal generator consists of the front panel
assembly A l , controller/audio assembly A2, rf When making rf frequency, VOR radial, DDM, and
modulator assembly A3, synthesizer assembly A4, percent modulation entries through t h e DATA
power supply assembly A5, chassis assembly A6, and ENTRY keys, after each numeral is recognized by the
backplane assembly A7, which includes the remote CPU, the information is stored until the DATA
tune circuits A8, store/recall assembly A9 (status - ENTRY - ENTER key is pressed.
002 or -003), and I E E E 48811975 program I/O A10
(status -003). Only the digitally controlled attenuator When the ENTER key d a t a is recognized by the CPU,
A6ATI portion of chassis assembly is discussed. the stored numeral information is processed. If a mis-
take is made during entry of the information on the
9.2 Rlicroprocessor ( C P U ) Operation numeric keys, pressing the DATA ENTRY - CLEAR
key removes the stored information from the CPU.
9.2.1 General
The CLEAR key also removes information from the
The microprocessor (CPU), PROM, and RAM chips CPU when an invalid entry is made, producing a
are contained on CPU assembly A2A1. The CPU con- blinking display.
trols all internal signal generator operations; it is in-
terconnected with the front panel assembly A l , rf 9.2.4 Loop Operation
modulator assembly A3, TDM board A2A3, and
backplane assembly A7 by a parallel control bus. The During periods between interrupts, if all key activity
control bus is capable of handling 8-bit addresses, 8- is finished, the CPU returns to its normal routine. In
bit data, and I/O read and write pulses. The 8-bit ad- normal routine, the CPU monitors the keyboard to
dresses and I/O read/write pulses a r e generated only determine if a keystroke h a s been made, requests the
in the CPU, while the 8-bit d a t a can be generated by frequency count from A3 to ensure t h a t the frequency
the CPU or, on request, obtained from AlA1, A2A3, indicated on the display is accurate, requests the
A3A3, or A9 or A10 (-002 or -003 status units) depen- status of synthesizer phase lock from A3 to ensure
ding on 1/0 port addressed. t h a t selected synthesizer rf output frequency remains
phase locked to the reference frequency, and requests
The 8-b;t address selects the correct I/O port. The 1/0 rf level calibration status from A3 to ensure t h a t the
read pulse strobes d a t a out of the port over the con- rf level is within specified limits. If any of the infor-
trol bus to the CPU. The I/O write pulse strobes d a t a mation is not available when requested, the CPU
from the CPU into the correct I/O port via the con- proceeds through the loop and the information is ob-
trol/data bus. tained during the next loop.
9.3 Front Panel Assembly A1 Operation
9.2.2 Keyboard Scan
9.3.1 General
The CPU is strapped for one interrupt t h a t occurs a t
nnrninal 4-millisecond intervals. At each of these The front panel assembly provides operator interface
n o m i n ~ A-millisecond
' intervals, addresses, data, and with the signal generator. A keyboard that is p a r t of
I/O write pulses a r e supplied over the control bus to keyboard driver board A l ~ allows
l the operator to
A l . The I/O port on A1 supplies the data to a select the required signal generator outputs for
keyboard matrix and the keyboard is scanned to testing, trocl~leshooting, and/or aligning and ad-
determine it any keys have been pressed. If, during justing the unit under test.
the scan, the scan detects a pressed key, d a t a is
returned via the I/O port on A l . On request from the The digital displays and LED indicators on display
CPU, the data is returned to the CPU over the control board AlA2, plus lighted keys on A1A1, provide the
1
KEYBOARD
Vl
REMOTE
IEE E-STD
48811978
PROGRAM 110
operator with a readout of t h e output signal When an rf carrier frequency is selected, the CPU
parameters. supplies data over the control bus to the I/O ports on
A2A3. The data programs the modulation generator
9.3.2 Keyboard Driver Board A l A l to generate the correct audio signals. All internal
audio modulation signals and analog control signals
Keyboard driver board A l A l contains the I/O ports, are generated on A2A3 and supplied to A2A2.
keyboard, display driver circuits, bar/blanking cir- In the VOR mode, A2A3 generates 30-Hz variable AM
cuits, and key light driver circuits. The 1 / 0 ports are and 9960-Hz FM (30-Hz reference) signals that are
connected to the parallel control bus and receive and both supplied to A2A2. The phase relationship
transmit all information via the control bus. When between the 30-Hz variable and 30-Hz reference
the I/O port is addressed and an I/O write pulse oc- signals determine the VOR radial. TDM board A2A3
curs, the data a t the input to the I/O port is supplied generates VOR analog control signals that are
to the correct circuit on AlA1. When the input is for a supplied to A2A2. Analog board A2A2 filters the
keyboard scan, which occurs a t nominal 4-millisecond audio modulation signals and combines the 30-Hz AM
intervals, the data is supplied to the keyboard and 9960-Hz FM signals to produce a composite audio
switching matrix circuits. If a key is pressed, data is modulation signal t h a t is supplied to
returned to the I/O port and when the CPU transmits demodulator/ALC assembly A3A2.
the correct address and an I/O read pulse, the data is
transmitted over the control bus to the CPU. Phase information relating to the 30-Hz variable and
30-Hz reference signals is read back to the CPU by
When CPU data a t the A l A l I/O port is to light a dis- TDM board A2A3 when requested by the CPU. This
play, the data is latched in display driver circuits. The phase information is transmitted to the CPU via the
driver circuits produce display driver signals that are control bus and is used to generate the VOR radial
supplied to AlA2. displayed on the front panel.
In either localizer or glideslope mode, TDM board
When the CPU data a t the A l A l I/O port is to either A2A3 generates 90- and 150-Hz AM signals. Both
bar or blank a digital display, the data is supplied to signals are supplied to A2A2 with a localizer or
the bar/blank circuit that produces the correct bar or glideslope mode analog control signal. Analog board
blank signals. The bar/blank signals are supplied to assembly A2A2 filters the 90- and 150-Hz AM signals
AlA2. to produce the composite audio modulation signal
that is supplied to A3A2.
When CPU data a t the A l A l I/O port is to light a
specific keyboard key, the data is latched in the key To change DDM, the CPU reprograms TDM board
light driver circuit. The driver circuit provides a lamp assembly A2A3 to modify a s required the amplitudes
drive signal to a lamp located in the key, under the of the 90- and 150-Hz tones.
key cap. In marker beacon mode, TDM board A2A3 generates
one of three available audio modulation signals,
depending on keyboard selection and subsequent data
9.3.3 Display Board ..11A2 Operation from the CPU. When the outer marker tone is
selected, A2A3 generates a 400-Hz audio tone; when
Display board A1A2 contains 7-segment digital dis- the middle marker tone is selected, A2A3 generates a
plays and LED indicators. The digital displays and 1300-Hz audio tone; and when the inner marker tone
LED indicators indicate rf output signal parameters. is selected, A2A3 generates a 3000-Hz audio tone. A
All displays and indicators are driven by signals from marker beacon analog control signal is produced on
AlAl. A2A3 and supplied to A2A2. Analog board A2A2
filters the audio tone and supplies the tone to A3A2.
In VOR and localizer modes, a 1020-Hz audio tone
9.4 Audio Modulation Generator Operation
also can be added to the composite audio modulation
signal. The 1020-Hz audio tone simulates an iden-
The audio modulation generator consists of TDM tification signal. The 1020-Hz signal is combined with
board A2A3 and analog board A2A2. The modulation
the other two modulation signals on A2A2.
generator produces audio signals that are used to
modulate the selected rf carrier signal. The modula- In VOR mode, the FM signal can be removed from
tion signal requirements depend on the selected rf the standard 9960-Hz FM tone by depressing the
frequency (mode of operation). 9960-Hz key.
Analog board A2A2 also supplies the composite When the sampled rf carrier frequency is phase-
modulation signal to a COMP connector on the rear locked to a 25-kHz loop-lock frequency, a phase-lock
panel and a 30-Hz reference signal (VOR mode only) status signal is supplied to A3A3.
to an AUX connector on the rear panel.
The CPU also transmits data over the control bus to
9.5 RF Section Operation the I/O ports on A3A3, indicating the mode selected.
Counter-I/O board A3A3 converts mode data into I/O
9.5.1 General control signals that are supplied to demodulator/ALC
assembly A3A2. The I/O control signals adjust audio
The rf section consists of rf modulator assembly A3, modulation level from A2A2 to the correct level to
synthesizer assembly A4, and digitally-controlled provide a standard percent of modulation for each
attenuator A6AT1. The rf modulator assembly con- mode. Percent modulation values other than standard
s i s t s of r f s t r i p l i n e a s s e m b l y A 3 A 1 , are obtained by adjustment of the modulation signals
demodulator/ALC assembly A3A2, and counter - I/O in the audio modulation generator circuits. The level
board A3A3. The rf section generates selected rf of the modulation signal is checked and automatically
carrier signal, modulates the carrier signal with the adjusted on A3A2 and is then supplied to A3A1. The
audio modulation signal, and adjusts rf output level. external modulation signal is not automatically
The modulated rf signal is applied from the digitally- checked and adjusted for correct modulation levels.
controlled attenuator to the RF OUT connector on the These levels must be calculated and the external
front panel. In addition, an external modulation modulation source must be adjusted to provide cor-
signal can be inserted through the rear panel con- rect modulation levels. (Refer to the operation section
nector into demodulator/ALC assembly A3A2 in for calculation and adjustment of correct external
place of the composite audio modulation signal. modulation signal levels.)
Synthesizer assembly A4 generates the rf carrier The composite audio modulation is combined with the
signal a t the frequency specified by the rf tune signal rf carrier signal on A3A1 to produce a modulated rf
from A3A3. The synthesizer employs a phase-lock signal that is supplied through the digitally controlled
loop to provide a stable rf output frequency. A attenuator to the R F OUT connector on the front pan-
variable oscillator in the synthesizer allows frequency el. The digitally controlled attenuator sets the rf out-
slewing when requested by keyboard entries. put level.
The rf output from A4 is supplied to rf strip line The CPU also transmits data over the control bus to
assembly A3A1. The audio modulation signal from the I/O ports on A3A3 to select the desired rf output
demodulator/ALC assembly A3A2 is also supplied to level. Counter-I/O board A3A3 routes control bus
A3A1, and is used to modulate the rf carrier. The data to a digitally controlled attenuator. The binary
modulated rf signal is supplied to the digitally con- control signal sets the attenuator to the correct level
trolled attenuator, which is set to the correct attenu- required to produce the selected rf output level a t the
ation for the output level selected. RF OUT connector. When microvolt readings are be-
ing displayed on the RF LEVEL display, an ad-
Counter-I/O board A3A3 contains I/O ports that con- ditional 6-dB attenuation is inserted, making the
nect the rf section to the control bus. Board A3A3 also signal output a t the RF OUT connector one-half of the
contains an rf frequency counter that provides rf displayed RF LEVEL value. This results in an output
frequency information to the CPU to be displayed on which is "hard" microvolts, without the use of an ex-
the front panel. ternal 6-dB pad. When the rf output is being dis-
played in dB mW, the extra 6-dB attenuation is
9.5.2 RF Frequency Selection removed and the rf output level a t the RF OUT con-
nector is absolute (the level indicated in the RF
The CPU transmits rf frequency control data over the LEVEL display).
control bus to I/O ports on counter-I/0 board A3A3.
Counter-I/O board A3A3 routes the control bus data
to synthesizer assembly A4. The rf strip line assembly produces an rf signal that
is the rf carrier frequency; it also produces a
The bcd rf tune signal tunes A4 to the selected rf demodulator signal that is the modulation signal with
carrier frequency. Synthesizer assembly A4 the rf carrier removed. The rf signal is supplied to the
generates the selected rf carrier frequency and frequency counter on A3A3, and the demodulator
supplies the signal to rf strip line assembly A3A1. signal is supplied to A3A2.
Counter-I/O board A3A3 counts the rf signal to deter- store/recall board A9 to allow storage of signal
mine the frequency of the output signal and supplies generator setup's in memory. These setup's can then
the count to the rf counter output ports. When the be recalled a t any time and used to test a receiver.
CPU requests the frequency count, the information is
supplied from the I/O port over the control bus to the Equipment is configured as desired and a 2-digit
CPU. The CPU uses the frequency count to supply memory address is entered on data entry keys.
frequency information over the control bus to A1 for
display in the FREQUENCY display. 9.9 IEEE 48811978 Interface Board A10 I
When requested by the CPU, the phase-lock informa- I E E E interface board A10 provides the capability for
tion is also supplied from an I/O port on A3A3 over control of the signal generator to originate outside the
the control bus to the CPU. The CPU data uses the in- signal generator. This board conforms to IEEE stan-
formation to supply data over the control bus to A1
for control of R F STATUS - P H LOCK indicator.
dard 488-1978. I
10. DETAILED THEORY OF OPERATION
The demodulator signal supplied to A3A2 is used to
level the rf carrier and to linearize the modulation 10.1 Introduction
signal supplied to A3A1. The demodulation signal is
also supplied to the DEMOD connector on the rear The detailed theory of operation is a discussion of
panel. When the rf output is within the specified the 479s-6A VOR/ILS Signal Generator a t the
limits, a logic 1 level calibration signal is supplied to functional circuit level on each circuit card or
an I/O port on A3A3. The level calibration Status in- module assembly. This discussion provides assistance
formation is continuously sampled and returned over to the technician in understanding signal generator
the control bus to the CPU. The CPU uses the level operation for maintenance and troubleshooting
calibration information to supply data over the con- purposes.
trol bus to A1 for RF STATUS - LEVEL CAL; in-
dicator. 10.2 Front Panel Assembly A1
9.6 Power Supply Assembly A5 Operation
10.2.1 General
The signal generator can be operated on either 115
Front panel assembly A1 provides operator interface
volts or 230 volts 50160 Hz. The generator is shipped
with the signal generator. The front panel keyboard
wired for 115-volt operation. If 230-volt operation is
allows the operator to select the test signal
required, refer to the maintenance section for rewir-
ing information. parameters required to test, troubleshoot, and/or
align VOR, localizer, glideslope, and marker beacon
The power supply assembly produces +5, +9, +12, receivers. The front panel display indicates the signal
+15, -15, and +24 V dc and 15 V ac, for signal genera- g e n e r a t o r rf o u t p u t s i g n a l p a r a m e t e r s a n d
tor operation. characteristics. Front panel assembly A1 consists of
keyboard/driver board A l A l and display board
AlA2. The keyboard is contained on AlA1; the front
9.7 R e m o t e Tune Board A8 panel display on AlA2.
Remote tune board A8 provides 2-of-5 tuning that 10.2.2 O v e r ~ l lOperation (Refer t o figure 5.)
meets ARINC 410. Address and data information is
used to turn on relays that provide grounds and supp- C o n t r o l l e r / a u d i o a s s e m b l y A2 c o n t a i n s a
ly tuning information to the radio under test. microprocessor that transmits &bit addresses, 8-bit
data, and I/O read/write pulses over a parallel 18-line
Information is also provided to generate the following
control bus to the internal circuits of the signal
control signals: mode select A, NAV disable, LOC/GS
generator, including keyboard driver board AlA1.
energize, mode select B, COM disable, and timing
Addresses and I/O read/write pulses determine
trigger.
operational functions to be performed, and the data
bits provide the intelligence.
9.8 StorelRecall Board A9
CPU address and data bus information, along with Keyboard switches contained on A l A l are connected
I/O r e a d a n d w r i t e signals, a r e provided t o in a switching matrix that uses the inputs to the
0 l SPLAYS
/
C
/
/
/
/ \ ., J
/ KEYBOARD W T R l X
I D l SPLAY BOARD
AlA?
I
D I SPLAY /
OR l VER
matrix and the switch position in the matrix to deter- 10.2.3 KeyboardJDriver Board A l A l
mine the operational function or signal characteristic
selected by the operator. The microprocessor on A2 a. Overall Operation (Refer to figure 6.)
produces addresses, data, and I/O read/write pulses
which occur a t nominal 4-millisecond intervals, caus-
ing the switching matrix to be scanned. The scan The I/O read, I/O write, and address bits A0
determines whether the operator has made an entry through A7 from the parallel address bus and CPU
on the keyboard. Addresses, data, and I/O read/write assembly A2A1 a r e supplied to the address
pulse from A2 are transmitted over the parallel con- decoder circuit. The address decoder circuit
trol bus to A l A l . If no keyboard entries have been decodes the hexadecimal address information to
made, the keyboard switching matrix produces no determine A l A l and A1A2 circuit functions. Refer
output during the scan and the signal generator to table 3 for hexadecimal-to-decimal conversion.
remains in the last selected test condition. If an entry
has been made, the matrix produces a data hit output Decoded addresses OUT 40 through OUT 44 and
during the scan and the data bit is returned to the OUT 4E are supplied to the RDL/DDM/MOD dis-
microprocessor over the control bus. The data bit in- play driver circuit. Decoded addresses OUT 45
dicates the selected function or test characteristic. through OUT 4A and OUT 4F are supplied to the
FREQUENCY display driver circuit. Decoded ad-
Display driver signals are produced on A l A l from in- dresses OUT 4B through OUT 4D and OUT 50 are
formation received from A2 over the parallel control supplied to the R F LEVEL display driver circuit.
bus. Driver signals are applied to display board AlA2 Decoded address OUT 51 is supplied to the
and light the applicable indicators for the informa- bar/blank circuit and OUT 52 through OUT 55 are
tion received from A2. The display provides a visual supplied to key indicator circuits. All of these ad-
indication of signal g e n e r a t o r o u t p u t signal dresses are supplied to their applicable circuits
parameters and characteristics. when an I/O write pulse occurs.
D l G l T 1)
RDL/DDM/MOD IND
CPU ADDRESS
I A3
1
BUS DlGlT 1
DlGlT 2
DISPLAY DRIVE S I G -
DISPLAY BD A I A 2
J
DlGlT 5
DlGlT 6
RDL/DDH/MOD I ND
FREQUENCY I ND
MODE IElD
:$ DATA 1 DO
Dl
!i
05
06
07
DlGlT 1
DIGIT 2
DlGlT 3
J
RF LEVEL IND
)
RF STATUS IND
RF LEVEL
DIGITAL
0 1 SPLAY
NUMBER CODE
SYSTEM
Decimal 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 15
Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F
Decoded address OUT 56 and IN 5X are supplied to Data bits from the parallel data bus and the CPU,
the keyboard matrix circuit. The OUT 56 address and the OUT 40 through OUT 45 and the OUT 4E
occurs when an 1 / 0 write pulse occurs and the IN decoded addresses from the address decoder cir-
5X address occurs when an I/O read pulse occurs. cuit, are supplied to the RDL/DDM/MOD display
driver circuit and determine the information to be
Data bits DBO through DB7 from the parallel data supplied to the display circuit board. The display
bus and CPU assembly A2A1 are supplied to the drive signals from the RDL/DDM/MOD display
keyboard matrix, key indicator, bar/blank, driver circuit are supplied to the RDL/DDM/MOD
RDL/DDM/MOD display driver, FREQUENCY digital display and indicators, and to the AUDIO
display driver, and R F LEVEL display driver cir- STATUS indicators.
cuits and contain the intelligence for circuit opera-
tion. FREQUENCY display driver circuit operation is
the same a s described for the RDL/DDM/MOD
Every 4 milliseconds, the data bits and decoded ad- display driver circuit, except that decoded ad-
dresses supplied to the keyboard matrix cause a dresses OUT 45 through OUT 4A and OUT 4F are
complete keyboard scan to determine if any entries used to latch the data bit input and the circuit
have occurred. When an entry is made on the provides FREQUENCY digital display and in-
keyboard, the IN 5X address causes a data bit to be dicator drive signals, RDL/DDM/MOD display in-
returned over the parallel data bus to CPU dicator drive signals, and MODE display indicator
assembly A2A1. The data bit indicates the matrix drive signals.
position of the key and identifies the key function.
When the entry is made on a key that lights, the R F LEVEL display driver circuit operation is the
CPU supplies data bits and addresses back to same as described for the RDL/DDM/MOD dis-
AlA1. The I/O write pulse and the decoded ad- play driver circuit, except that decoded addresses
dress cause the key indicator circuit to accept the OUT 4B, OUT 4C, OUT 4D, and OUT 50 are used to
data bits, and the key indicator produces a signal latch the data bit input, and the circuit provides
that lights the key, indicating that the key func- R F LEVEL digital display and indicator and R F
tion is selected. STATUS indicator drive signals.
Data bits from the parallel data bus and the CPU b. Address Decoder Circuit Operation (Refer to
are supplied to ,the bar/blank circuit. When the figure 7.)
I/O write pulse occurs with a decoded address of Address bits A0 through A7 are supplied to con-
OUT 51, the bar/blank circuit accepts the data nector J1 from CPU assembly A2A1. Address bits
bits. The data bits cause the circuit to produce AO, A l , A2, and A6 are supplied to decoders U5,
either bar or blank signals that are supplied to the U19, and U47. Address bit A6 is also supplied to
RDL/DDM/MOD, FREQUENCY, and R F LEVEL NAND gate U1C. Address bit A3 is supplied to
displays. Blank 1, 2, and 3 signals blank the NAND gate U28B, and through inverter UlB, to
RDL/DDM/MOD, FREQUENCY, and RF LEVEL NAND gates U28A and U28C. Address bit U4 is
displays respectively. Bar 1 and 2 signals cause the applied to NAND gate U28A and, through inverter
RDL/DDM/MOD and FREQUENCY displays, UlD, to U28B and U28C. Address bit A7 is applied
respectively, to display dashes. The bar 3 signal through inverter U1A to U28A, U28B, and U28C.
causes the RF LEVEL display to display OFF. Address bit A5 is not used in the decoder circuit.
Data bits determine the specific signal produced When the hexadecimal address from A2A1 is 40 to
by the bar/blank circuit. 47, U28C produces a logic 0 that enables decoder
OUT 4 0 7
OUT 44 J
OUT 45
OUT 46
OUT 47 1 FREQUENCY-MODE
DISPLAYS
OUT 48
OUT 49
OUT 4A I
-
O r DECODER
U19
-
48,49 O -C
-
U1D 4A-4F ENABLE OUT 40)
A4 14 - I\.
4)
U28B
--
OUT 4E; RDL/DDM/MOD D!SPLAY
OUT 4F; FREQUENCY DISPLAY
-- - -C
OUT
OUT
5 0 . RF LEVEL D l SPLAY
51 ; BAR/BLNK CKT
- 1
OUT 52
DECODER
-
0 U47 OUT 53 KEYBOARD INDICATORS
-
r OUT 54
-
50-56 ENABLE OUT 55
U1A
A7 7
U28A
- -
OUT 5 6 ; KEYBOARD MATRIX
u 1C
U48A
- I N 5X; KEYBOARD MATRIX
!/OR0 15
DECODER OUTPUT
LOGIC 1
OUT 40
OUT 41
OUT 42
OUT 43
OUT 44
OUT 45
OUT 46
OUT 47
OUT 48
OUT 49
OUT 4A
OUT 48
OUT 4C
OUT 40
OUT 4E
OUT 4F
OUT 50
OUT 51
OUT 52
OUT 53
WT 54
CUT 55
OUT 56
U5. When the hexadecimal address is 48,49, or 4A gate U66, U67. Location of the key in the matrix
through 4F, U28B enables decoder U19. When the determines the data bit that is a logic 0 when the
hexadecimal address is between 50 and 56, U28C switch is closed. Refer to figure 8 for a table of scan
enables decoder U47 and NOR gate U48A. Refer to data bits supplied to the keyboard matrix and the
figure 7 for a n address decode truth table. data bit out for each'key closure.
The I/O write (F) pulse from CPU assembly A2A1 When the address decoder supplies an IN 5X (F)
is applied through J1 to decoders U5, U19, and signal to the keyboard read gate, the gate applies
U47. When the address is between 40 and 47, data bit pattern to connector J1 and, through the
decoder U5 is enabled and the I/O write (F) pulse data bus, to CPU assembly A2A1.
strobes the decoder, which produces a logic 0
decoded address output pulse. The decoded address d. Keyboard Indicator Circuit (Refer to figure 9.)
label is the same number a s the hexadecimal code
on the parallel address bus. For example, if the Data bits DBO through DB5 from the parallel data
binary/hexadecimal code on the address bus is 40, bus and CPU assembly A2A1 are applied through
the decoded address label is OUT 40. connector J1 and buffer U63 to TONE SELECT
key indicator latch no 1 U56, TONE SELECT key
Decoders U19 and U47 operate in the same manner indicator latch no 2 U58, FUNCTION/CONTROL
a s U5, except that U19 is enabled by U28B when key indicator latch U60, and R F SELECT key in-
the parallel address on the bus is between 48 and dicator latch U65. The address decoder circuit
4F, and U47 is enabled by U28A when the address supplies the decoded port address OUT 52 to U56,
on the parallel bus is between 50 and 56. OUT 53 to U58, OUT 54 to U60, and OUT 55 to U65.
When the decoded port address strobes the latch,
Figure 7 contains a chart showing the parallel ad- the data bits a t the latch input are latched and a
dress bus inputs and the decoded address output logic 1 is applied through the applicable inverting
when an I/O write (F) pulse occurs. Destinations lamp driver to the key lamp. The lamp driver
of the decoded addresses are also shown. supplies a ground to the lamp causing the lamp to
light, indicating that the key function is selected.
The I/O read (F) pulse from CPU A2A1 is applied Refer to figure 9 for a chart containing keyboard
through J1 to U48A. When the address is between indicator operational data.
50 and 57 and an I/O read (F) pulse occurs, U48A
supplies a logic 1 to U1C that is ANDed with ad- e. Bar/Blank Circuit (Refer to figure 10.)
dress bit A6, causing U21C to supply a logic 0 IN Data bits DBO through DB5 from the parallel data
5X signal to the keyboard matrix input port. bus and CPU assembly A2A1 are applied through
connector J1 and buffer U63 to bar/blank latch
U26. Decoded address OUT 51 from the port ad-
c. Keyboard Matrix Circuit (Refer to figure 8.) dress decoder circuit is supplied to U26. When the
decoded address strobes U26, the parallel data bits
Data bits from the parallel data bus and CPU a t the input are latched in U26.
assembly A2A1 are applied to connector J1. Data
bits DB6 and DB7 are applied from J1 directly to When DB5 is a logic 1, a bar 1 logic 1 is applied
keyboard scan latch U62, U64. Data bits DBO through buffer U27B, inverters U32A, U32F,
through DB5 are applied through buffer U63 to the U34A, U34E, and U34F, and connector 52 to the g
keyboard scan latch. segments of the RDL/DDM/MOD display on
AlA2. When DB4 is a logic 1, a bar 2 logic 1 is
During the keyboard scan that occurs a t 4- applied through buffer U27C, inverters U39A,
millisecond intervals, each data bit is a logic 0 in U39F, U42A, U42F, U45A, and U45F, and connec-
sequential order starting with DBO. When each tor 52 to the g segments of the FREQUENCY dis-
data bit is a logic 0, all other data bits ar;! a logic 1. play on AlA2. When DB3 is a logic 1, a bar 3 logic 1
Decoded address OUT 56 from the address decoder is applied through buffer U27A, inverters U49,
circuit enables the keyboard scan latch, and the U52, and U54, and connector 52 to the appropriate
logic 0 data bit signal is applied to each row of the segments of the RF LEVEL display on A2A1. The
keyboard matrix sequentially. When a key is bar 1, bar 2, and bar 3 signals are also supplied to
pressed, the logic 0 from the keyboard scan latch is OR gates U55C, U55B, and U55A, respectively,
supplied through the closed key to keyboard read causing the display decoders to blank all segments.
W T 56;
ADDRESS
DEOCDER 7
KEYBOARD SCAN GATE
U62. U64
Keyboard Operation
Figure 8
+12 v oc
OS1 pmGmq
0s: pizxl
OSI4pJ
~ s 1 5 m
~~27-1
OS3 1-
0 ~ 1 6 m
0~28-
BUFFER
D S Z ~ ~
0~321-
OS4
OS6
DSIS piFE-j
0544 f
0 ~
OSll 1-
~~13-
OES 1 KEY
11
1
OCO AORS
OUT 5 4
OES I KEY
I
I
(
DCO ADRS
OUT 5 5
OES I KEY
I
10527 1 4 0 0 Hz IDS28 1 1 3 0 0 Hz I DS32 ISTO I N/C 1 (RSVO)
1 1 3 ~ ~ ~ 1 :?:1
~ A
(RSW)
R (RSVO) 1 izz RF FREQ I
( RSVO )
When the bar 1 signal is a logic 1, logic 1 is applied The bcd-to-7 segment driver U29 converts the bcd
t h r o u g h U55C a n d i n v e r t e r U32E t o t h e input to the 7-segment outputs required to drive
RDL/DDM/MOD display driver circuit and causes t h e digital display for digit no 1 of t h e
the circuit latch to remove all outputs (blank). The RDL/DDM/MOD display. The seven outputs from
bar logic 1 is then applied through an inverting the driver are applied through 52 to the 7-segment
driver to the display, causing the digital display to digital display on AlA2.
produce a bar for each digit. The bar 2 signal When a bar 1 (F) signal is produced in the
o p e r a t e s in t h e s a m e m a n n e r f o r t h e bar/blank circuit, a blank 1 signal is also
FREQUENCY display using U55B and inverter produced. The blank 1signal is supplied to U29 and
U36F. The bar 3 signal operates in the same inhibits the outputs. The bar 1 signal is then
manner as the bar 1 signal using U55A and in- supplied through 52 to the 7-segment digital dis-
verter U21D, except the RF LEVEL display in- play for digit no 1 of the RDL/DDM/MOD display
dicates OFF. on A1A2 and causes only a bar (segment 9) to be
displayed. When the bar/blank circuit produces
When DB2 is a logic 1, a blank 1 signal is applied only a blank 1 signal, the outputs of U29 are in-
through U55C and U32E to the RDL/DDM/MOD hibited and display is blanked.
d i s.~ l "a vcircuit and all latch outputs are removed,
causing the corresponding digital display on A2A1
to be blank. When DB1 is a logic 1, a blank 2 signal g. RDL/DDM/MOD and AUDIO STATUS Driver
is applied through U55B and U36F to the and Display Circuit (Refer to figure 12.)
FREQUENCY display and blanks the correspon- Data bits DBO through DB5 from the parallel bus
ding digital display. When DBO is a logic 1, a blank and CPU assembly A2A1 are applied through con-
3 signal is applied through U55A and U21D to the nector J 1 and buffer U63 to decimal point latch U9;
RF LEVEL display on AlA2, and blanks the cor- digit no 1 driver circuit U2, U29; digit no 2 driver
responding digital display. circuit U3, U30; digit no 3 driver circuit U4, U31;
digit no 4 driver circuit U6, U33; and digit no 5
driver circuit U8, U35. The address decoder circuit
f . Display Driver Circuit supplies decoded addresses OUT 4E to U9; OUT 40
to U2, U29; OUT 41 to U3, U30; OUT 42 to U4, U31;
Figure 11 shows the RDL/DDM/MOD display OUT 43 to U6, U33; and OLTT 44 to U8, U35. When
digit no 1 circuit as a typical display circuit that is a driver circuit receives the applicable decoded ad-
used for discussion purposes. All display driver dress, data bits a t the input are strobed and
circuits for the RDL/DDM/MOD, FREQUENCY, latched in the driver circuit. The data bits deter-
and RF GAIN displays are shown on figures 12 mine the numeral and the indicators that are to be
through 14. displayed on AlA2. The decimal latch determines
the decimal position in the display. The decimal
Data bits DBO through DB5 from the parallel data latch output and outputs from the driver circuits
bus and CPU assembly A2A1 are applied through are applied through connector 52 to applicable
connector J 1 and buffer U63 to RDL/DDM/MOD digit displays on AlA2.
digit no 1 latch U2. When decoded address OUT
40 from the address decoder circuit is supplied to
the latch, the data bits a t the input to U2 are Display board A1A2 contains the 7-segment dis-
latched. plays and LED's that provide a readout of signal
generator output parameters and characteristics.
Data bits DBO through DB3 determine the The displays and LED's are driven by signals from
numeral that is to be displayed, and data bits DB4 keyboard/driver board AlA1. A chart on figure 12
and DB5 determine the indicators to be lit. Latch provides the inputs required for a specific 7-
U2 supplies data bits DBO through DB3, which segment display.
comprise the bcd number to be displayed to bcd-to-
7 segment driver U29. Data bit DB4 is applied h. FREQUENCY and MODE Driver and Display Cir-
from the latch through driver U7D and connector cuits (Refer to figure 13.)
52 to the RDL/DDM/MOD display TO indicator.
Data bit DB5 is applied from the latch through Operation of FREQUENCY and MODE driver and
driver U7B and connector 52 to the AUDIO display circuits is the same as described for the
STATUS display VAR FREQ indicator. RDL/DDM/MOD and AUDIO STATUS driver
Revised 1 October 19 78 37
Scans by ArtekMedia © 2008
description 523-0768882
W T 40;
-
P/O J1 ADDRESS
DECCOER -
\
DB5
-
P/O J2
-
RDL,nDM/
DO 27 A' BUFFER Mm
Dl 23
-
-
U63 DIGIT
NO. 1
084
47 ) T O 1 INOICATIX
- 1
02 30 LATCH DB3
03 25 / U2
04 28 085 '
D5 29 -, + 5 V M: * DRIVER
-
R3
r
N/C 4
BAfi/BLANK 1
BAR/BLANK
CIRCUIT
w
and display circuits described in paragraph g, ex- signals necessary for the internal operation of the
cept that the information is displayed on the 7- signal generator.
segment FREQUENCY display and indicators and
the MODE indicators. All audio modulation signals required for signal
generator operation are input to analog board A2A2
i. RF LEVEL and R F STATUS Driver and Display from TDM board A2A3.
Circuits (Refer to figure 14.)
10.3.3 CPU Assembly A2Al (Refer t o figure 15.)
Operation of R F LEVEL and R F STATUS driver
and display circuits is the same a s described for A 16-MHz crystal-controlled clock is frequency
the RDL/DDM/MOD and AUDIO STATUS driver divided to provide a 2-MHz @I (CLOCK) signal to the
and display circuits described in paragraph g, ex- CPU and a 1-MHz input to the interrupt timer, which
cept that the information is displayed on the 7- is strapped to provide an interrupt signal every 4
segment RF LEVEL display and indicators and on milliseconds for use as a real time clock for system
the R F STATUS indicators. The R F LEVEL 7- timing.
segment displays indicate OFF when bar inputs
are supplied to the 7-segment drivers. A delayed I/O request (I/O REQ) is gated with either
a read (m) or a write (WR) pulse from the CPU to
provide
- one of the two major 1/0 control signals, I/O
10.3 CONTROLLER/AUDIO ASSEMBLY A2
RD or I/O WR. A memory request signal (MREQ) is
gated with an RD or WR signal to provide one of the
10.3.1 General
two major memory control signals, MEMRD or
Controller/audio assembly A2 consists of CPU MEMWR.
assembly A2A1, analog board A2A2, and TDM board
A2A3. There are 16 address lines (A0 through A15) and 8
data lines (DO through D7) available on the CPU chip.
10.3.2 Overall Operation All eight data lines, and address lines A0 through A7
are bused to other assemblies in the signal generator
The CPU assembly A2A1 section of controller/audio to provide I/O data transfers. All eight data lines are
assembly A2 provides all the control and information also bused to the 2716 2-k EPROM's and the 8111-4
256 x 4-bit RAM'S in the memory array for program applied through phase adjust control R11 and buffer
and data storage. Address lines A0 through A10 are amplifier U6 to the AUX connector on the rear panel
used to address the ROM memory, consisting of 12 of the signal generator. Phase adjust control R11
(maximumj 2-k memory chips for 24-k (maximum) allows the phase of the 30-Hz reference signal a t the
total program storage. Address lines A0 through A7 AUX output to be adjusted with respect to the 30-Hz
are used to address the RAM memory, consisting of 1 variable signal a t the COMP output.
k maximum in 256-byte blocks. Addresses A8, A9,
and A l l through A15 are decode by decoder chips When any of the other tones are selected, switch U2B
U27 and U36 and provide chip enable signals m,for is enabled to the up position by a logic 1 EO ENABLE
the ROM memories, and m f o r the RAM memories. signal from P1-30. The modulation tone is then input
The memory read (MEMRD) signal is used as a chip to summing amplifier U15.
select (m) for the ROM memories and controls the
bus buffers. Memory write (MEMWR) controls the The DAC B (P123) input provides the 30-Hz variable
read/write mode of the RAM memory. signal in VOR mode and the 90-Hz, 150-Hz, or 90/150-
Hz composite signals in ILS mode. The modulation
10.3.4 Analog Board A2A2 tones are applied through amplifier U7, and level ad-
justment is provided by R3. In VOR mode, when the
10.3.4.1 General 30-Hz variable tone is selected, switch U3B is disabled
to the ground position and switch U2A is enabled to
The analog board takes the required modulation the up position by enable signals from PI-27 and PI-
signals from TDM board A2A3. The anlog board then 32. The 30-Hz variable tone is applied through VOR
adjusts the gain and phase, filters, and combines phase adjust control R8 and VOR gain adjust control
these signals. The composite modulation signal is R9 to summing amplifier U15. VOR phase adjust con-
supplied to the COMP connector on the rear panel and trol R8 adjusts the phase of the 30-Hz variable signal
to demodulator/ALC assembly A3A2. . When the VOR composite signal. This phase relationship is
signal generator is in the VOR mode, the 30-Hz measured a t the COMP output using a VOR bearing
reference signal is supplied to the AUX connector on standard. In ILS mode when 90 Hz, 150 Hz, or 90 and
the rear panel. 150 Hz is selected, switch U2A is disabled to the
ground position and switch U3B is enabled to the up
Digital pulse density inputs from TDM board A2A3 position by enable signals from PI-27 and PI-32. The
are input to the analog board. The digital signals are 90/150-Hz tone is applied through ILS balance and
converted to dc voltages and sent back to TDM board filter circuit and ILS gain adjust control R4 to sum-
A2A3 for d/a converter operation, and to synthesizer ming amplifier U15. ILS balance control R7 balances
assembly A4 through demodulator/ALC assembly the amplitudes of the 90- and 150-Hz tones.
A3A2 for rf frequency slewing (AF) control.
The DAC C (PI-21) input provides the following
10.3.4.2 Modulation Circuits (Refer t o figure 16.) signals:
All modulation tones are input to analog board A2A2 a. The 9960-Hz or 9960 FM tone in VOR mode.
through the DAC A, DAC B, and DAC C inputs. The b. The variable audio in LOC or GS modes.
DAC A input (Pl-29) provides the following signals: c. COMM variable audio tones, 3000 to 10 000 Hz.
d. VOR variable audio tones, 3000 to 14 000 Hz.
a. All marker beacon tones.
b. The VOR 30-Hz reference signal. Modulation tones are applied through sample and
c. VOR variable audio tones 10 to 2999 Hz. hold circuit U19, Q1, C11, and C16. The 1-MHz
d. COMM variable audio tones 10 to 2999 Hz. SAMPLE signal (PI-15) is applied to sample chopper
Q1. The DAC C signal is sampled a t the same rate as
The modulation tones are applied through amplifier the d/a conversion rate (1 MHz) on TDM board A2A3
U11, and level adjustment is provided by R12. The to eliminate d/a conversion switching spikes. Gain
signal is then applied through low-pass filter R110, adjustment for the sample and hold circuit is
C3, R112 and gain adjust control R10 to switch U2B. provided by level adjust control R2.
When VOR 30-Hz reference signal is selected, switch When ILS variable audio tone is selected, switch U3C
U2B is disabled to the ground position by a logic 0 EO is disabled to the ground position and switch U3A is
ENABLE signal. The 30-Hz reference signal is then enabled to the up position by signals from PI-24 and
LT
49
-111 AUDIO STATUS
n VAR % MOD VAR FREQ STANDARD
u360
55
=
(CR17)
=
tCR19)
=
(CR211
OUT 4 1 , 1 U32D -
AWRESS D E C M X R ~
BUFFER U7C
RDL/WM/MDO
Y
2 D I G I T NO. 2 a
/ DRIVER CKT .b
U3, U30 c
-
d
e
0 f
cl
l NPUT
D l SPLAYED
U32B NUMERAL
0 0 1 0 1 ~ 1 0 1 0 1 0 1 1
i!Ffz ~1 ~
RSVD
l o u T 4 2 ;
ADDRESS DECODER DRIVER CKT
24
BLANK 11 11 11 11 1 1 11 11
BAR 11 11 1 1 11 1 1 11 10
NOTE
REFER TO FREQ 0 ISPLAY D IAG FOR C IRCll ITRY
Rc~l~iserl
1 October 1978
Scans by ArtekMedia © 2008
P/O J2 1 P/O P2
I P/O KEYBOARD/ DRIVER BOARD
AlA1 1 h U37E
1581 1 I FREQUENCY
63 MODE
DECIMAL LATCH
SELF TEST ME VOR LOC GS
P I 0 DISPLAY BOARD
ADDRESS DECODER A1A2
D l G l T NO. 1
DDRESS DECODER
D l G l T NO. 2
ADDRESS DECCOER
D l G l T NO. 3
DRIVER CKT
U13.U41
OUT 4 8
ADDRESS DECOOEP
--
OUT 49 ADgRESS
DECOOER
FREQ NOTE :
D l G l T NO. 5
DR IVER CKT 102 @ REFER TO RDL/DDMA403 0 ISPLAY FUNCT l ONAL
U16,U44 D l A G FOR INDICATOR LOCATION.
O L
104
WIT 4 A ; ADORESS
P
U45F 110
DECODER
117
* Y
R e ~ t i s ~1dOctober- 1978
description 523-0768882
256 x 4-bit RAM'S in the memory array for program applied through phase adjust control R11 and buffer
and data storage. Address lines A0 through A10 are amplifier U6 to the AUX connector on the rear panel
used to address the ROM memory, consisting of 12 of the signal generator. Phase adjust control R11
(maximum) 2-k memory chips for 24-k (maximum) allows the phase of the 30-Hz reference signal a t the
total program storage. Address lines A0 through A7 AUX output to be adjusted with respect to the 30-Hz
are used to address the RAM memory, consisting of 1 variable signal a t the COMP output.
k maximum in 256-byte blocks. Addresses A8, A9,
and A l l through A15 are decode by CE decoder chips When any of the other tones are selected, switch U2B
U27 and U36 and provide chip enable signals m,
for is enabled to the up position by a logic 1 EO ENABLE
the ROM memories, and CE2 for the RAM memories. signal from PI-30. The modulation tone is then input
The memory read (MEMRD) signal is used a s a chip to summing amplifier U15.
select (m) for the ROM memories and controls the
bus buffers. Memory write (MEMWR) controls the The DAC B (P123) input provides the 30-Hz variable
read/write mode of the RAM memory. signal in VOR mode and the 90-Hz, 150-Hz, or 90/150-
Hz composite signals in ILS mode. The modulation
10.3.4 Analog Board A2A2 tones are applied through amplifier U7, and level ad-
justment is provided by R3. In VOR mode, when the
10.3.4.1 General 30-Hz variable tone is selected, switch U3B is disabled
to the ground position and switch U2A is enabled to
The analog board takes the required modulation the up position by enable signals from PI-27 and P I -
signals from TDM board A2A3. The anlog board then 32. The 30-Hz variable tone is applied through VOR
adjusts the gain and phase, filters, and combines phase adjust control R8 and VOR gain adjust control
these signals. The composite modulation signal is R9 to summing amplifier U15. VOR phase adjust con-
supplied to the COMP connector on the rear panel and trol R8 adjusts the phase of the 30-Hz variable signal
to demodulator/ALC assembly A3A2. .When the VOR composite signal. This phase relationship is
signal generator is in the VOR mode, the 30-Hz measured a t the COMP output using a VOR bearing
reference signal is supplied to the AUX connector on standard. In ILS mode when 90 Hz, 150 Hz, or 90 and
the rear panel. 150 Hz is selected, switch U2A is disabled to the
ground position and switch U3B is enabled to the up
Digital pulse density inputs from TDM board A2A3 position by enable signals from PI-27 and P1-32. The
are input to the analog board. The digital signals are 90/150-Hz tone is applied through ILS balance and
converted to dc voltages and sent back to TDM board filter circuit and ILS gain adjust control R4 to sum-
A2A3 for d/a converter operation, and to synthesizer ming amplifier U15. ILS balance control R7 balances
assembly A4 through demodulator/ALC assembly the amplitudes of the 90- and 150-Hz tones.
A3A2 for rf frequency slewing (AF) control.
The DAC C (PI-21) input provides the following
10.3.4.2 M o d u l a t i o n Circuits (Refer t o figure 16.) signals:
All modulation tones are input to analog board A2A2 a. The 9960-Hz or 9960 FM tone in VOR mode.
through the DAC A, DAC B, and DAC C inputs. The b. The variable audio in LOC or GS modes.
DAC A input (PI-29) provides the following signals: c. COMM variable audio tones, 3000 to 10 000 Hz.
d. VOR variable audio tones. 3000 to 14 000 Hz.
a. All marker beacon tones.
b. The VOR 30-Hz reference signal. Modulation tones are applied through sample and
c. VOR variable audio tones 10 to 2999 Hz. hold circuit U19, Q1, C11, and C16. The 1-MHz
d. COMM variable audio tones 10 to 2999 Hz. SAMPLE signal (PI-15) is applied to sample chopper
Q1. The DAC C signal is sampled a t the same rate a s
The modulation tones are applied through amplifier the d/a conversion rate (1 MHz) on TDM board A2A3
U l l , and level adjustment is provided by R12. The to eliminate d/a conversion switching spikes. Gain
signal is then applied through low-pass filter R110, adjustment for the sample and hold circuit is
C3, R112 and gain adjust control R10 to switch U2B. provided by level adjust control R2.
When VOR 30-Hz reference signal is selected, switch When ILS variable audio tone is selected, switch U3C
U2B is disabled to the ground position by a logic 0 EO is disabled to the ground position and switch U3A is
ENABLE signal. The 30-Hz reference signal is then enabled to the up position by signals from PI-24 and
BUFFER P/O P 2
I
- 10 AUX OUT
7 COMP M)N
EO ENABLE
VOR
E l ENABLE
DAC B
I LS
E l ENABLE
I LS
E2 ENABLE
DAC C
SAMPLE
m VOR 9 9 6 0 Hz OR 9 9 6 0 FM ENABLE 1
E2 ENABLE
PI-25. The signal is applied through filter R38, R39, composite modulation signal. The composite signal is
C15 and gain adjust control R5 to summing amplifier applied through filter L1, L2, L3, C19, C20, C21 to
U15. remove d/a converter switching noise to buffers U14
and U20. Buffer U20 is output through P2-4 to
When any of the other tones are selected, switch U3A demodulator/ALC assembly A3A2. Buffer U14 is out-
is disabled to the ground position and switch U3C is put t l ~ r o u g hP2-7 to the COMP connector on the rear
enabled to the up position by signals from PI-24 and of the signal generator.
PI-25. The 9960 signal is applied from PI-21. The 9960
signal is applied through filter R33, R34, R35, C16, 10.3.4.3 Pulse Density Circuits (Refer to
C17 and gain adjust control R6 to summing amplifier figure 1 7 . )
U15.
Analog board A2A2 contains four similar pulse den-
Amplifier U15 sums all selected modulation tones sity circuits. For simplicity, only one circuit is sllown
from switches U2 and U3 and combines them into a in figure 17.
'-----l
1LOW PASS F I L T E R
I BUFFER
TUNE
The PDO through PD3 pulse density inputs to analog amplitude level of the modulation tones output to the
board A2A2 are digital signals whose pulse densities analog board.
can be changed by TDM board A2A3. Signal PD3
from PI-10 is input to inverter U5A. The supply 10.3.5 TDM Board A2A3
voltage to U5 is provided by +12-V \dc regulator U1,
VR3, R1. Temperature-compensated precision Zener 10.3.5.1 General
reference diode VR3 controls the reference voltage to
amplifier U1, and voltage adjustment is provided by TDM board A2A3 is provided frequency, phase, and
+12-V dc adjust control R1. The +12-V dc output modulation requirement information from the CPU
from U1 is filtered by L9 and C34 before being input control bus and uses that information to generate the
to inverter U5A. The output of U5A is then applied required modulation signals.
through the remaining inverters of U5 in parallel.
The output of the parallel inverters is applied through 10.3.5.2 Overall operation (Refer t o figure 18.)
low-pass filter R58, C39, R62, C40 and buffer U4 to
connector P2-1. The low-pass filter converts the pulse The control logic provides the control and timing for
density input signal to a dc voltage. As pulse density the audio generator. Control registers CO and C1 are
decreases, dc voltage decreases; as pulse density in- programmable by the CPU. CO is a t address 30 and C1
creases, dc voltage increases. In standard signal is a t address 31 (hexadecimal). The control register
generator operations, the AMO, AM1, and AM2 are outputs provide control signals to all parts of the
fixed voltage levels. TDM board and to analog board A2A2 switching cir-
cuits.
The VCXO TUNE output dc voltage controls an os-
cillator frequency on synthesizer assembly A4. When When the CPU writes to addresses 20 through 2F,
the A F key on the front panel of the signal generator data is loaded into the buffer memory. At the end of
is pressed, the VCXO tune voltage is slewed under con- the I/O read or write pulse, the data is shifted into
trol of the CPU until the rf frequency display in- whatever memory is addressed by the control latch.
dicates an rf frequency near the channel frequency.
The rf frequency can then be increased or decreased The phase buffer memory is loaded with the phase of
by varying the VCXO tune voltage up or down. the four TDM generator channels following an I/O
read or write if the TDM generator is addressed by
The AMO, AM1, and AM2 outputs control the the control latch. The contents of the phase buffer
reference voltage to the multiplying d/a converters memory may be read during an I/O read, regardless
on TDM board A2A3. These d/a converters produce of the control latch memory address.
audio modulation waveforms. When the percent of
modulation is changed on the front panel of the signal The AM generator provides the programmable dc
generator, the AMO, AM1, or AM2 dc level increases voltages (AMO, AM1, and AM2) used to control the
or decreases. This changes the reference voltage to amplitude of the audio signals (DAC A, DAC B, DAC
they multiplying d/a converters, which changes the C) produced by the TDM and FM generators. The dc
t
table 5.
The FM generator operation is similar to that of the Address bit Refer to
TDM generator except that it has a frequency table 5.
modulation input. Mode bit Refer to
table 6.
The center frequency is programmed by the CPU via
the buffer memory. The sinusoidal FM deviation
signal is derived from the TDM generator.
CPU
DATA
CPU
TS
ADDRESS
A7
- - - -
- -T TO.-
FMWEN
FM GENERATOR r - - I - - - Scans
- - - -by
- -ArtekMedia
- - -FSAW
- - 0-9© 2008 FSAW 9 CHC 7
1,
1 7 ILS E2
I I U45
U48
U46
U47
U70
U71
'
U69
U72
VOR E2 I,
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-
1 1
MEM CI * /I/M MA rn v1 1 SAMPLE TO
BOARD
ANALOG
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C
CHC
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I
REG
- C 5 A XOR SINE
XOR
0-7
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U20
U43
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FMlNCK-
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REG FMSELEN -D
0s'~
I I
I
U4 1
U65 U66
-
U67
FM SINE CODE CONVERTER
-
a
30 Hz REF
I
------- ----- ----- - - --
P
t C
U2, U6
-C U5r 29 1
4 CHANNELS
32 - BITS
TDM SINE CODE CONVERTER -1 TDM ACCUMULATOR LOGIC
VOR E l -- I
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FREQ
CI r I
-
MEM
REG cI r
NV\ m
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REG SINE U39,59,62 U40.60 > U118
4 co XOR ROM * XOR '
- I I
(Tl-T4)
t
CK
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1
1 U4
I ,DAC
REG (0-9)
U28 c REG
REG CK
F CO1
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I U11
U15
U12
U36 iL
U13
U37
R R
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TO ANALOG
BOARD
I
CK CK
0
MEM
-
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I- F
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U38
U58 t C06 t
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0 DATA
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A
U30
REG
CH A
(0--8)
U92, 117
DAC
I
----- CORRECTION A
-- U56, U81
AMGENERATOR
U102
4 DC VOLTAGES GENERATED
A M O 4 A M 2 = DAC REF
--
CONT
C13 I VXCO TUNE C04 DACACK
a -1
---- ------
LATCH SHIFT (T2)
1
-
U115 U116
U103
U104
I - SHIFT
REG
c REG
-
LEVEL
SHIFT I
TDM TIMING
TO ( 4 MHz)
b I
-
C
CONT
0
LATCH - COO I U114
CK
t
U52
OSC (8 MHz)
4 U 75
41
U83
CK
I
T4 DECODE
U89
P
, I3 CI r
1
3113
I MHz +2 . -
*
C 2 -
i
r COUNT a
w 0
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NABLE I ,T ( 1 4 ) D I
1
U87
AMWEN
U88
REGCK REGCK I I I
I I I I
signals: SYNC TIMING, P H READ ENABLE, in U75 to provide 4-MHz TO and signals. is
BUFWEN, and BUFFER XFER. The sync timing used to clock counter chip U82 that drives U83 to
signal is used to clock in data to the control latch and provide timing signals T I through T4. T1 is a t a rate
synchronize the update of control registers 0 and 1 of 2 MHz and T2, T3, and T4 are a t frequencies one-
with the TDM board internal clock. Phase read enable half the rate of the next lower T ( ) signal; for exam-
allows the 3-state buffer (U55 and U79) to write phase ple, T2 is one-half the rate of T1, or 1 MHz.
information on the CPU data bus; BUFWEN (buffer
write enable) allows information on the CPU data bus 10.3.5.6 AM Generator (Refer t o figure 18.)
to be written into the buffer memory (U54, U78) dur-
ing an I/O write to a proper I/O port. BUFFER XFER The AM generator has four time division multiplexed
goes low a t the end of an I/O read or write pulse and channels each consisting of 4 nibbles of data (1 nibble
stays low until the next rising edge of clock signal ~ 4 . = 4 bits). The 16 nibbles of data are input from the
I t is used to transfer control of tlie data and phase least significant 4 bits of the data buffer memory, 1
buffer memory address lines to the CPU to allow nibble a t a time, to the pulse density memory U87.
CPU-TDM board data exchange. BUFFER XFER is The pulse density memory inverts data when read
also used to generate the sync timing signal discussed from. The pulse density memory outputs go to adder
earlier. chip U88 where they are summed with the outputs of
memory U113. Outputs from U88 are fed back and in-
CPU address information is available from BAD (0-3) verted through register U89 to memory U113. This
lines only when BUFFER XFER is low. This coincides time division multiplexed digital integration process
with the write enable pulses from U84 and allows the results in carry pulses from the C4 output of U88. At
transfer of data from buffer memory to whatever proper times, these carry pulses are input to shift
memory is specified by C13 and C14 if an I/O write is register U114. Outputs from the shift register drive
taking place. latch chip U115. U116 is an open collector inverter
chip that inverts and level shifts the outputs of U115.
The outputs of U116 go to analog board A2A2, which
10.3.5.4 TDM Data 110 (Refer t o figure 18.) has pullup resistors to 15 V dc. A large binary number
stored in the pulse density memory causes fewer
Buffer memory chips U54 and U78 are write enabled carry pulses, in turn causing the pulse density output
by the BUFWEN signal, which can be updated only to be high a larger percentage of the time. These pulse
during an I/O write pulse. Information on the CPU density outputs are used by analog board A2A2 to
d a t a bus is input to the buffer memory and control the amplitude of the generated audio signals.
transferred to addressed memory a t the end of the
I/O write pulse. 10.3.5.7 TDM Phase Generator (Refer t o
figure 18.)
When the TDM phase generator frequency memory
(U2, U26) is write enabled by control bits C13 and Frequency memory chips U2 and U26 are loaded
C14, the phase buffer memory is also write enabled. when control bits C13 and C14 activate and
The instantaneous phase of each TDM channel is BUFFER XFER is activated a t the end of an I/O read
loaded into the phase buffer memory (U56, U81). This or write pulse. Data in frequency memory is added to
phase information may then be read during properly data in phase memory by adders U4 and U28. The
addressed I/O read, regardless of the status of control outputs of the adders are used to drive registers U5
bits C13 and C14, by generating a phase read enable and U28. The outputs of register U5 and U29 drive
from the address decode circuits. The phase read phase memory (U6, U30). They also go to the TDM
enable signal turns on the phase buffer chips (U55, error corrections circuits.
U79) and allows the phase information onto the CPU
data bus. The frequency constant in frequency memory is
made available to the adder inputs on a time division
10.3.5.5 TDM T i m i n g (Refer t o figure 18.) multiplexed basis. The frequency constant is added to
thc phase constant from phase memory each time
The timing signals for TDM board A2A3 a r e that channel is addressed by the timing signals. The
generated from a crystal-controlled 16-MHz oscillator phase memory is then updated with the previous
(Y1 and associated components). The 16-MHz is fre- sum. This digital integration process, consisting of
quency divided by 2 in U52 to provide an 8-MHz (OSC) the continual addition of frequency and phase con-
signal. The OSC signal is again frequency divided by 2 stants, with the phase constant equaling the sum of
the previous frequency and phase, produces a digital 10.3.5.10 TDM Accumulator Logic (Refer t o
sawtooth signal that will be modified to produce the figure 18.)
desired audio outputs.
At this point in the circuit, each TDM channel (CH 0
Time division multiplexing of the frequency memory through CH 3) has 10 bits for representation of phase
outputs; addressing -
the -
frequency memory with tim- and frequency. Table 7 shows the TDM channel
ing signals, TlD, T2, T3, and y; provides four assignments.
separate channels, each programmable in both fre-
quency and phase. Each channel has 32 bits for Table 7 TDM Chanr~elAssign7nent.s.
representing frequency and phase.
MODE CHANNEL
Memory chips U20 and U43 are loaded from buffer Demodulator/ALC Assembly A3A2 will also process
memory when FMWEN is activated by control bits an external modulation signal from the EXT MOD
C13 and C14 and BUFFER XFER goes active a t the connector on the rear panel.
end of an I/O write pulse.
10.4.2 RF Strip Line Assembly A3A1 (Refer t o
When FMSELEN is active, select chips U42 and U66 figure 19 and schematic diagram i n
are strobed to allow selection of accumulator data diagrams section.)
through latches U41 and U65. Adder chip U18 sums
the outputs of the select chips and the outputs of The rf output from synthesizer A4 is input through
demultiplexer chips U21 through U24. connector 52 to power divider/attenuator R1, R2, R3.
With a 50-ohm input, the power divider provides 50-
Adder U19 sums the outputs of U18 and memory ohm outputs with 6-dB attenuation to rf amplifier Q1,
chips U20 and U43 with t h e result going to Q2 through a microstrip delay line and 7.75-dB
demultiplexers U21 through U24. The demultiplexer attenuator R4, R5, R36 and to the microstrip
circuit (U21 through 24) consists of four shift modulator.
registers that are used to store the results of previous
operations for controlled periods of time. The register Rf amplifier Q1, Q2 and associated circuitry amplifies
outputs are available to be latched into U45 and U48 the unmodulated rf signal to +20 dB mW and inputs
to be processed as 10 time concurrent data bits and to the signal to 6-dB attenuator R15, R16, R17. The out-
be fed back as data to U18. put from this attenuator is applied to the microstrip
coupler. The microstrip coupler provides 0-dB mW rf
signal through connector J1 to counter-I/0 board
10.3.5.12 FM Sine Code Converter (Refer t o A3A3 for frequency counting. A through output from
figure 1 8 . ) the microstrip coupler is routed through a microstrip
delay line and 6-dB attenuator R22, R23, R24 to mixer
The 10 signal inputs to the sine code converter from U1. Mixer U1 functions as a synchronous detector by
the FM generator are clocked out of registers U45 and mixing a sample of the modulated rf signal from
U48 as 10 bits representing a sawtooth waveform. As directional coupler CP1, with the +7-dB mW un-
in the TDM generator, they are exclusive ORed to modulated carrier signal from 6-dB attenuator R22,
form triangle waves and converted to digital R23, R24. The output of the mixer is applied through
representations of full-wave rectified sine waves by low-pass filter L4, C14 and P1-6 to demodulator/ALC
the sine ROM (U70, U71). That signal is exclusive assembly A3A2. Filter L4, C14 filters out the mixer
ORed to generate sinusoidal waveforms. sum products and supplies only demodulated audio
and a dc level to A3A2. The dc voltage represents the
The sinusoidal waveform, channels 0 through 7, are level of the rf carrier; ac voltage represents the level
input to DAC C to be output to analog board A2A2. of the modulation sidebands.
10.4 RF Modulator Assembly A3 The rf signal from power divider R1, R2, R3 and the
modulation signal from demodulator/ALC assembly
10.4.1 General A3A2 are applied to the logarithmic microstrip
modulator. The microstrip modulator is composed of
Rf modulator assembly A3 consists of rf strip line C15 through C23, R27 through R35, CR1 through CR8,
assembly A3A1, demodulator/ALC assembly A3A2, and the microstrip circuit. Capacitors C15 through
and counter-I/0 board A3A3. Demodulator/ALC C23 are dc blocking capacitors. Resistors R27 through
assembly A3A2 receives the composite audio signal R34 provide bias voltage to pin diodes CR1 through
from controller/audio assembly A2 and sets reference CR8. The pin diodes are special semiconductor devices
rf and modulation levels. Rf strip line assembly A3A1 that do not rectify a t rf frequencies. Diodes behave
combines the rf carrier signal with the audio modula- like variable resistors whose values are controlled by
tion signal. The unmodulated rf carrier is amplified the dc bias current supplied to them by resistors
and then coupled to counter-I/O board A3A3 to allow whose values are controlled by the dc bias current
a frequency count to be supplied to the front panel supplied to them by resistors R27 through R34. The
display through the processor. Counter-1/0 board microstrip circuit between each diode represents one-
A3A3 also contains I/O ports to allow the processor to quarter wavelength a t center frequency of 205 MHz.
output attenuator select, synthesizer frequency The dielectric constant of the board assembly is ap-
select, and mode control functions. proximately 10.5, which causes the actual length of
the microstrip to be divided by approximately 2.6. is also supplied through amplifiers U7 and U8 and
The actual wavelength of 205 MHz is 365.76 mm (14.4 connector 52-2 to the DEMC)D connector on the rear
in). Dividing by 2.6, the actual length of microstrip panel of the signal generator.
circuit between pin diodes is 138.66 m m (5.459 in). External modulation signals a r e applied to U14
The output of the modulator is applied through through the EXT MOD connector on the rear panel of
capacitor C28 to directional coupler CP1. Capacitor the signal generator and 52-5. The signals a r e in-
C28 allows adjustment for phase compensation in the verted and buffered by U14 and then input to summer
glideslope frequency range. CP1 is a 10-dB rf direc- U16. Output level of modulation signal is set by R5.
tional broadband coupler. A sample of the modulated Amplifier U16 (figure 20) s u m s the inputs and
rf signal is provided to mixer U1 a s discussed integrates to establish the proper loop parameters. A
previously. The through output of directional coupler double integration method is used to minimize phase
CP1 is provided through connector 53 to digitally con- shift introduced into the modulation signal and to
trolled attenuator A6AT1. give optimum noise performance.
10.4.3 DemodulatorlALC Assembly A3.42 The output of U16 is applied to exponential linearizer
(Refer to figure 19.) circuit U12 and to level comparator circuit U17A and
The composite audio signal from analog board A2A2 U17B. The level comparator senses if the output from
is input to demodulator/ALC assembly A3A2 U16 drops above or below a specified dc window level.
through connector 52-1 and low-pass filter L1-C20 to During normal operation, the output of the level com-
modulation level adjust circuit U9 and U13 (refer to parator is low and the LEVEL CAL indicator on the
figure 19. The gain of amplifier U9 is controlled by front panel is on. If the output level from U16 exceeds
switch a r r a y U13. I/O A and I/O B control signals the specified U17 window level, the comparator out-
from 52-10 and 52-7 are input to a binary to 1-of-4 put will go high and is output a s the rf level bit
decoder in U13. The code present a t the input to the through connector U2-80. The output goes high only if
decoder determines which switch is energized. The the rf signal is s h u t off on the front panel, or if a cir-
four switches select which feedback resistor will set cuit fails in the signal generator. If the rf signal is
the gain on amplifier U9. Variable resistors R1, R3, shut off on the front panel or if a circuit fails, the
R2, and R4 adjust the percent of modulation for audio LEVEL CAL indicator on the front panel will turn
tones for marker beacon, glideslope, localizer, and off, signifying t h a t the signal generator must be
VOR frequencies respectively. Refer to the chart in repaired.
figure 20 for I/O A and B inputs required for modula- Exponential linearizer circuit (figure 21) U12 is re-
tion selection. The selected composite signal from U13 quired to compensate for the logarithmic modulator
is applied to U10. U10 and associated circuitry is a on rf strip line assembly A3A1. When the exponential
high impedance ac follower circuit. The output of U10 and logarithmic functions a r e combined, t h e resul-
is then applied to summer/integrator circuit U16. t a n t output from A3A1 will be the required linear
Rf level adjust circuit U1 and U4 provides a dc function. Q1 through Q4 are connected a s diodes.
reference value through buffer U5 to summer/ When the input to U12 is low, current output through
integrator circuit U16. U1 and U4 work identically the feedback loop is insufficient to turn on any tran-
a s the U9, U13 circuit. The I/O C and D signals from sistor, and the gain of the circuit is low. As input to
52-11 and 52-12 control the switch selection in U4. U12 is increased, Q4 will turn on and effectively
Variable resistor R7 sets the gain of amplifier U1 in remove its leg from the feedback loop, and gain will
the marker beacon range, R6 sets the gain in the increase. Again, a s the input increases, Q3, Q2, and
glideslope range, a n d R8 s e t s t h e gain in the Q1 will t u r n on and remove their legs from the feed-
VOR/localizer range. back loop until the effective resistance in the feed-
back loop is the value of R15. Values of the resistors
The demodulated audio signal from rf strip line
in the feedback loop a r e selected so t h a t the resultant
assembly A3A1 is also supplied to summer/
gain of the circuit from minimum to maximum out-
integrator circuit U16 through connector 53-6 and
put will be an exponential curve, a s shown in figure
amplifier U11. The demodulated signal is an ac-plus-
a-dc signal. The ac signal level is proportional to the 21). Clamping diode CR3 prevents the circuit from os-
cillating when the rf output is s h u t off on the front
input ac signal to the summer/integrator, and the dc
panel of the signal generator.
signal level is proportional to the dc signal to the
pq
I
summer integrator. The ratio of the ac and dc signal
holds the percent of modulation constant, a s dis-
cussed in paragraph 10.4.2. The demodulated output Later units of the 479s-6A do not contain CR3.
-
CURRENT
The VCXO TUNE voltage from analog board A2A2 is end of 100-ms gate from USA-Q, flip-flop U9B-Q is set
input to the demodulator/ALC assembly a t connector t o a "1" signifying a "counter-ready" status. The CPU
52-14 (figure 19). The dc voltage is input to low-pass monitors the "counter-ready" status by executing an
multiple feedback filter U15. U15 is a noise filter to IN 14 during the software idle loop. As long as the
eliminate all frequencies above 10 Hz. The output "counter ready" is a "O", the CPU processes the P H
from U15 is input to amplifier U18 (gain = 2) and LOCK and RF LEVEL bit status only. This occurs
provided to connector J1-Al. This variable frequency many times in the 200-ms period during which the
control voltage is sent to synthesizer assembly A4 for counter is either counting or waiting to count. With a
oscillator control. "1" a t USB-Q, the next software cycle would
acknowledge the counter-readv status (IN 14 data bit
10.4.4 Counter-110 Board A3A3 (Refer t o 7 = I), and read in the frequency count by enabling
figure 2 2 . ) outputs ~ ,TN, m 5~ , in sequence., After
the frequency- data is read by the CPU, the software
Counter-I/O board A3A3 outputs frequency display enables input IN 13, which resets flip-flop USB-Q, set-
information, phase lock, rf level bit, and counter com- ting the "counter-ready" status back to 0. The CPU
plete data to the CPU data bus. Inputs from the CPU processes the P H LOCK and RF LEVEL bit status a t
data bus to A3A3 are synthesizer rf frequency se- this time, then returns to the remainder of the idle
lects, attenuator level select, mode control selects, rf loop.
on/off, and VCXO select data.
The 100-ms counter enable pulse from USA-Q is
All 1 / 0 functions on A3A3 are controlled by 3-to-8 applied to NAND gate U36B, producing a 100-ms win-
line address decoders U3 and U10. The CPU address dow time for counting. The output of U36B is applied
bus (A0 through A7), I/O WR and I/OD are input to
to a chain of seven decade counters (U33-U35, U30,
the decoders. Address bits AO, A l , and A2 supply 3- U18, U27, U21, U24, and U16) connected in series. The
bit binary code, and address bits A3, A4, A5, A6, and 100-MHz through 100-Hz decode bed count is held a t
A7, along with I/O RD and I/O WR bits, enable the outputs of the decade counters until the CPU re-
decoder operation. Refer to chart on figure 22 for quests frequency count information.
decoder data outputs. The enable outputs from U10
and U13 control data inputs and outputs to ,the CPU
data bus. When front panel rf frequency, rf output, or mode is
changed, the CPU data bus transmits this data to
The actual rf frequency being output from the signal counter-I/O board A3A3 data latches. The data
generator is applied to divide-by-10 circuit U34 latches retain the last active data bus data until new
through connector P1. U34 output is applied to NAND data is strobed in by the OUT 10 through OUT 13
gate U36B. The 100-kHz clock from connector 52 is latch enable lines. The 8-bit latches U8, U l l A , U l l B
divided by 10 000 by U1, U4, U6, and U7, producing a and U14, U17A, U17B provide frequency tune bits to
20-percent duty cycle, 10-Hz signal (refer to figure synthesizer assembly A4; 7-bit latch U23, U20A
23). Flip-flop U9A divides this signal by 2 for one cy- provides rf output level bits RFI through RF64 to
cle, producing a 100-ms counter enable pulse. At the digital attenuator A5AT1; and 6-bit latch U5 provides
1-41
awm
xd -
n n m -
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I
10,000 O U T P U T
(~6-11) I
C O U N T E R COM-
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I/O bits A through D for mode selection to board are generated in 25-kHz steps. Frequencies generated
A 3 A 2 , m signal when rf is shut off a t the front are in the following ranges:
panel, and VCXO SELECT signal to synthesizer
assembly A4 when signal generator AF operation is RF CARRIER
I
required. FREQUENCY RANGE
MODE (MHz)
10.5 Synthesizer Assembly A4 (Refer t o figure 2 4 . )
Marker beacon 74.6 to 75.4
VOR 108.00 to 117.95
Localizer 108.10 to 111.95
R F F
(ON = 1 )
VAR FREQ
CONTROL
VOLTAGE
VCXO SELECT
(VCXO = 1
TCXO = 0 )
The vco on/off signal is applied through PI-1 to the FL5. The output of the loop filter is a dc voltage
band selector circuit and enables operation of the proportional to the duty cycle of the 25-kHz pulse
selector circuit when the signal is a logic 1. The rf train. The vco tuning voltage is supplied to vco
carrier frequency select control signals are supplied assembly A4A3. The phase-frequency discriminator
through P1 to the variable ratio divider circuit. Refer circuit also produces signals that are supplied to the
to figure 24 for connector pin numbers and specific loss-of-lock detector circuit. The signals indicate
control signal nomenclature. The 100-MHz LSB and whether the circuit is locking on the selected frequen-
MSB inputs are also supplied to the band selector cir- cy.
cuit. The loss-of-lock detector circuit compares signals
from the phase-frequency discriminator circuit and,
The variable ratio divider circuit is a programmable when loss of lock occurs, produces a loss-of-lock signal
divider that uses the selected rf carrier control signals that is supplied to PI-3
to set the division ratio. The rf output frequency from
the rf output amplifier is applied through an isolation The band selector circuit uses the 100-MHz LSB and
amplifier to the variable divider circuit. The rf out- MSB input logic to determine whether the frequency
put frequency is divided down to provide clock signals selected is in the marker beacon, VOR/localizer, or
that cause the divider circuit to produce a 25-kHz out- glideslope band. The selector supplies the correct
put when the phase-lock loop is locked to the 25-kHz band-enable signal to vco assembly A4A3.
reference frequency. When the phase-lock loop is
locking on the selected rf carrier frequency, variable Vco assembly A4A3 uses the vco tuning voltage and
ratio divider circuit output frequency is increased or the band selector signals to generate the selected rf
decreased, a s required, from 25 kHz to slew the carrier frequency. Generated rf carrier frequency is
phase-lock loop to the correct frequency. The nominal applied through an rf output amplifier circuit to c m -
25-kHz variable divider output is supplied to the nector P2 and to the variable ratio divider circuit.
phase-frequency discriminator circuit.
WASE-FREQ
DSCRM U5. U8
-4 0 / -41 ECL/TTL
PRESCALER
GENERATED
RF OUTPUT,
OUTPUT AMPL
BOARD A2
Revised 1 October 19 78
description 523-0 768882
Scans by ArtekMedia © 2008
counters U13 and U17 are a s shown in the following Thus, 26 is loaded into the binary .counters, cor-
tabulation: responding to the number of 25-kHz increments in
0.650 MHz (26 x 25 kHz = 0.650 mHz). The maximum
value required is 39 (39 x 25 kHz = 0.975 MHz) or a
COUNTER U13 U17
decimal value of 39. Therefore, inputs D and Con U13
are not required, and are grounded.
Preset D C B A D C B A
inputs
For discussion purposes, assume that the selected rf
Code * * 0 1 1 0 1 0 carrier frequency is 112.65 MHz (VOR mode). For
112.65 MHz, the following inputs are supplied to
*Tied to ground counters U16, U12, U11, U13, and U17:
When the preceding inputs are loaded into the At the start of each variable divider circuit cycle, a
counters a t the beginning of each variable divider cy- logic 0 from the FOUT terminal on U15 is supplied to
cle, the variable ratio divider is set to a division ratio the load (L) inputs of counters U16, U12, U11, U13,
of 4506. The division ratio causes the variable ratio and U17. The bcd and binary signals for the selected
divider circuit to produce one output pulse for each rf carrier frequency are loaded in the counters and a
4506 rf output cycles. With the synthesizer locked on logic 0 minimum maximum (MM) signal from U13 is
frequency and the divider ratio set to 4506, the supplied to B2 of U15 and a logic 0 MM signal from
variable ratio divider circuit produces a 25-kHz out- U16 is supplied to B1 of U15. The logic 0 MM signal in-
put signal when the rf output signal is 112.65 MHz. hibits the zero detector circuits on U15 (ZO through
The division ratio can be calculated using the follow- 23) and the programmed input circuits (PO through
ing formula: P3). With ZO through 23 inhibited, a logic 0 is applied
from ENOUT on U15 to the mode 1 (MI) input of
Division ratio = 4000N1 + 400N2 + 40N3 + prescaler U19 and the FOUT signal is a logic 1. The
4N4 + N5 prescaler circuit consists of prescaler U19, flip-flops
U18A and U18B, and switch Q10. The circuit con-
Where figuration causes one output pulse to be produced for
N1 = 100-MHz selected input every 41 input cycles of the generated rf output signal
when mode 1 is selected, or one output pulse for every
N = 10-MHz selected input
2 40 input cycles when mode 2 is selected.
N = 1-MHz selected input
3
The generated rf output signal from output amplifier
N = 0.1-MHz selected input
4 board A2 is applied through isolation amplifier Q13,
N = 25-kHz selected input Q14 to the clock and VREF inputs of U19. With a logic
5
(0 kHz = 0, 25 kHz = 1, 50 kHz = 2, 0 supplied to M1 of U15, the prescaler circuit is set to
75 kHz = 3) divide by 41 and, with a 112.65-MHz frequency
generated, produces a 2747.561-kHz clock signal that
For example, substituting the selected rf carrier fre- is supplied to counters U14 and U17 and to logic com-
quency of 112.65 MHz: biner U15.
Counters U13 and U17 are cascaded, with the outputs
from U17 supplied to the zero detector inputs (ZO
through 23) of U15. Counters U16, U12, and U14 are 10.5.3 VCXO and T C X O Circuits (Refer t o
cascaded, with the outputs of U14 supplied to figure 26.)
program inputs (PO, P2, and P3) of U15, and the MM
output of U12 supplied to P1 of U15. All counters are The VCXO and TCXO circuits generate the reference
set to count down from the programmed (selected rf frequencies used by t h e phase-frequency dis-
carrier) input. Therefore, counters U13 and U17 are criminator circuit. The VCXO is used only when the
counted down from 26 and counters U16, U12, and selected rf carrier frequency is varied about the
U14 are counted down from 112. selected channel frequency when performing receiver
selectivity tests. The TCXO supplies the 25-kHz
When counter U13 is counted down to zero, the MM reference frequency during normal signal generator
output switches to a logic 1. With a logic 1 supplied to operation.
the B2 input of U15, the zero detector circuits are
enabled and the logic 0 inputs to ZO through 2 3 10.5.3.1 VCXO Circuit
switches ENOUT to a logic 1. The logic 1 supplied to
the MI input of U19 switches the prescaler circuit to A variable frequency control voltage (dc) from rf
divide by 40 for the remainder of the variable divider modulator assembly A3 is applied through P l A l to
circuit cycle, causing the prescaler to produce a frequency range adjust circuit R7, R8. Resistor R8 is
2816.25-kHz clock signal for the counters and logic selected during alignment/adjustment procedures to
combiner. set the minimum and maximum operating range for
the VCXO. The control voltage is applied from R7, R8
Three counter outputs from decade counter U14 and to crystal oscillator CR1, CR2, CR3, Q1 that generates
the MM output from decade counter U12 are supplied a nominal 16.0-MHz signal. The VCXO output fre-
to the programmed (PO through P3) inputs of U15. quency is varied with the control voltage by changing
The MM output from decade counter U16 is supplied the capacitance produced by varactors CR1, CR2, and
to the B1 input of U15. When U16 counts down to CR3.
zero, the MM output switches to a logic 1and the logic
1 input to B1 of U15 enables the programmed circuits The nominal 16.0-MHz signal is applied through
in U15 to accept the PO through P 3 inputs. Toggle con- amplifier Q2 and level translator Q3 to divide-by-4
dition for the P( ) inputs of U15 occurs with U12 and counter U21. Counter U21 produces a nominal 4-MHz
U16 outputs all in zero state and U14 output a t the 2 signal that is supplied to binary counter U1, which
count. With logic 0 a t the PO, P2, and P 3 inputs and functions a s a divide-by-16 counter and produces a
logic 1 a t the P1 input, a negative pulse is produced a t nominal 250-kHz signal that is supplied to decade
the FOUT output of U15 after two additional clock counter U2. Counter U2 produces a nominal 25-kHz
pulses occur. The FOUT output of U15 is supplied to signal that is supplied to U4D in reference frequency
the load inputs, t h e counters, and t h e phase- logic circuit U4. The 25-kHz reference frequency that
frequency discriminator circuit. is being varied is multiplied by the fixed channel
divider ratio. The rf channel frequency is produced
When the generated rf output frequency is the same only when the reference frequency is exactly 25 kHz.
as the selected rf carrier frequency, the phase-lock
1 loop is locked and U15 produces a F O ~ J Tpulse for As the input control voltage is varied, the oscillator
every 4506 cycles of the generated rf output frequen- frequency is varied from the nominal and all other
cy, or a 25-kHz signal. For a locked condition, the frequencies are varied proportionally.
40
width of the negative FOUT pulse = -microseconds,
f
1 where f is the rf output frequency in MHz. 10.5.3.2 T C X O Circuit
During lock-on, if the generated rf output frequency The TCXO circuit produces the 25-kHz reference fre-
is above or below the selected rf carrier frequency, quency for the phase-frequency discriminator circuit
the variable divider still divides by a ratio determined during standard 479s-6A operation.
by the selected rf carrier frequency. This causes a
phase shift in the 25-kHz signal produced by U15, The TCXO assembly A4A4 produces a continuous 3.2-
which in turn changes the vco control voltage MHz signal that is supplied to divide-by-16 counter
produced by the phase-frequency discriminator cir- U7. Counter U16 produces a 200-kHz signal that is
cuit. This continues until the phase-lock loop is supplied to divide-by-2/divide-by-8 counter U6.
generating the selected rf carrier frequency. Counter U6 produces a 25-kHz reference frequency
----------
R
I
FREQ OSC (VCXO) P/O A1 A1
t5 V OC
1
CRYSTAL OSC RF AMPL
IP
/ ~ FREQ RANGE- ( 1 6 . 0 MHZ NOM) 16 MHZ ~m
VARIABLE
FREQ CONT A '
% AOJ CR1 ,CR2. TRANSLATOR
R7.88 CR3,Ql
VOLTAGE
I +
*
- +4
COUNTER
4
MHz
NOM
+
BINARY
RIPPLE
COUNTER
250
kHz
. NOM
DECADE
COUNTER r-- REF FREQ LOGIC P/O AlAl
C U2 1 ( + l o ) U2
( + 1 6 ) U1
------ I
VCXO
SELECT 2)
P/O
PI
VCXO = 1
TCXO = 0
- -- VCXO O N = O TCXO ON - 1
LOSS OF LOCK
DET CKT
U4A
II
TCXO ON = 25 kHz
---------
P X O CIRCUIT P/O AlAl
3.2 MHz
TCXO ASSY
A4
1- 716
COUNTER
U7
200kHz
- ~ 2 , - 8
COUNTER
U6
25kHz
100 k ~ z
BUFFER
U3A. U30 '
I 0
( A2
100kHz
CLOCK
that is supplied to U4C in the reference frequency When the TCXO is selected, the frequency standard
logic circuit and a 100-kHz signal that is applied select signal is a logic 0 that is supplied to U4D and,
through buffer U3A, U3D to PlA2. through U4A, to U4C and the VCXO oscillator. The
output of U4A inhibits the VCXO oscillator and
10.5.3.3 Reference Frequency Logic Circuit enables gate U4C. The logic 0 supplied to U4D inhibits
the VCXO output to U4B. The 25-kHz reference fre-
The reference frequency logic circuit is controlled by quency from the TCXO is applied through U4C and
a VCXO SELECT signal from rf modulator assembly U4B to the phase-frequency discriminator a s the
A3 and determines whether the VCXO or TCXO reference frequency.
reference signal is to be used by the phase-frequency
discriminator circuit. When the VCXO is used during
the AF operation of the 479s-6A, a logic 1 VCXO 10.5.3.4 Phase-Frequency Discriminator Circuit
SELECT signal is applied through PI-2 to U4D and
through inverter U4A to U4C and to the crystal os- The phase-frequency discriminator circuit compares
cillator in the VCXO. The logic 0 supplied to the the reference frequency with the variable divider out-
crystal oscillator enables the oscillator. The logic 0 put frequency and phase and converts the difference
supplied to U4C inhibits the TCXO output to U4B. to a vco dc control voltage. The circuit consists of two
The logic 1 supplied to U4D enables the VCXO fre- major functional circuits: a phase-frequency dis-
quency to be applied through gate U4B to the phase- criminator circuit, and a level shifter (loop amplifier)
frequency circuit a s the reference frequency. circuit.
Revised 1 October 19 78 69
description 523-0768882 Scans by ArtekMedia © 2008
10.5.4 Phase-Frequency Discriminator Circuit which cause UlOA to produce a logic 0 loss-of-lock
(Refer t o figure 27.) signal.
10.5.7 B a n d Selector Circuit ( R e f e r t o figure 27.)
The phase-frequency discriminator circuit compares
the output from the variable divider circuit with a 25- The band selector circuit determines whether the
kHz reference frequency. When the frequency and selected rf carrier frequency is in the marker beacon,
phase of the variable ratio divider output remain VDR/localizer, or glideslope frequency ranges and
constant, the discriminator circuit produces a rec- supplies vco control signals to vco assembly A4A3.
tangular wave. The duty cycle of the wave is used to Refer to figure 27 for circuit operation.
produce a vco control voltage by determining the 10.5.8 VCO A s s e m b l y A4.43 (Refer t o figure 27.)
average dc voltage of the discriminator circuit output
wave. The vco assembly uses the control voltage from the
loop filter and the band control signals from the band
The nominal 25-kHz VCXO or TCXO reference fre- selector circuits to generate the selected rf carrier
quency is supplied to the clock input of U8B and the frequency. Resistors R3, R4, and R5 are selected dur-
variable ratio divider output frequency is supplied to ing alignment/adjustment procedures to set os-
the clock input of U8A. For operation of the dis- cillator output levels. The oscillator is capable of
criminator circuit, refer to the timing diagram shown producing required marker beacon frequencies from
in figure 28. 74.6 to 75.4 MHz, the required VOR/localizer frequen-
10.5.5 Level Shifter ( L o o p A m p l i f i e r ) Circuit cies from 108.00 to 117.95 MHz, and the required
(Refer t o figure 27.) glideslope frequencies from 329.15 to 335.00 MHz.
Each band has an independent output level deter-
The rectangular wave from the phase-frequency dis- mined by R3, R4, and R5 values.
criminator circuit is applied to loop amplifier Q4. The
Vco assembly A4A3 is a nonrepairable potted
output of Q4 is applied through connector P 3 to low-
assembly.
pass filter assembly A4A5. Resistor R22 with the in-
ternal capacitance of FL5 form a n integrator that 10.5.9 RF O u t p u t Amplifier Circuit
converts the rectangular wave to a sawtooth wave a t ( R e f e r t o figure 29.)
the input to FL5. Low-pass filter FL5 converts the
sawtooth wave to a dc tuning voltage t h a t is equal to
The rf output amplifier circuit (CPN 629-9760-001) 1
consists of two broadband isolation rf amplifiers t h a t
the average dc level of the sawtooth wave. Therefore,
produce the required gain for the rf carrier signal.
t h e t u n i n g voltage depends on t h e d u t y cycle
The 74.6- to 335.0-MHz vco output signal is applied
produced by the discriminator circuit. When the
through amplifiers Q3 and Q1 to connector P 2 and to
phase-lock loop is locked, the duty cycle remains cons- the variable divider circuit. Q2 provides gain stability
t a n t and the tuning voltage is steady. by varying the base current supplied to Q1 a s a func-
10.5.6 Loss-of-Lock D e t e c t o r Circuit tion of temperature. Variable capacitors C4, C12, and
(Refer t o figure 27.) C14 a r e adjusted d u r i n g alignment/adjustment
The loss-of-lock detector circuit determines whether procedures to ensure flatness across the operating
the phase-lock loop is locked on the selected rf carrier hand.
frequency. The rf amplifier circuit (CPN 634-9681-001) consists
of two broadband isolation rf amplifiers t h a t produce
The VCXO or TCXO reference frequency and the the required gain for the rf carrier signal. The 74.6 to
variable divider output frequency are supplied to the 335.0 MHz vco output signal is applied through
clock inputs of U9A and U9B respectively. The two amplifiers Q1 and Q3 to connector P2 and to the
rectangular wave signals from the phase-frequency variable divider circuit. Q2 provides gain stability by
discriminator a r e supplied to the d a t a inputs of U9A varying the base current supplied to Q3 a s a function
and U9B. When the phase-lock loop is locked on the of temperature. Variable capacitors C1, C2, C10, and
selected rf carrier frequency, U9A and U9B produce
C11 a r e adjusted during alignment procedures to en-
logic 0 signals t h a t a r e supplied to gate UlOA. Gate sure flatness across the operating band.
UlOA produces a logic 1 lock signal t h a t is supplied to
10.5.10 +5- a n d +20-V DC Voltage Regulators
PI-3.
The +5- and +20-V dc voltage regulators convert the
When the phase-lock loop is not locked, . t h e rec- +9- and +24-V dc input voltages to a regulated +5
tangular wave signals from the phase-frequency cir- and +20 V dc respectively. The +20 V dc provides
cuit are not uniform a n d cause U9A and U9B to operating voltage for analog circuit operation, and the
produce outputs t h a t are 180 degrees out of phase, + 5 V dc provides operating voltage for digital circuit
---- ----
T LOSS OF LOCK DETECTOR
+5 DC
1
U9B
10
8
3 c,Q-
4
13
UlOA P/O
PI
I 3 PH LOCK
D S QL
+5 v M:
I
LEVEL SHIFTER (LOOP AMPL)
- A4A3
7 4 . 6 TO
335.00 MHz;
OUTPUT
AMPL BOARD
A2
----- ----
BAND SELECTOR
100 MHz 10
LSB 11 3, BAND 1 ENABLE (MARKER BEACON)
-
RF OFF
(l=LIN) 5
6 - 11 BAND 2 ENABLE (VOR/LOCALIZER)
10 U l l C
BAND 3 ENABLE (GLIDESLOPE)
100wz 12> 9 8
MSB
I
1 -----
25 kHz
REF FREO,
U8B-11 0 1
25 kHz V A R
D I V I D E R OUT
U8A-3 0 -
NOTE:
@ WAVFFORhnS SHOWN A R E I D E A L I Z E D .
;i:g+lDER CKT
7 4 6 TO 3 3 5 0 MHz
o s c OUTPUT,
VCO ASSY A 4 A 3
j++?L< Q2 ,Q3
P2 R F OUTPUT
( T O MODULATOR)
A 4 A 2 CPN 6 3 4 - 9 6 8 1 - 0 0 1
7 4 . 6 TO 3 3 5 . 0 M-lz 01. Q 2
RF W T F V T
OSC OUTPUT; (TO MODULATOR)
VCO ASSY A 4 A 3
C14 C12
I I
RF OUT.
VAR D I V I D E R CKT
-
FLATNESS AOJ
TP5-4881-013
A 4 A 2 CPN 6 3 7 2 7 18 - 0 0 1
operation. The regulated +20-V dc supply also fur- it provides power to store/recall board A9. The
nishes the reference voltage for the +5-V dc rectifier and filter converts the ac voltage to an
regulator. The voltage regulator adjustment is set unregulated +21 V dc. Series regulator A5A4Q2,
during alignment/adjustment procedures to provide VR1, VR2 converts the unregulated voltage to a
+5 and +20 V dc within the required tolerances. regulated +12 V dc that is applied through filter C3,
C5 to t h e signal generator circuits. Regulator
10.6 Power Supply Assembly A5 (Refer t o A5A2U3, C14, C15 converts the unregulated voltage
figure 30.) to a +15 V dc that is supplied to the signal generator
circuits. Series regulator A5A2U2, Q4 converts the
Power supply assembly A5 is factory wired to operate unregulated voltage to a regulated +9 V dc that is
on 115 V ac, 50 or 60 Hz. The power supply can be applied through current limit sensor A5A2R21 and
rewired to operate on 230 V ac, 50/60 Hz by changing filter A5A2C10 to the signal generator circuits. The
wiring connections on a barrier strip. Changing the current limit sensor resistor controls output current
barrier strip wiring connections changes the input to limiting protection for the +9-V dc regulator cir-
the primary winding of transformer T1. For detailed cuitry. Resistors A5A2R19 and R18 form a voltage
information on changing wire connections for 230-V divider that controls the regulator output voltage.
ac operation, refer to the maintenance section.
Connectors and connector pins are omitted from The nominal 9-V ac output from T1 is applied through
figure 30 to clarify discussion of A5. If connector in- rectifier A5AlCR3, CR4; fuse A5AlF1; and filter C2,
formation is required, refer to the schematic diagram C3 to series regulator transistors A5A4Q1, A5A3Q1,
for power supply assembly A5 contained in the A5A3Q2. The rectifier and filter circuits convert the
diagrams section. ac voltage to an unregulated +13 V dc. The regulator
transistors operate in conjunction with regulator
A5A2U1 to form a series regulator that converts the
The 115/230-V ac, 50/60-Hz input power is applied unregulated voltage to a regulated $5 V dc. The
through emi filter C4, C5, C6, C7, L1, L2 to the regulated + 5 V dc is applied through current
POWER switch on front panel assembly A l . When equalizer resistors A5A2R9, R11, R13; current limit
the POWER switch is ON (depressed), 115/230 V ac is sensor resistors A5A2R10, R12, R14, R15, R17, R20,
applied through fuse F1 to the barrier strip. The input R22, R23, R25; crowbar circuit A5A2Q1, VR1; and
power is applied from the barrier strip to transformer filter A5A2C4, C6, C7 to the signal generator circuits.
T1 and to fan B1. Transformer T1 converts the Regulator A5A2U1 is biased by the unregulated +21
115/230 V ac to a nominal 24-V ac output, two V dc. A5A2U1 supplies a control voltage to tran-
nominal 15-V ac outputs, and a nominal 9-V ac output.
sistors A5A4Q1, Q2, Q3. The current equalizer
resistors balance the current passed through each
The nominal 24 V ac from transformer T1 is supplied series regulator transistor. The current limit sensor
to rectifier/filter A5AlC2, CR2 which converts the ac resistors allow foldback current limiting protection
voltage to an unregulated +33 V dc. The +33 V dc is for the +5-V dc regulator circuitry. The output
applied to regulator A5A2U4, C16, C17 that converts voltage is controlled by potentiometer A5A2R2 and
the unregulated dc voltage to a regulated +24 V dc. resistors A5A2R5, R4. The crowbar circuit monitors
The +24 V dc is supplied to the internal signal the regulator voltage output and when the voltage ex-
generator circuits. ceeds specific limits, the + 5 V dc is removed from the
One of the nominal 15-V ac outputs from T1 is signal generator logic circuits to prevent damage to
supplied to rectifier/filter A5AlC1, CR1 that con- the logic devices. The crowbar circuit is adjusted by
verts the ac voltage to an unregulated -21 V dc. The A5A2R1 to set the voltage limit.
unregulated -21 V dc is supplied to regulator A5A2U5,
C12, C13 that converts the unregulated dc voltage to a 10.7 Remote Tune Board A8
regulated -15 V dc. The -15 V dc is supplied to the in-
ternal signal generator circuits. CPU address and data bus information are supplied
to remote tune board A8. Addresses are decoded and
The second nominal 15-V ac output from T1 is applied used to control data input to storage latches. Data
through rectifier A5AlCR5, CR6 and filter C1 to supplied is used to drive relays which close ap-
series regulator A5A4Q2, VR1, VR2; regulator propriate contacts to provide 2-out-of-5 tuning that
A5A2U3, C14, C15; and series regulator A5A2U2, Q4. conforms with ARINC Specification 410, mode dis-
The 15-V ac output is also applied to fuses F2 and F3. c r e t e ~ ,and normal control-head contact closures for
The fused output is applied to backplane A7, where NAV disable, LOC/GS energize, and COM disable.
10.8.1 General
A high logic input to the relay drivers will cause a low
output, which provides a return for relay power and Store/recall board A9 provides the capability for
closes the relay. storage of signal generator conditions and for recall
of those conditions a t any time.
For the 2-of-5 10-MHz, 1-MHz, 0.1-MHz, and 0.01-
MHz digits, two of the five latch outputs that corres- 10.8.2 Overall Operation (Refer to figure 32.)
pond to data bits DO through D4 will be a t a high logic
level and the appropriate relays will be closed. Clos- CPU address bus information is supplied to port
ing the relays shorts the appropriate frequency tun- decoder U8B and control decode circuit U5B. I/O read
ing line to frequency common. This provides frequen- and write signals are also input to the control dQcode
cy tuning information to the using receiver. Data bit circuits. The four MSB of address, AB4 through AB7,
D5 is used to control 0.005-MHz signals B and C. The must be high or data cannot be transferred through
0.001-MHz frequency digit is controlled by the 0.005- the data buffers.
MHz B and C signals in the following manner:
When AB4 through AB7 are high and the I/O write
signal goes low, port decoder U8B decodes ABO and
AB1 to provide clock signals for data registers U12,
U13, and U16. U8B also outputs a control signal to
WE control circuits (U3C, U l l D , U11F). The control
decode output that enables U8B also causes U24 to
output a wait signal to the CPU and enables data
buffers U19, U20, and U21 to allow data from the
When AF is activated, the 2-of-5 turning data cor- CPU data bus onto the A9 board. The storage
responds to that of the last channel frequency the memories (U6, U22, U2, U23, U9, U18) will not accept
operator selected prior to pushing AF. Data bits DO data until they are chip enabled.
through D4 provide the following control signals:
mode select A, NAV disable, LOC/GS energize, mode When AB4 through AB7 are high and the I/O read
select B, and COM disable. D5 controls the timing signal goes low, the data buffers allow data from the
trigger output, causing it to be low if D5 is high, and A9 board onto the CPU data bus. An I/O read also
vice versa. triggers U24 to output a wait signal to the CPU,
NOTE.
@ APPLIES TO 4 7 9 s - 6 A AND 4 7 9 3 - 6 SB1 ONLY
v FREQ COMMON
9
I
Di)~~~c~
1
{
0.01 MHz
RELAY
DRIVER D
E
D5 B 0.005 MHz
CK
I u9 U10
II i
7
DO RELAYS K 1 - K 6
LATCH
RELAY
D5 E J
C 0.005 MHz
U1 CK
u3
17 -
- ADDRESS
U4
19
- DECODER 4
I 4b
-
9
21
R E L A Y S K12 - K 1 6
{I
DO
1]
31 LATCH
4b RELAY D 1 MHz
15 DRIVER
D4 E
CK
I -- 1 U7 U8
I l l I
ADDRESS
DECODER
IDO u RELAYS K7 - K11 I
MODE COMMON
MODE SELECT A
N A V DISABLE
LOCIGS ENERGIZE
DRIVER
MODE SELECT B
COM DISABLE
TIMING TRIGGER
DBO
DB 1
DB2
DB3
D B4
DB5
DB6
DB7
A00
ABl
R e ~ y i s e d l October
j 1980 7:1/80
Scans by ArtekMedia © 2008 description 523-0768882
which holds data on the data bus long enough for the CR4 through CR12, C8, Q2, Q3, Q4, and U15 provide
storage memories t o respond. The C P U is the -30-V dc operating power for the 1024 byte
programmed to output a n I/O write with an I/O read memories. Zener diodes CR4 and CR5 provide over-
to the store/recall board to latch a memory address voltage p r o t e c t i o n t o p r e v e n t d a m a g e t o t h e
into registers U16, U13, and U12. Once the address is memories. CR6 prevents reverse charging of voltage
latched, CO and C1 must be latched in read mode doubler capacitor C8.
(table 8 shows memory mode control inputs) and chip
enable, m, must be active to allow the memory mode The sequence to store or recall 1 byte is a s follows:
to take place.
Store
When I/O write is low, the output of write enable chip IEEE-488/1978 bus interface board A10 makes the (
U l l F is high, which enables U3 and causes %% to be signal generator capable of communicating with ex-
held off until goes low. This allows d a t a to be ternal control devices.
entered into addressed memory if memory is in write
mode (table 8). A description of basic bus operation is given in
paragraph 10.9.2. Overall operation for A10, CPN 601-
Refer to schematic diagrams for the following infor- 5883-001 is given in paragraph 10.9.3, and A10, CPN
mation. 601-2309-001 in paragraph 10.9.4.
The power-up clear circuit (CR3, R6, C4) holds pins 1 10.9.2 IEEE-48811978 Bus Operation
and 13 on U7 low until the power-up sequence is com-
plete. This ensures t h a t C1 and CO a r e always in the The following terms a r e used in this paragraph.
read mode and keeps the d a t a in the memories from
being inadvertently destroyed. Talker - sends device dependent data to the bus.
Listener - receives device dependent d a t a on the bus.
The power-up sequence involves delaying the -30 volts Controller - manages the bus. A controller is the only
by holding Q4 off until C13 charges negative through
device t h a t may send GPIB bus commands on the bus
R12 to approximately -10.6 volts. and t h u s determines what devices may be talkers and
The power-down sequence of the -30 volts is ac- listeners on the bus. I t is also the only device that
complished when C10 discharges to approximately -10 may activate the ATN, RON, and IFC bus manage-
volts. ment lines described later in this paragraph.
The GPIB bus consists of 16 lines: 8 data lines, 3 data a t the rate of the slowest device. Refer to
handshake lines, and 5 control and status lines. The figure 35 for handshake sequence.
function of these lines is described below.
Table 9 indicates the status and control lines with
a. Data lines: DIOl through DI08
a description of their respective functions.
Data lines are used for transferring bus commands
and device dependent data in a bit-parallel, byte- 10.9.3 Overall Operation (A10 CPN 601-5883-001
serial fashion. With the 479s-6A, the 7-bit ASCII only)
code is used. CPU address bus information, except address lines
b. e and shake lines: DAV - data valid, NRFD - not ABO and AB1, is supplied to chip select control U17
ready for data, NDAC - not data accepted. and decoded to provide a CS signal to one of the I/O
interfaces, U7 or U8, each of which internally decode
Handshake lines provide for the transfer of com- one of four port address registers via CPU address
mands and data on the data lines between devices. lines ABO and AB1.
The talker activates the DAV line to indicate valid
data on the data lines. Listeners assert the NRFD Read control circuits UZA, U l l A , and U l l D combine
and NDAC lines to indicate when they are ready the chip select outputs with an I/O read signal to
for data and have accepted data, respectively. provide the selected chip with a read signal. The read
signal is used to activate data buffers U6, U10, and
During one "handshake cycle" one byte of data is U12 to allow data from assembly A10 to be placed on
transferred on the bus. Because of the open collec- the CPU bus.
tor configuration of the bus drivers, the RFD and Data buffers U6, U10, and U12 are enabled, in one
DAC conditions are wired - ANDed together on the direction or the other, a t all times. An active read
bus, creating multiple listeners. Multiple listeners signal causes data from assembly A10 to be input to
mean the talker will not see a "ready for data" con- CPU data bus, and an inactive read signal causes data
dition until all listeners are ready for data, or a on CPU data bus to be input to assembly A10.
"data accepted" condition until all listeners have
accepted data. Because of this method of opera: Address lines ABO and AB1 from the CPU address
tions, the multiple listeners on the bus accept data bus are supplied directly to read/write control logic
a t different rates, and the talkers will transfer inputs A0 and A l , respectively, on U7 and U8. These
IFC - interface clear Activated by controller to clear interface. When true, will place all talkers and
listeners to the inactive state.
ATN - attention Activated by the conti-oller to distinguish between device dependent data and bus
commands on the data lines. When true, the information on the data lines i s
interpreted as a bus command.
REN - remote enable Activated by the controller to enable it to selectively place devices in the
remote mode. Only those devices addressed to listen with R E N true will enter
the remote mode. When this line goes false all devices will return to the local
mode.
SRQ - service request Activated by devices on the bus when they reqmre the controller's attention. The
controller must poll the devices to determine which one(s) activated this line.
The 479s-6A activates this line to notify the controller of an e r r o r condition
such as invalid o r out-of-range data.
ED1 - end o r identity Activated by a talker to indicate the end of a multiple-byte sequence o r by a
controller during a parallel poll. This line is not used by the 479s-6A.
inputs in conjunction with read, write, and chip select are set for input, port C (higher) and port B are set for
inputs decide which ports are interfaced to the data output, a passive state is output to the 488 data bus,
bus. If the chip select input is high, the interface cir- bus fault latch (U9) is reset then enabled, a n d m is
cuits are disabled and no operation can be performed. enabled via U11B. The bus data lines are serviced by
If both I/O read and I/O write are inactive, the same U8 ports A and B. The bus control lines are serviced
restriction applies. An active I/O read signal allows by U7 ports A and B. U7 port C is unused while U8
three possible operations to be performed for com- port C does internal control and monitoring of the in-
I binations of A0 and A1 during an I/O read. Table 10 terface circuitry. Port assignments (in hexadecimal)
are as follows:
shows the operations performed for combinations of
A0 and A1 during an I/O read.
a. Port AOH: Bus management input
I Ttr ble 10. Reud Opemtiorl kfodes. b.
c.
Port AlH: Bus management output
Port A2H: Not used
r
A1 All OPERA TION d. Port A3H: I/O control port
e. Port A4H: Bus data input
f. Port A5H: Bus data output
0
1
0
0
Port B
Port C
-
P o r t A +Data
-
bus
Data bus
Data bus
g. Port A6H: Status in/control out
h. Port A7H: I/O control port
-
An active ATN input to U14 is output on OA. The OA
output disables data bus transceivers U15 and U16
1 1 Not allowed
and enables address comparator U1. If ATN is
received while device is already in service, U9A will
An active I/O write signal allows four possible be clocked to hang the bus in fault condition until ser-
( operations to be performed. Table 11 shows the vice sequence can terminate. The five LSB's of the
operations performed for combinations of A0 and A1 IEEE-488 ASCII data bus are applied to the address
during an I/O write. decoder. They are compared to the switch positions of
S1, and if the device addresses match, U1 outputs a
-
high level signal. The high output of U1, gated by an
active DAV signal, clocks device service latch U5. -
A1 A0 OPERATION Clocking U5 provides a nonmaskable interrupt, NMI,
to the CPU. The CPU then calls a service routine
0
which handsakes the bus under software control and
0 Data bus -Port A
transfers the data from the bus to memory, or from a
0 1 Data bus -Port B memory buffer to the bus. Refer to figure 35 for
handshake sequence.
1 0 Data bus- Port C
-
1 1 Data bus-Control word register
The active talker must then generate a DAV, data
available, control signal when all listening devices in-
dicate they are ready for data (RFD true). Data
Bus transceivers U13, U14, U15, and U16 interface available (DAV) must remain true until all listeners
the bidirectional IEEE-488 bus signals to the TTL -must
indicate data accepted (DAC true). The listener
level input and output ports in U7 and U8. Each go to not ready (RFD false) upon receipt or DAV true,
transceiver IC contains four identical interface cir- indicate data accepted when it is latched in, and then
cuits with separate system input and output pins and indicate ready again when prepared for the next data
common bus pin. Internal resistor networks match byte. This handshake will ensure the bus transfers oc-
the bus characteristics. The bus receivers are always cur a t the rate allowed by the slowest active device on
enabled, and the bus transmit input is ANDed with the bus.
the enable input to drive the bus. The bus side of the
interface has open-collector type outputs to permit -
wired -OR conditions on the bus. The logic signal is in- A service request, SRQ, will be generated by the
verted between the bus pin and the 1 / 0 pins. Refer to signal generator if it receives an invalid command
figure 34 for bus transceiver schematic. character, or receives out-of-range data.
The IEEE hardware is initialized by the software into Once operating control is released from the front pan-
the following conditions: port C (lower) and port A el switches to an external controller, it will remain
' US, U l 0, U7
-
DATA
BUFFER
110
INTERFACE
PA3
--
DBO 18 . DBO U4
DBl U13 1
DB1 20 BUS HANDSHAKE
.
DB2
DB3
22
24
082
083
D7 D7 PA7 TRANSCEIVER
0D
A SYNCHRONIZATION -
D B4 26 DB4
-
PB
(0 3) BA 68 -
DAV
DB5 28 D6 5 T BB .
DB6 30 . DB6 PB7 ID BC 69 RFD
DB7 32 -DB7 I
RD WR A0 A1 CS E BD 72 SRQ
L 4I
I)
110 WR 15 . 11
ABO 17 ,
U14 E
AB1 19
- 41 BUS
TRANSCEIVER
0D
21
25
AB2
AB4
'
I PB
BA . 73
-
ATN
27 . - AB5 - ID
BB u 67
-
29 . AB6
41
BC 79
-
REN
31 - 0A BD 71 IFC
AB7
U17 Cc R D WR A0 A1 CS
.
1-I
U8 COMP
I10
INTERFACE PA7
r b
0A
A0 A=B -
t
PA0 U15
DO
C
PA3
(k BUS
TRANSCEIVER
'}
OD
= A4
63 DO
U2A PB
(0-31 BA
16 UllA D
pB7
BE - 64 Dl
-
BUFF'ER
CONTROL
D7
J BC 65 D2
PC1 BD 66 D3
PC0
PC7
PC6 U3B. C. U5,
U2B U9, U11 B. C
4I PC1 - 110 CONTROL
PC0 LOGIC
PC7
-9 -
NMI
U16
E BUS
TRANSCEIVER OD
BA 75 D4
(4-71 BB . 76 05
ID BC . 77 D6
BD 78 D7
TP55643-013
IEE;%-ARX/1!17+8 B~rs111trrfirc.cBoard A / / /
ICPiV /iOl-5XX3-0011.Fiirtctiortcrl Lhtrqrtr rrr
Fiqlt re 3Q
there until one of two things happen; the 479s-6A is The end of self-test will result with the signal
powered down or it is put into self-test mode. The generator in initial power-up configuration under
front panel display will, however, continue to show manual control. The external controller can then
valid mode and data information. resume remote operation or request the test results.
- NOT
DAV VALID
VALID
RFO
DAC
([q ACCEPTED
NONE
ACCEPTED
10.9.4 Orerall O p ~ r a t i o n(AIO, CP,V 601 -2309-001 Ttrhle 12. GPIB I/O P111.t . i l s s i g ~ ~ ~ n ~ w t . s .
only) (Refer to figure 36)
CPU address and control lines a r e provided to U4, PORT READ/ FUNCTION
U7A, and U13A to decode t h e r signals
~ for the GPIB NUMBERS WRITE
interface, IC U:3, GPIB address select buffer U5, and
interrupt enable latch U9. A0 Read/write GPIB data transfer
'Al-A7 Read/write GPIB status and
control
Inteface between A10 d a t a lines and CPU d a t a lines is A8 Read GPIB address
provided via bidirectional tri-state buffer U1. CS select/interrupt
signals a r e combined via U7B to enable U1. CPU con- reset
trol line I/O RD determines signal direction. A8 Write Interrupt reset
AS-AF Not used
GPIB I/O port assignments a r e given in table 12.
A 2-MHz clock is provided to U3 and U9 by a 16-MHz The GPIB hardware is initialized by the CPU writing
oscillator divided by 8. The oscillator consists of U6D, into appropriate registers of U.3. During initializa-
U6E, R9, R10, C8, C12, and Y1. Division by 8 is ac- tion, the CPU reads s\vitch S 1 positions through U5
complished hy U8. and converts this information into U3 talk-listen ad-
tlrcsses. Switch-position information is also used to
Bus transceivers U2, U10, U11, and U12 interface the reset U9 to a predetermined state. The dip switches
GBIP signals to U3. The bus side of these transceivers ( S l ) a r e read a t power up only. Changing switch posi-
have open collector type outputs to provide a wired- tion after power up will have no effect on GPIB ad-
OR function on the bus. Each line is bidirectional, the dress until a self-test or device clear is initiated.
direction of which is determined by U 3 in response to
conditions on the bus. When the C P l i is processing a GPIB interrupt on the
bus, U3 is prevented from interrupting the CPU by
Special purpose GPIB interface IC U 3 properly han- 179. A t the end of each GPIB interrupt, the CPU
dles all GPIB protocol without CPU interface. When a resets U9 to enahle it to generate a n y pending or
condition has occurred on the GPIB bus t h a t is of in- future interrupt to the CPU.
Scans by ArtekMedia © 2008 description 523-0768882
CLOCK
Rockwell
International
Collins 479s-6A
VOR/ILS Signal Generator operation
I Collins Government Avionics Division
table of contents
Paragraph Page
4. (:ort~rolsa n d Indir-ators . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . 1
3. Operation P r o ( - e d u r ~ s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . .. . . . . . 6
Pace So Issue
"Title . . . . . . . . . . . . . . . . . . . . . . . . . 15 Oct 80
*List of Effective Pages . . . . . . . . 15 Oct 80
1 thru 7 . . . . . . . . . . . . . . . . . . . . . . . 1 Sep 78
$8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Oct 80
9 thru 20 . . . . . . . . . . . . . . . . . . . . . . 1 Sep 78
*20A thru 20B Added . . . . . . . . . . 15 Oct 80
"21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5. Oct 80
2'2 thru 28 . . . . . . . . . . . . . . . . . . . . . 1 Sep 78
*X9 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5 Oct 80
:I0 t h r u 31 . . . . . . . . . . . . . . . . . . . . .1 Sep 78
*:<2 thru $2 . . . . . . . . . . . . . . . . . . . . 15 Oct 80
ll\lS10 ISSI .]<TION Sl; XI'%lJ<k:lt lt13.1 ' Ill..\.ISlOS lXSk:l{'~lOS S1: S1..11111<1{
I ).\'I7../l<Y lS('l.l.l)El) S() I ).\Tk. I ):\'lT:/ftY lS(.l.1.l)P.I)
15 O c t 80 1 thru I0
Scans by ArtekMedia © 2008
operation
TO
FROM
? H z '
RDUDDMlMOD
/-/
I- ' .-I
. I-l
I
/-,
-
ROLIDtGI
oOM
MOO<%/ 1
i 1-1
1-1 f
FREOUENCY
r
-1
LEVEL-
1-1
I ,
L ,
,","""
O/R<L)OHZI
T O N E SELECT D A T A ENTRY
Controls and Indicators NOTE: SHADED KEYS ARE LIT WHEN ON.
Figure 2 (Sheet 1 of 4)
KEY I FUNCTION
I
I 30 Hz VAR 1 Selects 30-Hz variable VOR signal.
I
Selects 9960-Hz FM (30-Hz reference) VOR signal.
Selects 9960-Hz ordy signal.
Selects 1020-Hz audio o r AUX tone when used in conjunction with VAR FREQ o r % MOD-FUNCTION/
CONTROL key.
Selects 90-Hz ILS signal.
Selects 150-Hz ILS signal.
Selects 400-Hz (outer m a r k e r ) m a r k e r beacon signal.
Selects 1300-Hz (middle m a r k e r ) m a r k e r beacon signal.
Selects 3000-Hz (inner m a r k e r ) m a r k e r beacon signal.
I KEY I FUNCTION 1
% MOD Enables selection of percent modulation through DATA ENTRY keys and switches RDL/DDM/
MOD display to indicate percent modulation.
STD Switches RDL/DDM/I\.IOD, AUDIO STATUS, FREQUENCY, and R F LEVFL displays back to the
p r e s e t condition f o r the selected mode.
RDL/DDM Enables selection of radial in VOR mode o r DDM in ILS mode through DATA ENTRY keys.
STEP ARDL A DDM Steps VOR radial in +30-degree steps o r ILS DDM in standard DDM steps.
T/F U/L D/R Selects e i t h e r a FROM o r M radial in VOR mode o r a 90-Hz predominant o r 150-Hz predominant
signal in ILS mode.
VAR FREQ Enables DATA ENTRY keys f o r varying standard tones (30, 9960, 9960 F'M, 90, and 150 Hz).
Enables selection of AUX audio frequencies through DATA ENTKY keys when used in conjunction
with 1020/AUX-TONE SELECT key.
+10 STEP Steps VOR mode radial in +lo-degree steps.
-f Slews VOR mode radial in 10.01-degree steps, LOC mode DDM in 0.001 (left) steps, o r GS mode
DDM in 0.002 (up) steps.
-10 STEP Steps VOR mode radial in -10-degree steps.
I
Slews VOK mode radial in -0.01-degree steps, LOC mode DDM in 0.001 (right) steps, o r GS mode
DDM in 0.002 (down) steps.
Enables storage of selected setup by entry of memory location in DATA ENTRY keys (operational
only on units with options 1 o r 2).
RCL Enables recall of entries in storage by entering memory location in DATA ENTRY keys (opera-
tional onlv on units with ootions 1 o r 21.
Scans by ArtekMedia © 2008 operation 523-0768883
KEY FUNCTION
Numerical 0/60" Provides numerical entry of rf c a r r i e r frequency, VOR radials, ILS DDM, and percent
through 9/330° modulation, auxiliary audio frequency, o r entry of VOR radials at every 30" major
heading when modifier ( f ) key is enabled (lit). In ILS mode 0/60°, key selects A ILS PH
when modifier ( f ) key is enabled (lit).
(decimal)/3O0 Used for numerical entries requiring a decimal point o r for a 30-VOR radial when
modifier (f) key is enabled (lit).
ENTER Enables numerical entries to signal generator circuits.
CLEAR Clears numerical key entry before ENTER key is pressed and also clears nonvalid
entries.
f Selects lower function (") of DATA ENTRY keys. Used a s a modifier when in ILS mode
to select A ILS PH.
KEY FUNCTION
RF FREQ Enables selection of rf c a r r i e r frequencies through DATA ENTRY keys. Also used to
step rf frequencies.
LOC/GS Switches rf c a r r i e r frequency from selected localizer frequency to paired glideslope
frequency o r vice versa.
AF Enables rf c a r r i e r frequency slewing through FAST INCR, SLOW INCR, FAST DECR,
and SLOW DECR keys.
R F ON/OFF Switches output of R F OUT connector alternately from ON to OFF.
FAST INCR Increases rf output level in 10-dB steps o r , when AF key is enabled (lit), increases rf
c a r r i e r frequency at a fast rate.
SLOW INCR Increases rf output level in 1-dB steps or, when AF key is enabled (lit), increases rf
c a r r i e r frequency at a slow rate.
FAST DECR Decreases rf output level in 10-dB steps o r , when AF key is enabled (lit), decreases
.
rf c a r r i e r frequency at a fast rate
SLOW DECR Decreases rf output level in 1-dB steps o r , when A F key is enabled (lit), decreases
rf c a r r i e r frequency at a slow rate.
Scans by ArtekMedia © 2008
AUDIO STATUS-
DISPLAY/INDICATOR FUNCTION
5-digit digital display Provides numerical indication of generated radial, DDM, o r percent modulation.
AILS PH Indicates a 60-degree phase shift of the 150-Hz component with respect to the 90-Hz
component, as measured between positive-going zero crossing of the 90-Hz and 150-
Hz components of the ILS composite waveform.
VAR % MOD Indicates percent modulation displayed is variable through DATA ENTRY keys.
indicator
VAR FREQ Indicates 30-, 9960-, 9960 FM-, 90-, and 150-Hz tones o r AUX audio tone a r e
variable through DATA ENTRY keys.
Coiitrols u t ~ dI?~ldzc(~tors
Fzgure 2 (Sheet 4 )
DISPLAY/INDICATOR 1 FUNCTION
FREQUENCY Display
6-digit digital display Provides numerical indication of actual rf c a r r i e r frequency o r selected variable
audio frequency.
MHz indicator Indicates rf c a r r i e r frequency resolution is 1kHz.
kHz indicator Indicates rf c a r r i e r frequency resolution is 0.1 kHz.
Hz indicator Indicates audio frequency with 0.1-Hz resolution to 1kHz and 1.0-Hz resolution
above 1kHz.
MODE Display
SELF TEST indicator Indicates signal generator is in self-test mode.
MB indicator Indicates marker beacon frequency selected and signal generator is in marker
beacon mode.
VO R indicator Indicates VOR frequency selected and signal generator is in VOR mode.
LOC indicator Indicates localizer frequency selected and signal generator is in localizer mode.
GS indicator Indicates glideslope frequency selected and signal generator is in glideslope mode.
COMM indicator Indicates vhf communication frequency selected and signal generator is in vhf
comm mode.
DISPLAY/PJDICATOR FUNCTION
R F LEVEL Display
3-digit digital display Provides numerical indication of rf output level and indicates when rf output i s
turned off.
-dBmW indicator Indicates digital readout i s displaying rf power in dB mW.
pV indicator Indicates digital readout i s displaying rf output level in microvolts.
mV indicator Indicates digital readout is displaying rf output level in millivolts.
k~ STATUS Display
P H LOCK indicator Indicates rf frequency synthesizer i s locked onto the selected frequency.
LEVEL CAL indicator Indicates the rf output from the signal generator i s within the specified limits.
Scans by ArtekMedia © 2008
operation 523-0 768883
O/Rl9OHzl
AUDIO STATUS- MODE -RF STATUS-
A lLS PH VAR % M O D YAR FREO STANDARD SELFTEST ME VOR LOC 0 3 COMM PH LOCK LEVEL CAL
I I I I
SELF TEST
SLOW
ON/O(F INCR INCR
RF OUT
POWER
0
ON OFF 4 7 9 s - 6 A VOR/ILS Slgnal Generator
3.1 Initial Power On (Refer t o figure 3 . ) the RAM'S has an incorrect output, the R F LEVEL
display will indicate the RAM that has failed (. . .
a. Press POWER switch to ON. 1). The signal generator will start another RAM
b. A computer memory check is performed im- check and will continue to sequence until malfunc-
mediately after power is turned on to determine if tion is corrected. If an incorrect output occurs on
the output from the memories is correct. If one of the ROM check, the number of the malfunctioning
Scans by ArtekMedia © 2008
MOO[%]
1 1 Ll 1 1 1 17, Ll 1 1 1
oI-I,IpI.CI,!-I,I-f,f-I
MODE
.
:rH'
Hz
o 1 1 1 :::--
111
o~-~o~-~o~-~
-R F STATUS-
mv
A ILS P H V A R I MOD VAR FRED STANDARD SELFTEST ME VOA LOC GS COMM PH LOCK LEVEL CAL
1 1 1 1 1 1 1 1 1 1 I I
SELF TEST
0 RF OUT
400 1300 3000
POWER
n
ON
0
.U
OFF
0
4 7 9 5 - 6 A VOR/ILS Signal Generator
RDVDDMlMOD FREQUENCY
TO ROLIDEGI MHz
FROM -1 I / DOM kHz
u/uISonrle LI -1 Moo[O/al HZ
O/RIOOHzI
AUDIO STATUS- MODE
A lLS PH VAR % M O D VAR F R E D STANDARD SELFTEST ME VOR LOC GS COMM
1
Self-Test Operation
Figure 4
Scans by ArtekMedia © 2008
dicator is off.
1 R F LEVEL- 11
RF Output Co)!trol
Fzgure 5 (Sheet 1 o j ' 2 i
-RF LEVEL-
1 1 1 1-1 * yyw
-1 L I ,,
c. RF Output Level Decrease (Refer to view C.) -R F STATUS-
PH LOCI LEVEL CAL
I
@
4 7 9 s - 6 A VOR/ILS Slgnal Generator
PH L O C I
mv
L N E L CAL
11
( Note I
When t h e R F LEVEL is displayed in
pV/mV, an additional 6 dB of attenuation is R F OUT
placed in the rf output circuit that provides a
"hard microvolt" output a t the RF OUT con-
nector. With a "hard microvolt" output, the
actual voltage a t the RF OUT connector is
one-half the voltage indicated on the R F
LEVEL display. This eliminates the require-
/ 4 7 9 s - 6 A VOR/ILS Signal Generator
ment for an external 6-dB pad. Vie149D RF Oziflrut Reference Level Change
RF Output Control
Figure 5 (Sheet 2)
Scans by ArtekMedia © 2008
-
3.4 On-ChannellRF FrequencylMode Selection
(Refer t o figure 6 . ) I -RF LEVEL-
R F LEVEL-
e. RF STATUS-PH LOCK AND LEVEL CAL in-
dicators are lit, indicating signal generator is
locked on the selected frequency and the rf output
is calibrated. Refer to view C. If either indicator is
not lit, repair signal generator. I - -RF STATUS-
PH LOCK LEVEL CAL
I II
View C. RF Status Indicators
Frequency/Mode Selection
Figure 6 (Sheet 1 of
Scans by ArtekMedia © 2008
f. When the R F SELECT-RF key is lit and the channeling information remains tuned to the last
carrier is being modulated, each successive depres- rf channel selected prior to entering the variable rf
sion of the R F FREQ key will step the carrier up mode. T h e REMOTE TUNE connector also
one channel in the mode selected. The signal provides NAV disable, COMM disable, and
generator will step to the highest frequency and LOC/GS energize mode discretes, as well as two
then return to the lowest frequency for the selected logic signals for control of antenna relay switching.
mode on the next step in all modes except LOC. j. In the ILS modes, if a localizer rf carrier frequency
When the highest channel is reached in LOC mode, is selected and it is desired to change to a paired
the next step will place the signal generator in VOR glideslope rf carrier frequency or vice versa, press
mode (112.00 MHz). R F SELECT-LOC/GS key a n d t h e signal
g. When the R F SELECT-RF FREQ key is lit and generator will switch to the paired frequency and
the carrier is not modulated (all TONE SELECT mode in a preset condition. Refer to view D.
keys off), each successive depression of the R F
FREQ key will step the carrier up in 50-kHz steps
in VOR/LOC, 150-kHz steps in GS, and 25-kHz I RF SELECT
steps in COMM.
h. Selection of a new mode automatically initializes
standard modulation a t the proper level. Refer to
figure 7 for preset conditions. Rf power level, RF OUT
Table 9. Standard VOR, ILS (Localizer and Glideslope), and Marker Beacon Frequencies.
Scans by ArtekMedia © 2008 operation 523-0768883
0 RF OUT
POWER
n
ON
0
11
OFF
Q
4 7 9 s 6 A VOR/ILS Slgnal Generator
Preset Conditions
Figure 7 (Sheet 1 of 3)
operation 523-0768883 Scans by ArtekMedia © 2008
0 RF OUT
POWER
n
ON
0
n
OFF
0
4 7 9 s - 6 A VOR/ILS Signal Generator
SELF TEST
0 RF OUT
POWER
n
ON
0
El
OFF
0
4 7 9 s - 6 A VOR/ILS Slgnel Generator
Preset Conditions
Figure 7 (Sheet 2)
Scans by ArtekMedia © 2008 operation 523-0768883
.
RDUDDM/MOD FREQUENCY -RF LEVEL-
yHT
TO RDLIDEG!
FROM -1
-
-1
1-1
1-11.-1
1-1 DDM
MOD,,! I
1 1 \ I / 1-1
I LI,I-I
1-1 1-1
CI 1-1
C
-1
1-1
CI
,","""
,v
U/L1150Hz!
DIRISOHz)
AUDIO STATUS- MODE -R F STATUS-
& R S PH VAR % M O D VAR FREO STANDARD SELF TEST ME VOR LOC GS COMM PH L O C I LEVEL C A L
I I I I
0 RF OUT
POWER
n
ON
0
E
L
OFF
0
4 7 9 8 6 A VORllLS Signal Generator
Prvset Condztto7r.s
figure 7 (Sheet 3)
Scans by ArtekMedia © 2008
a. Radial Selection
The VOR radial can be selected from 000.00 to
359.99 in 0.01-degree increments or on major
headings a t every 30 degrees.
1. Incremental Selection
(a) Check that FUNCTION/CONTROL-
RDL/DDM key is lit. Refer to view A. If key
is not lit, press RDL/DDM key to enable
entry of selected radial through DATA
ENTRY keys. RDL/DDM key lights and
remains lit after the radial selection so that
additional radial selections can be made. DATA ENTRY
-
AUDIO STATUS-
selected VOR radial in degrees and provides A lLS PH VAR % M O D Y A R FREQ STANDARD
I
a FROM indication. Refer to view C. If dis-
play is blinking, the data entered is un-
acceptable. Press DATA ENTRY-CLEAR
key to clear display and repeat steps a
through c.
b. Radial Adjustment
1. +30-Degree Adjustment
Press FUNCTION/CONTROL-STEP/ARDL/
ADDM key once for each 30-degree-step increase
required. Holding key depressed does not provide NOTE: SHADED KEYS INDICATE LIT KEYS.
continuous 30-degree-step increases. View E. Radial Adjustment
2. +lo-Degree Adjustment
3. -10-Degree Adjustment
4. +O.Ol-Degree Adjustment
5. -0.01-Degree Adjustment
Press FUNCTION/CONTROL-
-bKey once
for each 0.01-degree-step decrea e required.
Holding key depressed provides continuous
View G. TO-FROM Signal Switching
-
AUDIO STATUS-
Press FUNCTION/CONTROL-T/F U/L D/R key A ILS PH VAR % M O D VAR FREQ STANDARD
I
to change from a TO radial to a FROM radial, or
vice versa. RDL/DDM/MOD display TO/FROM View H. TO-FROM Signal Indicator
indicator changes; however, bearing display
remains a t the last selected bearing. Refer to view VOR Radial Selection and Adjustment
H. Figure 9 (Sheet 2)
Scans by ArtekMedia © 2008
3.7 VOR Mode Tone Selections 3. Enter new selected frequency on DATA ENTRY
(Refer t o figure 10.) numerical keys. The decimal point must -be
entered explicitly. For example, if 31.50 is to be
a. In the preset condition, 30-Hz variable and 9960- entered, enter 31.5 on the DATA ENTRY keys.
Hz FM (30-Hz reference) are selected and the If an error is made during the entry and before
TONE SELECT-30 Hz VAR and 9960 FM keys the ENTER key is pressed, press CLEAR key to
are lit. Either signal or both signals can be remove incorrect entry and reenter correct fre-
removed for flag checks or other test requirements quency. Press DATA ENTRY-ENTER key to
by pressing the applicable key. The key light is enter selected frequency in signal generator cir-
turned off when the signal is removed. Press key cuits.
again to add the removed signal. Refer to view A. 4. New frequency will be displayed. To observe
b. To obtain a 9960-Hz-only signal (30-Hz reference frequency of the 9960-Hz tone, press TONE
removed) for flag or other receiver checks, press SELECT-9960 FM or 9960 Hz keys.
TONE SELECT-9960 Hz key. 9960 Hz key lights
and 9960 FM key light goes out. Press 9960 FM key
to return to 9960 FM signal containing 30-Hz
reference.
key. The key will light and the VAR FREQ in-
dicator will light. Press STD key to turn off. n
ON
n
OFF
/ FREQUENCY I
--
1 1-1 1-1 yH:
-1 l - l * l L l
SELF TEST
10
POWER
0
n
ON
n
OFF
3.8 ILS DDM Selection and Adjustment (Refer and the slewing increments for each mode of opera-
t o figure 1 1 . ) tion.
Different but equivalent terminology is used between used. and ratio of audio tones expressed in dB. Ad-
generations of test equipment used for testing ILS ditionally, equivalent percent amplitude modulation
Receivers. Table 11 provides the necessary informa- lt>vels and nominal receiver microamp levels are
tion for conversion between DDM factors commonly provided.
(1) Conversion of any tone r a t i o ( e x p r e s s e d i n dB) to the equivalent difference i n depth of modulation (DDM)
is accomplished a s follows:
(a) Convert dB t o r a t i o
dB
R = loX, w h e r e x =-
20
@ ) Calculate
DDM =
R- 1
nix-
R+ 1
where M = modulation peak e x p r e s s e d a s a decimal.
(c) DDM R - 1
= 0.4~-
(LOC ) R+ 1
R - 1
(d)DDhl =0.8xP
(GS) K i- 1
I
1 (2) Calculating theoretical receiver output deflection given a DDM i s accomplished a s follows:
= DDRZ x 967.7
1I
(a) P ~ ( L O C )
@)p.A~GsjDD11i857.1
2. Divide by 2.
-
3. Add to 20(LOC) or 40(GS). This result i s the mod % of the larger tone.
-
4. Subtract the mod % of the larger tone from 40 (LOC) o r 80 (GS) to get the mod
- R of the smaller tone.
*DDM
(!/EL?
SMALLER
KCVR
DEFLECTION
bA)
*DDM
)
(!gR
SMALLER
RCVR
DEFLECTION
@*)
20 .oo 4o.00
0.000 0 0.000 0
20 .OO 40 .OO
0.012
20.58
12 0.023
41.15 20
19.42 38.85
0.023
21.13 22 0.045
42.25 39
18.87 37.75
22.28 44.55
0.0456 44 0.091 78
17.72 35.45
22.29 44.59
0.0458 44 0.092 79
17.71 35.41
0.046
22.30
45 0.092
44.60 79
17.70 35.40
0.087
24.37
84 0.175
48.75 150
15.63 31.25
0.091
24.53
88 0.181
49.05 155
15.47 30.95
0.093
24.65
-- 90 0.186
49.30 159
15.35 30.70
27.75 55.50
0.155 150 0.310 266
12.25 24.50
7.50 0.163
28.14
158 0.325
56.27 279
11.86 23.73
9.54 0.200
30 .OO
194 0.400
sO.00 343
10 .oo 20 .00
oc 0.400
40.00
- 387 0.800
80.00 686
00.00 00.00
*DDM (Difference i n Depth of Modulation) - the l a r g e r percent (70) of modulation l e s s the s m a l l e r percent (%)
of modulation divided by 100.
I-
NOTE: 150-Hz tone predominant: localizer is left, glideslope i s up;
90-Hz tone predominant: localizer is right, glideslope is down.
B. & lLS PH
AUDIO STATUS-
VAR % M O D VAR FREO STANDARD
I
b. DDM Slewing
-
2. Press FUNCTION/CONTROL-T/F U/L D/R modes. Press DATA ENTRY-f key to enable
key to switch DDM to D/R (90 Hz). phase shift. Key will light.
3. Change DDM to next required DDM either by 2. Depress DATA ENTRY 60, 0 key to produce an
stepping, slewing, or keyboard selection.
4. Press FUNCTION/CONTROL-T/F U/L D/R ILS composite signal with a 60-degree phase
key to switch DDM to U/L (150 Hz). shift between the 90- and 150-Hz signals. (Phase
shift equals 60 degrees of the 150-Hz compo-
nent, measured between positive-going zero
crossings.) The AUDIO STATUS-ILS P H in-
The above procedures are typical for discus- dicator lights when the phase shift is entered.
sion of signal generator operation and can be (a) DDMts may be entered from the keyboard.
varied as required during actual receiver When e n t e r e d f r o m keyboard, press
testing. FUNCTION CONTROL-= to turn off
DDM
f. ILS Phase Adjustment (Refer to view F.) DATA ENTRY-f and then make entry.
(b) When stepping DDMts, DATA ENTRY-f
key c a n s t a y o n . P r e s s FUNCTION
1. The phase between the 90- and 150-Hz signals CONTROL-STD key or DATA ENTRY-
can be varied in either localizer or glideslope 2 key to disable phase shift.
60"
/
/
AUDIO STATUS- MODE
A ILS PH VAR % M O D VAR FREO STANDARD SELF TEST MB VOR LOC GS COMM
I I
SELF TEST
0
POWER
0
a Il
ON OFF
h . Adjusting the 90- and 150-Hz Audio Modulation 4. E n t e r selected frequency on DATA ENTRY
Frequency numerical keys. The decimal point must be
entered explicitly. For example, if 92.5 Hz is
The 90- and 130-Hz frequencies a r e variable &5 desired, enter 92.5 on the DATA ENTRY keys.
percent. Refer to view H. If a n error is made during the entry and before
1. P r e s s t h e F U 5 C T I O S / C O N T R O L - V A R the ENTER key is pressed, press CLEAR key to
FREQ key. The key will light and the VAR remove incorrect entry and reenter correct
FREQ indicator will light. frequency. Press DATA ENTRY ENTER key to
2. Press the TONE SELECT 90-Hz or 150-Hz keys enter selected frequency in signal generator cir-
to select desired frequency. The selected fre- cuits.
quency will be displayed. 5. New frequency will be displayed. To observe
3. The tones may be deleted or added in the frequency of other tone, press TONE SELECT
variable frequency mode by depressing the 90-Hz and 150-Hz keys to select other tone. Ad-
VAR FREQ key again. The signal generator justing either tone will cause a corresponding
will remain in the variable frequency mode. To change in the other. For example, changing 90-
make subsequent changes depress VAR FREQ Hz 2 percent to 91.8 will cause the 150-Hz to
key again. also change 2 percent to 133-Hz.
FREQUENCY
MHz
\
,,,
-
I I -1
AUDIO STATUS-
- - -1
MODE
-i a i- i *HZ
i. Audio Tone Addition entry. Pressing any front panel key causes
flashing to cease.
A preset 1020-Hz or an auxiliary 30-Hz to 4-kHz
audio tone may be added to the localizer signal. For piq
special test purposes 10- to 30-Hz and 4- to 10-kHz Entries from 10 to 30 Hz and from 4 to 10
audio tones may also be added. The preset 1020-Hz kHz are also allowed for special test pur-
audio tone cannot be added to the glideslope signal. poses and will not cause the FREQUENCY
Refer to view I. indicator to flash.
1. Preset 1020-Hz Audio Tone (Localizer Only) (1) Frequency Selection
Press TONE SELECT 1020/AUX key. Key Enter selected audio frequency on DATA
lights and a 1020-Hz audio tone is added to the ENTRY numerical keys. The decimal
localizer signal if VAR FREQ key is not lit. point must be entered explicitly. For ex-
Press key again to remove audio tone. ample, if 25.5 Hz is desired, enter 25.5 on
the DATA ENTRY keys. If an error is
2. AUX (30-Hz to 4-kHz) Audio Tone made during the entry and before the-
(a) Press FUNCTION/CONTROL-VAR FREQ ENTER key is pressed, press CLEAR
key. Key lights and VAR FREQ indicator key to remove incorrect entry and
lights. Press STD key to turn off. reenter correct frequency. Press DATA
(b) Press TONE SELECT 1020/AUX key. Key ENTRY-ENTER key to enter selected
lights and a 1000-Hz audio tone is added to audio frequency in signal generator.
the localizer or glideslope signal and dis- (2) AUX Audio Frequency Slewing
played on the FREQUENCY-indicator. To Press FUNCTION/CONTROL-+key
t u r n off AUX a u d i o t o n e , d e p r e s s once for each step increase desired.
FUNCTION/CONTROL-VAR FREQ key Holding key depressed provides con-
followed by TONE SELECT 1020/AUX key. tinuous frequency increase. Slewing is in
If VAR FREQ is pressed while 1020 is on, 1.0-Hz steps above 1000 Hz and in 0.1-
the 1020 will go off. s t e p s below 1000 Hz. P r e s s
FUNCTION/CONTROL- +key once
(c) Frequency Adjustments for each step decrease desired. Holding
The frequency can be adjusted from 30 Hz to key depressed provides continuous fre-
4 kHz. Entries that would exceed the range quency decrease. Slewing is in 1.0-Hz
cause the FREQUENCY indicator to flash steps above 1000 Hz and in 0.1-Hz steps
and AUX frequency to remain a t last valid below 1000 Hz.
FREOUENCY
11-1
I 1-1
1-1
1-1
1-1 1-1
CI,I-I
1-1
LI
rH:
HZ
An auxiliary audio tone may be used in place of the Enter selected audio frequency on DATA
standard audio marker beacon frequencies for ENTRY numerical keys. The decimal point
specialized tests. Refer to view D. must be entered explicitly. For example, if
375.5 Hz is desired, enter 375.5 on the
1. Press FUNCTION/CONTROL-VAR FREQ DATA ENTRY keys. Of an error is made
key. Key lights and VAR FREQ indicator lights. during the entry and before the ENTER key
2. TONE SELECT-1020/AUX key lights, the is pressed, press CLEAR key to remove in-
p r e s e t 400-, 1300-, o r 3000-Hz t o n e i s correct entry and reenter correct frequency.
automatically deleted (if present) and a 1000-Hz
audio tone replaces the marker beacon signal (b) AUX Audio Frequency Slewing
and is displayed on the FREQUENCY indicator. Press FUNCTION/CONTRO# key once
for each step increase desired. Holding key
3. Frequency Adjustments depressed provides continuous frequency
inirease. slewing is in 1.0-Hz steps above
The frequency can be adjusted from 100 Hz to 1000 Hz and in 0.1-Hz steps below 1000 Hz.
4000 Hz. Entries that would exceed the range Press F U N C T I O N / C O N T R O L ~once
~~~
cause the FREQUENCY indicator to flash and for each step decrease desired. Holding key
AUX frequency to remain a t last valid entry. depressed provides continuous frequency
Pressing any front panel key causes flashing to decrease. Slewing is in 1.0-Hz steps above
cease. 1000 Hz and in 0.1-Hz steps below 1000 Hz.
e. Interference Check
I FREQUENCY I
/
A
-
lLS PH
AUDIO STATUS-
VAR % M O D
F
VAR F R E a
I
STANDARD
d
SELFTEST MB
I
MODE
VOR LOC GS COMM
0
POWER
0
a
ON
Ll
OFF
I
I
NOTE: SHADED KEYS INDICATE LIT KEYS.
viex D. A UX Tone Selection
1
11
TO
FROM
UILII5OHzl
D/RISOHzI
RDUDDM/MOD FREQUENCY I
SELF TEST
0
POWER
0
n 1?
ON OFF
VOR
30 Hz VAR' 30 .O
9960 Hz F M 30.0
AUX audio 30.0
Localizer
90/150 Hz 20.0
AUX audio 30.0
Glideslope
90/150 Hz
AUX audio
M a r k e r Beacon
400/1300/3000 Hz
AUX audio
Communication
AUX audio
This paragraph provides operational instructions for GET group execute SPE serial poll enable
the IEEE Interface Card A10. Paragraph 3.15.2 ap- trigger
plies only to 479s-6A units with A10 CPN 601-5883-
001. Paragraph 3.15.3 applies to 479s-6A units with TCT take control SPD serial poll
A10 CPN 601-2309-001. disable
Table 13 contains the talk/listen addresses which
Because IEEE bus data lines D6 and D7 are not should be avoided when configuring for IEEE bus
decoded while an address byte appears on the bus, operations.
D7 D6 D5 D4 D3 D2 D1
X X 0 0 0 0 1 ! A
X X 0 0 1 0 0 $ D
X X 0 0 1 0 1 9 E
X X 0 1 0 0 0 ( H
X X 0 1 0 0 1 1 I
x x 1 o o o 1 1 Q
X X 1 0 1 0 0 4 T
X X 1 0 1 0 1 5 u
X X 1 1 0 0 0 8 X
X X 1 1 0 0 1 9 Y
3.15.2 / E K E O p e r a t i o n .for I-nits with A10 CP>Y sembly A10. The signal generator is shipped from
601 -5883-001 I n s t a l l e d the factory preset to:
@ STD
/
0
T/F, U/L, D/R
0
A
B
* 1""'
N/A
1 1 C CLEAR
2 2 D RDL/DD~I
3 3 E ENTER
4 4 F R F FREQ
5 5 G 30 Hz VAR
6 6 H 9960 FLI
7 7 I 9960 Hz
8 8 J 1020/AUX
9 9 K 90 Hz
SELFTEST L 150 Hz
, VAR FREQ nl RLIOD
< RC L N 400 Hz
-
- DELTA F 0 R F ON/OFF
> ST0 P 1300 Hz
? f Q 3000 Hz
*Rf attenuation i s programmed directly. See text for definition and usage of these two symbols.
*
SELF TEST
0 RF OUT
POWER
n
ON
0
E
LOFF
@
4 7 9 s - 6 A VOR/ILS Slgnal Gensrator
release the IEEE bus until it has completed character ":" is then sent. The generator then
processing the last message string received lvill enter the self-test mode, which requires ap-
(that is, the NDAC interface line is held low). proximately 15 seconds. During this interval,
4. Rf level data is programmed directly into the the signal generator ROM and RAM memory is
signal generator. Two basic modes are available: tested, the rf frequency is tested, the digital
( a ) The signal generator can be programmed in waveform generator is tested by programming
the dB mW mode. In this mode, the R F a VOR 0 degree bearing into it and requiring a
LEVEL display indicates in -dB mW and valid response (phase indication), and, lastly,
displays the actual rf level a s measured a t the PH LOCK and LEVEL CAL statuses are
the rf output connector of the generator. Rf determined. At the termination of the self-test,
level is programmed by transmitting an A, the internal CPU reprograms the signal
followed by a 1-, 2-, or 3-digit number generator to the power-up condition (refer to
representing the desired rf level expressed description section, paragraph 8.3) and restores
in dB. (Examples: A6, A50, A120.) Allo~ved signal generator operation to the manual mode.
range is 6 to 120, corresponding to rf levels At this point, the remote controller can resume
of -6 to -120 dB mW respectively. executing its normal program or request the
( h ) In the "hard pV" mode, level is displayed in self-test results from the signal generator.
hard pV, and the level a t the generator rf 2. To request self-test results, the remote control-
output if 6 dB lower than that displayed. ler addresses itself to listen, then sends the talk
(This eliminates the need for an external 6- address of the signal generator. For a valid self-
dB pad.) Rf level is programmed by tran- test, the signal generator will reply with the fol-
smitting an A, followed by a 1-, 2-, 3-digit lowing ASCII character string:
number representing the dB equivalent for
the hard level desired, followed by a "B." P L F B
The signal generator will automatically in-
sert an additional 6 dB, simulating an exter-
nal 6-dB pad. For example, a level of 5 pV
First byte t
("hard pV1') is required. The equivalent 3. The intelligence conveyed by the ASCII
level, in dB, corresponding to 5 pV is -93 dB character string is a s follows:
mW; thus the generator is programmed to
A93B. The rf level display indicates 5 pV
and the signal generator output level is 2.5 CHARACTER
PV. TRANSMITTED FUNCTION
5. The device clear (DC) and device trigger (DT) in-
terface functions are not used. Successful self-test of the signal
6. The interface clear (IFC) and end or identify generator rf synthesizer phase-
(EOI) bus management interface lines are not lock status
used.
Successful self-test of the signal
3.15.2.2 Talker Z n t ~ r f a c eFunction generator rf level status
1. The remote controller can initiate a self-test of 4. The signal generator holds control of the bus
the signal generator. The generator is first ad- during the entire self-test interval by holding
dressed as a LISTEN device; the test command the NDAC line low. (This is also true during
normal ATE operation whenever the signal c. Service Request and Serial Polling
generator is processing a complete character
string.) If either the ROM or RAM check fails 1. A request for service (SRQ) will be generated
during t h e self-test interval, t h e signal asynchronously whenever the signal generator
generator will enter a "flash display" loop detects invalid data ( t h a t is, a n "out-of-range" rf
routine and will never allow the NDAC line to frequency) or an invalid command character.
go high, thus the self-test pass-fail status is 2. The signal generator sets the SRQ bus manage-
automatically annunciated. ment interface line TRUE (logic 0) and, when
5. Results of the self-test should not be requested addressed during a serial poll, transmits a
by the controller until completion of the entire status byte to the controller. The format is a s
self-test interval, or a n erroneous or failed con- follows:
dition may occur.
8 7 6 5 4 3 2 1
-
-
\ 1
II
0 = Data 1 = Service Reserved 0 = Command OK
requested
1 = Invalid command
1 = Data character
out of
range
STATUS BYTE
( a ) Data bit 1 will be 1 if an invalid command sed during a serial poll, respond with the status
character was received by t h e signal 11yte. Bit 7 will be 0, indicating service was not
generator. The remote controller must then requested by the generator. Bits 1 and 8 will
repeat the entire character string. likewise be 0.
(t)) Data bits 2 through 6 are reserved for future 5. The parallel poll ( P P ) interface function is not
applications and may be in either the 1 or 0 used.
states independently. 3.15.3 I E E E Operation .for ( ; n i t s w i t h
(c) Bit 7 will be a 1 indicating service was re-
.4 10 (:P.V 601 -2309-001 Installed
quested.
( d ) Bit 8 will be 1 if out-of-range d a t a is The signal generator may be remotely controlled via
received by the signal generator ( t h a t is, a n the I E E E standard digital interface for program-
invalid rf frequency character was in- mable instrumentation (IEEE STD-488/1978).
advertently transmitted). The remote con- a . General
troller must then repeat the entire character
string. In general, the signal generator may be program-
3 . D u r i n g a serial poll sequence, t h e signal med remotely in the same manner a s manually.
generator does not recognize either the serial That is, sequential d a t a characters a r e transmitted
poll enable ( S P E ) or serial poll disable (SPD) in the proper order and content the same a s if the
universal commands, but instead monitors the signal generator front-panel keys were being
state of the SRQ line. Consequently, the control- pushed manually. Certain manual keystrokes are
ler should not request the status byte from the not emulated remotely when the manual function
signal generator while the SRQ line is FALSE was to provide "operator convenience" features
(logic 1) or an incorrect or failed condition may (that is, + 10 and -10 degree bearing step keys). Ad-
occur on the bus. ditionally, the rf attenuation level is programmed
4. If any other device on the bus requests service directly from the remote controller instead of
from the controller (by setting SRQ = TRUE, or emulating the FAST INCR, SLOW INCR, FAST
logic 0), the signal generator u~ill,when addres- DECR, and SLOW DECR keystrokes. I t must also
be noted that, since several of the keys provide a SH1 - Complete source handshake capability
toggle function, the programmer must keep track
of the previous state of these keys or an incorrect T6 - Basic talker, serial poll, unaddress if MLA,
result could be obtained. no talk only mode
'
1 b. Address Selection
Address selection for the signal generator is
L4 - Basic listener, unaddress if MTA, no listen
only mode
Not implemented:
TE0 - Extended talker
Per appendix E of IEEE STD-488/1978, this corre-
sponds to a LISTEN address of "611 and a corre- LE0 - Extended listener
sponding TALK address of "V". PP0 - Parallel poll
c. Address Selection Switch DT0 - Device trigger
A 5-position DIP switch on assembly A10 can be
C0 - Controller
reset to select another address. Viewed from the
component side of the A10 assembly, the switches
are arranged from right (MSB) to left (LSB) to cor- 3.15.3.1 Listener Interface Function
respond with the lower order bits of the ASCII
data bus. A closed switch indicates logic 1 on the a. General
ASCII data bus and an open switch indicates logic The signal generator can receive device dependent
0. data over the interface when addressed to listen.
d. GPIB Functions Implemented b. Syntax (Refer to figure 17)
The following functions are implemented per
IEEE STD-488/1978: The following ASCII characters and their as-
sociated functions are recognized by the signal
AH1 - Complete acceptor handshake capability generator when in the LISTEN mode.
STD
T/F,
0
1
U/L, D/R
* {;;;
CLEAR
2 RDL/DDM
3 ENTER
4 R F FREQ
5 30 Hz VAR
6 9960 Fhl
7 9960 Hz
8 1020/AUX
9 90 Hz
SELFTEST 150 Hz
VAR FREQ 7h l 0 D
RC L 400 Hz
DELTA F R F ON/OFF
ST0 1300 Hz
f 3000 Hz
*Rf attenuation is programmed directly. See text for definition and usage of these two symbols.
1
Revised 1 5 October 1980 37
operation 523-0768883 Scans by ArtekMedia © 2008
-
TONE SELECT FLINCTION/CONTROL DATA ENTRY RF SELECT
SELF TEST
0 R F OUT
ON
POWER
0
nOFF
a
4 7 9 S ~ 6 AVOR/ILS Signal Generator
1 -
Revised 15 Octob~r.1980
Scans by ArtekMedia © 2008
operation 523-0768883
( a ) Data bit 1 will be 1 if an invalid command enable ( R E N ) bus control line true, the signal
c h a r a c t e r w a s received by t h e signal generator will enter the remote mode. In this mode
generator. The remote controller must the bus has control and the front-panel keyboard is
then repeat the entire character string. locked out (except for the power switch). If the signal
ih) Data bits 2 through 6 a r e reserved for generator is addressed to listen with the REN line
future applications and may be in either false, the signal generator will remain in the local
the 1 or 0 states independently. mode and the generator will handshake in but ignore
ic) Bit 7 will be a 1 if service was requested. all d a t a on the bus. Addressing the signal generator
(dl Bit 8 will be 1 if out-of-range d a t a is to talk has no effect on the remote-local status. When
received by the signal generator ( t h a t is, a n the generator is in the remote mode, it may be
invalid rf frequency character was in- returned to the local mode in one of three ways:
advertently transmitted). The remote con-
troller m u s t then repeat t h e entire a . Initiate a power-up state. This may be done by
character string. sending either the self-test command ":'I or one of
the bus commands "DEC" or "SDC".
3.15.3.1 Derice C l e a r I n t e r f a c e F u n c t i o n h. Address the signal generator to listen and send the
addressed bus command I'GTL" (go to local-hex
The device clear interface function provides the signal code 0). This will not change any conditions set up
g e n e r a t o r w i t h t h e c a p a b i l i t y t o be cleared on the signal generator, but will return the front
(initialized). panel to the active state.
c. Set the R E N line to a false state. The signal
Sending the universal bus command "DCL" (device generator will respond to this in the s a m e way a s a
clear - hex code 14) or the addressed bus command "GTL" command.
"SDC" (selective device clear - hex code 04) will
return the signal generator to the power-up state, The signal generator has no "local lockout" capability.
with the exception of remaining in the remote mode.
Upon power-up, the 479s-6A will be in the local mode Bus commands associated with functions not used, a s
(front panel is activated). The first time the signal well a s undefined bus commands, will be ignored by
generator is addressed to listen with the remote the signal generator.
5.15.4 ZEEE P r o g r a m m i n g E x a m p l e s
a. Example Number 1
The following example demonstrates how the signal generator can be programmed to perform rf sensitivity
measurements (s+n/n) a t several different frequencies.
1. 329.15 MHz
5. 30% modulation
10. No modulation
12. 332 MHz modulated Display reads 100 FV. Generator output is 50 pV
30% by 150 Hz
(rf level to be 100
PV)
14. No modulation
b. Example Number 2
The following example demonstrates how the signal generator may be programmed to perform rf selectivity
measurements.
c. Example Number 3
The following example programs the signal generator for ILS on-center and off-course DDM's. Both 90 > 150
and 150 > 90 Hz situations are illustrated.
1: 332 MHz, 700 pV F332EA50B Upon initial selection of the glideslope mode, a standard
(hard pV), stand- on-center condition is established.
dard centering signal
2. DDM.091, D.O91E/ Initial DDM selection upon entering glideslope mode will
90 > 150 Hz automatically be 150 > 90 Hz. T/F U/L D/R command
toggles off-course DDM's to select predominating tone.
Rockwell
International
Collins 479s-6A
VORIILS Signal Generator installation
I Collins Government Av~onicsDivision,
.b
2
Printed ~n USA 523-0768884-101118
1 September 1978
1st Revision, 15 October 1980
Zr
V)
table of contents g
3
!
3
i?
S
Paragraph Page %
:
2. Iinpackirtg and Inspectiurt ............................................................................ 1
3. Parking ............................................................................................. 1
4. Installation .......................................................................................... 1
Issue
'Title . . . . . . . . . . . . . . . . . . . . . . . . . 15 Oct 80
*List of Effective Pages ........ 15 Oct 80
*1 thru 4 . . . . . . . . . . . . . . . . . . . . . . 15 Oct 80
! 15 Oct 80 1 thru 10
Scans by ArtekMedia © 2008
installation
This section provides information on unpacking and Prior to installing the 479s-6A in a n equipment
inspection, preparation for shipment, rack mounting, rack, the rack mounting kit must be installed. Mount
and connector information for the 479s-6A VOR/ILS the flanges contained in the kit as follows:
Signal Generator.
a. Remove screws that secure dust cover: two from
2. UNPACKING A K D INSPECTIOY each side and six from bottom of signal generator.
b. Slide dust cover off of signal generator.
Unpack equipment and inspect for signs of damage. c. Remove four screws and washers (two located on
Refer to figure 1 during performance of the un- each side behind dust cover mounting bracket)
packing procedure. The container a n d packing securing front panel assembly to chassis.
material should be saved for storage or reshipment. d. Pull front panel assembly forward to clear rf con-
nector and tilt forward, taking care not to pull
a. Use a sharp tool, such a s a knife, and carefully cut loose the connecting wiring.
sealing tape of shipping container. e. Remove one flathead screw securing left-side dust
b. Fold back container flaps. cover mounting bracket and handle to front panel
c. Remove top mold and polyethylene film sheet. assembly.
d. Remove unit from shipping container. Do not f. Remove left handle and position rack mounting
remove protective caps or covering from connec- flange in its place with lip facing out.
tors. g. Reposition left-side dust cover mounting bracket
e. Replace all packing material in shipping container, and secure with one flathead screw.
and save container for storage and/or reshipment h. Remove one flathead screw securing right-side
purposes. dust cover mounting bracket and handle to front
panel assembly.
3. PACKING i. Remove right handle and position rack mounting
flange in its place with lip facing out.
Prepare the 479s-6A for storage or shipment in accor- j. Reposition right-side dust cover mounting bracket
dance with the following procedure: and secure with one flathead screw.
k. Reposition front panel assembly on chassis and
a. Obtain original shipping container for unit and secure with four screws and washers.
remove all packing material except bottom mold. 1. Slide dust cover on signal generator and secure
Refer to figure 1. with ten screws.
b. Install protective connector caps or covers over all
connectors.
c. Place unit on bottom mold of shipping container.
d. Install top foam mold over unit, ensuring foam is 4 . 2 Rack Mounting
fitted properly over unit.
e. Close flaps of shipping container and seal. Mount the 479s-6A in an equipment rack a s fol-
IOIVS.
4. INSTALLATION
a . Install the rack mounting kit (refer to paragraph
The 479s-6A is shipped from the factory in a standard 4.1).
bench configuration. A rack mounting kit (CPN 638- b. Locally fabricate support for the rear of the 4798-
2250-001) is available to allow mounting the 479s-6A 6A and install it in t h e equipment rack. Recom-
mended method of adequate support is aluminum
I in a n equipment rack. Rack mounting procedures a r e
described below. angle side rails mounted in the equipment rack.
6. OPERATIONAL TEST
c. Position the 479s-6A in the equipment rack and
secure with f o u r m o u n t i n g screws (locally Refer to the operation section for power-up and self-
procured). test procedures.
N O T E . U N L E S S O T H E R W I S E SPECIFIED, D I M E N S I O N S A R E I N
MILLIMETRES [INCHES].
2 M I L THICK POLYETHYLENE
/ F I L M SHEET.
- E l
- E
7
D 0 MHz
]D 0 MHz
- D
- E
] 0 . 0 MHz
- FREQ COM
- NAV DISABLE
- LOC/GS ENERGIZE
- MODE SELECT B
-COMM DISABLE
- MODE SELECT A
- GND
- SCOPE TRIGGER
SPARE
I IEEE-STD 4 8 8 / 1 9 7 8 PROGRAM l / O 1
-
DAV
DAC
SRQ
GND (DAV)
GND ( R F D ) NOTES:
m
- CONNECTOR T Y P E N
REN FEMALE
TF€
GND (SRQ) @ CONNECTOR. CPN 3 7 1 - 0 3 9 7 -
GND (ATN) 030 ( M A T I N G CONNECTOR
GND (LOGIC) FURNISHED)
GND (DAC) @ CONNECTOR T Y P E BNC
GND ( IFC) FEMALE
D@
DI CONNECTOR T Y P E IEEE
D2 STANDARD CPN 3 7 2 - 0 0 1 8 -
p3 710. M A T E S W I T H H E W L E T T
D4 -PACKARD H P - 1 0 I N T E R -
D5 CONNECT CABLES. 1 0 6 3 1
S E R I E S . OR EQUIVALENT.
D6
D7
SH l E L D
@) FREQ COM AND MODE COM
PINS REQUIRE JUMPER I N
E X T E R N A L CONNECTOR FOR
MOST A P P L I C A T I O N S
Rockwell
International
Collins 479s-6A
VORIILS Signal Generator maintenance
I C o l l i n s G o v e r n m e n t A v i o n i c s Division
a
-I
a
Printed in USA 523-0768885-102118 'P
3rd Edition, 15 October 1980 $
<
0
Z
F
table of contents
A
Scans by ArtekMedia © 2008
maintenance
Range: 0 to 60 dB in 10-dB s t e p s
Hewlett-Packard 355D
I
Vswr: 1.20 m a x Special calibration data r e -
q u i r e d f o r attenuation accuracy
r e q u i r e m e n t s . The 8- to 11-
MHz r e q u i r e m e n t s a r e only
2 I October 1978
IZel~is~cl
Scans by ArtekMedia © 2008 maintenance 523-0768885
Calibrator: 300 m V
Horizontal t i m e base: 5 p s to 50
ms/division ( s e l e c t a b l e in 1, 2 , and
5 sequence)
Sweep a c c u r a c y : + l % , 5 p s to 5 ms!
division; 5 2 4 , 1 0 m s t o 50 ms/division
Loss: 3 50.5 d B
Loss: 6 *0.25 d B
M e a s u r e m e n t bandwidth: 1 0 I l z to
1 5 kH7
T e m p e r a t u r e : 25 *lo "C
<0.2% f o r 3 0 5 Ahl
<0.7$ f o r 90"( Ahl
Distortion: <0.5'(
If output: 8 to 1 2 > M I
Bandpass flatness: I 1 d B f r o m i l l
to -3000 kIIz f r o m c e n t e r frequency
R ~ r i s ~1 dOctober 1978 i 5
maintenance 523-0768885
Scans by ArtekMedia © 2008
2.38 A3A1 t e s t F a b r i c a t e a s d e s c r i b e d in p a r a g r a p h
fixture 5.4.3.1.
PWR SUPPL
ASSY A 5
COVER
B A R R I E R STRIP
COVER SCREW (2)
BARRIER
STR IP
P/O BARR l ER
A5Al J1
230 V AC.
50/60 Hz
4
Reitist.rl 1 October*1.9%
Scans by ArtekMedia © 2008
maintenance 523-0768885
TO
FROM
RDUDDM/MOD
ROLlOEGl
DDM
FREQUENCY -RF LEVEL- 1
V/L(ISOHzI I-' .'-I '-'el-' I-' MOD(%)
O/RISOHzI
SELF TEST
0
RF OUT
POWER
n
ON
0
11
OFF
0
4 7 9 s - 6 A VOR/ILS Signal Generator
0
RF OUT
400 1300 3000
n
ON
POWER
0
E
L
OFF
a
4 7 9 5 6 A VOR/ILS Sbgnal Generator
b. Press 9960 FM key. The 9960 FM key indicator h. Press 1020/AUX key. The 1020 Hz key indicator
must turn off. must light.
c. Press 1020/AUX key. The key indicator must turn c. Press 30 Hz VAR, 9960 FM, 9960 Hz, 400 Hz, 1300
on. Hz, and 3000 Hz keys, one a t a time. Verify no
d. Sequentially, press 90 Hz, 150 Hz, 400 Hz, 1300 Hz, changes occur on the front panel.
and 3000 Hz keys. Verify no changes occur on the d. Press 1020/AUX key. The key light must go out.
front panel. e. Sequentially press f key and 0/60° keys. The f key
e. Set TI frequency to 108.00 MHz. and the A ILS P H indicator must light.
f. Press T/F U/L D/R key. RDL/DDM/MOD FROM f. Press STD key.
indicator must turn off and TO indicator must turn g. Press 90 Hz and 150 Hz keys. The key lights must
on. go out.
g. Press STD key. RDL/DDM/MOD TO indicator
must turn off and FROM indicator must turn on. 4.2.6 Glideslope
h. Press STEP A RDL A DDM key. RDL/DDM/MOD
indication must increase 30 degrees. a. Sequentially, select TI GS frequencies of 329.15,
i. Press + l o 0 STEP key. RDL/DDM/MOD indication 332.15, and 335.00 MHz. TI display status must be
must increase 10 degrees. as follows for each selected frequency:
j. Press -10" STEP key. RDL/DDM/MOD indication
must decrease 10 degrees. DISPLAY INDICATION
k. Press and h o l d 4 key. RDL/DDM/MOD indica-
tion must increase. Release key. RDL/DDM/MOD U/L (150 Hz), .000 DDM
1. Press and h o l d F k e y . RDL/DDM/MOD indication AUDIO STATUS STANDARD
must decrease. Release key. FREQUENCY (Frequency selected) MHz
m. Press RDL/DDM key and enter i23.45 on DATA MODE GS
ENTRY keys. Press DATA ENTRY ENTER key. R F LEVEL 50 dB mW
RDL/DDM/MOD display must indicate 123.45 RF STATUS P H LOCK, LEVEL CAL
degrees. TONE SELECT 90 Hz, 150 Hz
n. Press f key. Key must light and RDL/DDM key FUNCTION/CONTROL No keys lit
light must go out. DATA ENTRY No keys lit
o. Press 120" key. Verify RDL/DDM/MOD display R F SELECT R F FREQ
indicates 120.00 degrees.
p. Press STD key. RDL/DDM/MOD display must in- h. Sequentially, press 1020/AUX, 30 Hz VAR, 9960
dicate 000.00 degree. FM, 9960 Hz, 400 Hz, 1300 Hz, and 3000 Hz keys.
Verify no changes occur on the front panel.
4.2.5 Localiaer c. Sequentially, select TI LOC frequencies of 108.10,
110.10, and 111.95 MHz and press R F SELECT --
a. Sequentially, select TI LOC frequencies of 108.10, LOC/GS key. TI display must change to paired GS
110.10, and 111.95 MHz. TI display status must be frequencies of 334.70, 334.40, and 330.95 MHz
a s follows for each selected frequency: respectively.
DISPLAY INDICATION
status must be a s follows for each selected fre- e. Press RDL/DDM keg and enter 2 0 0 on DATA
quency. ENTRY keys. Press DATA ENTRY ENTER key.
RDL/DDM/MOD display must indicate 3 0 0 DDM.
DISPLAY INDICATION f. Press T / F U/L D/R key. RDL/DDM/MOD U/L
(150 Hz) indicator must turn off and D/R (90 Hz)
RDL/DDM/MOD 30.0 MOD (9) indicator must turn on.
AUDIO STATUS STANDARD g. Press STD key. RDL/DDM/MOD D/R (90 Hz) in-
FREQUENCY (Frequency selected) MHz dicator must turn off and U/L (150 Hz) indicator
MODE COMM must turn on.
RF LEVEL 50 -dBmW 4.2.10 Frequency F'erni~r
TONE SELECT 1020/AUX
FlJNCTION/CONTROL No keys lit a . Set TI for an output frequency of 108.000 MHz
DATA ENTRY No keys lit without modulation (no TONE SELECT keys lit).
R F SELECT R F FREQ b. Set TI rf output level to -6 dB mW and press TI AF
key for AF operation. TI frequency displays
b. Press 1020/AUX key. Verify key light and STAN- between 07 990.0 and 08 010.0.
DARD indicator go out. c. P r e s s a n d hold T I S L O W DECR key. TI
c. Press all remaining TONE SELECT keys one a t a FREQUENCY indication must decrease. Release
time. Verify no changes occur on the front panel. key.
(1. Press STD key. d . P r e s s a n d hold T I S L O W I N C R k e y . T I
FREQUENCY indication must increase. Release
key.
4.2.8 Localizer DD,M e. P r e s s a n d hold T I F A S T D E C R k e y . T I
FREQUENCY indication must decrease. Hold
a. Set TI FREQUENCY to 108.10 MHz. FAST DECR key until display counter frequency
b. Repeatedly press S T E P ARDL ADDM key. decreases to a t least 07 950.0.
RDL/DDM/MOD indication must increase from f . P r e s s a n d hold T I F A S T INCR key. T I
.000 in the following steps: ,046, .093, ,155, and FREQUENCY indication must increase. Hold
,200. FAST INCR key until display counter frequency
c. Press and hold
t- key. RDL/DDM/MOD indica-
tion must decrease. Release key.
increases to a t least 08 050.0.
d. Press and h o l d 4 key. RDL/DDM/MOD indica-
tion must increase. Release key.
e. Press RDL/DDM key and enter .400 on DATA a . Set TI output frequency to 75.000 MHz and rf out-
ENTRY keys. Press DATA ENTRY ENTER key.
RDL/DDM/MOD display must indicate .400 DDM.
put level to -50 dB mW. Delete audio tone.
b. Press TI dB mW/uV key. TI R F LEVEL indication I
f. Press T / F U/L D/R key. RDL/DDM/MOD U/L must be 700 pV. Press dB mW/uV key again and
(150 Hz) indicator must turn off and D/R (90 Hz) R F LEVEL indication must be 50 dB mW.
indicator must turn on. c. Press and hold TI SLOW DECR key. TI R F LEVEL
g. Press STD key. RDL/DDM/MOD D/R (90 Hz) in- indication must decrease in 1-dB increments.
dicator must turn off and U/L (150 Hz) indicator d. Press and hold TI SLOW INCR key. TI R F LEVEL
must turn on. indication must increase in 1-dB increments.
e. Press and hold TI FAST DECR key. TI R F LEVEL
indication must decrease in 10-dB increments.
4.2.9 Glideslope DDM
f. Press and hold TI FAST INCR key. TI R F LEVEL
indication must increase in 10-dB increments.
g. Set TI rf output level to -6 dB mW and press TI R F
a. Set TI FREQUENCY to 335.00 MHz.
SELECT -- R F ON/OFF key. Observe following TI
b. Repeatedly press STEP ARDL ADDM key. RDL/ displays for proper indication.
DDM/MOD indication must increase from
,000 DDM in following steps: .045, .091, ,175, and
DISPLAY INDICATION
,400.
c. Press and hold key. RDL/DDM/MOD indica- FREQUENCY - - - - - - MHz
tion must decrease. Release key. RFLEVEL OFF
d. Press and hold- key. RDL/DDM/MOD indica- R F STATUS P H LOCK, LEVEL CAL indicators
tion must increase. Release key. off
h. Press TI R F SELECT -- R F ON/OFF key. Ob- modulation (NO TONE SELECT keys lit) a t -6 dB
serve following TI displays for proper indication. mW. Results: frequency counter displays TI frequen-
cies within limits given below.
DISPLAY INDICATION FREQUENCY COUNTER
TI FREQUENCY DISPLAY LIMITS
FREQUENCY 75.000 MHz
(MHz) (MHz)
R F LEVEL 6 dB m W
RF STATUS P H LOCK, LEVEL CAL indicators lit 74.600 74.599 851 to 74.600 149
75.400 75.399 849 to 75.400 151
4.3 Total Performance Test 108.000 107.999 784 to 108.000 216
117.950 117.949 764 to 117.950 236
4.3.1 Introduction 329.150 329.149 342 to 329.150 658
335.000 334.999 330 to 335.000 670
The total performance test procedures contained in 118.000 117.999 774 to 118.000 236
this paragraph may be performed to isolate and/or 151.975 151.974 698 to 151.975 302
correct a malfunction before performing the calibra-
4.3.5 RF Output Frequency Response
tion verification procedures. When an incorrect result
is obtained during the performance of the test a . Connect rf pourer meter (2.4) to TI R F OUT connec-
procedures, the applicable alignment/adjustment tor.
procedures contained in paragraph 8 should be per- b. Set TI rf output level to -6 dB mW without
formed before starting t h e troubleshooting modulation (no TONE SELECT keys lit) a t fre-
procedures. If the alignment/adjustment procedures quencies of 74.60, 75.00, 75.40, 108.00, 110.00,
do not correct t h e malfunction, refer to 111.95, 114.00, 116.00, 117.95, 329.15, 331.10,
troubleshooting procedures to isolate the malfunc- 333.50, and 335.00 MHz. Power meter must in-
tion. The steps contained in the troubleshooting dicate -6 dB m W witHin h0.5 dB a t each frequen-
procedures correspond to the steps in the total perfor- cy. Modulation must be removed after each change
mance test procedures. in frequency.
c. Disconnect power meter from TI.
The number in parentheses following the support
(test) equipment is the item number of equipment a s 4.3.6 RF O u t p u t Attenuator Accuracy
listed in table 1 which specifically identifies the
equipment. a. Set TI frequency to 108.000 MHz without modula-
tion (no TONE SELECT keys lit).
4.3.2 Initial Turn-On b. Set TI rf output level to levels listed below. The
change in power meter indication from the -6 dB
Perform initial turn-on procedure described in mW level (measured in paragraph 4.3.5, step b)
paragraph 4.2.1. If malfunction occurs, troubleshoot must be within limits given.
a s described in figure 21.
C. Connect test equipment to TI a s shown in figure 6 g. Set spectrum analyzer scan width to zero and set
without rf amplifiers. video filter to 10 kHz, and adjust fine frequency
control for maximum vertical trace deflection. Us-
d. Make following instrument control settings. ing log reference level attenuators, set reference
level for center screen display.
1. TI h. Set TI rf output level and step attenuator to the
following settings and observe spectrum analyzer
CONTROL SETTING display. Record change from reference in + or -
values.
FREQUENCY 108.00 MHz
R F LEVEL 20 dB m W TI R F OUTPUT STEP ATTEN
TONE SELECT No keys lit LEVEL (2.5) SETTING
1 CONTROL SETTING
-30
-40
1 Attenuation 40 dB
3. Spectrum Analyzer (2.1) i. Determine if TI attenuator is within following
tolerances using following equation:
CONTROL SETTING
TI attenuator change = A +B-C
Frequency 108.00 MHz
Tuning stabilizer Off Where:
Bandwidth 10 kHz A = Recorded TI rf output level change from -6 to
Scan width 0.5 MHz -20 dB m W a s recorded in step b.
Input attenuation 0 dB
Scan time 10 ms/division B = Change in step attenuator from 40-dB
Log reference level -60 dB mW reference setting (derived from special
Vertical sensitivity 2 dB/division calibration d a t a on step attenuator).
Video filter Off C = Recorder display difference from step h.
Scan mode Internal
Scan trigger Automatic For example, if the recorded TI rf output level
Display controls As required change from -6 to -20 dB mW is -13.9 dB mW, the
change in step attenuator from the 40-dB reference
e. Adjust spectrum analyzer frequency control and setting is -10.3 dB, and the recorded display
log reference level attenuators for center screen difference is -0.5, the TI attenuator change is
display of 108.000-MHz signal. calculated a s follours:
f. Set spectrum analyzer scan width to 200 kHz, tun-
ing stabilizer to on, and adjust frequency control TI attenuator change = -13.9 + (-10.3) - (-0.5)
for center screen display. TI attenuator change = -23.7 dB
3 dB
TI -- ATTEN ---- ATTEN ATTEN - -- - --- - ANALYZER
(2.131 (2.5) (2.141
I
Scans by ArtekMedia © 2008 maintenance 523-0 768885
Rc~r~isr~d
1 October 1978
maintenance 523-0768885 Scans by ArtekMedia © 2008
Results: harmonics displayed are below the 108- being used a s a local oscillator i s n o t known
MHz fundamental a s follows: or specified, replace the TI with a signal
generator identical to the local oscillator and
measure their combined output noise a t the
2nd harmonic (216 MHz) >30 dBc
>30 dBc s t a t e d t e s t frequencies. F o r t h e signal
3rd harmonic (324 MHz)
>30 dBc generator to be acceptable for use, the
4th harmonic (432 MHz)
measured sideband noise of the two signal
5th harmonic (540 MHz) >30 dRc
generators must be 10 dB less than the TI
noise specification. Measurements on the H P
c. Make the following instrument setting changes. 8640B indicate t h a t it is an acceptable signal
generator for use a s a local oscillator.
4.3.8.1 M a r k e r Beacon
FREQUENCY 329.150 MHz
TONE SELECT No keys lit a. Make the following instrument settings.
SPECTRUM
ANALYZER (2.1) FREQUENCY 75.000 MHz
R F LEVEL -10 d B m W
Frequency 0 MHz TONE SELECT No keys lit
Scan width mode 0-1250 MHz AF Off
Scan time As required (display
uncalibrated indicator SIGNAL
is off)
GENERATOR (2.11)
Log reference As required to set 329.15-
level display MHz signal to top line
adjust of graticule Frequency 85.020
Output level +7 dB mW
Results: harmonics displayed are below the AM Off
329.15-MHz fundamental a s follows: FM Off
Phase lock On
2nd harmonic (658 MHz)
3rd harmonic (987 MHz) STEP
ATTENUATOR (2.5)
d. Disconnect spectrum analyzer from TI.
Attenuation 60 dB
4.3.8 Broadband .Yoise (SSB) and Close-In
Spurious Signals
SPECTRUM
I Note I ANALYZER (2.1)
b. Connect test equipment a s shown in figure 7. Results: a n y spurious signal present is greater
c. Adjust spectrum analyzer frequency control than 80 d B below 75-MHz carrier.
and log reference level attenuators for center
screen display of 10.020-MHz if frequency.
d. Make the following spectrum analyzer control
settings. a . Make the following instrument settings.
CONTROL SETTING
--
R SPECTRUM
NOTCH RF A M P L
S T E P ATTEN
MIXER
(2.20) '
L
FILTER
(2.21)
(2.5) (2.10)
ANALYZER
(2. I )
i S I G GEN
(2.11)
FREQUENCY
COUNTER
(2.7)
Tuning stabilizer On TI
-
Bandwidth 0.3 kHz
Scan width 20 kHz/division FREQUENCY 335.000 MHz
Scan time 10 seconds/division R F LEVEL -10 dB mW
Video filter 10 Hz TONE SELECT No keys lit
AF Off
18 1 October 1.078
R<~r!is~o'
Scans by ArtekMedia © 2008 maintenance 523-0768885
SPECTRUM e. P r e s s a n d hold T I / F A S T D E C R k e y . T I
ANALYZER (2.1) FREQUENCY indication must decrease. Hold
FAST DECR key until display counter frequency
Log reference level -50 dB m W indicates 34 850.0 kHz. Release key. Counter must
Log reference level 10 dB log indicate a frequency between 334.850 000 and
mode 334.852 500 MHz.
Video filter Off f . P r e s s a n d hold T I SLOW INCR key. T I
Scan mode Internal FREQUENCY indication must increase. Release
Scan trigger Automatic key.
g. P r e s s a n d hold T I F A S T INCR k e y . T I
b. Adjust spectrum analyzer frequency control and FREQUENCY indication must increase. Hold
log reference level attenuators for center screen FAST INCR key until display counter frequency
display of 10.050-MHz if frequency. indicates 35 050.0 kHz. Release key. Counter must
c. Make the following spectrum analyzer control indicate a frequency between 335.050 000 and
settings. 335.052 500 MHz.
h. Disconnect counter from TI.
SETTING
4.3.10 Audio Tone Frequency Accuracv
I
Tuning stabilizer On
Bandwidth 1 kHz I Note 1
Scan width 50 kHz/division
Video filter 100 Hz Since all of the audio tones are derived from
Scan time 5 seconds/division the same reference crystal, only the frequen-
Scan mode Manual cy accuracy of one tone is measured.
d. Adjust spectrum analyzer manual scan, frequency a. Connect frequency counter (2.7) to TI AUX output
tune, and reference log level attenuators for full- on rear panel.
screen amplitude display one division to right of b. Set TI output frequency to 108.00 MHz and
center screen. measure period of 30-Hz reference signal. Fre-
e. Set signal generator (2.11) frequency to 345.000 quency counter must indicate between 33 331.67
MHz. and 33 335.00 ps (30.0015 and 29.9985 Hz).
f. Set step attenuator (2.5) to 0 dB. Set spectrum c. Disconnect frequency counter from TI.
analyzer scan mode to single and press start sweep
switch. The reference level (top horizontal 4.3.1 1 .-iudio Tone Distortion
graticule) is now -60 dB mW. Check spurious a. Connect distortion analyzer (2.6) to TI AUX output
signals a t 335 MHz f 25 kHz, f 5 0 kHz, f75 kHz, on rear panel. Set TI to 108.00 MHz and measure
and &I00 kHz. Results: spurious signals are distortion. Results: distortion is less than 0.25%.
greater than 80 dB below 335-MHz carrier. b. Connect distortion analyzer (2.6) to TI COMP out-
g. Set spectrum analyzer scan width to 100 kHz/divi- put on rear panel. Set TI for output frequencies,
sion and scan time to 10 seconds/division. Results: tones, and percent modulation shown below, and
any spurious signal present is greater than 80 dB measure distortion.
below 335-MHz carrier.
h. Disconnect test equipment from TI. RF MAX
FREQ R DISTOR-
4.3.9 RF Frequency Vernier (MHz) TONE MOD TION (5%)
CONTROL SETTING
( Note 1
Tuning Auto
There are two methods available for measur- High pass (Hz) 10
ing the AM modulation of the TI to the re- Low pass/ Out (low pass (kHz))/l5
quired accuracy. The first method, begin- De-emphasis
ning a t 4.3.12.1, uses a modulation meter Peak PK-PK
(2.17) a n d distortion analyzer (2.6) t o 2
measure both the amplitude modulation and Range 100
rf distortion. Function %, AM
Level control Fully ccw (in detent)
In case the modulation meter is unavailable,
an alternate procedure using a spectrum c. Modulation meter must indicate between 29.3 and
analyzer (2.1) is provided. The alternate 30.7'Z modulation.
procedure cannot, however, verify rf distor- d. Measure distortion of demodulated rf signal with
tion levels. T h i s a l t e r n a t e p r o c e d u r e distortion analyzer. Measured distortion must be
preliminary operation begins a t 4.3.12.2. <1.0f7,.
MODULATION DISTORTION
TI METER (2.17) ANALYZER
-R F I N AUDIO OUTp- (2.6)
e. Repeat steps c and d selecting TI rf frequencies, tion levels and distortions measured must meet
modulating tones, and AM levels listed below. Note limits specified.
filter settings on the modulation meter. Modula- f. Connect equipment a s shown in figure 9.
MODULATION
TI
METER (2.17)
RF RF AUDIO
DEMOD OUT IN OUT
1
I I
VOLTMETER (2.3)
OSCl LLOSCOPE
(2.8)
I I DISTORTION
ANALYZER (2.6)
- - - SPECTRUM
10 dB STEP 10 dB ANALYZER
S I G GEN (2.1) 0 1FF
(2.11)
ATTEN
( 2 . 1 2 )
ATTEN
(2.5)
-ATTEN
(2.12)- VERT OUT VOLTVCTCF!
(2.3)
CONTROL SETTING
Attenuation 20 dB
CONTROL SETTING
The modulation level output for the 1020-Hz
Function Dc volts ident tone is always 3096, regardless of the
Range 2 TI modulation display indication.
Scans by ArtekMedia © 2008 maintenance 523-076888.5
TI 10 dB SPECTRUM
RF
ATTEN ANALYZER VERT
DEMOD OUT (2.12) (2.1)
OUT
8YT
- - - - - - - --
1
D V M (2.2)
VOLTMETER (2.3)
R c ~ i s e d1 October 1.Y78 25
Scans by ArtekMedia © 2008
maintenance 523-0768885
I g. Make the following equipment settings. limits. Results: calculated voltage recorded in
step m must be between these limits.
o. Disconnect dvm from TI.
OSCILLOSCOPE (2.8)
The TI radial specification for the composite
Coupling Dc VOR signal ( f 0.01" before modulation and
Remainder of As required f0.05" after demodulation of the rf signalj is
controls referenced to the accuracy of the VOR bear-
ing standard used to calibrate the signal.
h. Obtain oscilloscope trace and note level difference This specification means the TI will change
between amplitude of the two waveform peaks a s n o t m o r e t h a n t h i s specified a m o u n t
shown in figures 13 and 14. between calibration intervals with respect to
the standard used. The TI absolute radial ac-
curacy, therefore, is f 0 . 0 1 " (audio) o r
*0.05" (demodulated rf audio) plus the ac-
curacy of the VOR bearing standard used for
calibration. The TI was set a t the factory
during manufacture for 0.00" measured
radial error a t the TI COMP output and d. TI RDL/DDM/MOD radial indication must be
verified to measure less than f0.05" error a t within the accuracy of the VOR bearing standard
the DEMOD output using a Collins 4788-3 multiplied by 2, plus f0.01".
Zifor. This VOR standard is specified to be e. Connect VOR bearing standard to TI DEMCID out-
within f0.01" a t VOR zero and to f0.02" a t put on rear panel.
all other radials referenced to a standard f. Obtain a heading of 000.00" on VOR bearing stan-
Collins 478A-3 Zifor, which is maintained by dard by stepping TI reading in + or - 0.01" in-
Collins Avionics Metrology Department a s crements.
an absolute VOR standard. g. TI RDL/DDM/MOD radial indication must be
within the accuracy of the VOR bearing standard
A problem occurs in trying to verify the ac- multiplied by 2, plus f0.05".
curacy of the TI a t the end of the TI cycle
rate period, due to the accuracy of available I Note (
VOR bearing standards. The following situa-
tion exists. Perform steps h through s only if VOR bear-
ing 0" adjustment is required. This adjust-
1. If the same VOR standard (same model ment is a t the discretion of the user.
and serial number) is used, the TI may be
expected to agree with the standard h. Press TI POWER switch and release to O F F posi-
w i t h i n f0.01" ( a u d i o ) a n d f0.05" tion.
(demodulated rf audio). i. Remove two screws from each side and six screws
2. If a like model VOR standard is used but a from bottom of signal generator t h a t secure dust
different serial number, the TI can only cover, and slide dust cover off of signal generator.
be expected to agree within the accuracy Refer to figure 1 in the maintenance section for
of the standard times 2, plus 0.01" (audio) dust cover screw locations.
or 0.05" (demodulated rf audio). j. Press TI POWER switch to ON position.
3. If a different model of VOR standard is k. Connect VOR bearing standard to TI COMP output
used, the TI can only be expected to agree on rear panel, and set TI rf frequency to 108.00
within the sum of the tolerances of the MHz (VOR mode).
two standards, plus 0.01" (audio) or 0.05" 1. Obtain a heading of 000.00" on VOR bearing stan-
(demodulated rf audio). dard by adjusting TI VOR zero adjustment poten-
tiometer A2A2R8 (identified a s R8 on left side of
This procedure was written assuming the modulator bracket).
same model of standard would be used to m. Connect VOR bearing standard to TI DEMOD
verify the TI t h a t was used for initial output on rear panel.
calibration (Collins 478A-3 Zifor); therefore, n. Obtain a heading of 000.00" on VOR bearing stan-
the above situation 2 applies. If this is not dard by stepping TI bearing in + or - 0.01" in-
the case, appropriate tolerances may be sub- crements.
stituted in the procedure. After verification o. TI RDL/DDM/MOD radial indication must in-
of the incoming TI status, the procedure dicate 0.00 f0.05".
gives instructions to set the TI for 0.00" p. Press TI POWER switch and release to OFF posi-
measured VOR error a t the discretion of the tion.
user. The TI accuracy after calibrating will q. Disconnect VOR bearing standard from TI
then be t h a t of the user's VOR bearing stan- r. Install signal generator dust cover and secure with
dard. two screws on each side and six screws on the bot-
tom.
s. Press TI POWER switch to ON position.
Oscilloscope (2.8)
H P 5360A COMPUTING COUNTER (2.17)
,
For TI 9960-Hz signal to be deviating f 480 Hz c. Depress H P 5375A MANUAL pushbutton.
f 5 S o r better, width of jitter must be between d. Clear registers a , b, c, z, and y by pressing each
46.1 and 50.9 ps. of five REGISTER EXCHANGE keys followed
e. Disconnect scope from TI. by CLEAR x.
Rc ~ i s e d1 October 1978
Scans by ArtekMedia © 2008
maintenance 523-0768885
X = Continuity; O = Open
R e f e r e n c e pin 11 a s common f o r frequencies
l l e f e r e n c e pin 9 a s common f o r mode s e l e c t s
N O T E : F U N C T I O N SELECTOR
/ SWITCH M U S T BE SET T O '7'
HP
GENERAL
HP 98210Af
STRING - A D V PROGRAMMING R O M
TO S6A
IEEE 488
CONNECTOR
15 V R T N
+9 V D C
9 V RTN
+24 V DC
24 V R T N
+5 V DC
5 V RTN
I/O WR
I/O R D
A7
NOTES:
@ J1, CPN 371-01 18-000, M A T E S W I T H W I R I N G HARNESS CONNECTOR P5.
NOTES:
I
store/recall assembly -49, and IEEE-488/1978 110
The module level troubleshooting procedures are
card is accomplished by installing the cards on an ex- presented in flow-chart format. Refer to figure 20 for
tender card (2.28, table 1).
an explanation of the flow-chart procedure.
Minimum performance test and total performance
5.2 Preliminary Procedure test procedure troubleshooting is provided in figures
21 and 22 respectively. Whenever a test or calibration
verification procedures fails, enter the
a. Remove eight screws and remove module bracket. troubleshooting procedure a t the corresponding test
Refer to figure 44. number shown in the flow diagram. The flow charts
b. Loosen four captive fasteners that secure con- assume that all preceding tests were successfully
troller/audio assembly A2 to chassis. Lift A2 completed. Since the troubleshooting flow diagrams
straight up and align two bottom mounting holes contain the test procedure numbers from the
on A2 with two top captive fasteners on chassis, minimum and total performance test procedures, the
and tighten two captive fasteners to secure A2 in following list provides a cross-reference between the
the extended position. calibration verification procedure test numbers and
c. Set TI POWER switch to on. If initial turn-on, wait the minimum and total performance test procedure
30 minutes for TI warmup. numbers.
CALIBRATION MINIMUM OR
VERIFICATION TOTAL PERFORMANCE
STEP NUMBER TEST DESCRIPTION TEST STEP NUMBER
Turn-on operation
Self-test operation
Frequency range, marker beacon
Frequency range, VOR
Frequency range, localizer
Frequency range, glideslope
Frequency range, communication
Frequency accuracy
Frequency vernier
Rf harmonics
Rf output level, functional operation
Frequency response
Output attenuator accuracy
Modulation tones, frequency accuracy
Audio distortion
VOR tones, functional operation
VOR tones, 9960-FM deviation, function verification
Radial accuracy
Localizer DDM, functional operation
Glideslope DDM, functional operation
Glideslope DDM, on-course accuracy
Glideslope DDM, off-course accuracy
AM modulation
Broadband noise (SSB) and close-in spurious
signals
ILS phase (90/150-Hz composite signal)
9960-FM deviation
-DOUBLE L l N E STEP
INSTRUCTION:
PROVIDES A SECOND STEP
FOR REPAIR IN CASE THE
1ST METHOD FAILS. A L -
WAYS D O STEP 1 FIRST.
I F STEP 1 REPAIRS THE
F A U L T YOU W I L L NOT
RETURN TO THlS INSTRUC-
TION A G A I N . IF YOU RE-
TURN TO THIS INSTRUCTION
THE 2ND TIME D O STEP 2.
STEP NUMBER IS INDICATED
BY NUMBER ABOVE THE
ARROW GOING TO THE
TEST PROCEDURE
INSTRUCTION.
CHECK FUSE
P A R A 4.2.
SH 5
PARTIALLY
SH 2
RO L D I S P L A Y
READING
SHOULD BE
000.00
YES REPLACE
DEFECTIVE
SWITCH
NO
REPLACE
A1
SH 3
REPLACE
DEFECTIVE
SWITCH.
I
1 I REPLACE I \ 1
REMOVE POWER
REMOVE A8, A9, N0
REPLACE A 9
AND A10
REAPPLY POWER
REINSTALL A8
SH 10
YES
NO
REPLACE A 8
6 sti 1
REINSTALL A9
SW IS DEPRESSED R D L OR RF
A N D COUNT I N LEVEL DISPLAY
R D L DISPI-AY /
/
YES REPLACE
A2A1
1
REPLACE
A4
-
2
REPLACE
A3A3
Mitcttt~11 Pt,t-fi~rttctr
tlce Test. Trou bleshooti~cgProcer1uw.s
Figurv 21 (Shvet 8)
EXERCISE A L L
FREQUENCY
/
/
/ /
/
NO
, RKDEE PYF LBEACOCTAEIRVDE
'
SWITCH
YES
REPLACE
A2A3
- REPLACE
A1 b
SH4
NO
REPLACE
A4
Mit~itti~rtt~
Per:ti)rt~~trtccr
Test. Trol~blrshootinyPruced~rre.s
Fiqtrre 21 (Shrc--f9)
R E M O V E POWER
REMOVE P5
FROM A3.
YES REPLACE
AlA1
-
REAPPLY POWER.
RECONNECT
P6 TO A l .
R E M O V E POWER.
RECONNECT P5
TO A 3 . R E M O V E
A2A3.
REAPPLY POWER
YES
REPLACE
A2A3
REMOVE POWER.
R E I N S T A L L A2A3.
REMOVE P6
FROM A l .
REAPPLY POWER
AM O N I T O R J1
SCOPE. SET V E R T
SENS TO 2 V I D I V
AND HORIZ.
PERIOD TO
5 ms/D I V .
Tottrl P~rfijr),ttriccc,
Test. Troll b/e.shoofir~y
Proced~crrs
Ft{j~tre21 (Sl~eet1)
R~l?i.s~rl
1 October 1978
maintenance 523-0768885 Scans by ArtekMedia © 2008
Totc~lPer:firrrrc~~lce
Test, Troubleshooting Procedures
Figure 22 (Sheet 3)
1, REPLACE
A2A2
-
YES
N0
AUDIO
YES YES
REPLACE
'u REPLACE
iJ 6 TEST
4.3.1 1
YES
A
REPLACE
2A3.
b
REPLACE
A2A2 b
Totctl Pf,t:fi,t.tt~tr
I I ~ . C , Test. T ~ ~ o ~ t h l f ~tirr~l
s l i oProcrrllcws
o
Fiqct re 22 (Shotlt 8 )
REPLACE A2A2
YES
2
REPLACE A 2 A 3
Before replacing any subassemblies in the TI, per- 5.4 Functional Level Troubleshooting
form the following:
The troubleshooting procedures given in the following
paragraphs provide fault isolation to the functional
a. Ensure all wiring harness connectors a r e securely level on a circuit card,
mated with the modules.
b. Verify supply voltages a r e present on suspected The following criteria must be used when performing
failed modules; no supply voltage may indicate these troubleshooting procedures unless specified
fault in wiring harness. otherwise.
Unless a specific instruction is given in t h e a. Logic 1 voltages must be between +2.4 and +5.5 V
troubleshooting procedure after replacing a sub- dc.
assembly, the following alignment procedures b. Logic 0 voltages must be less than +0.4 V dc.
(paragraph 8) must be performed before restarting c. Clock and data waveform frequencies and periods
the troubleshooting procedures. must be within f 10 percent of the stated value.
d. All measurements are made with respect to
ASSEMBLY ALIGNMENT PARAGRAPHS
chassis ground.
REPLACED TO BE PERFORMED
MALFUNCTION PROCEDURE
TI d o e s not respond t o a row o r column of Row: Check b u f f e r s U66 and U67 and pullup r e s i s t o r s
k e y s a s shown in key m a t r i x o n s c h e m a t i c on inputs.
diagram.
Column: Check U62 and U64.
One key l a m p d o e s not light. Check l a m p and latch, and i n v e r t e r feeding lamp.
1300 H z , 3000 H z , 9960 H z , and 150 H z key Check U58, U59, and U47.
l a m p s d o not light.
~ / oMOD, RDL/DDM, VAR FREQ, STO, Check U60, U61, and U47.
R C L , and f key l a m p s do not light.
R F FREQ and AF key l a m p s d o not light. Check U65, U68, and U47.
DSI t h r u DS5 blank when rf i s shut off. Check U55C and U32E.
DS12 t h r u DS14 do not display O F F when r f i s Check U27A, U26, U55A, U21D, and i n v e r t e r s connected
shut off. t o display input lines.
NOTE
1 W IS A GROUND P A D
F I Y ItJPI/)IC,/
I .4.s.s<,rtt h/!/ '41, c!~)
F ~ ! / I I24 / / S / I ~ , C
rcj
F R O N T PANEL A S S Y A l , R E A R V I E W
NOTE :
Scans by ArtekMedia © 2008 maintenance 523-0768885
1 a . Connect d v m (2.2) t o V R l cathode. a , +5.3 t o +5.9 V dc. a. Check VR1, LA, and a s s o -
ciated c i r c u i t r y .
b. Waveform s i m i l a r to f i g u r e
27.
a. Check A2A3.
b. Check U22.
II )I
d. Connect scope t o U10-10. d. Waveform s i m i l a r to f i g u r e d. Check U10.
27.
i. R e m o v e p o w e r f r o m TI. Disconnect
h. +8.10 t o +8.40 V dc. h. Check U9 and f i l t e r s R59,
R63, C41, C42.
1 1 I 1I I
Set TI t o 75.000-MHz, 400-Hz tone.
3
I 1 a. Connect s c o p e t o Ull-6.
b. 400-Hz waveform.
a . Check U11.
Ttr Ole, 3. A ictr log Bocrrrl A2A2, Trou blrsl/oofiir!! Procrdu res (Con tl.
c . Connect scope t o COMP connector c. 30-Hz waveform. c . Check U2A, R8, R9, and
o n r e a r panel of TI. associated circuitry,
Set TI t o 110.10-MHz, 1020-Hz tone 1020-Hz waveform. Check U3A, R5, and f i l t e r s *
only. R39, R38, C15.
NOTE:
1 II S A GROUND PAD
maintenance 523-0768885 Scans by ArtekMedia © 2008
AM2 Wnvefi)rms
Figure 27
68
Revised 1 October 1978
Scans by ArtekMedia © 2008 maintenance 523-0768885
NOTE :
1. H IS A GROUND PAD.
b. Set TI to the modes given in table 4 and verify logic t o check or replace. Before replacing any components
levels a t the given test points. on the assembly, check assembly and assembly
c. Connect oscilloscope to test points shown in figure connectors for damage.
30 and verify waveforms.
d . P e r f o r m p a r a g r a p h 8.3, 8.5, 8.6, a n d 8.7
alignments.
Allow a 15-minute warmup period for A3Al
and test equipment setup.
Tuble 4. A M 3 Test Poirrts.
I I I 5.4.3.2 D e m o d u l a t o r l A L C A s s e m b l y A3A2
Troubleshooting
a. Set TI POWER switch to off.
b. Remove cover from A3. Refer to figure 46.
c. Remove four screws that secure A3A3 to A3A2 and
carefully fold back card A3A3, leaving flat cable
attached. This provides access to A3A2 test points.
d. Press TI POWER switch to on.
e. Perform troubleshooting procedures contained in
table 6. Refer to figure 32 for component locations.
If a malfunction occurs, the I F INDICATION IS
ABNORMAL column gives the components to
check or replace. Before replacing any components
on the circuit board, check printed circuit board
I * 1-MHz square wave I
and circuit board connector for damage.
f. After completion of troubleshooting, carefully fold
back A3A3 on A3A2 and secure with four screws.
5.4.3 RF M o d u l a t o r .-lssembly A3
Troubleshooting
If A3A3 troubleshooting is required, proceed
t o p a r a g r a p h 5.4.3.3. If A 3 A 3
I Note 1 troubleshooting is not required, perform
step g.
Always troubleshoot demodulator/ALC
board A3A2 before troubleshooting rf strip-
line assembly A3A1. g. Install cover on A3.
5.4.3.1 RF S t r i p - L i n e A s s e m b l y A3Al
5.4.3.3 (Jounter-110 Board A3A3
Troubleshooting
Troubleshooting
In order to properly troubleshoot strip-line assembly
A3A1, a special test fixture must be fabricated. a . Set TI POWER switch to off.
Information necessary for fabrication is contained b. Remove cover from A3 (figure 46) to provide access
in figure 31A; troubleshooting is accomplished a s to A3A3 test points. Refer to figure 33 for compo-
described below. 'nent locations.
c. Set TI POWER switch to on.
a. Remove and disassemble modulator assembly A3 d. Perform troubleshooting procedures contained in
as described in paragraph 6.1.6. t a b l e 7. If m a l f u n c t i o n occurs, t h e I F
b. Connect' A3A1, A3A2, and test equipment as MALFUNCTION IS ABNORMAL column gives
shown in figure 31B. Set S1 through S4 to 0 on A3A1 the components to check or replace. Before replac-
test fixture. ing any components on the circuit board, check
c. Perform troubleshooting procedures contained in printed circuit board and circuit board connectors
table 5. Refer to figures 31 and 32 for component for damage.
locations. If a malfunction occurs, the I F INDICA- e. After completion of troubleshooting, s e t TI
TION IS ABNORMAL column gives the components POWER switch to off and install A3 cover.
Rct~is~rl
15 October 1.980 71
maintenance 523-0 768885 Scans by ArtekMedia © 2008
U2-1
( I R IGGER l
U26-5
1126 7
U26-9
i;:?C'-5
(TRIGGER)
1120-5C
if 20-$'
ti20.7
(120-G
1,61 l r
UG'
Revised 1 October 19 78
Scans by ArtekMedia © 2008 maintenance 523-0768885
U87-5 -
U87-7 -
U87-9 -
U87-11 -
STD L O C , 119 10 b l t i ~
NOTES:
CONTROL SETTING
Tuning AUTO
High p a s s 1 0 Hz
Low p a s s 1 5 kHz
Peak ~ k - ~ k / 2
Range 100
Function % AM
I I AUTO
(Cont)
R ~ c t i s ~15
d October I!l8O 81
maintenance 523-0768885 Scans by ArtekMedia © 2008
'Con tl
2 (Cant) piTl
C29 may not be
installed if C28
travel does not
exceed one-half
CW.
/-Yq
If C28 is adjusted,
repeat step 2.
82 R<~r~i.sr~rl
October 1,980
1 .i
Scans by ArtekMedia © 2008 maintenance 523-0768885
Set rf signal generator to 332 MHz at +12 +0.1 dB mW. Set test fixture
switches a s follows:
CONTROL SETTING
Tuning AUTO
High pass 1 0 Hz
Low pass 15 kHz
Peak ~k-~k/2
Range 100
Function 9% AM
Level AUTO
,
c. Set rf signal generator to 332 MHz at +12 i 0 . 1 dB mW. Set A3A2R6 for
-4 i 0 . 1 dB mW at A3AlJ3.
q. Set modulation meter LOW PASS to 120 kHz. Disconnect power meter
and connect modulation meter to A3AlJ3.
DESIRED RESULTS
a. Connect power m e t e r t o A 3 A l J 1 .
Tl1111vli I I ~ I I I I ~ (tor/ALC
J I I I ( I Boc~rtlA . M 2 Troll blc~sliootc Pt.occ,d~rrr.\
I
S e t T I to 108.00 M H z and p r e s s TI AF
key. E n s u r e AF key lamp i s lit.
b. Connect dvni t o U15-6. b. -4.75 t o -5.25 V dc. b. Check U15 and associated
circuits.
P r e s s TI AF key. E n s u r e A F key
c . +9.3 t o +11.3 V dc. c . Check U18.
I
l a m p i s off.
GROUND * -
COMPOSITE H
MOD IN
1/0 A
ml
LOC
NOTES:
@
@
DMENSIONS ARE IN MlLLlMETRES [INCHES].
OSCl LLATOR
HP 200CD
(2.18)
1
I
POWER I ANALYZER
SUPPLY +15 I HP 331A
1 (2.36) I
HP 62058 I
--
1
-
J1
A 3 A l TEST
r
PI J2
MOD METER
J3 A3A2 BOONTON 82AD
FIXTURE DEMOL CARD (2.1 7)
-
J4 (2.38) \
LJ2 J3
-
- PI
POWER % 1
SUPPLY +24
2 12.37)
HP 6289A
J2
RF SIGNAL n A3A1 POWER METER
GENERATOR STRIPLINE HP 435Al
(2.1 1 ) HP 86408 ASSEMBLY 8482A (2.41
NOTES :
I. IS A GROUND PAD.
2 C53 THRU C56 MOUNTED ON REARSIDE O F BOARD.
3. U14, C49 THRU C51, R 5 , AND R 7 4 THRU R 7 7 ARE ON THE - 0 0 2 STATUS ONLY
Scans by ArtekMedia © 2008 maintenance 523-0768885
NOTES :
I. IS A GROUND PAD.
2. R13, C15, AND J2 ARE MOUNTED ON BACKSIDE OF BOARD
U13-12
U13-13
U13-14
U13-15
Connect s c o p e t o t h e following t e s t
points.
Set TI to f r e q u e n c i e s listed in
DESIRED RESULTS column and m e a - FREQUENCY (MHz)
s u r e logic l e v e l s with dvm a t t h e
following t e s t points.
Check U17
and U10
Check U14
and U10
Check U11
and U10
and U10
n.
0.
P.
1. Logic 0.
2. Logic 0.
3. Logic 0.
4 . Logic 0.
1. Logic 1.
2. Logic 1.
3. Logic 1.
'3.. } k;;:; U2.115, and
4. Logic 1.
b. L E V E L CAL indicator is
a. Check U22D.
b. Check U 2 2 F .
I
lit.
c. Frequency display is
correct,
c. Display digit:
1. 1 0 0 MHz - Check U 1 9 E ,
I
U 1 9 F , and U16.
2. 1 0 M H z - Check U25A
t h r u D and U24.
94 R~t~isecl
1.5 October I Y X O
Scans by ArtekMedia © 2008 maintenance 523-0768885
11 3. 1 MHz - C h e c k U22A
(Con€) t h r u D a n d U21.
4. 1 0 0 kHz - C h e c k U28A
t h r u D a n d U27.
5. 1 0 k H z - C h e c k U19A
- t h r u D a n d U18.
6. 1 kHz - C h e c k U31A
t h r u D a n d U30.
12 P r e s s A F key f o r A F operation. 100-Hz d i g i t is d i s p l a y e d C h e c k U25E, U 2 5 F , U31E,
correctly. U 3 1 F , U36A, U36D, U33,
a n d U35.
2. +5-V d c Connect dvm t o A4AlAlC52(+) +5.0 *0.1 V d c . Check A4A 1A 1U20 and Q12.
supply
3. TCXO A4A4 Connect oscilloscope (scope) 3.2-MHz s q u a r e wave. Check A4A4. P e r f o r m p a r a -
(2.8) to A4AlA 1U7-14. g r a p h 8.8 alignment.
1 2 . Logic 1
3 . Logic 0
4 . Logic 0
5. Logic 1
6. Logic 1
2 . Logic 1
3 . Logic 1
4 . Logic 0
5 . Logic 0
6. Logic 0
2 . Logic 1
3. Logic 0
4 . Logic 1
5 . Logic 0
6. Logic 0
Rct~isr~d
1:; October 1980 97
maintenance 523-0768885 Scans by ArtekMedia © 2008
Table 9 provides the troubleshooting procedures for The IF INDICATION IS ABNORMAL column in
power supply assembly A5. The table is presented in table 9 gives t h e components to check o r replace if a
the form of a malfunction checklist assuming the procedure fails. Before replacing any components on
power supply voltage checklist in figure 21 has failed. the module, check t h e printed circuit, wiring, and
Refer to figure 35 for component locations. module connectors for damage.
1. No voltage
present
I=-=
PROCEDURE
a. Check
b. Check A5F1.
A IS54 (POWER).
c . Check A5T1.
DESIRED RESU1,TS I F INDICATION
IS ABNORMAL
2. No +5 V d c a. Check A5AlF1.
5 . No +15 V'dc
6. No +9 V d c
Check A5A2U3.
FILTER /
REGULATOR- DIVIDER
BOARD ASSY A4A1
- TCXO ASSY
A4A4
PI-A
VCO ASSY
A4A3
RF AMPLIFIER
- A4A2
NOTE
I. .
IS A GROUND PAD
P2
RF OUTPUT
Q i- B
FILTER /
REGULATOR-DIVIDER \
BOARD ASSY A4A1
TCXO ASSY
A4A4
PI-AI -
VCO ASSY
A4A3
RF AMPLIFIER
A4A2
NOTE
I. .
IS A GROUND PAD
@ F2 AND F3 ONLY IN 4 7 9 s - 6 A OR
4 7 9 8 - 6 WITH SERVICE BULLETIN 1
5.4.6 Rentote Tune Assembly A8 U7; channels 1and 2 do not go to logic 1, check LT7-1
Troubleshooting and U7-13 for logic 0.
d. Connect oscilloscope to U3-11 and observe a
Table 10 provides the troubleshooting procedures for negative 0.5-ps pulse.
remote tune assembly A8. Before s t a r t i n g t h e e. Connect oscilloscope to U8-4 and observe a
procedure, remove the A8 from the TI a s described in negative 0.5-ps pulse.
paragraph 6.1.10. Install the extender card (2.283 and
mount the A8 on the extender to gain access to the
test points.
5.4.8 IEEE-48811978 Bus Interjace Board A10
Troubleshooting
1
Before replacing any components on the module, Before starting the procedure, remove the A10 board
check the printed circuit board and circuit board con- from the TI a s described in paragraph 6.1.12. Install
nector for damage. Refer to figure 36 for component the extender card (2.28) and mount A10 on the ex-
locations. tender to gain access to test points.
MALFUNCTION
I I DESIRED RESULTS
No f r e q u e n c y o r m o d e s e l e c t s C h e c k A8U1 a n d U2.
a t any frequency
Rcrti.sc~i11.7 October* 1 % ~
Scans by ArtekMedia © 2008
maintenance 523-0768885
t1 M 15us
t2M 1 . 5 m s
t3 M JITTER BETWEEN .2 A N D . 4 ms
f 4 M 14 ms
c. Observe a logic 1 pulse - on oscilloscope channel 1 a. Connect oscilloscope to UX-6 and observe a 2-MHz
followed by a logic 0, NMI, pulse on channel 2. In- srluare ival-e.
correct results: no pulse on channel 1, verify k). Connect the H P - 9 8 2 3 controller to t h e 4798 tiA
AlOSl switch positions described in t h e operation IEEE-188 connector a t r e a r of unit. Set controller
section; no pulse on channel 2, verify Ull-5 a t logic t o repeat t h e follo\ving sequence: LA,"@", CR, LF
1 level after power-up. where "LA" is t h e listen address of t h e signal
d. Verify input/output signals by connecting os- generator.
cilloscope channel 1 t o input a n d channel 2 to out- c. Observe U3-11 t o be a logic 0 when t h e con-
p u t of bus transceivers U13, U14, U15, U16. troller is inactive, and, to be changing states when
Observe a corresponding change on each channel t h e controller is executing t h e sequence in s t e p b.
for a n y control or d a t a signal. tl. 01,serve U9-8 to he a logic 1 (NMI) when the,
controller is inactive, and, to be changing states
5.4.8.2 IEEE-48811978 Bus Interface Board A10 when t h e controller is executing t h e sequence in
(CP,lr 601-2309-001) Troubleshooting s t e p b.
e. While t h e controller is executing step b, observe
Rrforc replacing a n y components on the module, all CPlJ data, address, a n d control lines to be
check t h c printed circuit board a n d circuit board changing states. Also observe all G B I P bus lines
connector for damage. Refer t o figure 39A for to be changing s t a t e s except IFC, REN, SRQ, and
component locations. EOI.
maintenance 523-0768885 Scans by ArtekMedia © 2008
NOTE :
NOTE :
3.3 V NOM
maintenance 523-0768885 Scans by ArtekMedia © 2008
/
/
/
CHECK A4A1 A1
) U12, U13, U14,
U15. U16. AND U17.
CONNECT RF
VOLTMETER (2.32)
AND DIVIDER (2.33)
TO A4A3-E7 RF
OUTPUT.
CHECK A4A1 A1
YES
SH. 1
A.s.sririhl!/ .4 i . Tro~tbl~~shooti,,!Isiootiii~
S!;,I t/ic~.si~c~r Proc.er1itr.r~~
Fi{jiire 41 (Sheet 2)
A 4 A l P 3 FROM CONNECT R F
A4FL5. CONNECT VOLTMETER TO
JUMPER FROM A4A2 Q1 -B
A4A3 E l VC+ TO
TXCO A4A4 +5 V
ON. SET T I TO
75.00 MHz. (FREQ
IND. M A Y NOT
AGREE WITH SEL
FREQ).
CONNECT R F
CONNECT RF VOLTMETER
VOLTMETER
(2.26) TO A4A3-E7
RF OUTPUT
CHECK A4A2
CIRCUITRY
CONNECT
CONNECT D I G I T A L OSCILLOSCOPE
VOLTMETER (2.2) (2.8) TO A 4 A l A 1
TO A 4 A 2 0 1 - B U19-16
4
NOMINAL A T
m
CHECK A 4 A 2
Q 1 . 0 2 AND
ASSOCIATED
ClRCU ITRY
S ! / Jtl~c,sizrr
I A s s e ~ hl!!
~ t ,A$. Troir hleshooti~igProcerln res
Fi~prre$1 (Sheet 3)
NOM
/
CHECK A 4 A l A 1
NOM
I
CHECK A 4 A l A 1
U12,U13,U14
U15, U16, AND U17
/
/
/
/
/
YES
SH 5
Scans by ArtekMedia © 2008 maintenance 523-0768885
REMOVE JUMPER
FROM A4A3 TO
CHECK A4A1 A1 0 4 . A4A4. RECONNECT
A T Q4-C A4A1 P3 TO
A4F L5.
I
FROM A4A3 TO
A4A4. RECONNECT
A4A1 P3 TO
A4F L5.
\
\
\
\ 6 SH. I
1 TO 108.00, 117.95,
329.15, AND 335.00
MHz, ,
1 /,I dBmW ON 329.1 5
AND 335.00 MHz.
OUTPUT
11 TO 13 REPLACE RFA
A4A2.
1 NO OUTPUT
Rrj~>isc~tl
1:; October I.fl80
maintenance 523-0768885 Scans by ArtekMedia © 2008
DISCONNECT
A4A1 P3 F R O M CHECK A 4 A 2 Q2
A4FL5. CONNECT AND
JUMPER F R O M p ASSOCIATED
A4A3 E l VC+ T O CIRCUITRY.
TCXO A 4 A 4 +5 V.
T U R N T I POWER CONNECT
ON. SET T I T O DIGITAL
75 MHz. ( F R E Q VOLTMETER (2.2)
IND MAY NOT T O A 4 A 2 Q3-C
AGREE W I T H SEL A N D BETWEEN
FREQ.). 03-E A N D 0 3 - 8 .
CONNECT RF
VOLTMETER
(2.26) TO
A4A3-E7 RF
CIRCUITRY.
OUTPUT.
CHECK A 4 A 2 Q3
CONNECT
DIGITAL DIGITAL
VOLTMETER (2.2) VOLTMETER (2.2)
T O A4A2 02-E, T O A 4 A 2 Q1 -C
A N D BETWEEN SH. 5 A N D BETWEEN
Q2-E A N D 0 2 - 8 . Q l -E A N D 0 1 -B.
CHECK A 4 A 2 CHECK A 4 A 2 0 1
AND
ASSOCIATED
CIRCUITRY. CIRCUITRY.
YES
SH. 5
CHECK A 4 A 2 Q1
CONNECT
OSCl LLOSCOPE
(2.8) T O A 4 A 1 A1
U19-16.
4. G r o u n d a n y tools ( i n c l u d i n g s o l d e r i n g
equipment) t h a t will contact the unit. Contact
6.1 Disassembly with the operator's hand provides a sufficient
ground for tools t h a t are otherwise electrically
6.1.1 General isolated.
5. When .MOS assemblies are removed from the
The disassembly procedures provide instructions for signal generator, they should be placed on the
removal and disassembly of the circuit card and conductive work surface or in conductive con-
module subassemblies in the signal generator. tainers. When a n MOS assembly is inserted in
o r removed from a container, t h e repair
6.1.2 Precautions a n d General Techniques operator should maintain contact with the con-
ductive portion of the container.
a. Always remove power cable from power source 6. When not being worked on, wrap disconnected
before removing or disassembling any circuit card circuit boards in aluminum foil or in plastic
or module assembly. bags t h a t have been coated or impregnated with
b. Mark or otherwise identify all disconnected wires conductive material.
and/or cables. 7. Do not handle MOS assemblies unnecessarily or
c. Note color coding, placement, and methods of in- remove from their packages until actually used
sulation installation (if used) on all wires, cables, or tested.
and/or components before unsoldering or remov-
ing. Failure to observe all of the MOS assembly
d. To prevent pin damage, always pull printed circuit precautions can cause permanent damage to the MOS
board connectors straight out until pins clear devices. This damage can cause the devices to fail im-
mating connector. mediately or a t a later date when exposed to an
e. To prevent damage to the circuit card pads due to adverse environment.
cable torque, unsolder coaxial cable connections
from circuit card assembly before removing cable I Note 1
clamp.
f. CPU assembly A2A1, analog board A2A2, TDM Refer to figure 2 in the description section
board A2A3, demod/ALC assembly A3A2, store for subassembly locations.
recall assembly A9, a n d IEEE-488/1975 I/O
assembly A10 contain MOS devices t h a t can be 6.1.3 Removal of (,'over
damaged by static voltages present in most repair
facilities. Although most MOS devices contain in- a. Stand signal generator on its handles and remove
ternal gate protection circuits, good practice dic- four screws from sides of cover (two screws on
tates careful handling of assemblies containing each side located toward front of signal generator).
MOS devices and the following precautions should b. Remove six screws securing cover to bottom of
be observed: signal generator (three on each side), and remove
1. Deenergize or disconnect all power, signal cover.
sources, and loads used with t h e signal
generator.
2. Place the signal generator on grounded conduc- 6.1.4 Rernoval a n d Disassembly of Front
tive work surface. Panel Assembly .41
3. Ground the repair operator through a conduc-
tive wrist strap or other device using a 1-MR
series resistor to protect the operator. No two
objects, including fingers, workbench, test Perform step a only if lens switch or light
equipment, and tools, shall simultaneously con- bulb must be replaced.
tact an MOS assembly unless the two objects
have first been placed in electrical contact with a. Remove front panel lens switch and light bulbs a s
one another. The electrical contact shall have a follows:
path resistance of 1 MR or less and shall have 1. Remove key cap with extraction tool (item 2.29
been maintained for a t least several seconds in table 1).
when the second object contacts the MOS 2. Remove light bulb behind lens switch by pulling
assembly. light bulb straight out with tweezers.
b. Remove four screws and four flat washers (two wires from S E L F TEST switch to keyboard
screws and two flat washers on each side of signal driver board AlA1.
generator located behind the bracket that is 2. Remove eight screws securing AlAl (one screw
behind handles). Refer to figure 42. in each of six corners, one in top middle of
c. Carefully pull front panel assembly A1 from board, and one in bottom middle of board).
chassis far enough to gain access to wiring harness 3. Lift AlAl with attached display board A1A2
mating connectors P6 and 54. Use care when from front panel assembly Al.
removing front panel assembly A1 so a s not to 4. Remove three screws securing A1A2 to AlA1.
damage the R F OUT coax connector.
d. Disconnect the wiring harness mating connectors
(printed circuit board connector P6 and white
translucent connector 54) from f r o n t panel Use extreme care when disconnecting A1A2
assembly Al. from AlAl so as not to break AlA2.
e. Disassemble front panel assembly A1 a s follows:
1. Lay front panel assembly A1 on its handles. 5. Carefully remove A1A2 from the mating con-
Refer to figure 43. Unsolder and tag the two nector pins on AlA1.
RF OUT COAX
ASSEMBLY
Re~~isecl
15 October 1980
Scans by ArtekMedia © 2008
maintenance 523-0768885
SELF
TEST
SWITCH
-
AIA2
ATTACHING
HARDWARE ( 3 )
A2A1
MOUNTING
SCREWS (41
A2
ASSEMBLY
MOUNTING
/
BRACKET
A2A3
MOUNTING
SCREWS (6I
\
-
4
PANHEAO
/ /SCREWS (41
/
B
\ 7
/ A 3/A4
A2A2 MODULE
-
A-
MOUNTING
SCREWS ( 41 BRACKET
b MODULE
0 2
BRACKET E N 0
MOUNTING
DZUS 1 SCREWS (41
FASTENER
(41 n II
I
f. A3 and A4 are held together with two guide pins, 6.1.7 Removal and Disassembly of
one coax connector, and one rack and panel connec- Synthesizer Assembly A4
tor. Carefully pull the two assemblies apart. a. Remove module bracket from rf modulator
g. Disassemble A3 according to the following steps. assembly A3 and synthesizer assembly A4 accor-
Refer to figure 46. ding to the following steps. Refer to figure 44.
1. Remove cover from assembly A3. 1. Remove four screws securing module bracket to
2. Remove four screws and four flat washers top of A3 and A4.
securing counter-I/0 board A3A3. 2. Remove four screws (two a t each end) securing
3. Carefully lift A3A3 from A3 chassis to gain module bracket to chassis, and remove module
access to coax connectors. bracket.
4. Disconnect ribbon cable connector A3WlP1 b. Disconnect coax connector from side of A3 (coax is
from A3A3, coax connector A3A3W3P1 on cable from attenuator A6AT1, P/O A6). Refer to figure
from A3A3 to rf strip-line assembly A3A1, and 45.
coax connector A3AlW2Pl from A3A3J2. c. Disconnect connector P5 from rear of A3. Refer to
Remove A3A3. figure 42.
5. Remove two screws and two lockwashers secur- d. Lift assemblies A3 and A4 from the chassis.
ing connector A3A2J1 to back of A3 chassis e. Remove two large screws, two lockwashers, and
(screws are on same side of A3 as guide pins). two flat washers from opposite corners of A4.
6. Disconnect A3AlWlP1 (on cable assembly from Refer to figure 45. Screws are used to secure A4 to
A3A1) from A3A2 and remove A3A2 from A3 A3.
chassis. f. A3 and A4 are held together with two guide pins,
7. Remove 14 screws and 1 flat washer securing one coax connector, and one rack and panel connec-
cover on A3A1 and remove cover. tor. Carefully pull the two assemblies apart.
8. Remove four screws and four washers securing g. Remove eight screws and eight lockwashers, and
A3A1 to A3 chassis, and remove A3A1. remove A4 cover.
h. Remove regulator/divider/filter assembly A4A1 b. Remove seven panhead screws a t rear of A5.
according to the following steps. Refer to figure 47. c. Remove one screw (viewing from front of unit)
1. Remove six screws, six flat washers, and six located on right side of chassis just below upper
lockwashers securing regulator/divider board rail.
A4AlA1 to A4 chassis. d. Loosen two captive fasteners securing front of A5
2. Remove three screws securing transistor moun- to bottom of chassis. Refer to figure 49.
ting bracket on A 4 A l A l to side of A4 chassis. e. Remove connectors P I and P 2 from A5. Refer to
3. Remove three screws securing bracket to A4 figure 42.
chassis (one screw a t each end of bracket and f. Lift front end of A5 approximately 3 to 4 inches
one screw on bottom of A4 chassis near connec- from bottom of chassis, and remove A5 from rear
tor A4AlP1). of chassis. Use extreme care when removing A5 so
4. Remove two screws and associated hardware a s not to damage BNC connectors a t rear of
securing connector A4AlP1 to rear of A4 chassis.
chassis. g. Remove five screws and two flat washers securing
5. Disconnect coax connector A 4 A l P 3 from filter printed circuit board A5A2, and remove A5A2.
FL5 next to vco assembly A4A3. Refer to figure 49.
6. Unsolder and tag wires from enclosed area con- h. Remove process A board A5A1 a s follows:
t a i n i n g vco a s s e m b l y A 4 A 3 a n d o u t p u t 1. Remove six screws securing cover a t top of A5.
amplifier board A4A2. 2. Remove t w o s c r e w s s e c u r i n g h e a t - s i n k
7. Unsolder and t a g wires from TCXO assembly assembly A5A3 (screws on side of A5A3 nearest
A4A4, or remove its attaching hardware, four fan A5B1).
screws, and four lockwashers. 3. Remove three flathead screws and one panhead
8. Remove A4A1 from A4 chassis. screw (securing A5A1 to A5 chassis) from bot-
tom of A5.
i. Remove output amplifier board A4A2 a s follou~s: 4. Remove A5A1, unsolder, and t a g wires a s
1. Remove three nuts, three flat washers, three necessary.
lockwashers, and three screws securing A4A2 to i. Remove fan A5B1 a s follows:
A4 chassis. 1. Remove two screws securing protective cover a t
2. Unsolder and t a g connections to A4A2. bottom of A5B1, and remove cover.
3. Remove connector adapter and spring washer 2. Unsolder and t a g wires to A5B1.
from coax connector on back side of A4 chassis, 3. Remove two screws securing top of A5B1, and
and remove A4A2. remove A5B1.
j. Remove vco assembly A4A3 and filter F L 5 a s j. Remove heat-sink assembly A5A3 or A5A4 by
follows: removing four screws from each assembly (one
1. Remove four screws and four lockwashers screw a t each corner). Unsolder and t a g wires, and
securing TCXO assembly A4A4, and remove remove assembly.
from A4 chassis.
2. Remove two screws, two nuts, two lockwashers, 6.1.9 Removal of Digitally Controlled
two flat washers, and two ground lugs securing Attenuator .46.4Tl
filter FL5.
3. Disconne&coax connector A 4 A l P 3 from filter a. Remove module bracket from rf modulator
FL5. assembly A 3 and synthesizer assembly A4 accor-
4. Remove four screws and four lockwashers (on ding to the folloving steps. Refel. tc "igure 44.
back of A4) securing A4A3. 1. Remove four screws securing module bracket to
5. Unsolder and t a g wires, and remove F L 5 and the top of A 3 and A4.
A4A3. 2. Remove four screws (two a t each end) securing
k. Remove TCXO assembly A4A4 a s follows: module bracket to chassis, and remove module
1. Remove four screws and four lockwashers bracket.
securing A4A4 to A4 chassis. b. Disconnect coax connector from side of A3 (coax is
2. Unsolder and t a g wires, and remove A4A4. from attenuator A6AT1, P/O A6). Refer t c figure
45.
6.1.8 Rerrtoval and Disassembly of Power
c. Disconnect P 5 from rear of A3. Refer to figure 42.
Supply .-lssembly .15 d. Lift assemblies A3 and A4 from chassis.
a . Remove six flathead screws a t rear of A5 (three on e. Remove two screws securing A6AT1 mounting
each side). Refer to figure 48. bracket to bottom of chassis. Refer to figure 50.
f. Remove two screws securing AGAT1 mounting sitive and require special handling a s
bracket to side of chassis. described in Collins document 523-0763405,
g. Disconnect connector P7 on chassis wiring harness Repair Instructions for Planar Assemblies
from connector on AGAT1 mounting bracket. and Cables.
Unscrew coax connector on A6AT1 (connected to
R F OUT connector), and remove A6AT1 with a . Lift up on circuit card extractors a t top edges of
mounting bracket from chassis. assembly.
h. Unscrew coax connector on end of A6AT1 (coax b. Pull assembly straight up out of card cage.
was from module A3). Remove two screws and
four flat washers securing A6AT1 to mounting
bracket, and remove A6AT1 from mounting
6.1.12 Removal of IEEE-48811978 Program
I 1 0 A10
I
bracket.
6.1.10 Removal of R e m o t e T u n e A s s e m b l y A8
T h e f o l l o w i n g d e v i c e s on A 1 0 a r e
a. Lift up on circuit card extractors a t top edges of electrostatic sensitive and require special
assembly. handling a s described in Collins document
b. Pull assembly straight up out of card cage. 523-0763405, Repair Instructions for Planar
6'
Assemblies and Cables.
6.1 .I 1 Removal of Store/Recall A s s e m b l y A9
A10 (CPN 601-5883-001) - U7 and US
A10 (CPN 601-2309-001) - U3
FEEDTHRU
A4AlPI
BRACKET
SCREWS ( 3 ) I HARDWARE ( 2 )
/ \
A4AlA1
ATTACHING
HARDWARE 161
Scans by ArtekMedia © 2008
maintenance 523-0768885
DZUS
FASTENERS (21
BOTTOM
MOUNTING
BRACKET
SCREWS (2)
COAX
CONNECTOR
FROM A3
SIDE
MOUNTING
BRACKET
SCREWS (2)
ATTENUATOR
AGATI
COAX CONNECTOR
FROM RF OUT
CONNECTOR
6.2.3 Reassembly and Replacement of Digitally 4. Attach connectors P I and P2 from chassis wir-
Controlled Attenuator A6ATl ing harness to mating connectors on A5. Refer
to figure 49.
a. Position A6AT1 on mounting bracket so A6AT1
terminals are toward top of signal generator, and 6.2.5 Reassernbly and Replacernent of RF
secure to mounting bracket with two screws and Modulator Assembly '43 and
four flat washers. Refer to figure 50. Synthesizer Assembly A4
b. Connect white translucent connector (P7) on
chassis wiring harness to mating connector on a. Reassemble A4 according to the following steps.
A6AT1. Refer to figure 47.
c. Position A6AT1 mounting bracket in signal 1. Secure filter FL5 to A4 chassis wall with two
generator chassis and secure with four screws, two screws, two nuts, two lockwashers, two flat
screws on side and two screws on bottom of signal washers, and two ground lugs.
generator chassis. 2. Secure A4A3 from back side of A4 with four
d. Screw coax connectors to both ends of A6AT1 (one screws and four lockwashers.
f r o m R F OUT connector a n d one f r o m r f 3. Refer to notes made during disassembly and
modulator assembly A3). solder wires/components to filter FL5 and
A4A3.
6.2.4 Reassembly and Replacement of Power 4. Secure A4A2 to A4 with three nuts, three flat
Supp1-y Assembly .45 washers, three lockwashers, and three screws.
5. Screw connector adapter and spring washer to
a. Secure top of fan A5B1 to power supply chassis coax connector from A4A2 extending out back
with two screws and two flat washers. of A4 chassis.
b. Refer to notes made during disassembly and solder 6. Refer to notes made during disassembly, and
wires to terminals a t bottom of A5Bl. solder connections to A4A2.
c. Position protective bracket a t bottom of A5B1, and 7. Place A4A1 in A4 chassis and secure as
secure bracket and bottom of A5B1 to rear of A5 follows:
chassis with two screws. (a) Secure A4AlP1 to rear of A4 chassis with
d. Refer to notes made during disassembly and solder two screws and attaching hardware.
wires to heat-sink assembly A5A3 and A5A4. (b) Secure bracket with three screws.
Secure A5A4 to rear of A5 chassis with four (c) Secure transistor mounting bracket on
screws. Secure A5A3 to rear of A5 chassis with A4AlA1 to side of A4 chassis with three
two screws (attach with two screws nearest screws.
A5A4). (d) Secure A4AlA1 with six screws, six flat
e. Reattach process A board A5A1 to power supply washers, and six lockwashers.
A5 chassis with two screws thru heat sink A5A3 a t 8. Secure A4A4 with four screws and four
rear of A5 and three flathead screws and one pan- lockwashers.
head screw from bottom of A5 chassis. Refer to 9. Refer to notes made during disassembly, and
figure 49. solder connections to A4A1 and A4A4.
f. Position A5A2J1 to mate with the pinfield on A5A1 10. Connect coax connector A4AlP3 to coax on
and secure A5A2 with five screws and two flat filter FL5.
washers. 11. Secure cover on A4 with eight screws and eight
g. Replace cover on A5 and secure with six screws. lockwashers.
h. Place power supply assembly A5 in signal b. Reassemble A3 according to the following steps.
generator chassis, taking care not to damage BNC Refer to figure 46.
connectors a t rear of signal generator chassis or 1. Secure A3A1 to A3 chassis with four screws and
pinch cable under fan guard of power supply, and four washers.
secure a s follows: 2. Secure cover over A3A1 with 14 screws and 1
1. Tighten two captive fasteners to secure front of flat washer.
A5 to bottom of signal generator chassis. Refer 3. Connect ribbon cable connector A3WlP2 to pin-
to figure 49. field on A3A2.
2. Replace and tighten one screw on side of signal 4. Position A3A2 in A3 chassis, and secure
generator under rail. Refer to figure 48. A3A2J1 with two screws and two lockwashers.
3. Replace and tighten seven panhead screws and 5. Mate connector A3AlWlP1 (on cable assembly
six flathead screws a t rear of signal generator. from A3A1) with pinfield on A3A2.
6. Mate coax connector A3A2WlPl (on cable from 6.2.7 Reassembly and Replacement of Front
A3A2) with A3A3J2. Panel Assembly A1
7. Mate coax connector A3A3W3P1 (on cable from
A3A3) with coax from A3A1. a. Position printed circuit board connector on A1A2
8. Connect ribbon cable connector A 3 W l P l to pin- over mating pinfield on AlA1, and carefully press
field on A3A3. two boards together. Ensure A1A2 is completely
9. Place A3A3 over A3A2 and secure the two sub- mated with AlA1.
assemblies to A3 chassis with four screws and b. Secure A1A2 to standoff posts on A l A l with three
four flat washers. screws. Refer to figure 43.
10. Place cover on A3 assembly.
c. Attach A3 to A4, ensuring guide pins, coax connec-
tor, and rack and panel connectors all engage E n s u r e t h a t all LED's a r e properly
properly. positioned so a s to fit into narrow slots of
d. Secure A4 to A3 with two screws, two flat front panel. These LED's must be positioned
washers, and two lockwashers. Refer to figure 45. exactly to prevent breakage of LED's or wir-
e. Connect P 5 from chassis wiring harness to mating ing. Do not force A1 assembly onto front
connector on A3, and place A3/A4 in signal panel. Assembly falls into place when LED's
generator chassis. Refer to figure 42. Press coax are properly positioned.
connector, from A6AT1, onto mating connector a t
end of A3. c. Place A1 in position on front panel and secure with
f. Place module bracket on rf modulator assembly A3 eight screws.
and synthesizer assembly A4 and secure a s follows: d. Refer to notes made during disassembly, and
1. Install four screws (two a t each end) to secure solder two wires from S E L F TEST switch to
module bracket to chassis. AlA1.
2. Install four screws to secure module bracket to e. Mate connector P6 to pinfield on A l A l and 54 to
the top of A3 and A4. A l P l ( A l p 1 on cable assembly from AlA1). Refer
to figure 42.
6.2.6 Reassembly a n d Replacement of (A70ntroller/ f. Secure front panel to signal generator chassis with
Audio Assembly A2 four screws and four flat washers.
6.2.12 Replacement o f Lens Switches and Bulbs a. Unsatisfactory results are obtained during perfor-
mance of minimum or total performance tests con-
a. Refer to bulb removed from behind lens switch tained in this section.
during disassembly. Cut and bend leads on new b. Unsatisfactory results are obtained during perfor-
bulb to same dimensions and same bends a s old mance of calibration verification procedures con-
bulb. Press bulb into position behind lens switch. tained in the calibration verification section of this
b. Press lens switch into place on front panel until it instruction book.
snaps into place. c. As instructed in the module or functional
7. REPAIR troubleshooting procedures.
d. After replacement of specific circuit boards or
If repair of planar assemblies (circuit card or process module assemblies. The following alignment
board assemblies) is to be attempted, request docu- procedures must be performed after replacement
ment entitled "Repair Instructions for Planar of t h e specified circuit board o r module
Assemblies and Cables," Collins part number 523- assemblies.
0763405, dated 1 January 1978. Send requests to
Publications Department, Collins Government BOARD OR ALIGNMENT
Avionics Division/Rockwell International, Cedar ASSEMBLY PARAGRAPHS
Rapids, Iowa 52406. REPLACED TO BE PERFORMED
I ing are U1, U2, U4, U11, U12, U17, U18, U19, U20,
li25, and U26. The devices on A2A2 are U2, U3, U5,
IJ10, U18, and U22. The devices on A2A3 are U12,
points referred to in the alignment procedures.
I
lJ9, U18, U22, and U23. The devices on A10 (CPN
601-5883-001) are U7 and U8. The device on A10 6.1.6.a.
(CPN 601-2309-001) is U3. c. Loosen four captive fasteners that secure con-
troller/audio assembly A2 to chassis. Lift A2
If repairing rf strip-li?e assembly A3A1, additional straight up and align two bottom mounting holes
precautions should be taken. Excessive heat or solder. on A2 with two top captive fasteners on chassis,
from the soldering iron may change the and tighten two captive'fasteners to secure A2 in
characteristics of the microstrip circuitry if a pad is the extended position.
lifted.
8. ALIGNMENT
8.1 Introduction Refer to figure 35 for component, test-point,
This paragraph provides the alignment procedures and adjustment locations.
required to adjust the signal generator for correct
operation. The alignment procedures should be per- d. Remove wiring harness connector P1 from power
formed only under the following conditions. supply connector A5A2P1.
./o-H: Rc;fi~rr,rccc~
rrirrl Sttr,irlnrrl VOR i l t t r l i o
('oiriliosite Siqiitr1.s (TO)
Fiq~lrr>52
q. Adjust A2A2R9 for 1.000 f 0.001 V rms. g. Set TI to 150-Hz tone only.
r. Set TI to 1020-Hz tone only. h. Adjust A2A2R4 for 1.000 fO.OO1 V rms. Record
s. Adjust A2A2R10 for 1.000 f 0.001 V rms. voltage.
t. Disconnect differential voltmeter. i. Set TI to 90-Hz only.
u. Perform total performance test a s described in j. Check t h a t voltage is 1.000 f0.001 V r m s and
paragraph 4.3. within 50 pV of voltage recorded in step h. If
tolerance is incorrect, repeat steps f through j until
8.5.2 1L.S Signal correct requirements a r e met.
k. S e t TI for 1020-Hz tone only.
a. Press TI POWER switch to on. If initial turn-on, 1. Adjust A2A2R5 for 1.5000 f0.0015 V rms.
wait 30 minutes for TI warmup. m. Disconnect differential voltmeter from TI.
b. Set TI to standard localizer signal of 108.10 MHz.
c. Connect oscilloscope (2.8) to COMP connector on
rear panel of TI. 8.5.3 M a r k e r Reacon Signal
d. Check t h a t displayed signal is similar t o signal
shown on figure 53. a. Press TI POWER switch to ON. If initial turn-on,
e. Disconnect oscilloscope fr.om TI, and connect true wait 30 minutes for TI warmup.
r m s differential voltmeter (2.3) t o COMP connec- b. S e t TI to standard marker beacon signal a t 75.000
tor. MHz with 400-Hz tone.
f. Balance 90-Hz and 150-Hz tones by deleting and c. Connect t r u e r m s differential voltmeter to COMP
adding t h e two tones on TI keyboard (such t h a t connector on TI rear panel.
only one tone is present a t a time) and adjusting d. Check for 1.00 f0.01 V rms.
A2A2R7 until t h e two voltages a r e within 50 pV of e. S e t TI to 1300-Hz tone.
each other. f. Check for 1.000 f0.005 V rms.
R P V ~ S15POctober
~ 1980
maintenance 523-0768885 Scans by ArtekMedia © 2008
b. Set TI POWER switch to on. If initial turn-on, b. Remove 30-Hz VAR and 9960-FM tones.
wait 30 minutes for TI warmup. c. Adjust A3A2R8 for -6 f0.1 dB mW.
c. Set TI to standard VOR signal a t 116.000 MHz. d. Set TI to standard VOR signal of 108.00 MHz and
d. Adjust A2A2R8 for 0-degree bearing. set R F LEVEL to -6 dB mW.
e. Advance radial in 30-degree steps through 360 e. Remove 30-Hz VAR and 9960-FM tones.
degrees. Check t h a t bearing standard reading is f. Check that power meter indicates -6.0 f0.3 d B
within f 0.02 degree of selected radial. mW.
f. Disconnect VOR bearing standard from TI. g. Set TI to standard VOR signal of 117.95 MHz and
g. Connect phasemeter (2.15) to TI with reference in- set R F LEVEL to -6 dB mW.
put connected to COMP connector and test input h. Remove 30-Hz VAR and 9960-FM tones.
connected to AUX connector on rear panel. i. Check t h a t power meter indicates -6.0 f 0.3 dB
h. Set TI to 30-Hz VAR tone only a t a 0-degree radial. mW.
i. Adjust A2A2Rll for 0.00 40.10-degree phase
difference. 8.9.3 (;lideslope Signal
j. Set TI to 180-degree radial.
k. Check that phase difference is 179.80 to 180.20 a. Set TI to standard glideslope signal of 332.00 MHz
degrees. and set R F LEVEL to -6 d B mW.
1. Disconnect phasemeter. h. Remove 90-Hz and 150-Hz modulation tones.
c. Adjust A3A2R6 for -6.0 f0.1 dB mW.
8.8 RF O u t p u t Frequency d. Set TI to standard glideslope signal of 329.15
MHz and set R F LEVEL to -6 d B mW.
a. Connect frequency counter (2.7) to R F OUT con- e. Remove 90-Hz and 150-IIz modulation tones.
nector on TI front panel. f. Check t h a t power meter indicates -6.0 f 0.3 dB
b. Set TI POWER switch to ON. If initial turn-on, mW.
wait 30 minutes for TI warmup. g. Set TI to standard glideslope signal of 335.00 MHz
c. Set TI to standard VOR signal a t 108.000 MHz with and set R F LEVEL to -6.0 dB mW.
all tones removed and rf level of -6 d B mW. h. Remove 90-Hz and 150-Hz modulation tones.
d. Adjust A4 TCXO ADJUST for 107.999 946 to i. Check t h a t power meter indicates -6.0 f 0.3 dB
108.000 054 MHz. mW.
e. Disconnect frequency counter. j. Disconnect power meter from TI.
k. Slide cover over A3 test points and tighten two
8.9 RF O u t p u t Level screws.
8.1 1 Synthesizer VCO A4A3 Alignment o. Alternately switch T I between 108.00 and 117.95
MHz while adjusting the resistor substitution box
I Note 1 to obtain a power meter reading of +12 f 1 dB m W
a t both frequencies.
Do not perform these alignment procedures p. Record resistor substitution box reading that
unless VCO A4A3 or A4A2 h a s been repaired produces output closest to +12 d B m W a s test
or replaced with a new assembly. Do not per- select A4A3R4.
form any adjustments other than those q. Disconnect resistor substitution box and reconnect
listed. Remove A4A3R3, R4, and R5 if it across A4A3C50 and A4A3C53.
previously installed. r . Set TI to 332.00 MHz. Adjust resistor substitution
box until power meter indicates +12 f 0.2 d B mW.
a . Remove and disassemble rf modulator assembly Note resistance value t h a t produces the level
A3 and synthesizer assembly A4 to the extent closest to 12 dB mW a s test select value for
described in disassembly/assembly paragraph A4A3R3.
6.1.7, steps a through g. s. Connect oscilloscope to A4AlAlQ4 collector and
b. Connect rf module extender cable (2.24) to TI wir- observe 25 kHz waveform.
ing harness connector P 5 a n d rf modulator t. If necessary, adjust A4A3C34 and A4A3L12 to ob-
assembly connector A3A3J4. tain a 95-percent d u t y cycle of t h e 25-kHz
c. Connect synthesizer module extender cable (2.27) waveform.
to synthesizer assembly connector P1 and rf u. Alternately switch TI between 329.150 and 335.000
modulator assembly connector A3A2J1. MHz and verify a power meter reading of +12
d. Connect power meter (2.4) directly to synthesizer f 0 . 4 dB m W a t both frequencies.
assembly connector P2. v. Press TI POWER switch to OFF.
e. Connect resistor substitution box (2.25) across w. Select resistor values for A4A3R3, R4, and R5
A4A3C51 and A4A3C54 terminals. Refer to figure from test select resistor kit list (1 to 15 kQ),
34 for test connection locations. Collins p a r t number 637-4321-001, closest to the
f. Set TI POWER switch to ON. Set TI to 74.60 MHz. recorded values.
x. Install and solder selected resistors.
y. Press TI POWER switch to ON. Set R F LEVEL to
-6 dB mW.
Disregard FREQUENCY display during z. Sequentially select TI frequencies of 75.000,
alignment. Ensure AF is off during the 108.000, 117.95, 329.15, and 335.00 MHz. Verify
alignment procedures. power meter indicates +12 f 1 dB mW a t 75.000,
108.000, and 117.95 MHz, and +12 f 0.5 d B mW a t
g. Adjust resistor substitution box until power meter 329.15 and 335.00 MHz.
indication is 12 f 1 dB mW. aa. Press TI POWER switch to OFF.
h. Set TI to 75.40 MHz and adjust resistor substitu- ab. Disconnect power meter a n d connect s t e p
tion box until power meter indication is 12 f 1 dB attenuator (2.5) to synthesizer connector P2.
mW. Connect s p e c t r u m a n a l y z e r (2.1) t o s t e p
i. Repeat steps g and h to obtain a resistance value attenuator.
that produces the power meter indication closest to ac. Set step attenuator to 20 dB.
12 dB mW a t both frequencies. ad. Press TI POWER switch to ON. Set R F LEVEL
j. Record resistor substitution box reading a s test to -6 dB mW.
select value for A4A3R5. ae. Secluentially select TI frequencies of 75.000,
k. Disconnect resistor substitution box and reconnect 108.000, and 335.000 MHz. Verify t h a t second and
it across A4A3C51 and A4A3C55. third harmonics a r e a t least 30 dB below carrier
1. Set TI to 108.00 MHz. Adjust resistor substitution a t 75.000 and 108.000 MHz, and a t least 25 dB
box until power meter indicates +12 f 0.2 dB mW. below carrier a t 335.000 MHz.
m. Connect oscilloscope (2.8) to A4AlAlQ4 collector af. Press TI POWER switch to O F F and disconnect
and observe 25 kHz waveform. test equipment.
n. If necessary, adjust A4A3C5 and A4A3L2 to ob- ag. Reassemble and reinstall synthesizer assembly
tain a 5-percent d u t y cycle of t h e 25-kHz A4/rf modulator assembly A3 a s described in
waveform. paragraphs 6.2.5.a.11 and 6.2.5, steps c through f.
f. Leave sweep generator and spectrum analyzer set- i. Adjust C1, C2, C10, and C11 to obtain a flat fre-
tings the same a s in step e. Connect equipment a s quency response between 75 and 335 MHz a t an 8
shown in figure 57. ItO.5-dB m W output level. Use the actual sweep
g. Turn TI on. After TI has completed initial self-test, generator output obtained in step e a s a reference
t u r n rf off by pushing R F ON/OFF button on front level when making these adjustments.
panel.
-
SWEEP
GENERATOR
WAVETECH 2001
A 6 dB
PAD
A A
-R18
I319
R F AMPL
637-2718-001
0R
634-9681 -001
SPECTRUM
HP141T/8552B/
85548
Printed m USA
8.
4. ~ a l i b m t i o nVerifihtion P r 0 e e . s ~...................................
. 1 . ..... ....
i . ........;.
i..
.%.is.. ;.~-,. ./ ,%,$+%# .
?id
g. -
Scans by ArtekMedia © 2008
Scans by ArtekMedia © 2008
calibration verification
The calibration verification procedures contain the Table 1 lists calibration verification parameters, per-
detailed information necessary for an experienced formance specifications, and test methods.
calibration technician to perform the calibration
verification process. The technician is assumed to be
familiar with the 479s-6A, the specified test equip- 2. MEASURING AND SUPPORT
ment, and general metrology techniques, ter- EQUIPMENT REQUIREMENTS
minology, and definitions.
Table 2 is a list of test equipment required to verify ,
It is recommended that the calibration verification calibration of the signal generator. The table provides
process be performed a t 6-month intervals until an equipment item number, equipment
calibration history in the user's environment in- nomenclature, minimum use specifications, and a
dicates that a shorter or longer interval should be representative type. The item number is used in the
assigned. calibration verification procedure to identify the
equipment used. The minimum use specifications are
The following nonstandard abbreviations are used the principal parameters on which calibration integri-
throughout this section. ty is based. The representative type of equipment
listed meets the minimum use specifications. Alter-
ABBREVIATION DEFINITION nate equipment may be used if it meets or exceeds
minimum use specifications.
COMP Composite
dBc Decibel below carrier level
DEMOD Demodulation Items 2.19 through 2.23 (listed under ADDITIONAL
D/R Down/right REQUIRED T E S T EQUIPMENT FOR
MB Marker beacon SUPPLEMENTAL CALIBRATION VERIFICATION
T/F To/from PROCEDURES) are required if the supplemental
TI Test instrument calibration verification procedures are to be per-
U/L Up/left formed.
ITEM
--r
TEST INSTRUMENT
PARAMETER
Rf output
PERFORMANCE
SPECIFICATIONS
1
N0TE.S TEST METHOD
1.1.2 Frequency vernier >*I channel spacing. Measured with frequency counter a t R F OUT.
1.1.3 Frequency accuracy < *2 ppm, +10 to +40 Measured with frequency counter a t R F OUT.
"C (+50 to +I04 O F ) in-
cluding aging, after
calibration at 25 "C
(+77 OF).
1.1.4.2 Spurious levels >80 dBc > +15 kHz 1, 3 Measured with spectrum analyzer.
from c a r r i e r .
>I17 ~ B C / H Z> 30
kHz from c a r r i e r .
1.2.1.2 3 0 Hz v a r 50.005%
1.2.1.3 90 Hz &0.005%
1.2.2 Distortion
30 Hz ref <0.25%
30 Hz v a r <0.25%
1020 Hz ident <0.5%
9960 Hz <0.5%
Aux audio <l.O%
I
calibration verification 523-0768886 Scans by ArtekMedia © 2008
30 Hz v a r < 1.0%
9960 Hz < 1.5%
Aux audio <2.0%
1.2.2.2 Modulation
30 Hz v a r <l.O%
1020 Hz ident <1.0%
9960 H z <1.5%
Aux audio <2.00/0
30 Hz v a r <1.50/0
9960 Hz <2.0%
Aux audio <3.0%
1.2.3.1 Fixed
1.2.3.2 Selectable
1.2.4.1 9960 F M deviation 480 i2-Hz peak. 1 Measure with computing counter a t TI
COMP output.
1
Scans by ArtekMedia © 2008 calibration verification 523-0768886
1.2.6 GS DDM
1.2.6.2 Preset settings 0.000, j-0.045, *0.091, Functionally verified by observing display.
i0.175, and *0.400
DDM.
1.3.1 Range
1.3.1.1 VOR
1.3.1.2 LOC
1.3.1.3 GS
1.3.1.4 MB
1.3.2 Accuracy
GS-preset mode
GS-variable mode
Marker beacon-preset
mode (95% modulation)
Marker beacon-
variable mode (15
to 97% modulation)
Aux audio
L&70/0of indicated
modulation.
1. Parameter need be checked only when a problem i s suspected, o r after repair a t the discretion of the user.
2. When the 479s-6A i s selected to display pV1s, the rf output is "hard microvolts.'' This eliminates the need
for an external 6-dB attenuator.
3. VOR/LOC/GS and marker beacon frequencies only.
4. Referenced to the accuracy of the standard used in calibration.
calibration verification 523-0 768886 Scans by ArtekMedia © 2008
Vertical output: Provides linear detected Hewlett-Packard 8554B, Opt E58 (includes
output. Calculated dc offsets derived 1 4 1 ~ / 8 5 5 4 BOpt ~ 5 8 / 8 5 5 2 BOpt H58)
from %lo-dB rf input level changes from i s available from Hewlett-Packard
a reference -200-mV dc vertical output a s a precalibrated system.
level must be equal within 2 mV.
Vswr: <1.3:1
2.5
(Cont)
Attenuation accuracy: pill
8 to 11 MHz, change in attenuation Special calibration data re-
from 0 to 60 dB known within quired for attenuation
i0.5 dB. accuracy requirements. The
8- to 11-MHz requirements
30 MHz, attenuation change between a r e required only to perform
lo-, 20-, and 30-dB steps known supplemental calibration
within 0.02 dB. verification procedures
described in paragraph 4.3.2.
108 MHz, attenuation change of
each step from 0 to 40 dB known
within M.2 dB.
30-MHz calibration data not
required if modulation meter
(item 2.17) i s available.
Vswr: <1.20.
Vswr: <1.20.
2.16 Resistive Input/output voltage ratio: 2/1 Constructed using two 47-kilohm,
divider l/4-watt, 10%resistors.
Voltage rating: 2 V min.
20 to 40% AM:
(Cont) +0.70/o of reading.
Scans by ArtekMedia © 2008 calibration verification 523-0768886
2.17
(Cont )
pzT
AM accuracy from 20 to 40%
assumes the following
conditions :
a . Measurement bandwidth:
10 Hz to 15 kHz
b. Temperature: 25 +10 "C
c. Rf input level: 100 mV to
1 volt
Distortion: <0.5%.
If output: 8 to 12 MHz.
The calibration verification process should be per- The calibration verification procedures contained in
formed under the following environmental con- this paragraph verify that the 479s-6A is correctly
ditions: temperature, +10 to +40 (+50 to +I04 O C calibrated and within performance specifications. All
relative humidity, 95 percent maximum.
O F ) ; r e s u l t s obtained d u r i n g performance of t h e
procedures may be recorded on checklist/data forms
Environmental conditions must be met in order to ob- in order to maintain a calibration history for the TI, if
tain the specifications listed in table 1and the results so desired. Recommended checklist/data forms are
contained in the calibration verification procedures shown in table 4. The calibration verification
described in paragraph 4. procedures are divided into two parts, periodic and
supplemental. The periodic calibration verification
Before performance of calibration verification procedures should be performed a t every calibration
procedures, the technician should become familiar interval; they are required to ensure that the TI is
with the procedures that are to be performed. o p e r a t i n g correctly within t h e performance
specifications. The supplemental calibration verifica-
3.2 Turn-On Operation tion procedures should be performed only when a
problem is suspected in the area the verification
Press TI POWER switch to ON. TI display must be in procedure checks, or after repair, a t the discretion of
standard VOR mode condition as shown in figure 1. the using organization.
0 RF OUT
POWER
a
ON
0
Il
OFF
0
4 7 9 s - 6 A VOR/ILS Slgnsl Generator
• TO
.FR,.,
RDUDDM/MOD
1 1 1 IZI 1 1 1 1 1 1 1 1 1 1 1 1
.ILI,I-I,I_I./I,CI,I-I
:yH:
Hz
-RF
111 o ,=,
.CI 0I- I 0-I I
LEVEL-
:.","""
,v
DIRlSOHll
AUDIO STATUS- MODE -RF STATUS-
A lLS PH VAR % M O D VAR FREQ STANDARD SELFTEST MB VOR LOG GS COMM PH L O C I LEVEL CAL
1 1 I I 1 1 1 1 1 1 1 I
0 RF OUT
400 1300 3000
POWER
n
ON
0
E
L
OFF
0
4 7 9 9 6 A VORllLS Sagnal Generator
MODE LOC
e. P r e s s and hold TI SLOW DECR key. TI n. Counter must indicate between 334.849800 and
FREQUENCY indication must decrease. Release 334.850200.
key. o. Disconnect counter from TI.
f . P r e s s a n d hold T I F A S T DECR k e y . T I
FREQUENCY indication must decrease. Hold
FAST DECR key until display counter frequency 4.2.4 Harmonics/Spurious Signals
decreases to a t least 107.95 MHz.
g . P r e s s a n d hold T I S L O W INCR k e y . T I a. Set TI rf output level to -20 dB mW. Connect spec-
FREQUENCY indication must increase. Release trum analyzer (2.1) to TI R F OUT connector.
key. b. Set TI to 75.000-MHz marker beacon frequency
h . P r e s s a n d hold T I F A S T INCR k e y . TI without modulation (no TONE SELECT keys lit),
FREQUENCY indication must increase. Hold and observe spectrum analyzer. All harmonic
FAST INCR key until display counter frequency related signals must be greater than 30 dB below
increases to a t least 108.05 MHz. carrier level. If any nonharmonic spurious signals
i. Set TI for an output frequency of 335.000 MHz are observed, the spurious signals calibration
without modulation (no TONE SELECT keys lit). verification procedure described in paragraph 4.3.1
j. Set TI rf output level to -6 dB mW and press TI AF must be performed.
key for AF operation. c. Repeat step b for several other VOR, localizer, and
k. TI FREQUENCY display must indicate between glideslope frequencies. Harmonic related signals
35000.0 and 35001.0. must be greater than 30 dB below carrier level for
1. Set the TI for an output frequency of 334.850 MHz. VOR/localizer frequencies and greater than 25 dB
m. TI FREQUENCY display must indicate between below carrier level for glideslope frequencies.
34850.0 and 35850.2. Refer to table 3 for a list of available frequencies.
STEP 6 dB
~1
3 dB
-- ATTEN - ATTEN -ATTEN - - - --- ANALYZER
(2.13) (2.5) (2.14) T
I
L RF AMPL
(2.10)
RF AMPL
(2.10)
A
g. Set spectrum analyzer scan width to zero, video TI NOMINAL CHANGE FROM RDNG
filter to 10 kHz, and adjust fine frequency control RF OUTPUT AT -6-dB mW SETTING
for maximum vertical trace deflection. Using log LEVEL NOMINAL MIN/MAX
reference level attenuators, set reference level for (dB mW) (dB) LIMITS (dB)
center screen display.
h. Set TI rf output level and step attenuator to the
following settings and observe spectrum analyzer
display. Record change from reference in + or - -54 -53 to -55
values. (record TI cal-
culated change
for later use)
TI RF OUTPUT STEP ATTEN
LEVEL (2.5) SETTING j. Set step attenuator (2.5) to 40 dB and insert two rf
(dB m W) (dB) amplifiers (2.10) in measurement system a s shown
in figure 3.
k. Adjust spectrum analyzer log reference level
attenuators for center screen reference level on
display. Ensure that spectrum analyzer fine fre-
quency control is adjusted for maximum trace
deflection.
i. Determine if TI attenuator is within following 1. Set TI rf output level and step attenuator (2.5) to
tolerances using following equation: the following settings and record change in spec-
t r u m analyzer display. Record change f r o m
TI attenuator change = A +B- C reference in +or - values.
Where: TI RF STEP ATTEN
OUTPUT LEVEL SETTING
A = Recorded TI rf output level change from -6 (dB mW) (dB?
to -20 dB mW as recorded in step b.
f. Press -10" STEP key. RDL/DDM/MOD indication a t the end of the fifth cycle would be 48.5 ps
must decrease 10". f 5 % (or f 2 . 4 ps).
g. Press and hold +I key. RDL/DDM/MOD indica-
tion must increase. Release key. a. Connect oscilloscope (2.8) channel 1 vertical input
h. Press and hold key. RDL/DDM/MOD indica- to TI COMP output on rear panel, and make the
tion must decrease. Release key. following instrument settings:
i. Press RDL/DDM key and enter 123.45 on DATA
ENTRY keys. Press DATA ENTRY ENTER key.
RDL/DDM/MOD display must indicate 123.45".
j. Press STD key. RDL/DDM/MOD display must in- CONTROL SETTING
dicate 000.00".
k. Press DATA ENTRY-f key. Key must light. FREQUENCY 108.00 MHz
1. Sequentialljr press DATA ENTRY 30°, 120°, 210°,
and 330" keys. RDL/DDM/MOD display must cor- TONE SELECT 9960 FM only
respond with selected degree. (30 Hz VAR off)
m. Press STD key. RDL/DDM/MOD display must
indicate 000.00". 2. Oscilloscope (2.8)
1. If the same VOR standard (same model h. Press TI POWER switch, and release to OFF posi-
and serial number) is used, the TI may be tion.
expected to agree with the standard i. Remove two screws from each side and six screws
within f 0.01" (audio) a n d f 0 . 0 5 " from bottom of signal generator that secure dust
(demodulated rf audio). cover, and slide dust cover off of signal generator.
2. If a like model VOR standard is used, but Refer to figure 1 in the maintenance section for
a different serial number, the TI can be dust cover screw locations.
expected to agree only within the ac- j. Press TI POWER switch to the ON position.
curacy of the standard times 2, plus 0.01" k. Connect OR bearing standard to TI COMP output
(audio) or 0.05" (demodulated rf audio). on rear panel, and set TI rf frequency to 108.00
3. If a different model of VOR standard is MHz (VOR mode).
used, the TI can be expected to agree only 1. Obtain a heading of 000.00" on the VOR bearing
within the sum of the tolerances of the standard by adjusting TI VOR zero adjustment
two standards, plus 0.01" (audio) or 0.05" potentiometer A2A2R8 (identified a s R8 on left
(demodulated rf audio). side of modulator bracket).
m. Connect VOR bearing standard to TI DEMOD
This procedure was written assuming the output on rear panel.
same model of standard would be used to n. Obtain a heading of 000.00" on VOR bearing stan-
verify the TI that was used for initial dard by stepping TI bearing in + or - 0.01" in-
calibration (Collins 4784-3 Zifor); therefore, crements.
the preceding situation 2 applies. If this is o. TI RDL/DDM/MOD radial indication must in-
not the case, appropriate tolerances may be dicate 0.00" f 0.05".
substituted in the procedure. After verifica- p. Press TI POWER switch and release to OFF posi-
tion of the incoming TI status, the procedure tion.
gives instructions to set the TI for 0.00" q. Disconnect VOR bearing standard from TI.
measured VOR error a t the discretion of the r. Install signal generator dust cover and secure with
user. The TI accuracy after calibration will two screws on each side and six screws on the bot-
then be that of the user's VOR bearing stan- tom.
dard. s. Press TI POWER switch to ON position.
calibration verification 523-0768886 Scans by ArtekMedia © 2008
MODULATION DISTORTION
TI METER (2.17) ANALYZER
-R F I N AUDIO O U T
-12.6)
TP5-5477-011
.4M .\fOtili 1ntio)r rrird RF L1i.s tortiotr, Equipnreit t Setrip No I , lisiicg Modriltr tioii .tfrtr'r
Fig 11 re 4
CONTROL SETTING
CONTROL SETTING Range 100
FREQUENCY 113.70 MHz Function % AM
RF LEVEL -6 dBmW Level control Fully ccw (in detent)
TONE SELECT 30 Hz VAR c. Modulation meter must indicate between 29.3 and
7r MOD 30% 30.7% modulation.
2. Modulation Meter d. Measure distortion of the demodulated rf signal
with the distortion analyzer. The measured distor-
CONTROL SETTING tion must be <1.0%.
Tuning Auto e. Repeat steps c and d selecting TI rf frequencies,
High pass (Hz) 10 modulating tones, and AM levels listed below. Note
Low pass/deemphasis Out (low pass (kHz))/l5 the filter settings on the modulation meter. The
Peak PK-PK modulation levels and distortions measured must
2 meet the limits specified.
f. Connect the equipment a s shown in figure 5. 1. Modulation meter must indicate between 75 and
g. Set TI rf frequency to 332.00 MHz and delete the 85% AM.
90-Hz modulating tone. m. Increase audio oscillator level to produce 90%
h. Record the 150-Hz signal level indication on the modulation as measured on the modulation
differential voltmeter. meter.
i. Delete the 150-Hz modulating tone. n. Distortion analyzer must indicate <4% distortion.
j. Connect audio oscillator (2.18) to TI EXT MOD in- o. Oscilloscope signal display must not show clipping
put. a t positive or negative peaks.
k. Set audio oscillator to produce a 150-Hz signal 2 p. Disconnect test equipment from TI. (This com-
times the value recorded in step h a t the TI pletes the periodic calibration verification.
DEMOD output a s measured on differential Proceed to step 4.3.)
voltmeter.
MODULATION
TI
METER (2.17)
RF AUDIO
OEMOD 8LT IN OUT
SPECTRUM
10 d B STEP 10 d B ANALYZER
SIG GEN ATTEN ATTEN ATTEN (2.1) Ol FF
(2.11) (2.12)' (2.5) (2.12)- ViRT OUT VOLTMETER
(2.3)
a. Connect equipment as shown in figure 6 and make b. Adjust spectrum analyzer frequency and linear
the following instrument settings: sensitivity controls for center screen display of 30-
MHz signal.
-
1. Signal Generator (2.11) c. Set spectrum analyzer tuning stabilizer to on, scan
width to zero, and adjust frequency controls for
CONTROL SETTING peak amplitude indication (maximum dc voltage
indication on dvm). Maintain peaked condition
Frequency 30.0 MHz during this procedure.
o u t p u t level +7 dB mW
AM Off I Note I
FM Off
Record all voltages in steps d, e, and f to the
2. Step Attenuator (2.5) nearest tenth millivolt.
CONTROL SETTING
Frequency 30 MHz
Tuning stabilizer Off
andw width 300 kHz
Scan width 200 kHz/division
Input attenuation 10 dB Where:
Scan time 2 ms/division
Linear sensitivity 2 mV/division VoFF 1 = Offset voltage no 1
Vertical sensitivity Linear
Video filter Off VOFF 2 = Offset voltage no 2
Scan mode Internal
Scan trigger Automatic
Display controls As required V1 = Recorded voltage no 1 (20-dB setting)
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calibration verification 523-0768886
CONTROL SETTING
h. Spectrum analyzer linearity is adequate for c. Adjust spectrum analyzer frequency and linear
amplitude modulation calibration verification sensitivity controls for center screen display of
procedure and measurements if VOFF 1 equals 113.70-MHz signal.
VOFF 2 within f2 mV. d. Set spectrum analyzer tuning stabilizer to on, scan
i. Determine average of VOFF 1 and VOFF 2 and width to zero, and adjust frequency controls for
record as VOFF for later use. Calculate VOFF us-
ing the following equation:
SPECTRUM
ANALYZER I ' DlFF
ATTEN (2.1)
(2.12) VERT OUT VOLTMETER
(2.3)
For example:
TI 10 dB SPECTRUM
RF
ATTEN ANALYZER VERT
DEMOD OUT (2.12) (2.1)
OUT OUT
1 DFF
VOLTMETER (2.3)
I DVM (2.2)
AM M o d u l ( l t i o ~Equipment
~, Setup No 2, Using Spectrv nr A ~ a i y t e r
Figure 8
Scans by ArtekMedia © 2008 calibration verification 523-0768886
b. Connect test equipment as shown in figure 9. screen display and add 88.3 dB. Noise level
c. Adjust spectrum analyzer frequency control and measured must be within limits specified.
log reference level attenuators for center screen
display of 10.020-MHz if frequency. FREQ FROM MEASURED
d. Make the following spectrum analyzer control set- CENTER SCREEN NOISE LEVEL
tings: (kHz) (dB)
CONTROL SETTING
Tuning stabilizer On
Bandwidth 1kHz/division I Note I
Scan width 20 kHz/division
Scan time 10 s/division An explanation of the added 88.3-dB correc-
Video filter 10 Hz tion factor is a s follows:
Scan mode Manual
Display controls As required +60 dB - step attenuator value used to
establish reference level in step
e. Adjust spectrum analyzer manual scan, frequency e.
tune, and reference log attenuators for full-screen
amplitude display one division to right of center +30 dB - conversion from 1-kHz
screen. measurement bandwidth to 1-
f. Set signal generator (2.11) frequency to 118.00 Hz specification bandwidth (10
MHz. log 1000/1).
g. Set step attenuator (2.5) to 0 dB.
h. Set spectrum analyzer scan mode switch to single, -1.7 dB - Hewlett-Packard spectrum
and press s t a r t sweep pushbutton. Adjust analyzer correction factor for
analyzer display controls as required. noise measurements (see
i. Note the level down from full-screen reference Hewlett-Packard Application
(step e) of highest spurious signal that is greater Note 150-4).
than *15 kHz from center screen display, and add
60 dB. Signal level measured must be down more 88.3 dB - Total correction.
than 80 dB.
j. Note the level down from full-screen reference
(step e) of the highest average noise signal that is k. Set spectrum analyzer scan width to 50 kHz/divi-
greater than the following frequencies from center sion, and repeat steps h through j.
R
NOTCH SPECTRUM
MIXER STEP ATTEN RF AMPL ANALYZER
-
FILTER
(2.20) (2.5) (2.10)
(2.21) (2.I )
L
1. Repeat steps a through k, setting signal generator A2 = peak amplitude of 90-Hz signal
(2.11) for appropriate offset frequencies for TI
marker beacon frequency of 75.000 MHz. Noise 4 = phase difference between the two signals
level measured in step k greater than f40 kHz a s defined in first note
from carrier must be down greater than 115 dB.
m. Repeat steps a through k, omitting step j, and set- t = time
ting signal generator (2.11) for appropriate offset
frequencies for TI glideslope frequency of 335.000
MHz. Note the level down from full-screen An analysis of this equation for various
reference of the highest average noise signal that periods of time and signal phase differences
is greater than the following frequencies from shows the following composite waveform
center screen display, and add 88.3 dB. Noise level amplitude characteristics:
measured must be within limits specified below.
1. The voltage difference between the peaks
FREQ FROM MEASURED of the waveforms a s shown in figures 11
CENTER SCREEN NOISE LEVEL and 12 to be 0 V if the amplitudes of the
(kHz) (dB) two signals are 1-V rms, and if they have
0" phase shift a s defined in the first note;
30 mV if the amplitudes of the two signals
are 1-V rms, and if the 150-Hz tone leads
or lags the 90-Hz tone by 1" rather than
0" a s defined in the first note.
n. Disconnect test equipment from TI. 2. The voltage peak of the waveform a s
shown in figure 13 to be between 370 and
4.3.3 ILS Phase (901150-Hz Composite Signal 418 mV if the amplitudes of the two
signals are 1V rms, and if the 150-Hz tone
I Note 1 phase is between 58 and 62" rather than
60" as defined in the first note.
0" phase difference between the 90- and 150-
Hz waveforms is defined a s the point where a. Set TI output frequency to 108.3 MHz and delete
both waveforms pass through zero in the 90-Hz modulation tone.
same direction a t the same time. The TI b. Connect true rms differential voltmeter (2.3) to TI
tolerance is the amount of deviation from COMP o u t p u t on r e a r panel a n d m e a s u r e
the in-phase condition just described, amplitude of 150-Hz tone. Record amplitude.
specified in terms of 150-Hz degrees. The TI c. Add 90-Hz modulation tone and delete 150-Hz
phase difference between the two tones is modulation tone.
normally fixed a t 0°, but can be selected to d. Measure amplitude of 90-Hz tone and record
be 60". amplitude.
e. Compare recorded amplitude of 90-Hz modulation
I Note I tone with recorded amplitude of 150-Hz modula-
tion tone. Amplitude must be equal within 0.5 mV.
The phase difference between the 90- and Record amplitude of 90-Hz tone (record voltage a s
150-Hz signals is verified to be within a fraction of a volt to the nearest 0.001 V). The
tolerance a t 0 and 60" by measuring recorded voltage will be used later in the procedure
amplitude levels a t selected points of the a s a correction factor.
composite signal with an oscilloscope. The f. Connect oscilloscope (2.8) to TI COMP output on
peak amplitude level of the composite signal rear panel.
a t any point in time may be determined from g. Make the following equipment settings:
the following formula:
CONTROL SETTING
Where:
FREQUENCY 108.3 MHz
A1 = peak amplitude of 150-Hz signal TONE SELECT 90 Hz, 150 Hz
calibration verification 523-0768886 Scans by ArtekMedia © 2008
TI
COMP 0 -
LOW- PASS F I L T E R ( 2 . 2 2 ) COMPUTING COUNTER (2.19)
0 A INPUT
CONTROL
FREQUENCY
SETTING
108.00 MHz -
1. LEARN
2. MODULEA
10.
11.
-
IFx <b
b-x
TONE SELECT 9960 FM (30
3. a-x
4 . a x y'
12.
13.
REPEAT
a
-
Hz VAR off) 5. bx- -4 14.
6. xFER PROG 15. -(SUBTRACT)
2. H P 53608 Computing Counter (2.17)
CONTROL SETTING -
7. MODULE A
8. I F x > a
9. a-x
16.
17.
18.
DISPLAY x
RUN
START
CYCLE RATE MAX
DIGITS 5 f. Counter must indicate peak-to-peak 9960-FM
DISPLAYED deviation to be between 956 and 964 Hz.
EXT Depressed g. Disconnect computing counter from TI.
PUSHBUTTON 3 X 10 ps
MEASUREMENT TIME
S e r i a l No Date
LIMITS MEASURED
PARA FUNCTION TESTED
VALUE
NOMINAL MINIMUM MAXIMUM
3 PRELIMINARY OPERATIONS
4 CALIBRATION VERIFICATION
PROCESS
a. M a r k e r beacon (4)
b. VOR (J)
c. Localizer (J)
d. Glideslope (J)
e. Localizer/glideslope paired (J)
frequencies
f. Communication (J)
4.2.2 Frequency A c c u r a c y
4.2.3 Frequency V e r n i e r
e. Slow d e c r e a s e Decrease J
f. Fast decrease Decrease U)
Minimum r a n g e -
<107.95 MHz M H z
g. Slow i n c r e a s e Increase v)
h. Fast increase Increase (4
Maximum r a n g e 2108.05 MHz M H z
4.2.4 ~armonics/SpuriousSignals
No nonharmonic spurious (4
signals present. (If
present, r e f e r to para
4.3.1 for additional veri-
fication procedures .)
c. VOR frequencies
No nonharmonic spurious (4
signals present. (If
present, r e f e r to para
4.3.1.)
Localizer frequencies
No nonharmonic spurious (4
signals present. (If
present, refer to para
4.3.1.)
Glideslope frequencies
No nonharmonic spurious (4
signals present. (If
present, refer to para
4.3.1.)
- 7 dB mW -1 dB 0 dB -2 dB -dB
-8 dB mW -2 dB -1 dB -3 dB dB
-10 dB mW -4 dB -3 dB -5 dB dB
-14 dB mW -8 dB -7 dB -9 dB I
dB
-20 dB mW -14 dB -13 dB -15 dB dB
-30 dB mW dB
-40 dB mW dB
-50 dB mW dB
-60 dB mW dB
-70 dB m W dB
-80 dB mW -dB
-90 dB mW -dB
(Cont) -100 dB m W dB
Scans by ArtekMedia © 2008
calibration verification 523-0768886
4.2.5.3
(Cont )
4.2.7.1 Audio
b. Tone distortion
75.00 MHz
30 Hz reference <0.25% %
30 Hz variable 30% mod '
<0.25% %
30 Hz variable 9% mod <l.O% %
9960 Hz 30% mod < 0.5% %
9960 Hz 9% mod <1.5% %
1020 Hz ident <0.5% %
14000 Hz AUX audio 30% mod <1.0% %
14000 Hz AUX audio 9% mod <2.0% %
3000 Hz AUX audio 9% mod <2.O% %
4.2.8 VOR Tones
b. T/F
accuracy) *0.0l0
piiq
Record data for steps
1 and o only if VOR
bearing 0" adjustment
is made. This adjust-
ment i s a t the discre-
tion of the user.
pq
Record data for step
u o r v only if VOR
bearing standard
being used can
measure tracking
accuracy.
pzq
Record data for step
v only if VOR bearing
0" adjustment i s
made. This adjustment
is at the discretion
of the user.
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calibration verification 523-0 768886
4.2.8.3
(Cont)
o
60" 60.00" 59.94" 60.06"
90" 90.00" 89.94" 90.06"
o
120" 120.00" 119.94" 120.06"
150" 150.00" 149.94" 150.06"
180" 180.00" 179.94" 180.06"
210" 210.00" 209.94" 210.06"
240" 240.00" 239.94" 240.06"
270" 270.00" 269.94" 270.06" 0
0.000
0.046
0.093
to
to
to
0.046
0.093
0.155
(Y
:$
( )
0.155 to 0.200
D / R ( ~ O Hz) indicator On
(Cont) ~ / L ( 1 5 0Hz) indicator Off
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0.045 V rms
0.400 V- rms
0.750 V- rms
0.790 V- rms
0.045 V rms
0.400 V
- rms
0.750 V
- rms
0.790 V
- rms
0.045 V rms
0.400 V- rms
0.750 V- rms
0.790 V- rms
150-Hz tone level (down)
0.045 V rms
0.400 V rms
0.750 V rms
0.790 V rms
j. Voltage ratio (down = 90 Hz;
150 Hz)
4.2.11 AM Modulation
pzq
Record data for
4.2.11.1 only i f
using modulation
meter.
4.2.11.1
(Cont) d. 30-Hz variable distortion 76
113.70 MHz
30-Hz VAR
Modulation %
Distortion 9i
9960-HZ
Modulation %
Distortion %
9960-HZ
Modulation %
Distortion %#
1020-Hz
Modulation %
Distortion 9%
3000-Hz (AUX audio)
Modulation %
Distortion %
14000-Hz (AUX audio)
Modulation 9%
Distortion %
110.10 MHz
90-Hz
Modulation %
Distortion %
90-Hz
Modulation %
Distortion ?G
150-HZ
Modulation %
Distortion %
150-Hz
Modulation 9%
Distortion %
1020-HZ
Modulation 9%
Distortion %
4000-Hz (AUX audio)
Modulation 9%
Distortion 9%
4000-Hz (AUX audio)
Modulation
(Cont) Distortion
calibration verification 523-0768886 Scans by ArtekMedia © 2008
332.15 MHz
90-Hz
Modulation
Distortion
90-HZ
Modulation
Distortion
150-HZ
Modulation
Distortion
150-HZ
Modulation
Distortion
75.00 MHz
400-HZ
Modulation
Distortion
1300-HZ
Modulation
Distortion
3000-HZ
Modulation
Distortion
EXT MOD
Modulation
Distortion
E X T MOD
No signal clipping
g. calculation
V~~~ 1 and 'OFF 2
R1 (voltage ratio)
R (voltage ratio)
2
V1- RlV2
m V
'OFF 1- i - R~
V3 - R2V1
m V
V O 2 ~ 1~- R2
'OFF 2
i. Calculate VOFF
V ~ + OFF^
~ ~ l
'OFF - 2
e. Calculate V
REF
Percent modulation =
'rms
x 100
0.2
113.70 MHz
30 Hz 30.00% 29.25% 30.75% %
9960 Hz 30.00% 29.25% 30.75% %
(Cont) 14 000 Hz 35.00% 32.55% 37.45% %
calibration verification 523-0768886 Scans by ArtekMedia © 2008
4.2.11.3
(Cont)
110.10 MHz
90 Hz 20.00% 19.50% 20.50% %
150 Hz 20.00% 19.50% 20.500/u %
1020 Hz 30.00% 29.25% 30.75% %
4000 Hz AUX audio 30.00% 28.50% 31.50% %
332.15 MHz
90 Hz 40.00% 39.00% 41.00% %
90 Hz 80.00% 76.00% 84.00% %
150 Hz 40.00% 39.00% 41.00% %
150 Hz 80.00% 76.00% 84.00% %
75.00 MHz
1300 Hz 95.00% 90.25% 99.75% %
1300 Hz 97.00% 91.67% 100.00% %
o. EXT MOD
Modulation 80.00% 75.00% 85.00% %
No signal clipping d)
4.3 Supplemental Calibration
Verification Procedures
(Cont)
Noise >*40 kHz from c a r r i e r
(108.00 MHz)
>I22 dBc (4
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NOMINAL MINIMUM
4.3.2
(Cont)
4.3.3
(Cont)
k. Waveform peak V
1. Deflection factor e r r o r V
Corrected waveform V
measurement
m. Calculated voltage V
n. Limit calculations
Rockwell
International
Collins 479s-6A
VORII LS Signal Generator parts list
list of illustrations
Figure Page
Page No Issue
2nd Ed 15 Oct 80 SR 1. 2, 3. 5, 6 ,
7, 8 !I, 10
Scans by ArtekMedia © 2008
parts list
INTERNATIONAL RECTIFIER
9220 SUNSET BLVD
P 0 BOX 2321 TERMINAL ANNEX The follo~vingusable on codes have been assigned in
L O 3 ANGELES CA 90054
t h e manual:
SWITCHCRAFT I N C SUB OF RAYTHEWJ CO
5555 N ELSTON AVE USABLE UNIT FIG-
CHICAGO I L 60630 ON CODE PART NUMBER ITEM
ROTRON I N C
7-9 HASBROUCK LANE
WOODSTOCK NY 12498
L I T T O N SYSTEMS I N C
USECO D I V
13536 SATICOY S T
VAN NUYS CA 91409 1.8 Reference Designation Prefixes
JOHANSON MFG CO
P 0 BOX 329 The following prefixes have been assigned in this
BOONTON N J 07005 manual:
K I N G S ELECTRONICS CO I N C UNIT FIG-
40 MARBLEDALE ROAD PREFIX PART NUMBER ITEM
TUCKAHOE NY 10707
MALCO A MICRODOT CO A1
12 PROGRESS DR AlAl
MONTGOMERYVILLE PA 18936
A1A2
WHITS0 I N C A2
9330 BYRON S T A2A1
S C H I L L E R PARK I L 60176
A2A2
RCA CORP RCA FREQUENCY BUREAU A2A3
50 BROAD S T A3
NEW YORK NY 10004
A3A1
M I L I T A R Y STANDARD A3A2
arts list 523-0769256
Scans by ArtekMedia © 2008
1-
1-
1-
1-
2-
3-
4-
5-
6-
6-1C
7-
8-
9-
10-
11-
12-
13-
14-
15-
16-
13-16
17-
18-
19-
October 1.980
Kcr~isorl1 .i
Scans by ArtekMedia © 2008 arts list 523-0769256
DETAIL A
fhC',
$a'&*
,::,::::;:,
. . .U. . Il**D,/*i "..O*.
"8.e."L&O
;
I
TP5-5341-017
+ UNITS USABLE
FIG- z
w
ITEM PART NO n DESCRIPTION PER ON
Z ASSY CODE
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM a
Z ASSY CODE
Kp,yborcrd/Dr?ver Board A l A l
F z g ~ i r e3 (Sheet 1 of 2j
Keyboard/Dnrler Board A l A l
Figzire .? (Sheet 2)
2 INTEGRATED CIRCUIT ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 6 2
2 RESISTCR ,FXD CP!FSN, l K , l o % , l / E A ( 8 1 3 4 9
745-2341-000 A l A l R 1 4
2 RESISTCR,FXD CNPSN, 1K, 1 0 % ~1/8W ( 6 1 3 4 9 )
745-2341-000 AlAlR13
2 RESISTCR,FXD CNPSN, 1K, 1 0 % ~1/'W (81349)
745-2341-000 A l A l R 1 2
2 RESISTOR,FSD CMPSN, 1K, 1 0 x 9 1/8W ( 8 1 3 4 9 )
745-2341-000 A l A l R l l
2 SWITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 4 9
2 SWITCH,PUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 3 6
2 SNITCHIPUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A l S 4 8
3 LANP,It:CASD ( 7 1 7 4 4 2 6 2 - 2 7 3 0 - 0 0 0 (P/'O A l A l S 4 8 1
2 SWITCH,PUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 3 5
2 SWITCHsPUSH ( A 1 6 4 3 ) 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 4 7
2 SWITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 3 4
2 SWITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 4 6
2 SWITCH,PUS!i (A16431 266-7532-010 A l A l S 3 3
2 INTEGRATED C I R C U I T ( 5 6 2 8 9 ) 3 5 1 - 0 1 9 6 - 0 1 0 A l A l U 6 1
2 SWITCHYFUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A l S 4 5
3 LAtlP,It4CAP:D ( 7 1 7 4 4 ) 2 6 2 - 2 7 3 0 - 0 0 0 ( P/O A l A l S 4 5 )
2 SKITCH,PUSH ( A 1 6 4 3 ) 2 6 6 - 7 5 3 2 - 0 2 0 A 1 4 1 5 3 2
3 LAMP,INCAND ( 7 1 7 4 4 ) 2 6 2 - 2 7 3 0 - 0 0 0 (P/O A l A S 3 2 )
2 SWITCH,FUSH ( A 1 6 4 3 ) 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 4 4
2 SXITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 3 1
2 SWITCH,FUSH (Al.643) 2 6 6 - 7 5 3 2 - 0 1 0 A l A l S 4 3
2 514ITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 1 0 A141530
2 INTEGRATED C I R C U I T ( 5 6 2 8 9 ) 3 5 1 - 0 1 9 6 - 0 1 0 A l A l U 5 9
2 SgITCHyFUSH ( A 1 5 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A I . 5 2 9
3 LAMP,INCAND ( 7 1 7 4 4 ) 2 6 2 - 2 7 3 0 - 0 0 0 ( P/O A l A l S 2 9 )
2 SNITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A l S 2 8
3 LAMP,INCAND ( 7 1 7 4 4 ) 2 6 2 - 2 7 3 0 - 0 0 0 ( P i 0 A l A l S 2 8 )
2 SWITCH,FUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A l S 2 7
3 LANP~INCAND ( 7 1 7 4 4 1 2 6 2 - 2 7 3 0 - 0 0 0 ( P / O A l A l S 2 7 )
2 INTEGRATED C I R C U I T ( 5 6 2 9 9 ) 3 5 1 - 0 1 9 6 - 0 1 0 A l A l U 5 7
2 SWITCHjFUSH ( A 1 6 4 3 1 2 6 6 - 7 5 3 2 - 0 2 0 A l A l S 1 4
3 LAIIP,INCAND ( 7 1 7 4 4 I 2 6 2 - 2 7 3 0 - 0 0 0 ( P / O A l A l S 1 4 )
2 INTEGRATED C I P C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 5 6
2 CAPACITOR,FXD CER D I E L , O.OlUF, PCRM10%, lOOV
( 6 1 3 4 9 ) 913-5019-200 AlAlC16
2 INTEGRATED C I R C U I T LOGIC GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 1 0
AlAlUl
2 CAFACITORpFXD CER D I E L , 0 - O l U F , PORtllO%r lOOV
( 8 1 3 4 9 ) 913-5019-200 A l A l C 3
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 3
2 IWTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 4
2 INTEGRATED CIRCUIT ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 6 - 0 3 0 A l A l U 5
2 CAFACITOR,FXD CER D I E L , O.OlUF, PORM10%, lOOV
( 8 1 3 4 9 ) 013-5019-200 A l A l C 4
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 6
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 7
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A141U8
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 9
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 3 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U l O
2 CAFACITOR,FXD CER D I E L , O.OlUF, FC?MlO%, lOOV
( 8 1 3 4 0 ) 913-5019-200 A l A l C 5
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U l l
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 1 2
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 1 3
2 CAPACITO2,FXD CER D I E L , O.OlUF, FORNlO%, ZOOV
( 8 1 3 4 9 ) 913-5019-200 A l A l C 6
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 1 5
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 1 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 1 6
2 CAFRCITCR tFXD CER D I E L , 0 . O l U F , FCRtllO;!, loo\'
( 8 1 3 4 9 ) 913-5019-200 A l A l C 7
2 INTESRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U l 8
2 It4TEGRAlED C I R C U I T ( 0 4 7 1 3 3 5 1 - 1 5 2 6 - 0 3 0 A l A l U 1 9
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2 0
2 It!TEZ!?ATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 0 3 2 - 0 1 0 A l A l U 2 1
2 CAFACIT07,FYD CER D I E L , O . O l U F j PCZN10%, 100'4
( 8 1 3 4 7 ) 013-5019-200 A l A l C 8
2 ItiTEG3ATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2 2
2 ItiTEG51ATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2 3
2 CAFLCITO!?,FXD CER D I E L , O.OlUF, FC=t110%, lOOV
( 8 l j s 9 ) 913-5319-200 A l A l C 9
2 INTtGR4TED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2 5
2 INTEGFATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A l A l U 2 6
2 It4TEGWTED C I E C U I T ( 1 6 3 2 4 3 5 1 - 1 2 6 7 - 0 2 0 A l A l U 2 7
2 CAPACITC??FSD CER D I E L , O.OlUF, FCRtllO%, 1 0 3 V
( 8 1 5 4 9 ) 913-5019-200 A l A l C l O
2 INTEGRATED C I R C U I T LOSIC GATE ( 1 8 3 2 4 3 3 5 1 - 1 5 2 3 - 2 6 0
AlftlU55
2 CAF'ACITORvFXD CER D I E L , O.OlUF, PORF110%, lOOV
( E l 3 h 9 ) 913-5019-200 A l A l C 1 5
2 RESISTOR,FXD CIIPSt4, ~ K Il o % , 1/8W ( 8 1 3 4 9 )
7 4 5 - 2 3 4 1 - 0 0 0 A141R6
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 5 4
2 IflTEGRITED CIRCUIT ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 5 3
2 CAPACITCR,FSD CER D I E L , O.OlUF, PCi;PIlO/, lCOV
( 8 1 3 4 9 ) 913-5019-200 AlAlC14
2 RESISTG2,FXD CIIFSNI 1 K , 1 0 2 , 1/8W ( 8 1 3 4 9 1
745-2341-000 A l A l R 5
2 INTEGRATED C I E C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 5 2
2 IIITESRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 5 1
2 IIITEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 5 0
2 RESISTC9,FXD CPIPSII, l K , l o % , l / e W ( 8 1 3 4 9 )
745-2341-000 A l A l R 4
2 It4TEGRATED C I R C U I T ( 0 1 2 9 5 1 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 4 9
2 INTEGRATED C I R C U I T LOGIC GATE ( 2 7 0 1 4 ) 3 5 1 - 1 5 2 3 - 2 2 0
AlAlU4S
2 II4TEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 6 - 0 3 0 A l A l U 4 7
2 INTEER.4TED C I R C U I T ( 2 7 0 1 4 ) 351-7544-0;O AlAlU46
2 CAFACITOR,FXD CER D I E L , O.OlUF, PORt110%, lOOV
( 8 1 3 4 9 ) 913-5019-200 A l A l C 1 3
2 INTEG44TED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 4 5
2 IIITEC-RATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l i i l U 4 4
2 RESISTC2,FXD CIIFSN, 1K, l o % , 1/6W ( 8 1 3 4 9 )
745-2341-000 A l A l R 3
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 4 3
2 RESISTCR2FXD CHFSN, 1K, 1 0 % ~1/6W ( 3 1 3 4 9 )
745-2341-000 A l A l R 2
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 4 2
2 IIdTEGPATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 4 1
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 4 0
2 CAFACITC2,FXD CER D I E L , O.OlUF, PORt110%, lOOV
( 8 1 3 4 9 ) 913-5019-200 A l A l C 1 2
2 IEITEGRATED C I R C U I T ( 0 1 2 0 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 3 9
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 3 8
2 It:TEG!?ATED C I F C U I T ( 0 1 2 0 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 3 7
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 3 6
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 3 5
2 It4TEGRATED C I R C U I T ( 0 1 2 9 5 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 3 4
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 3 3
2 INTEGRATED C I R C U I T ( 0 1 2 0 5 3 5 1 - 7 6 3 2 - 0 1 0 A l A l U 3 2
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 3 1
t-
FIG- z UNITS USABLE
ITEM PARTNO ,W, DESCRIPTION PER
ASSY
ON
CODE
L
DM7447AN 2 ItITECRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 3 0
CK05EX103K 2 C A P d C I T 0 9 , F S D CER D I E L I O.OlUF9 PORPIlO:,:, lOOV
( 8 1 3 4 9 ) '313-5019-200 A l A l C 1 1
RCRC5GlO2KS 2 RESISTCR,FXD CHFSN, 1 K , lo;!, 1/8W ( 8 1 3 4 9 )
745-2341-C00 A l A l R 1
DF17447AN 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 1 3 5 1 - 7 5 4 4 - 0 2 0 A l A l U 2 9
CK05ES103K 2 CAFCCITOR,FXD CER D I E L O . O l U F , PCRPllO:!, lOOV
( 8 1 3 4 9 3 913-5019-ZOO A l A l C 2
M39003-01-2257 2 C A P A C I T C R s F X a E L C T L T , 3 3 U F p 1 0 % r 1OV ( 8 1 3 4 9 )
164-9066-170 A l A l C l
Dtl74LSlON 2 I I I T E S P A T E D C I R C U I T L C G I C GATE ( 2 7 0 1 4 ) 3 5 1 - 1 5 2 3 - 2 3 0
AlAlU28
768-3177-004 2 POST
P313-0132-000 2 NUT,PLAIN,HEX SST, 4 - 4 0 ( 7 7 2 5 0 ) 3 1 3 - 0 1 3 2 - 0 0 0 ( A P )
372-2601-045 2 CC:IT4CT, ELEC
706-5919-003 2 PIN, INCEX
778-0422-023 2 SPACER, SLEEVE
parts list 523-0769256 Scans by ArtekMedia © 2008
I PART NO
t-
z
W
o
z
DESCRIPTION
p&Si
ASSY
M Z L E
CODE
+
z UNITS USABLE
FIG- w
PART NO n DESCRIPTION PER ON
ITEM ASSY CODE
Z
2 LED D I S P L A Y 1 2 8 4 8 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 2
2 LED D I S P L A Y ( 2 8 4 8 0 3 2 6 2 - 1 4 6 3 - 0 ' 1 0 A l A 2 D S 3
2 LED D I S P L A Y ( 2 8 4 3 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 4
2 LED D I S P L A Y ( 2 8 4 6 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 C S 5
2 RESISTC? NTWK D U A L - I N - L I t I E , 1 5 0 OHl:S, 2%, 125V
( 0 1 1 2 1 ) 350-4027-010 AlA2U7
2 LAMPYLED ( 2 8 4 6 0 ) 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 5
2 LAMP, LED ( 2 8 4 8 0 3 5 3 - 0 3 1 1 - 0 1 0 A l A T C R 6
2 LAIlP, LED f 26G30 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 7
2 RESISTOR NTWI; D U A L - I N - L I t < E , 1 5 0 OHMS, 2%, 125V
( 0 1 1 2 1 ) 350-4027-010 AlA2US
2 RESISTC? NTKK DUAL-IN-LIt:E, 1 5 0 OHMS, 2%, l25V
( 0 1 1 2 1 ) 350-4027-010 AlA2U2
2 RESISTOR NTKK GUAL-ItI-LIE:E, 1 5 0 OiiXS, 2 % ~1 2 5 V
( 0 1 1 2 1 ) 350-4027-010 AlA2U10
2 LED D I S F L A Y ( 2 8 4 8 0 ) 2 6 2 - 1 5 6 3 - 0 1 0 A l A 2 D S 6
2 LED D I S P L A Y ( 2 8 4 6 0 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 7
2 R E S I S T 0 7 NTWS DU?L-It4-LIt-IE, 1 5 0 OHMS, 2%, 125V
( 0 1 1 2 1 ) 350-4027-010 AlA2U11
2 LED D I S P L A Y ( 2 8 4 S O l 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S B
2 LED D I S F L A Y ( 2 6 4 8 0 3 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 9
2 RESISTCR t4TLY D U A L - I N - L I I Z E , 1 5 0 OHPlS, 2 x 9 125V
( 0 1 1 2 1 ) 350-4027-010 AlA2UlE
2 LED D I S P L A Y ( 2 8 4 8 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 1 0
2 LED D I S P L A Y ( 2 9 4 8 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A Z D S 1 1
2 RESISTOR NTWK DUAL-It4-LIt:E, 1 5 0 @li:lS, 2%, 125V
( 0 1 1 2 1 ) 350-4027-010 AlAZU13
2 LAtlP, LED ( 2 8 4 8 0 ) 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 8
2 LAMP,LED (2€'4803 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 9
2 LAPIP, LED I 2 6 4 9 0 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 1 0
2 RESISTCR NTGK DUAL-IN-LII:E, 1 5 0 OH:iS, 2 % ~1 2 5 V
( 0 1 1 2 1 ) 350-4027-010 AlA2U14
2 LED D I S P L A Y ( 2 8 4 8 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A Z D S 1 2
2 LED D I S P L A Y ( 2 8 4 3 0 ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 1 3
2 LED D I S P L A Y ( 2 8 % S O ) 2 6 2 - 1 4 6 3 - 0 1 0 A l A 2 D S 1 4
2 LAPIPPLED ( 2 8 4 8 0 ) 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 1 1
2 L4XPyLED 1 2 8 4 8 0 ) 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 1 2
2 LAtlP, LED ( 2 0 4 8 0 3 5 3 - 0 3 1 1 - 0 1 0 A l A 2 C R 1 3
2 RESISTCR NTKK D U A L - I t { - L I N E , 1 5 0 OHMS, 2 % ~1 2 5 V
( 0 1 1 2 1 ) 350-4027-010 AlA2U17
FIG- 2
W
ITEM PART NO DESCRIPTION
z
2 FOST
2 NUT,SLFLKGtHEX AL, 4-40 ( 7 2 9 6 2 ) 333-0347-000 (AP FOR
5-6 1
2 WASHEP,LOCK SST, 0.115 I D X 0.209 OD ( 9 6 9 0 6 )
310-0279-000 (AP FCR 5 - 6 ) ( EFF TO REV LTR F )
2 WASHERtFLAT CRESt 0.125ID X 0.250 OD ( 9 0 9 0 6 )
310-0779-030 (AP FOR 5 - 6 )
2 SCREW,PIACH STLp 4-40 X 5/8 ( 9 6 9 0 6 ) 343-0138-000 ( A P
FCR 5 - 6 1
2 FOST
2 GRACKET ASSEMBLY
3 RECEPTACLEITURN ( 7 1 2 8 6 ) 012-2786-000
3 RIVETySOLID AL, 3/32 D I A X 3/16 ( 9 6 9 0 6 ) 305-1361-000
( AP )
3 BRACKET
I-
FIG- z UNITS USABLE
PART N O W
ITEM a DESCRIPTION PER ON
Z ASSY CODE
I FIG-
ITEM I I I
DESCRIPTION
I-
FIG- UNITS USABLE
PARTNO z
w DESCRIPTION PER ON
ITEM
Z ASSY CODE
+ UNITS USABLE
FIG-
ITEM PART NO 5
n DESCRIPTION PER ON
Z ASSY CODE
Arrn1o.q Board A M 2
Fiqure 7 (Sheet 1 o,f'L)
I-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM a
Z ASSY CODE
I I I
t-
FIG- z UNITS USABLE
PARTNO W
ITEM a DESCRIPTION
I ASSY
PER CODE
ON
LMlOlAH 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 4 0 - 0 2 0 A P A 2 U 1 1
RCROiG152KS 2 RESISTO2,FXD CtlFSN, 1 . 5 K . l o % , 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 5 5 - 0 0 0 AZAZR102 '
CKO5EX150K 2 CAPACITOR,FXD CER DIEL., 1 5 P F , FORMlO%, 2OOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 0 3 0 A2A2C5
LP1101AH 2 I N T E G Q A T E D C I K C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 4 0 - 0 2 0 AZA2U6
Dfl2OFDZ22J04CR 2 CAPACITO2,FXD M I C A D I E L , ZZOOPF, 5 % 5~ 0 0 V ( 1 4 6 5 5 1
912-3339-000 A2A2ClO
RN55E1502B 2 RESISTORPFXD F I L P I , l E K , O . l % r l / l O W ( 6 1 3 4 9 )
7 0 5 - 5 9 7 5 - 6 1 0 AZA?R22
RCR07G474KS 2 RESISTOR,FXD CF:PSNI 0.47MEGOt 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 8 4 5 - 0 0 0 A2AZR41
RCR07G474KS 2 RESISTO9,FXD CMPSN, 0.47MEG0, l o % , 1/4W ( 8 1 3 4 9 )
745-0845-000 AZArR13
RCR07G474KS 2 RESISTOR,FXD CMPSN, 0.47MEG0, 1 0 % ~1/4W ( 8 1 3 4 9 )
745-OE45-00C A2A2R42
RNbOD8063F 2 R E S I S T O R y F X D F I L M , 8 0 6 K ~ 1 % , 1/4W ( 8 1 3 4 9 ) .
705-3601-420 A2A2R101
Rt460D8063F 2 RESISTORyFXD F I L M * 8 0 6 K , 1 % 1/4W ~ (81349)
705-3601-420 A2A2R100
RN55E17426 2 RESISTC?,FXD F I L M , 1 7 . 4 K , 0.1%, l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 5 - 9 3 0 A2A2R20
Dt:5F221J050WV 2 CAPACITOR,FXD M I C A D I E L , 2 2 0 P F 9 5 % 5~ 0 V ( 7 2 1 3 6 )
912-4141-450 A242C17
DM5F401J050W 2 CAPACITCR,FXO M I C A D I E L , 4 0 0 P F , 5x9 5 0 V ( 7 2 1 3 6 )
9 1 2 - 4 1 4 1 - 5 2 0 AZA2C16
1N825A 2 SEMICC'!3 D E V I C E ( 1 2 9 5 4 1 3 5 3 - 3 2 6 2 - 0 0 0 A2AZVR3
lCCOX381X5100C4 2 C A P A C I T C ~ I F X D CER D I E L , 0 . 0 0 0 3 3 U F , 5%, l O O V ( 5 6 2 8 9 )
9 1 3 - 3 1 1 7 - 0 7 0 b2ACC15
RI:55075OOF 2 R E S I S T O 2 r F X D F I L M , 7 5 0 OHMS, 1 % ~1/6W ( 8 1 3 4 9 )
705-0900-000 AZA2R69
RCR07G222KS 2 R E S I S T C R t F X D CMPSNI 2 . 2 K , l o % , 1/4W ( 8 1 3 4 9 1
7 4 5 - 0 7 6 1 - 0 0 0 A2.42R68
CK066X104K 2 CAP.&CITOR,FSD CER D I E L , O . l U F , PORMlO%r l O O V ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A2AZC50
RN55E6042B 2 RESISTC2,FXD F I L M , 60.4K, 0 . 1 % ~ l/lOW (81349)
705-5976-980 A2A2R34
RN55E4872B 2 RESISTOR,FXD F I L M , 4 8 . 7 K y 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 6 - 8 0 0 AZA2R33
RN55E5362B 2 RESISTCR,FXD F I L M , 5 3 . 6 K s 0.1%, l / l O W ( 8 1 3 4 9 )
705-5976-880 A2A2R39
F404$6PC 2 INTEG2ATED C I R C U I T ( E S D S ) ( 0 7 2 6 3 ) 3 5 1 - 8 1 5 9 - 2 1 0 A2A2U5
F4049BFC 2 ItdTEGRATED C I R C U I T ( ESDS ( 0 7 2 6 3 3 5 1 - 8 1 5 9 - 2 1 0
A2A2UlO
M39003-01-2286 2 CAFACITOR,FXD E L C T L T , 1 0 U F , 1 0 % ~2 0 V ( 8 1 3 4 9 )
184-9056-460 A2A2C34
MS75089-11 2 C O I L P R F lOOUH ( 9 6 7 0 6 I 2 4 0 - 2 7 1 5 - 3 7 0 A 2 A Z L 1 1
CK05BX101K 2 CAPACITORvFXD CER D I E L , 1 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
9 1 3 - 4 0 0 6 - 0 0 0 AZAZC47
M39003-01-2286 2 C A F A C I T C 2 , F X D E L C T L T , 1 0 U F , 1 0 % ~ZOV ( 8 1 3 4 9 )
1 8 4 - 9 0 9 6 - 4 6 0 A2AZC35
CK05BX101K 2 CAPACITOR,FXD CER D I E L , 1 0 0 P F ~l o % , 2 0 0 V ( 8 1 3 4 9 )
9 1 3 - 4 0 0 6 - 0 0 0 A2A2C46
LM103H 2 INTEGPATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 7 9 - 0 2 0 A 2 A 2 U 9
RCR07GlSZKS 2 RESISTCR,FXD CKPSN, 1 . 5 K , l o % , 1/4W ( 8 1 3 4 9 1
745-0755-000 A2A2955
RCR07G473KS 2 RESISTOR,FXD CtlPSN, 4 7 K 9 1 0 x 9 1/4W ( 8 1 3 4 9 )
745-0809-000 A2A2F59
PElSO-1-80-10 2 CAPACITCR,FXD PLSTC D I E L , O . l U F , l o % , SOV ( 2 7 7 3 5 )
933-1039-230 A2A2C41
PElS0-1-80-10 2 CAPACITOR,FXD PLSTC D I E L , O . l U F , 1 0 % ~8 0 V ( 2 7 7 3 5 )
933-1039-230 A2A2C42
- -
GROUP ASSEMBLY PARTS LIST
-I
FIG- z UNITS USABLE
ITEM PART N O XZ DESCRIPTION PER
ASSY
ON
CODE
I
D E T A I L 13 DETAIL D
DETAIL A DETAIL C
DETAIL A
DETAIL B
-- -
5:;T::;::::,:;:s '
%
o
.&
ie
--
G?.". PRec.L.0..
roe ".*DL*C ~
DETAIL C
DETAIL D
+ UNITS U S A B L E
FIG- z
w
PART N O n DESCRIPTION PER ON
ITEM
Z ASSY CODE
..33 -71 22 -- 22 22 33 44 -- 00 12 00 2
2
CONTACT,ELEC
COIITACT, ELEC
16
16
D:174175N 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 E 0 0 - 0 1 0 A2A3U10 1
S'474LSEbN 2 IIiTEG74TED C I R C U I T ( 0 4 7 1 3 3 3 5 1 - 1 6 9 6 - 0 1 0 A 2 A 3 U l l 1
629-9312-001 2 I t I T E G R T E D CST, FROM A:A3Ul2 1
5:!74LZ175N 2 IF:TEGR4TED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A2A3U34 1
S!474LS%N 2 1t;TEGRATED C I K C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 6 9 8 - 0 1 0 A2A3U35 1
623-9912-002 2 INTEGRATED CKT, FFO?I AZL3U36 1
CKObBX104K 2 C 4 P . ~ C I T O ? , F X D CER D I E L , O . l U F , FORMlOZ, l O 0 V ( 6 1 3 4 9 ) 1
9 1 3 - 5 0 1 9 - 4 4 0 A2A3C11
St174LS174N 2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 AZA3U60 1
St174 L S 1 7 5 N 2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A?A3U59 1
S1174E3AN 2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 7 5 2 - 0 1 0 C2A3C58 1
DM74155)4 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 3 5 1 - 7 6 8 1 - 0 1 0 A,C3t!C+ 1
DM74175N 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 8 0 0 - 0 1 0 A2A3US3 1
N74161A 2 It4TEGRATED C I R C U I T ( 1 8 3 2 4 ) 3 5 1 - 7 7 5 0 - 0 1 0 A2A3U82 1
316A472 2 RESISTC4 NTKS 4 . i K , 5 % , 1 . 2 5 A PK6 ( 0 1 1 2 1 ) 1
3 5 0 - 4 0 3 0 - 0 2 0 A2A3UlOG
DP174LSOZN 2 INTESRATED C I R C U I T L C S I C GATE ( 2 7 0 1 4 ) 3 5 1 - 1 5 2 3 - 2 2 0 1
A2A31J107
SN74LS174N 2 INTEGqATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A2A3U106 1
CK069X104E 2 CAPACITO2.FXD CER D I E L , O . l U F , FCZClOZ, lOGV ( 1 1 3 4 9 ) 1
9 1 3 - 5 0 1 9 - 4 4 0 AZA3C23
St474LS175N 2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A?C3U105 1
Sti74LS175N 2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A?A3U104 1
S!174LS174f4 2 INTEEP4TFD C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 3 A 2 1 3 U 1 0 3 1
D37489J 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 351-7676-0:O AZA3US1 1
314A152 2 RESISTO? NTUK D U 4 L - I N - L I t ! E , 1.5K.p 2x9 1 2 5 V ( 0 1 1 2 1 ) 1
3 5 0 - 4 0 2 7 - 1 3 0 AcA3USO
LlP174126t.1 2 INTEG4ATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 7 2 6 - 0 1 0 A2A3U79 1
CK066X104K 2 CAFACITC2,FXD CER D I E L , O . l U F , PC?P110%, lOOV ( 6 1 3 4 9 ) 1
9 1 3 - 5 0 1 9 - 4 4 0 A2A3C15
DMi4126t.I 2 INTECPATED C I R C U I T ( 2 7 0 1 4 ) 351-77;8-010 A2A3U55 1
DM7469-1 2 It1TEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 6 7 6 - 0 2 0 A2A3U56 1
Dil74157t.I 2 ItITEGRATED C I R C l J I T ( 2 7 0 1 4 ) 351-77;5-010 A2C.3U57 1
StI74S3CN 2 It4TEGETED CIRCUIT ( 0 1 2 0 5 3 5 1 - 7 7 5 2 - 0 1 0 A243U31 1
StI7417GN 2 IIITEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 8 1 7 - 0 1 0 A 2 A j U 3 2 1
St474LS175N 2 ItITEG?ATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A X 3 U 3 3 1
CK06EX104K 2 CAPACITORjFXD CER D I E L , O . l U F , FOE3lO%, l C O V ( 8 1 3 4 9 ) 1
9 1 3 - 5 0 1 9 - 4 4 0 A2A3C3
SN7483AN 2 INTEGRATED C I P C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 7 5 2 - 0 1 0 AZA3U7 1
314A152 2 RESISTOR NTLGi; DU4L-It4-LIb!E, 1 . 5 K - 2%, 1 2 5 V ( 0 1 1 2 1 1
3 5 0 - 4 0 2 7 - 1 3 0 A2A3US
S1174170N 2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 8 1 7 - 0 1 0 A2A3U9 1
Sb474LSF;SN 2 ItiTEGFATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 6 9 8 - 0 1 0 A2A3U13 1
St474S3At.I 2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 7 5 2 - 0 1 0 A2A3U14 1
CP64AU16-0000MHZ 2 CRYSTAL UIIIT,QTZ 16.00000MHZ ( 8 1 3 + 9 ) 2 6 9 - 7 0 8 2 - 0 1 0 1
AZA3Y1
Dt15C040D300WV 2 CAPACITCR,FXD MICA D I E L , 4 P F 1 PORM 0 . 5 F F t 3 0 0 V 1
( 7 2 1 3 5 ) 9 1 2 - 4 1 4 1 - 0 6 0 A2A3C8
53SOllCOP092R 2 CAPACITCQYVAR CER D I E L , 5 . 5 TO 1 6 F F , 350V ( 7 2 9 8 2 ) 1
9 1 7 - 1 2 2 2 - 0 0 0 A2A3C7
RCP07G103KS 2 RESISTCR,FXD CMFSf1, 1 0 K ~1 0 % ~1/4W ( 8 1 3 4 9 ) 1
7 4 5 - 0 7 6 5 - 0 0 0 A2A3R35
RCR07G472KS 2 RESISTC2,FXO CMFSN, 4.7K9 l o % , 1 / 4 U ( 8 1 3 4 9 ) 1
7 4 5 - 0 7 7 3 - 0 0 0 A2A3R21
2E4918 2 TRAtlSISTC2 ( 0 7 9 1 0 3 5 2 - 0 4 4 0 - 0 0 0 A 2 A 3 4 1 1
KC7404P 2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 7 6 3 0 - 0 1 0 A2A3U17 1
SN7463AN 2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 7 5 2 - 0 1 0 A 2 A j U 1 8 1
RCR07G333KS 2 RESISTORsFXD CIIFSN, 33K, 107.9 1/4W ( 8 1 3 4 9 ) 1
7 4 5 - 0 6 0 3 - 0 0 0 A2A3R3
DM5FlOlJ050UV 2 CAPACITCR,FXD MICA D I E L , l O O P F t 5 % ~5 0 V ( 7 2 1 3 6 ) 1
9 1 2 - 4 1 4 1 - 0 5 0 A2A3C9
I- UNITS USABLE
FIG- z
PART NO W DESCRIPTION PER ON
ITEM ASSY CODE
I
2 C A P A C I T O R , F X D CER D I E L I O . l U F , P O R M l O % r l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C4
2 1IITEGR.iTED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 6 9 6 - 0 1 0 A 2 A 3 U 4 6
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 6 9 8 - 0 1 0 A 2 A 3 U 4 7
2 ItiTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A2A3U48
2 I N T E G R A T E D CKT, PROM A 2 A 3 U 7 0
2 INTEGRATED CKT, F R 3 t l A 2 A 3 U 7 1
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 6 ' 3 8 - 0 1 0 AZA3U72
2 CAPACITDR,FXD CER D I E L , O . l U F , PORMlO%, l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C16
2 C A P A C I T O R V F X D CER D I E L , 1 5 P F , P O R f l l O Z , 2 0 0 V ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 0 3 0 A2A3C36
2 C A P A C I T C 2 , F X D CER D I E L , O . l U F , P O R M l O Z r l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C35
2 R E S I S T C R , F X D F I L M , 3 . 8 3 K , 1 % 1/8W ~ (81349)
705-1024-000 CZA3R27
2 RESISTCR,FXD F I L M , 1 . 2 7 K ~ 1%. 1/6W ( 8 1 3 4 9 )
705-1001-000 A2A3226
2 R E S I S T C R , F X D CMFSN, 4 . 7 K 9 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 7 3 - 0 0 0 AEA3Q29
2 C A P A C I T O R l F X D CER D I E L , O . l U F , PORM10%, l O O V ( 8 1 3 4 9 )
013-5019-440 A2A3C34
2 RESISTOR,FXD F I L M , 1 0 . 2 K y 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
705-5975-490 AZA3R11
2 C A P A C I T O R , F X D CER D I E L , O.1UFv P O R M l O % r l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C31
2 INTEG2ATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 1 5 2 - 0 1 0 A2A3U95
2 COH'\'ERTER ,DA ( 2 4 3 5 5 3 5 1 - 1 2 7 8 - 0 1 0 A P A 3 U 1 1 8
2 SCCBET,IC ( 2 3 8 8 0 ) 2 2 0 - 0 0 7 5 - 0 5 0
2 SPACERISLEEVE
2 C A F A C I T O R , F X D CER D I E L P O . l U F , PORM10%, l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C39
2 CAF:\CITOR ,FXD CER D I E L , O . l U F , PCRM10%, l O O V ( 8 1 3 4 9 )
913-5019-440 AZA3C33
2 r R E S I S T C 4 , F X D CEPSN, l 0 K 1 l o % , 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 6 5 - 0 0 0 A2A3R30
2 COIL,RF lO0UH ( 9 6 3 C 6 3 2 4 0 - 2 7 1 5 - 3 7 0 A 2 A 3 L 5
2 C A F A C I T O 2 , F X D CER D I E L , 3 3 P F , FORMlO%, 2 0 0 V ( 8 1 3 4 9 )
913-5019-070 A2A3C37
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 4 0 - 0 2 0 A 2 A 3 U 1 1 7
2 ItiTEGRATED C I R C U I T ( 0 1 2 0 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A 2 A 3 U 1 1 6
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 5 0 A Z A 3 U 1 1 5
2 C A P A C I T C 2 , F X D CER D I E L , O . l U F , PORMlOZ, l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C32
2 R E S I S T O R p F X D F I L M , 1 0 K , 1 % ~1 / 8 W ( 8 1 3 4 9 )
705-1044-000 A2A3R24
2 R E S I S T O R , F X D F I L M , 1 0 K , 1%, 1/8W ( 8 1 3 4 9 )
705-1044-000 A2A3R23
2 R E S I S T C R , F X D F I L M , 1 0 K t 1 % 1/8W ~ (81349)
705-1044-000 A2A3R25
2 INTEGRATED C I R C U I T ( E S D S ) ( 2 4 3 5 5 ) 3 5 1 - 1 1 5 9 - 0 5 0
A2A3U92
2 SCCKET,IC ( 2 3 5 8 0 ) 2 2 0 - 0 0 7 5 - 0 3 0
2 C A P A C I T C R , F X D CER D I E L , O . l U F , FORMlO%, l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C29
2 COILYRF lOCUH ( 9 6 9 0 6 ) 2 4 0 - 2 7 1 5 - 3 7 0 A2A3L6
2 CAPAC:TCR,FSD CER D I E L , O . l U F , FORMlO%, l O O V ( 8 1 3 4 9 )
913-5019-440 A243C30
2 CAPACITOR,FXD CER D I E L , O . l U F 9 PDRMlO%, l O O V ( 8 1 3 4 9 )
913-5019-440 A2A3C21
2 C A P A C I T C R , F X D CER D I E L , O . O l U F , PORMlO%, l O O V
( 8 1 3 4 9 ) 913-5019-200 A2A3C38
t-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
Rf'Mod1~lntorAssembly A3
Fi,ytrre 9
+ UNITS USABLE
FIG- z
w
ITEM PART NO o DESCRIPTION PER ON
z ASSY CODE
I-
z UNITS USABLE
FIG- W PER ON
ITEM PARTNO DESCRIPTION
z ASSY CODE
I-
FIG- U N I T S USABLE
PART N O z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
+ UNITS USABLE
FIG- z
w
ITEM PART N O o DESCRIPTION PER ON
Z ASSY CODE
SC9017TZ-50-OHM 2 RESISTOR,RF ( 2 4 6 0 2 ) 3 5 1 - 9 0 5 4 - 0 2 0 A 3 A l R 2 6
Vt:20020-4B 2 C O I L j R F 0 . 8 5 K , PORI120% ( 0 2 1 1 4 ) 2 4 0 - 2 6 7 9 - 0 4 0 A 3 A l L 4
RCR05G510JS 2 RESISTCR,FXD CMFSN, 5 1 0 H t j S 1 5 % r 1/8W ( 8 1 3 4 9 )
7 4 5 - 1 8 6 3 - 1 8 0 A 3 A l R 3 7 ( E F F REV LTR K )
101KUSX500 2 CAPACITOP,FXD CER D I E L , 1 0 0 F F ~l o % * 5 0 0 V ( 2 9 9 9 0 )
9 1 4 - 3 0 9 8 - 5 1 0 A3.41C14 ( E F F TO REV LTR K )
471KMSX200 2 CAP4CITC9,FXD CER D I E L , 47OPFY l o % , l O O V ( 2 9 9 9 0 )
9 1 4 - 3 9 9 5 - 6 4 0 A 3 C l C 1 4 ( E F F REV LTR K )
634-9307-001 2 CAPACITOR K I T (NON-FROCURABLE I T E U ) ( E F F REV LTR H I
2RZCUSX500 3 CAPACITORIFXD CER D I E L I 2 . 2 P F y POFM 0 . 2 5 P F ~ 5 0 0 V
( 2 9 7 9 0 ) 914-3098-710 A3AlC29
4R3CMSX500 3 C A P A C I T O 1 , F X D CER D I E L I 4 . 3 P F s PORM 0 . 2 5 P F ~ 5 0 0 V
(299903 914-30Q8-720 A3AlC?9
RCR05G101JS 2 RESISTOR,FYD CUPSN, 1 0 0 CHKSt 5 % r 1/8W ( 8 1 3 4 9 )
7 4 5 - 1 2 3 6 3 - 2 5 0 A 3 A l R 2 5 ( E F F TO REV LTR J )
634-9749-001 2 RESISTOR K I T (NON-PROCURABLE I T E M ) ( E F F REV LTR J )
RCR05G201JS 3 RESISTORBFXD CMPSN, 2 0 0 O H t l S l 5 % ~1/EW ( 8 1 3 4 9 )
745-1863-320 A3AlR25
RCR05G221JS 3 RESISTOR,FXD CMPSN, 2 2 0 OHMS, 5 % , 1/8W ( 8 1 3 4 9 )
745-1663-330 A3AlR25
RCR05G241JS 3 RESISTOR,FSD CMFSN, 2 4 0 OHMS, 5%, 1/8W ( 8 1 3 4 9 )
745-1853-340 A3AlR25
RCR05GZilJS 3 RESISTOP,FXD CMPSNI 2 7 0 OHMS, 5 % , l / 8 W ( 8 1 3 4 9 )
745-1863-350 A3AlR25
RCR05G301JS 3 R E S I S T C R , F X D CUPSN, 3 0 0 OHMS, 5%, 1/6W ( 8 1 3 4 9 )
745-1863-360 A3AlR25
RCR05G331JS 3 RESIST@R,FXD CMPSII, 3 3 0 OHMS, 5 % , 1/8W ( 8 1 3 4 9 )
745-1863-370 A3AlR25
RCR05G361JS 3 RESISTOR9FXD CMFSN, 3 6 0 OHMS, 57.9 1/6W ( 8 1 3 4 9 )
745-1863-350 A3AlR25
RCR05G391JS 3 RESISTCR,FSD CMPSN, 3 9 0 OHMS, 5 % , l / 8 w ( 6 1 3 4 9 )
745-1863-390 A3RlR25
RCR05G431JS 3 RESISTCR,FXD CHFSN, 4 3 0 OHMS, 5 % , 1/8W ( 8 1 3 4 9 )
745-1663-400 A3AlR25
RCR05G471JS 3 RESISTORpFXD CtlPSN, 4 7 0 OHMS, 57.9 1/8W ( 8 1 3 4 9 )
745-1863-410 A3AlPZ5
RCR05G511JS 3 RESISTOR,FXD CMFSN, 5 1 0 OHM, 5%, l / e w ( 8 1 3 4 9 )
745-1863-420 A3AlR25
RCR05G561JS 3 RESISTOR,FXD CMFSN, 5 6 0 OHMS, 5 % ~1/6W ( 8 1 3 4 9 )
745-1863-430 A3AlR25
RCR05G621JS 3 RESISTOR,FXD CMP5.14, 6 2 0 OHMS, 5 % r 1/8W ( 8 1 3 4 9 )
745-1863-440 A3AlR25
RCR05G681JS 3 RESISTORIFXD CMPSH, 6 8 0 OHMS, 57.9 1/8W ( 8 1 3 4 9 )
745-1863-450 A3AlR25
RCR05G751JS 3 RESISTCR,FXD CHPSt4, 7 5 0 OHMS, 5%, 1/6W ( 8 1 3 4 9 )
745-1863-460 A3AlRC5
RCR05G821JS 3 RESISTOR,FXD CMFSNV 8 2 0 OHMS, 5 % 1/PW ~ (81349)
745-1863-470 A3AlR25
RCR05G911JS 3 RESISTCR,FXD CHFSN, 9 1 0 OHMS, 5 % ~1/8W ( 8 1 3 4 9 )
745-1853-480 A3AlR25
RCR05G102JS 3 RESISTCR,FXD CMPSN, 1 K , 5 % , 1/8W ( 8 1 3 4 9 )
745-1863-490 A3AlR25
RCRO5G112JS 3 R E S I S T O R j F X D CMPSN, 1 . 1 K , 5 % ~1/8W ( 8 1 3 4 9 )
745-1863-500 A3AlR25
RCR05G132JS 3 RESISTORPFXD CKPSN, 1 . 3 K v 5 % r 1/8W ( 8 1 3 4 9 )
745-1863-520 A3AlR25
RCR05G162JS 3 R E S I S T O Z r F X D CMFSN, 1 . 6 K , 5%. 1/PW ( 8 1 3 4 9 )
745-1863-540 A3AlRZ5
RCR05G202JS 3 RESISTOR,FXD CMPSN, :K, 5 % ~1/8W ( 8 1 3 4 9 )
-.
/+5-1853-560 A3AlR25
RCR05G24ZJS 3 RESISTCR 9 FXD CMPSN, 2 . 4 K 5 % . 1/8W ( 8 1 3 4 9
745-1863-560 A3AlR25
C
z UNITS U S A B L E
FIG- W PER ON
PARTNO a DESCRIPTION
ITEM ASSY CODE
Z
D~wcod~rltrtor/ALCAssembly A3A2
Fzg7rre 11 (Sheet 1 of 2)
Revised 15 October 1 9 H O
Scans by ArtekMedia © 2008 parts list 523-0769256
Revised 15 O c t o b ~ r1980
.
parts list 523-0769256 Scans by ArtekMedia © 2008
+
z UNITS USABLE
FIG- W PER ON
PART N O DESCRIPTION
ITEM P
ASSY CODE
Z
2 CAPACITCR,FXD M I C A D I E L , 5 1 P F , 5%, 5 0 V ( 7 2 1 3 6 )
9 1 2 - 4 1 4 1 - 3 0 0 A3A2C56
2 CAPACITCR,FXD PLSTC D I E L , 5.6UFs 5 % 5~ 0 V ( 5 6 2 8 9 )
933-1084-370 A3A2C35
2 RESISTOR,FXD F I L M , 1 1 K , 1%, 1/8W ( 8 1 3 4 9 )
705-1046-000 A3A2R55
2 CAPACIT09,FXD M I C A D I E L , 2 0 P F 9 PORM 0.5PFp l O O V
( 7 2 1 3 6 ) 912-4141-150 A3A2C1
2 CAPACITCR,FXD M I C A D I E L , 5 1 P F , 5 % ~5 0 V ( 7 2 1 3 6 )
9 1 2 - 4 1 4 1 - 3 0 0 A3A2C2
2 CAPACITORIFXD M I C A D I E L , 5 P F , PORM 0 . 5 P F s 3 0 0 V
( 7 2 1 3 6 ) 912-4141-010 A3A2C55
2 INTEGqATED C I R C U I T ( 3 4 3 7 1 ) 3 5 1 - 1 2 8 1 - 0 1 0 A 3 A 2 U l l
2 R E S I S T C 4 r F X D F I L M , 9 0 . 9 OHMSs 1x9 1/8W ( 8 1 3 4 9 )
705-0946-000 A3A2R51
2 CAPACITOR,FXD CER D I E L , l U F , 2 0 % . 5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3AZC4
2 RESISTORVFXD F I L M , l C K , 1 % ~1/8W ( 8 1 3 4 9 1
7 0 5 - 1 0 4 4 - 0 0 0 A3A2R36
2 R E S I S T O 9 , F X D F I L M , 1 0 K , 1%. 1/PW ( 8 1 3 4 9 )
7 0 5 - 1 0 4 4 - 0 0 0 A 3 A 2 R 1 4 ( E F F TO REV LTR M I
2 RESISTOR,FXD F I L M , 4 . 5 3 K p 1 % 1/PW ~ (81349)
7 0 5 - 3 6 0 5 - 3 1 0 A 3 A 2 R 1 4 ( E F F REV LTR M TO REV LTR N )
2 R E S I S T C R p F X D F I L M , 6 . 1 9 K 9 1 % ~1/EW ( 8 1 3 4 9 )
7 0 5 - 1 0 3 4 - 0 0 0 A 3 A 2 R 1 4 ( E F F REV LTR N TO REV LTR R )
2 RESISTCR,FXD F I L M , 1 0 K , 1x9 1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 4 4 - 0 0 0 A 3 A 2 R 1 4 ( E F F REV LTR R TO REV LTR U )
2 RESISTOR,FXD F I L M , 1 4 K 1 1 % ~1/SW ( 8 1 3 4 9 )
7 0 5 - 1 0 5 1 - 0 0 0 A 3 4 2 R 1 4 ( E F F REV LTR U )
2 R E S I S T O S s F X D F I L M , 9 0 9 OHNS, 1 % 1/8W ~ (81349)
705-0094-000 A3A2R81
2 CAPACITORsFXD M I C A D I E L , 3 3 P F , 5 % ~5 0 V ( 7 2 1 3 6 )
9 1 2 - 4 1 4 1 - 2 2 0 A 3 A 2 C 1 7 ( E F F REV LTR N )
2 SEMICOND D E V I C E ( 8 1 4 8 3 ) 3 5 3 - 2 7 1 4 - 0 0 0 A 3 A 2 V R 1 ( E F F TO
REV LTR L )
2 SEtlICOND D E V I C E ( 0 4 7 1 3 ) 3 5 3 - 6 4 8 1 - 1 7 0 A 3 A 2 V R 1 ( E F F
REV LTR L )
2 CAPACITOR,FXO M I C A D I E L . 5 P F p PORM 0 . 5 P F r 3 0 0 V
( 7 2 1 3 6 ) 9 1 2 - 4 1 4 1 - 0 1 0 A 3 A 2 C 5 3 ( E F F TO REV LTR P )
2 CAPQCITCRpFXD M I C A D I E L , 1 0 P F p FORM 0 . 5 P F , 3 0 0 V
( 7 2 1 3 6 ) 9 1 2 - 4 1 4 1 - 0 2 0 A 3 A 2 C 5 3 ( E F F REV LTR P I
2 R E S I S T O R t F X D F I L M , ?OOK, 1x9 1/6W ( 8 1 3 4 9 )
705-3604-150 A3A2R15
2 CAPACITOR,FXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
913-3279-270 A3A2C10
2 TRCNSISTCR ( 0 7 2 6 3 ) 3 5 2 - 0 6 6 1 - 0 2 0 A 3 A 2 Q 1
2 R E S I S T O R s F X D F I L M , 3 . 8 3 K 9 l % r 1/8W ( 6 1 3 4 9 )
7 0 5 - 1 0 2 4 - 0 0 0 A3AZR22
2 TRANSISTOR ( 0 7 2 6 3 ) 3 5 2 - 0 6 6 1 - 0 2 0 A 3 A 2 9 3
2 RESISTCR,FXD F I L M * 3 . 2 4 K 9 1%, 1/6W ( 8 1 3 4 9 )
705-3605-240 A3A2R20
2 R E S i S T O 2 , F X D F I L M , 2 . 5 5 K ~ 1%, l / e M ( 8 1 3 4 9 )
7 0 5 - 3 6 0 5 - 1 9 0 A 3 A Z R 1 8 ( E F F TO REV LTR V )
2 RESISTOR,FXD F I L M , 2 . 1 5 K , 1%. 1/3W ( 8 1 3 4 9 )
7 0 5 - 1 0 1 2 - 0 0 0 A 3 4 2 R 1 8 ( E F F REV LTR V )
2 RESISTOR,FXD F I L M , 9 . 3 1 K s 1 % 1/8W ~ (81349)
7 0 5 - 3 6 0 5 - 4 6 0 A3A2R16
2 CAPACITO2,FXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
913-3279-270 A3A2C9
2 INTEGYATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 1 5 3 - 0 2 0 A 3 A Z U 8
2 RESISTCR,FXD F I L M , l K , 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 3 - 5 3 0 A3A2PSO
I FIG-
ITEM I PART N O DESCRIPTION
I
UNITS USABLE
APER
SSY ( CO
ODNE 1
2 CAPACITOR,FXD M I C A D I E L , 5 P F s PORN 0 . 5 P F s 3 0 0 V
( 7 2 1 3 6 1 9 1 2 - 4 1 4 1 - 0 1 0 A3AZC54
2 RESISTORpFXD CMPSN, 8 . 2 K t 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 8 2 - 0 0 0 A3AZR34
2 RESISTCR,FXD F I L M , 2 7 . 4 K s l % r 1/8W ( 8 1 3 4 9 )
705-1065-000 A3A2R9
2 CAPACITOR,FXD CER D I E L , l U F , 2 0 % , 5 0 V ( 1 6 5 4 6 1
913-3279-270 A342C7
2 CAPACITCR,FXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 1
9 1 3 - 3 2 7 9 - 2 7 0 A3A2C6
2 J A C K , T I P LY'r ( 7 4 9 7 0 3 6 0 - 0 4 8 4 - 0 1 0 A 3 A 2 T P 4
2 J A C K V T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 6 4 - 0 1 0 A3.42TP5
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 1 5 3 - 0 2 0 A 3 A 2 U 7
2 RESISTOR,FXD CKPSN, 8 . 2 K , 1 0 % ~1/4W 1 8 1 3 4 9 3
7 4 5 - 0 7 8 2 - 0 0 0 A3AZR78
2 RESISTOR,FXD F I L M , 3 8 . 3 K , 1 % 1~ / 8 U ( 8 1 3 4 9 )
7 0 5 - 1 0 7 2 - 0 0 0 A 3 A 2 R 3 2 ( E F F TO REV LTR T I
2 RESISTORvFXD F I L M , 2 7 . 4 K ~ 1%, 1/EW ( 8 1 3 4 9 1
7 0 5 - 1 0 6 5 - 0 0 0 A 3 A 2 R 3 2 ( E F F REV LTR T I
2 P I N , INDEXIRG
2 RESISTOR,FXD F I L N , 1 0 K , 1 % ~1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 4 4 - 0 0 0 A3A2R30
2 R E S I S T C R I F X D F I L M , 3 0 1 K , 1 % ~1/6W ( 8 1 3 4 9 1
705-1115-000 A3A2R40
2 INTEGRATED C I R C U I T ( 0 3 8 7 7 1 3 5 1 - 1 2 3 7 - 0 1 0 A 3 A 2 U 6
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 9 5 - 0 3 0 A 3 A i U 3
2 CAPACITGA,FXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 1
913-3279-270 A3A2C24
2 RESISTOR,FXD CMPSN, l K , 5%, 1/4W ( 8 1 3 4 9 1
7 4 5 - 0 7 4 8 - 0 0 0 A3AZR45
2 CAPACITO?,FXD M I C A D I E L , 1 5 0 P F s 5%, 5 0 V ( 7 2 1 3 6 1
912-4141-400 A3A2C25
2 RESISTOR,FXD F I L M , 1 0 K , 1 % 1/8W ~ (813491
7 0 5 - 1 0 4 4 - 0 0 0 A3AZRA4
2 RESISTCF2,FXD F I L M , 5 . 1 1 K I 1 % , 1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 3 0 - 0 0 0 A3AZR48
2 R E S I S T C R s F X D F I L M , 1 0 K p 1 % 1/8W~ (81349)
7 0 5 - 1 0 4 4 - 0 0 0 A3A2R46
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 1 3 5 1 - 1 0 9 5 - 0 3 0 A 3 A 2 U 2
2 R E S I S T C R I F X D F I L M , 1 0 K , 1 % 1/8W~ (81349)
705-1044-000 A3A2R47
2 CAPACITOR,FXD M I C A D I E L V 1 5 0 P F s 5%, 5 0 V ( 7 2 1 3 6 1
9 1 2 - 4 1 4 1 - 4 0 0 A3A2C26
2 CAPACITCR,FXD CER D I E L , l U F , 2 0 % , 5 0 V ( 1 6 5 4 6 )
913-3279-270 A3AZC48
2 RESISTOR,FXD F I L M , l o O K , 1 % 1/8W ~ (81349)
705-1092-000 A3A2R61
2 CAPACITOR,FXO CER D I E L , l U F , 2 0 % , 5 0 V 1 1 6 5 4 6 1
913-3279-270 A3AZC28
2 RESISTOR,FXD CMPSN, 0.10MEG0, 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 6 2 1 - 0 0 0 A3A,R53
2 R E S I S T O R t F X D CMPSN, O.1OMEGOv 1 0 % ~1/4W ( 8 1 3 4 9 )
745-0321-000 A3A2R57
2 RESISTOR,FXD CMPSNI 1 0 K , 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 6 5 - 0 0 0 A3A2R56
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 9 5 - 0 3 0 A 3 A Z U 1
2 CAPLCITOR,FXD CER D I E L , 1 U F s 2 0 % ~5 0 V ( 1 6 5 4 6 )
913-3279-270 A3A2C29
2 CCPACITCR,FXD M I C A D I E L , 1 5 0 P F s 5 % , 5 0 V ( 7 2 1 3 6 1
912-4141-400 A3A2C27
2 RESISTCRPFXD F I L N , 10K, 0 . 1 % ~ l / l O W ( 8 1 3 4 9 1
7 0 5 - 5 9 7 5 - 4 7 0 A 3 A 2 R 5 0 ( E F F TO REV LTR R l
Rerlised 15 October*1!1'KO
Scans by ArtekMedia © 2008 parts list 523-0769256
+ UNITS USABLE
FIG- z
w
ITEM PART NO n DESCRIPTION PER ON
Z ASSY CODE
2 RESISTOR,FXD F I L M , 2.3ZK, 0 . 1 % ~ l / l O W ( 8 1 3 4 9 1
7 0 5 - 5 9 7 4 - 2 4 0 A3A2R50 ( E F F REV LTR R )
2 RESISTCR,FXD F I L M , 9 . 3 1 K 1 0.1;!, l / l O W (61349)
7 0 5 - 5 9 7 5 - 4 1 0 A3A2R54 I E F F TO REV LTR R )
2 RESISTCRIFXD F I L M , 2K9 O . l % r l / l O U ( 8 1 3 4 9 )
7 0 5 - 5 9 7 4 - 1 2 0 A3A2R54 ( E F F REV LTR R )
2 RESISTOR,FXD F I L M , 1 0 . 5 K , 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 5 - 5 1 0 A3AZR52 ( E F F TO REV LTR R )
2 RESISTOR,FXD F I L M , 2.55Kv 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 4 - 3 2 0 A3A2R52 ( E F F REV LTR R )
2 RESISTOR,FXD F I L M , 2 0 . 5 K t 0.1%, l / l O W ( 8 1 3 4 9 3
7 0 5 - 5 9 7 6 - 0 8 0 A3AZR49 ( E F F TO REV LTR R )
2 RESISTORtFXD F I L M * 5.62K9 0 . 1 % ~ l / l O U ( 6 1 3 4 9 )
7 0 5 - 5 9 7 4 - 9 3 0 A3A2R49 ( E F F REV LTR R )
2 RESISTO2,FXD F I L M , ICOKI 1%, 1/6W ( 8 1 3 4 9 )
7 0 5 - 1 0 9 2 - 0 3 0 A3A2R60
2 RESISTCR,VAR 1 0 K j 5 % ~3/4W ( 8 1 3 4 9 ) 3 8 1 - 1 8 5 3 - 3 0 0
A342P6
2 RESISTO2,VAR 10Kp 5%. 3/4W ( 8 1 3 4 9 ) 3 8 1 - 1 8 5 3 - 3 0 0
A3ACR7
2 RESISTOR,VAR 1 0 K , 5%, 3/4W ( 8 1 3 4 9 ) 3 8 1 - 1 6 5 3 - 3 0 0
A31'2R3
2 J A C K , T I P KHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A2TP3
2 J A C K , T I P UHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A2TF2
2 J A C K , T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A2TP1
2 COIL,RF 39UH ( 9 6 9 0 6 ) 2 4 0 - 2 7 1 5 - 3 2 0 A 3 A P L l
2 RESISTORIFXD CHFSN, 10K, 1 0 % ~1 / 4 H ( 8 1 3 4 9 )
7 4 5 - 0 7 8 5 - 0 0 0 A3A2R72
2 RESISTOR,FXD CMFS:i, 1 0 K , 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 8 5 - 0 0 0 A3A2R73
2 CONTCCT,ELEC
2 CAPACITOR,FXD PLSTC D I E L , 0 . 3 9 U F I 2%, 5 0 V ( 5 6 2 8 9 1
9 3 3 - 0 2 6 4 - 2 0 0 A3A2C30
2 RESISTOR,FXD F I L M , 1 1 3 K , 1 % ~ 1/8W ( 8 1 3 4 9 )
7 0 5 - 3 6 0 4 - 0 3 0 A3AZR64
2 RESISTC2,FXD F I L M , 1 1 3 K , 1 % 1/8W ~ (61349)
7 0 5 - 3 6 0 4 - 0 3 0 A3A2F65
2 RESISTORjFXD F I L M , 5 6 . 2 K s 1 % ~ 1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 8 0 - 0 0 0 A3A2R66
2 CAPACITOR,FSD PLSTC D I E L , O.lUF, 2 % ~5 0 V ( 5 6 2 8 9 )
9 3 3 - 0 2 6 4 - 1 3 0 A3A2C39
2 RESIST07,FXD F I L M * lOOKs 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 7 - 4 1 0 A3A2G63
2 RESISTCR,FXD F I L M , l o O K , 1 % , 1/6W ( 8 1 3 4 9 )
7 0 5 - 1 0 9 2 - 0 0 0 A3AZR68
2 RESISTOR,FXD F I L M , 49.9Ks 1 % ~1/6W ( 8 1 3 4 9 )
7 0 5 - 3 6 0 5 - 8 1 0 A3A2R67
2 CAFACITOR,FXD M I C A D I E L , 1 0 P F , PORM 0.5PFp 3 0 0 V
( 7 2 1 3 6 ) 9 1 2 - 4 1 4 1 - 0 2 0 A3AZC43
2 CAPACITCR,FXD MICA D I E L , 1 0 P F , PORM 0.5PFp 3 0 0 V
( 7 2 1 3 6 1 9 1 2 - 4 1 4 1 - 0 2 0 A3AZC40
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 1 3 5 1 - 1 0 4 0 - 0 2 0 A3A2U18
2 CAPACITOR,FXD CER D I E L , l U F , 20%, 5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A2C41
2 CABLE ASSEMBLY A3A2W2
3 CONTACTPELEC ( 7 1 4 6 8 3 7 1 - 0 1 8 3 - 0 0 0
2 CAPACITORpFXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A2C52
2 RESISTORpFXD CMFSNv 33K9 1 0 Z r 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 8 0 3 - 0 0 0 A3A2R69
2 CAPACITOR,FXD CER D I E L , l U F s 20%, 5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A2C44
+ UNITS USABLE
FIG- z
w
ITEM PARTNO DESCRIPTION
Z ASSY CODE
I-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM D
Z ASSY CODE
2 C A P A C I T O R l F X D M I C A D I E L , 5 P F , PORM 0.5PFs 3 0 0 V
( 7 2 1 3 6 ) 9 1 2 - 4 1 4 1 - 0 1 0 A 3 A 2 C 5 3 ( E F F REV LTR P )
2 CAPACITOR,FXD M I C A D I E L , 5 1 0 P F , 5 % , 5 0 0 V ( 7 2 1 3 6 )
912-2667-000 A3A2C12
2 RESISTOR,FXD F I L M , 2 0 0 K , 1 % , 1/8W ( 8 1 3 4 9 )
7 0 5 - 3 6 0 4 - 1 5 0 A 3 A z R 8 3 ( E F F REV LTR P I
2 RESISTOR,FXD F I L M , 1 0 K , 0.1%, l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 5 - 4 7 0 A3A2R10
2 RESISTOR,FXD F I L M , 15CK, 1 % 1/8W ~ (81349)
705-3604-090 A3A2R11
2 RESISTOR,FXD F I L M , 6 . 6 5 K 9 1%. 1/8W ( 8 1 3 4 9 )
705-3605-390 A3A2R12
2 CAPACITCR,FXD CER D I E L , l U F p 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3AZC42
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 4 0 - 0 2 0 A 3 A 2 U 1 5
2 RESISTORIFXD F I L M , l o O K , 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
705-5977-410 A3A2R79
2 RESISTOR,FXD F I L M , l O K p 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
705-5975-470 A3A2R42
2 CAPACITORvFXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A2C36
2 INTEGRATED C I R C U I T ( 3 4 3 7 1 ) 3 5 1 - 1 2 8 1 - 0 1 0 A 3 A 2 U 1 0
2 CAPACITOR,FXO CER D I E L , 1 U F s 207.9 5 0 V ( 1 6 5 4 6 )
913-3279-270 A3A2C37
2 CAPACITOR,FXD M I C A D I E L , 5 1 P F p 5 % ~5 0 V ( 7 2 1 3 6 )
912-4141-300 A3AZC34
2 RESISTOR,FXD F I L M , 1 . 5 8 K ~ 0 . 1 % , l / l O W ( 6 1 3 4 9 )
7 0 5 - 5 9 7 3 - 9 1 0 A 3 A 2 R 3 8 I E F F TO REV LTR R )
2 R E S I S T 0 4 , F X D F I L M , 2.21K9 0 . 1 % ~ l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 9 7 4 - 2 0 0 A 3 A 2 R 3 8 ( E F F REV LTR R TO REV LTR U )
2 RESISTORVFXD F I L M , 2 . 3 2 K ~ 0 . 1 2 , l / l O W ( 8 1 3 4 9 )
7 0 5 - 5 0 7 4 - 2 4 0 A 3 A 2 R 3 8 I E F F REV LTR U )
2 CAPACITORjFXD PLSTC D I E L , l U F , 5 2 , 5 0 V ( 5 6 2 8 9 )
933-1034-250 A3A2C33
2 CAPACITORsFXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 1
913-3279-270 A3A2C49
2 CAPACITORIFXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A2CSO
162 LMlOlAH 2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 1 0 4 0 - 0 2 0 A 3 A 2 U 1 4
163 DM5C1000300WV 2 CAPACITOR,FXD M I C A D I E L , 1 0 P F , PORM 0.5PF, 300V
( 7 2 1 3 6 ) 912-4141-020 A3A2C51
2 RESISTOR,FXD F I L M , 1 5 0 K , 1 % 1/8W ~ (81349)
705-3604-090 A3AZRi6
2 CAPACITORIFXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
913-3279-270 A3A2C46
2 RESISTOR,FXD CKPSN, O.lOMEG0,
745-0821-000 A3A2R27 - l o % , 1/4W ( 8 1 3 4 9 )
I-
z UNITS USABLE
FIG- w ON
PART N O n DESCRIPTION PER
ITEM
z ASSY CODE
I-
FIG- UNITS U S A B L E
PARTNO z
w DESCRIPTION PER ON
ITEM
1 ASSY CODE
2 INTEGRATED C I R C U I T ( 1 8 3 2 4 ) 3 5 1 - 1 2 6 7 - 0 2 0 A3A3U25
2 ItjTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U24
2 RESISTOR,FXD CHPSN, l K , 5 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 4 8 - 0 0 0 A3A3R7
2 INTEGRATED C I R C U I T ( 1 8 3 2 4 ) 3 5 1 - 1 2 6 7 - 0 2 0 A3A3U22
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A 3 A 3 U 2 1
2 CAPACITOR,FXD CER D I E L , 1UFs 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A3C4
2 INTEGRATED C I R C U I T ( 1 8 3 2 4 ) 3 5 1 - 1 2 6 7 - 0 2 0 A3A3U19
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U18
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U16
2 INTEGRATED C I R C U I T LOGIC GATE ( 2 7 0 1 4 ) 3 5 1 - 1 5 2 3 - 2 2 0
A3A3U15
2 CAPACITOR,FXD MICA D I E L I 3 3 0 P F , 5 Z r 5 0 V ( 7 2 1 3 6 )
9 1 2 - 4 1 4 1 - 4 9 0 A3A3C15
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 6 - 0 3 0 A3A3U13
2 INTEGPATED C I R C U I T LOGIC GATE ( 1 8 3 2 4 3 3 5 1 - 1 5 2 3 - 1 1 0
A3A3U12
2 RESISTCR,FXD CMPSN, l K , 1 0 % ~1/4W ( 8 1 3 4 9 )
745-0749-000 A3A3Rl
2 CAPACITOR,FXD CER D I E L , l U F , 2 0 % ~5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A3C10
2 INTEGRATED C I R C U I T F L I P FLOP ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 4 0
A3A3U3
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 6 - 0 3 0 A3A3U10
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U6
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U7
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 7 6 3 2 - 0 1 0 A3A3U3
2 CAPACITCR,FXD CER D I E L , l U F , 20%, 5 0 V ( 1 6 5 4 6 )
9 1 3 - 3 2 7 9 - 2 7 0 A3A3C8
2 TRANSISTOR ( 0 7 2 6 3 ) 3 5 2 - 0 6 6 1 - 0 2 0 A 3 A 3 4 1
2 RESISTOR,FXD CIIFSN, 1 0 K , l o % , 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 3 5 - 0 0 0 A3A3R8
2 RESISTG9,FSD CHPSN, l K , 1 0 % ) 1/4W ( 8 1 3 4 9 ) \
7 4 5 - 0 7 4 9 - 0 0 0 A3A3R5
2 RESISTCRIFYD CMFSNI 1 K t 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 4 9 - 0 0 0 A3A3R4
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U4
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A3A3U1
2 J A C K S T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A3TP8
2 J A C K , T I P UHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A 3 4 3 T P 7
2 J A C K S T I P KHT ( 7 4 9 7 0 3 6 0 - 0 4 8 4 - 0 1 0 A3A3TP6
2 J A C K Y T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 3 4 - 0 1 0 A3A3TP5
2 J A C K S T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A3TP4
2 J A C K S T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A3TP3
2 J A C K P T I P WHT ( 7 4 9 7 0 ) 3 6 0 - 0 4 8 4 - 0 1 0 A3A3TP2
2 J A C K t T I P WHT ( 7 4 9 7 0 3 6 0 - 0 4 8 4 - 0 1 0 A 3 A 3 T P 1
2 INTEGRATED C I R C U I T ( 2 7 0 1 4 ) 3 5 1 - 7 7 1 5 - 0 2 0 A3A3U2
2 CCt:NECTOR PLUG ELEC ( 7 1 4 6 8 3 7 1 - 0 3 8 5 - 1 0 0 A 3 A 3 J 4
2 S L I D I N G LK ASSY ( 7 1 4 6 8 ) 3 7 0 - 2 2 9 8 - 0 0 0 ( A P )
2 WCSHER,LOCK SST, 0 . 1 1 5 I D X 0 . 2 0 9 OD ( 9 6 9 0 6 )
310-0279-0001AP)
2 WASHERpFLAT PSVT CRES, 0 . 1 1 5 I D X 0 . 2 0 9 OD ( 8 0 2 0 5 )
310-0740-240 (AP)
2 POST
2 SCREW,MACH STL, 4 - 4 0 X 1 / 4 ( 9 6 9 0 6 ) 3 4 3 - 0 1 3 3 - 0 0 0 ( A P
2 WASHERpFLAT PSVT CRES, 0 . 1 1 5 I D X 0 . 2 0 9 OD ( 8 0 2 0 5 )
3 1 0 - 0 7 4 0 - 2 4 0 ( AP
2 WASHERPLOCK SST, 0 . 1 1 5 I D X 0 . 2 0 9 OD ( 9 6 9 0 6 )
3 1 0 - 0 2 7 9 - 0 0 0 ( AP
2 COt:NECTOR,RCPT ELEC ( 9 8 2 9 1 1 3 5 7 - 7 1 9 5 - 0 2 0 A 3 A 3 J 2
2 CONTACT, ELEC
2 CABLE ASSEHBLY A3A3W3
I-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
Synthesizer A.s.sembl~A4
Fiqure 13
+
z UNITS USABLE
FIG- W
PART N O DESCRIPTION PER ON
ITEM
Z ASSY CODE
I-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM
Z ASSY CODE
I FIG-
ITEM PARTNO
t-
z
W
Z
DESCRIPTION
UNITS U S A B L E
PER
ASSY
ON
CODE
RP!{II/(I~O 1 9~1/f[l)Bourd
~Ir A4A 1A 1
Auztrt. 1.5 (Sheet I of',!)
t-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
t-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM
I ASSY CODE
I-
FIG- UNITS USABLE
PARTNO z
w DESCRIPTION PER ON
ITEM a
Z ASSY CODE
Rcoisc~~l
In' October 1980
Scans by ArtekMedia © 2008 parts list 523-0769256
3 R E S I S T O R s F X D F I L M , l o O K , 1 % ~1/8W ( 8 1 3 4 9 )
705-1092-000 A4AlAlR7
3 RESISTORpFXD F I L M , 1 0 5 K v 1 % , 1/8W ( 8 1 3 4 9 )
705-1093-000 A4AlAlR7
3 RESISTORIFXD F I L M , l l O K , 1 % , 1/8W ( 8 1 3 4 9 )
705-1094-000 A4AlAlR7
2 RESISTOR,FXD F I L M , l o O K , 1 x 9 1/8W ( 8 1 3 4 9 )
705-1092-000 A4AlAlR8
2 C A P A C I T O R t F X D CER D I E L , O.OlUF, PORMlO%r l O O V
( 8 1 3 4 9 ) 913-5019-200 A 4 A l A l C 1
2 C A P A C I T O P B F X D CER D I E L I O.OlUF, PORMlOZ, l O O V
( 8 1 3 4 9 ) 913-5019-200 A4AlAlC2
2 R E S I S T O R s F X D CKPStl, l o O K , 5 % ~1/6W ( 8 1 3 4 9 )
745-1864-010 A4AlAlR10
2 RESISTOR,FXD CMPSN, l o O K , 5%. 1/PW ( 8 1 3 4 9 )
745-1864-010 A4AlAlR58
2 SEMICOND D E V I C E ( 0 4 7 1 3 ) 9 2 2 - 6 1 0 0 - 0 4 0 A 4 A l A l C R 2
2 SEMICOND D E V I C E ( 0 4 7 1 3 ) 9 2 2 - 6 1 0 0 - 0 4 0 A 4 A l A l C R 1
2 CRYSTAL U t i I T , Q T Z 1 6 .OflHZ ( 0 0 1 3 6 ) A 4 A l A l Y 1
2 TRANSISTOR ( 0 7 9 1 0 ) 3 5 2 - 0 4 4 0 - 0 0 0 A 4 A l A l Q l
2 CAPACITCR,FXD M I C A D I E L , 3 0 0 P F p 5 % ~5 0 V ( 7 2 1 3 6 )
912-4141-480 A4AlAlC3
2 CAPACITOR,FXD M I C A D I E L , 3 0 0 P F 9 5%. 5 0 V ( 7 2 1 3 6 )
912-4141-480 A4AlAlC5
2 LABELpPRESS SENS ( 1 2 9 9 8 ) ( E F F REV LTR P )
2 CAPACITORIFXD CER D I E L , 1 0 0 0 P F , 107.7 ZOOV ( 8 1 3 4 9 )
913-4018-000 A4AlAlC6
2 RESISTOR,FSD CMPSN, 6 . 2 K , 57.9 1/8W ( 8 1 3 4 9 )
745-1863-680 A 4 A l A l R l
2 R E S I S T O R t F X D CtlPSN, 1 . 3 K s 5%, 1/8W ( 8 1 3 4 9 )
745-1663-520 A4AlAlRZ
2 RESISTOR,FXD CNPSti, 2 . 2 K 9 1 0 % ~1/8W ( 8 1 3 4 9 )
745-2353-000 A441AlR3
2 CAPACITOR,FXD CER D I E L , O . O l U F , PORMlO%r l O O V
(81349) 913-5019-200 A4AlAlC7
2 TRANSISTOR ( 1 4 4 3 3 ) 3 5 2 - 0 5 9 6 - 0 3 0 A 4 A l A l Q 3
2 C A F A C I T C R j F X D M I C A D I E L I 1 5 0 P F p 5 % 5~ 0 V ( 7 2 1 3 6 )
912-4141-400 A 4 A l A l C 1 1
2 TRANSISTOR ( 1 4 4 3 3 ) 3 5 2 - 0 5 9 6 - 0 3 0 A 4 A l A l Q 2
2 RESISTORIFXD CtlPSN, l O K p 1 0 % ~1/8W ( 8 1 3 4 9 )
745-2377-000 A4AlAlR4
2 R E S I S T C R p F X D CMPSN, l 0 K 1 1 0 x 9 1/8W ( 8 1 3 4 9 )
745-2377-000 A4AlAlR5
2 INTEGRATED C I R C U I T L O G I C GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 1 0
A4AlAlU3
2 INTEGRATED C I R C U I T ( E S D S ) ( 0 1 2 9 5 ) 3 5 1 - 1 7 3 8 - 0 1 0
A4AlAlU6
2 INTEGRATED C I R C U I T ( E S D S ) ( 0 1 2 9 5 ) 3 5 1 - 1 7 3 8 - 0 1 0
A4AlAlU7
2 S H I E L D , RF ( E F F REV LTR N ) ( S B 9 )
2 C A P A C I T O R I F X D CER D I E L , 1 0 0 0 P F , 1 0 % ~ZOOV ( 8 1 3 4 9 )
913-4018-000 A4AlAlC24
2 RESISTOR,FXD F I L M , 4 6 4 OHMS, 1x9 1/8W ( 8 1 3 4 9 )
705-0950-000 A 4 A l A l R 2 1
2 R E S I S T O R j F X D F I L M , 4 . 4 2 K p 1%. 1/8W ( 8 1 3 4 9 )
705-1027-000 A4AlAlR22
2 RESISTORVFXD F I L M , 2 . 0 5 K s 1x9 1/8W ( 8 1 3 4 9 )
705-1011-000 A4AlAlR23
2 TRANSISTOR ( 1 4 4 3 3 1 3 5 2 - 0 5 9 6 - 0 3 0 A 4 A l A 1 9 4
2 R E S I S i O 2 , F X D CMPSN, l K , 1 0 % ~1/8W ( 8 1 3 4 9 )
745-2341-000 A4AlAlR24
2 CAPACITCR,FXD CER D I E L , l O O O P F t 1 0 % ~2OOV ( 8 1 3 4 9 )
913-4018-000 A 4 A l A l C 2 1
Rc~r~i.sc0
15 October 1980
parts list 523-0769256 Scans by ArtekMedia © 2008
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM a
Z ASSY CODE
2 C A P A C I T O R P F X D CER D I E L , 1000PF,, l o % , 2 0 0 V ( 8 1 3 4 9 1
913-4018-000 A4AlAlC20
2 CAPACITORIFXD E L C T L T I 6 . 8 U F ; 1 0 % ~3 5 V ( 8 1 3 4 9 1
184-0066-640 A4AlAlC25
2 I N T E G 4 A T E D C I R C U I T L O G I C GATE ( 2 7 0 1 4 ) 3 5 1 - 1 5 2 3 - 2 2 0
A4AlAlU10
2 C A F A C I T C R , F X D CER D I E L , 1 0 0 0 P F t l o % , ZOOV ( 8 1 3 4 9 1
913-4018-000 A441AlC54
2 C A P A C I T C R t F X D CER D I E L , l O O O P F t 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC55
2 INTEGRATED C I R C U I T LOGIC GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 2 0
A4AlAlU11
2 C O I L t R F 3.90UH ( 9 6 9 0 6 ) 2 4 0 - 2 0 3 0 - 0 0 0 A 4 A l A l L l
2 R E S I S T O R p F X D CMPSN, 9 1 OHHS, 5 % ~1/4W ( 8 1 3 4 9 )
745-0711-000 A4AlAlR60
2 C A F C C I T O R t F X D CER D I E L , 4 7 0 P F t 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4014-000 A4AlAlC38
2 R E S I S T C R t F X D CMFSN, 3 3 0 OHMS, 5 % ~1/4W ( 8 1 3 4 9 )
745-0730-000 A4AlAlR38
2 TRANSISTCR ( 0 7 9 1 0 ) 3 5 2 - 0 4 4 0 - 0 0 0 A 4 A l A l Q 1 3
2 R E S I S T O R t F X D CMPSN, 2 0 0 OH:lS, 5 % r 1 / 6 W ( 8 1 3 4 9 1
745-1863-320 A4AlAlR39
2 CAPACITOR,FXD M I C A D I E L s 3 0 P F v 5 % ~5 0 V ( 7 2 1 3 6 )
912-4141-200 A4AlAlC40
2 TRAtJSI'iTO? ( 0 7 9 1 0 ) 3 5 2 - 0 4 4 0 - 0 0 0 A 4 A l A 1 9 1 4
2 INSULATOR,DISK ( 3 2 5 5 9 ) 3 5 2 - 9 5 5 2 - 5 8 0
2 RESISTOR,FXD CM?SN, 5 1 OHMS, 5 % . 1/8W ( 8 1 3 4 9 )
745-1e63-180 A4AlAlR42
2 COILPRF 0.15UH ( 9 6 9 0 6 ) 2 4 0 - 2 0 1 3 - 0 0 0 A 4 A l A l L 3
2 CAPACITOR,FXD CER D I E L , 4 7 0 P F p l o % , ZOOV ( 8 1 3 4 9 1
913-4014-000 A 4 A l A l C 4 1
2 C A P A C I T C R t F X D E L C T L T , 6 8 U F s 1 0 % ~1 5 V ( 8 1 3 4 9 )
184-9086-340 A4AlAlC52
2 CAPACITOR,FXD E L C T L T , 4 7 U F s 1 0 % ~3 5 V ( 8 1 3 4 9 )
184-9086-720 A4AlAlC53
2 I N T E G R A T E D C I R C U I T V RGLTR ( 4 9 9 5 6 ) 3 5 1 - 1 0 3 5 - 0 1 0
A4.41AlUZO
2 R E S I S T O R V F X D CMPSN, 2 7 0 OHMS, 1 0 % ~1/4W ( 8 1 3 4 9 )
745-0728-000 A4AlAlR56
2 C A F A C I T C R t F S D CER D I E L , 1 0 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A 4 A l A l C 5 1
2 R E S I S T O R , F X D CMFSN, 1 . 5 K v 5 % ~1 / 4 W ( 8 1 3 4 9 )
745-0754-000 A4AlAlR55
2 R E S I S T O R I F X D CMFSN, 2 2 0 OHMS, 1 0 % ~1 / 4 W ( 8 1 3 4 9 )
745-0725-000 A 4 A l A l R 4 1
2 R E S I S T O R t F X D CMPSN, 3 3 0 OHMS, 5 % ~1/4W ( 8 1 3 4 9 1
745-0730-000 A4AlAlR40
2 COIL A4AlAlL4
2 C A P A C I T C R p F X D M I C A D I E L , 3 3 P F v 5 % ~5 0 V ( 7 2 1 3 6 1
912-4141-220 A4AlAlC39
2 R E S I S T O R t F X D CFlPSN, 1 2 OHMS, 5 % ~1/8W ( 8 1 3 4 9 )
745-1863-030 A4AlAlR35
2 RESISTOR,FXD CMPSNt 5 1 0 OHMS, 5 % 1/4W ~ (81349)
745-0738-000 A4AlAlR37
2 R E S I S T O R , F X D C t l P S N t 4 3 0 OHMS, 5%. l / 8 W ( 8 1 3 4 9 )
745-1853-400 A4AlAlR36
2 R E S I S T O R I F X D CMPSN, 4 3 0 OHMS, 5%. 1/8W ( 8 1 3 4 9 )
745-1863-400 A4AlAlR34
2 C A P A C I T O R , F X D CER D I E L , 4 7 0 P F p l o % , 2 0 0 V ( 8 1 3 4 9 )
913-4014-000 A4AlAlC37
2 INTEGRATED C I R C U I T F L I P FLOP ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 4 0
A4AlAlU9
I-
UNITS USABLE
FIG- z
w PER ON
ITEM PART N O n DESCRIPTION
Z ASSY CODE
2 CAPACITOR,FXD CER D I E L , 1 0 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC19
2 R E S I S T O R V F X D CHPSN, 6 8 0 OHMS, 1 0 % ~1/4W ( 8 1 3 4 9 )
745-0743-000 A4AlAlR16
2 C A F A C I T C R , F X O M I C A D I E L , 1 0 0 F F p 5 % ~5 0 V ( 7 2 1 3 6 )
912-4141-050 A4AlAlC59
2 C A P A C I T O 2 , F X D M I C A D I E L , 1 0 0 P F p 5%, 5 0 V ( 7 2 1 3 6 )
912-4141-050 A4AlAlCS8
2 INTEGRATED C I R C U I T F L I P FLOP ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 4 0
A4AlAlU8
2 C A P A C I T C 2 , F X D CER D I E L , 1 0 0 0 P F , l o % , 2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC14
2 C A P L C I T O R 9 F X D CER O I E L p 1 0 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC18
2 R E S I S T O R , F X D CMFSN, l K , 1 0 % ~1/PW ( 8 1 3 4 9 )
745-2341-000 A4AlAlR17
2 C A P A C I T C R , F X D CER D I E L , 1 0 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4015-000 A4AlAlC57
2 C A P A C I T O R , F X D CER D I E L , 1 0 0 0 P F p 1 0 % r 2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC17
2 INTEGRATED C I R C U I T F L I P F L O P ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 6 0
A4AlAlU21
2 C A P A C I T O R , F X D CER D I E L , l O O O P F t 1 0 % ~ZOOV ( 8 1 3 4 9 )
913-4018-000 A4AlAlC13
2 I N T E G R A T E D C I R C U I T L O G I C GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 1 0
A4AlAlU4
2 R E S I S T O R p F X D CMPSN, l K , 5%; 1/4W ( 8 1 3 4 9 )
745-0745-000 A4AlAlR18
2 C A P A C I T O R V F X D CER D I E L , 1 0 0 0 P F ~ 1 0 % . 2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC12
2 INTEGRATED C I R C U I T ( E S O S ) ( 0 1 2 9 5 ) 3 5 1 - 1 7 3 8 - 0 1 0
A4AlAlU1
2 C A P A C I T O R r F X D CER D I E L , 1 0 0 0 P F , l o % , 2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC16
2 I N T E G R A T E D C I R C U I T L O G I C GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 1 0
A4AlA1U5
2 C A P A C I T O R p F X D CER D I E L , 1 0 0 0 P F , 1 0 % . 2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC15
2 INTEGRATED C I R C U I T ( 0 1 2 9 5 ) 3 5 1 - 1 6 3 6 - 0 1 0 A 4 A l A l U 2
2 R E S I S T O R p F X D C f l F S N , l K , 5 % ~1/4W ( 8 1 3 4 9 )
745-0748-060 A4AlAlR19
2 R E S I S T O 2 , F X D CMFSN, 3 . 3 K ~ 5%. 1 / 4 W ( 8 1 3 4 9 )
745-0766-000 A4AlAlRZO
2 C A P A C I T O 2 , F X D CER D I E L , 1 0 0 0 P F , 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC23
2 CAPACITORIFXD CER D I E L , 1 0 0 0 P F p 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
913-4018-000 A4AlAlC22
2 S O C K E T , I C ( 2 3 8 8 0 3 2 2 0 - 0 0 7 5 - 0 2 0 ( E F F TO R E V L T R K )
2 S O C K E T P I C ( 2 3 8 8 0 ) 2 2 0 - 0 0 7 5 - 0 3 0 ( E F F TO R E V LTR K )
2 CONTACT, E LEC
2 CONTACT, E L E C
F
FIG- UNITS USABLE
ITEM PART N O ,w,Zz DESCRIPTION PER
ASSY
ON
CODE
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM
Z ASSY CODE
30 ' Ut I H I L H
32
DETAIL A
29
iC4)28
I , A t "C
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
2 PLATE-VOLTAGE
2 SCREWvM4CH SST, 2-56 X 1 / 8 ( 7 7 2 5 0 ) 3 4 7 - 1 2 6 8 - 0 0 0 ( A P )
2 TERMINAL STDF ( 9 2 8 2 5 ) 3 0 6 - 0 2 3 4 - 0 0 0
2 SCPEW,M4CH STL, 4 - 4 0 X 3 / 1 6 ( 9 6 9 0 6 ) 3 4 3 - 0 1 3 2 - 0 0 0 ( A P )
2 W4SHERjLOCK SST, 0 . 1 1 5 I D X 0 . 2 0 9 OD ( 9 6 9 0 6 )
3 1 0 - 0 2 7 9 - 0 0 0 CAP)
2 TERMINALSLUG ( 7 7 1 4 7 ) 3 0 4 - 0 0 1 5 - 0 0 0 CAP)
2 COILYRF 0.85Ky PORM20Z ( 0 2 1 1 4 ) 2 4 0 - 2 6 7 9 - 0 4 0 A5L2
2 CAPPCITOR,FXD CER D I E L , 4700PF, 2 0 % ~500V ( 8 1 3 4 9 )
9 1 3 - 1 1 8 7 - 0 0 0 A5C6
2 CAPACITOR,FXD CER D I E L , 4700PFs 2 0 % ~5 0 0 V ( 8 1 3 4 9 )
9 1 3 - 1 1 8 7 - 0 0 0 A5C7
2 COE:'dECTOR,RCPT ELEC ( 8 2 3 8 9 ) 3 6 8 - 0 3 8 5 - 0 1 0 A 5 J 4
2 NUT,PLAIN,HEX SST, 4 - 4 0 ( 0 6 9 0 6 ) 3 1 3 - 0 0 4 3 - 0 0 0 ( A P )
2 WASHERSFLAT SST, 0 . 1 2 5 I D X 0 . 2 8 1 OD ( 7 9 8 0 7 ) ( A P )
2 WASHER,LOCK SST, 0.115 I D X 0 . 2 0 9 OD ( 9 6 9 0 6 )
310-0279-000 ( A P )
2 TERMINAL, LUG ( 7 7 1 4 7 ) 3 0 4 - 0 0 1 5 - 0 0 0 ( A P )
2 SCREW,MACH STL, 4 - 4 0 X 1 / 2 ( 9 6 9 0 6 1 3 4 3 - 0 1 3 7 - 0 0 0 ( A P )
2 CAPACITCR,FXD CER D I E L , 4700PFs 2 0 % ~500V ( 8 1 3 4 9 )
9 1 3 - 1 1 8 7 - 0 0 0 A5C5
2 LABEL,PRESSURE ( 1 2 9 9 8 ) (EFF REV LTR J ) ( S B 1 )
2 CAPACITOR,FXD CER D I E L , 4700PF1 20%, 500V ( 8 1 3 4 9 )
913-1187-COO A5C4
2 TERMINALtLUC ( 7 9 9 5 3 ) 3 0 4 - 1 0 8 9 - 0 0 0
2 NUTyPLAIN,HEX SSTt 6 - 3 2 ( 7 7 2 5 0 ) 3 1 3 - 0 0 4 5 - 0 0 0 ( A P )
2 ,
WASHER LOCK SST, 0 . 1 4 1 I D X 0 . 2 5 0 OD ( 9 6 9 0 6
310-0282-000 (AP
2 SCREW,MACH SST, 6 - 3 2 X 5 / 1 6 ( 9 6 9 0 6 ) 3 4 3 - 0 1 6 8 - 0 0 0 ( A P )
2 COVER r CONNECTOR
3 LABEL,PRESSURE ( 1 2 9 9 8 )
3 COVER
2 FAN,TUPEAXIAL ( 8 2 8 7 7 ) 0 0 9 - 1 7 6 6 - 0 2 0 A5B1
2 GUARD,FGR ( 8 2 8 7 7 ) 0 0 9 - 1 7 6 6 - 0 5 0
2 NUT,RESILIENT BRS, 6 - 3 2 ( 0 4 7 1 4 ) 3 3 4 - 1 4 9 2 - 0 0 0 ( A P FOR
33, 3 4 )
2 SCREW,MACH SST, 6 - 3 2 X 2 - 1 / 4 ( 7 7 2 5 0 ) 3 4 3 - 0 1 8 3 - 0 0 0
( A P FOR 33, 3 4 )
2 SCREWvM4CH SST, 6 - 3 2 X 2 ( 9 6 9 0 6 ) 3 4 3 - 0 1 8 2 - 0 0 0 ( A P
FOR 33, 3 4 )
2 POWER SUPPLY PC BOARD ASSEMBLY A5A2 (SEE F I G 1 9 )
2 SCREW,MACH SST, 6 - 3 2 X 5 / 1 6 ( 9 6 9 0 6 ) 3 4 3 - 0 1 6 8 - 0 0 0 ( A P )
2 SCREWvflACH SST, 6 - 3 2 X 3 / 8 ( 9 6 9 0 6 ) 3 4 3 - 0 1 6 9 - 0 0 0 CAP)
2 WASHERpFLAT SST, 0 . 1 4 7 I D X 0.312 OD ( 7 9 8 0 7 ) ( A P )
2 CH4SSISs POWER SUPPLY
3 NUTsSLFLKG CD PL STL, 6 - 3 2 ( 7 2 9 6 2 ) 3 3 3 - 0 8 4 2 - 0 0 0
3 STUDtTURNLOCK FSTtJR, CD PL STL, 0 . 1 2 8 D I A X 0 . 3 8 4
( 7 1 2 8 6 ) 012-3160-000
3 WASHERPSPLIT CD PL STL, 0 . 1 5 6 I D X 0 . 2 7 4 OD ( 7 1 2 8 6 )
0 1 2 - 2 7 8 5 - 0 0 0 ( AP
3 CHASSIS
4 PLATE, REAR
4 FLOOR
I-
FIG- UNITS USABLE
PART NO z
w DESCRIPTION PER ON
ITEM n
Z ASSY CODE
I-
UNITS USABLE
FIG- z
w
PART NO n DESCRIPTION PER ON
ITEM
-
z ASSY CODE
DETAIL A
(RACK)
t-
FIG- UNITS USABLE
PARTNO z
w DESCRIPTION PER ON
ITEM
I ASSY CODE
Revised 15 O c t o b ~ rIYh'O
parts list 523-0769256 Scans by ArtekMedia © 2008
I FIG-
ITEM
l-- PART NO
I-
3
n
z
DESCRIPTION
I I
UNITS USABLE
ASSY
PER CODE
ON 1
2 NUT,PLAIN,HEX SST, 6 - 3 2 ( 7 7 2 5 0 ) 3 1 3 - 0 0 4 5 - 0 0 0 CAP)
2 TERMINAL,LUG ( 7 7 1 4 7 ) 3 0 4 - 0 0 1 6 - 0 0 0 ( A P )
2 WASHER,LOCK SST, 0 . 1 4 1 I D X 0 . 2 5 0 OD ( 9 6 9 0 6 )
3 1 0 - 0 2 8 2 - 0 0 0 CAP)
2 WASHERgFLAT SST, 0 . 1 4 7 I D X 0 . 3 7 5 OD ( 7 9 8 0 7 ) ( A P )
2 INSULATOR ( A P )
2 WASHERjMICA ( 0 8 2 8 9 ) 3 5 2 - 9 5 7 0 - 0 2 0 ( A P )
2 SCREW,MACH SST, 6 - 3 2 X 7 / 1 6 ( 9 6 9 0 6 ) 3 4 3 - 0 1 7 0 - 0 0 0 ( A P )
2 SEHICOND DEVICE ( 0 4 7 1 3 ) 3 5 3 - 6 5 4 5 - 0 2 0 A5AZCR1
2 NUT,PLAIN,HEX SST, 6 - 3 2 ( 7 7 2 5 0 ) 3 1 3 - 0 0 4 5 - 0 0 0 ( A P )
2 TERMINALILUG ( 7 7 1 4 7 ) 3 0 4 - 0 0 1 6 - 0 0 0 ( A P )
2 WASHER,LOCK SST, 0 . 1 4 1 I D X 0 . 2 5 0 OD ( 9 6 9 0 6 )
310-0282-000 ( AP)
2 WASHER,FLAT SST, 0 . 1 4 7 I D X 0 . 3 7 5 OD ( 7 9 8 0 7 ) ( A P )
2 INSULATOR ( A P )
2 INSULATOR,PLATE ( 0 8 2 8 9 ) 3 5 2 - 9 8 8 2 - 0 1 0 ( A P )
2 SCREW,MACH SST, 6 - 3 2 X 1 / 2 ( 9 6 9 0 6 ) 3 4 3 - 0 1 7 1 - 0 0 0 ( A P )
2 RESISTORIFXD 1 OHM, 5 % ~3W ( 8 1 3 4 9 ) 7 4 7 - 5 3 0 0 - 0 0 0
A5AZR21
2 CAPACITOR,FXD CER D I E L S O.lUF, PORMlOZ, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5A2C9
2 CAPACITOR,FXD CER D I E L , O.lUF, PORMlOZ, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5A2C10
2 RESISTOR,FXD CMPSN* l K , 1 0 2 , 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 4 9 - 0 0 0 A5AZR16
2 TRANSISTOR ( 0 7 2 6 3 ) 3 5 2 - 0 6 6 1 - 0 2 0 A 5 A 2 9 1
2 CAPACITOR,FXD CER D I E L , O.lUF, PORMlOZ, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5A2C8
2 INTEGRATED C I R C U I T V RGLTR ( 4 9 9 5 6 ) 3 5 1 - 1 0 3 5 - 0 1 0
A5AZU2
2 BRACKET, HEATSINK
2 NUT,PLAIN,HEX SST, 6 - 3 2 ( 7 7 2 5 0 ) 3 1 3 - 0 0 4 5 - 0 0 0 ( A P )
2 WASHER,LOCK SST, 0 . 1 4 1 I D X 0 . 2 5 0 OD ( 9 6 9 0 6 )
310-0282-000 ( AP)
2 WASHERBFLAT SSTI 0 . 1 4 7 I D X 0 . 3 7 5 OD ( 7 9 8 0 7 ) ( A P )
2 SCREW,MACH SST, 6 - 3 2 X 3 / 8 ( 9 6 9 0 6 ) 3 4 3 - 0 1 6 9 - 0 0 0 ( A P )
2 CAPACITOR,FXD CER D I E L , 470PF. 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
9 1 3 - 4 0 1 4 - 0 0 0 A5AZC11
2 RESISTOR,FXD F I L M , 7.15K9 1 % ~ 1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 3 7 - 0 0 0 A5AZR18
2 RESISTORsFXD F I L M t 1 . 8 7 K ~ 1 % 1/8W ~ (81349)
7 0 5 - 1 0 0 9 - 0 0 0 A5A2R19
2 CAPACITOR,FXD ELCTLT, 220UFs 1 0 % ~1 0 V ( 8 1 3 4 9 )
1 8 4 - 9 0 8 6 - 2 5 0 A5A2C6
2 CAPACITORtFXD ELCTLT, 220UF, 1 0 x 9 1 0 V ( 8 1 3 4 9 )
1 8 4 - 9 0 8 6 - 2 5 0 A5AZC7
2 RESISTOR,FXD CMPSN, 6 8 0 OHMS, 1 0 x 9 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 4 3 - 0 0 0 A5AZR8
2 CAPPCITOR,FXD CER D I E L , O.lUF, PORMlOZ, l O O V ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5A2C4
2 RESISTORtFXD CMPSN, 2 7 0 OHMS* 10%. 1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 2 8 - 0 0 0 . A5A2R3
2 RESISTOR,FXD F I L M , 2 . 1 5 K ~ 1 % 1/8W ~ (81349)
7 0 5 - 1 0 1 2 - 0 0 0 A5AZR4
2 CAPACITORIFXD ELCTLT, 47UF9 1 0 x 9 20V ( 8 1 3 4 9 )
1 8 4 - 9 0 8 6 - 5 5 0 A5A2C5
2 CAPACITORsFXD CER D I E L , O.1UFs PORHlO%, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5AZC3
2 RESISTORIFXD F I L M , 7 5 0 OHMS, 1%. 1/8W ( 8 1 3 4 9 )
7 0 5 - 0 9 9 0 - 0 0 0 A5AZR5
2 CAPACITOR,FXD CER D I E L , O.lUF, PORMlOZ, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A5A2C1
t- UNITS USABLE
FIG- z
w
PART N O DESCRIPTION PER ON
ITEM n ASSY CODE
Z
2 INTEGRATED C I R C U I T V RGLTR ( 4 9 9 5 6 ) 3 5 1 - 1 0 3 5 - 0 1 0
A5A2U1
2 CAPACITOR,FXD CER D I E L , 4 7 0 P F y 1 0 % ~2 0 0 V ( 8 1 3 4 9 )
9 1 3 - 4 0 1 4 - 0 0 0 A5A2C2
2 RESISTO2,FXD F I L M , 7 1 5 OHtlS, 1 % 1/PW ~ (81349)
7 0 5 - 0 9 8 9 - 0 0 0 A5A2R7
2 RESISTO?,FXD F I L M , 4 . 0 2 K 9 1 % ~1/8W ( 8 1 3 4 9 )
7 0 5 - 1 0 2 5 - 0 0 0 A5A2R6
2 HOUSING ,CCNN A 5 A 2 J 1
,
2 CONTACT E LEC
2 J A C K p T I P KHT ( 8 1 3 4 9 ) 3 6 0 - 0 1 5 9 - 0 0 0 A 5 A 2 T P 2
2 J A C K p T I P RHT ( 8 1 3 4 9 ) 3 6 0 - 0 1 5 9 - 0 0 0 A 5 A 2 T P 1
2 RESISTCR,VAR W W , 5 0 0 OHMS, PORM5Xr 3 / 4 N ( 8 1 3 4 9 )
3 8 1 - 1 7 2 1 - 0 3 0 A5A2R2
2 RESISTCR,VCR KU, 1 K s PORP15%, 3/4W ( 8 1 3 4 9 )
381-1721-040 A5AZR1
2 COt4TACT, E LEC
2 PIN, INDEX
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM
Z ASSY CODE
( K 3 ) 49
i K 8 ) 38
(C51 4 6
ICR 1 ) 4 5
1R 1 ) 4 4
(C1143
( C 2 ) 42
+
z UNITS USABLE
FIG- w PER ON
ITEM PART NO n DESCRIPTION
z ASSY CODE
2 RELAYvREED ( 0 1 1 0 1 ) 4 1 0 - 0 5 5 8 - 0 3 0 APK4
2 RELAYsREED ( 0 1 1 0 1 ) 4 1 0 - 0 5 5 8 - 0 3 0 A 8 K 3
2 RELAY ,REED ( 0 1 1 0 1 1 4 1 0 - 0 5 5 8 - 0 3 0 ASK2
2 INTEGRATED C I R C U I T L O G I C GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 2 6 0
AEUZ
2 RELAY ,REED ( 0 1 1 0 1 4 1 0 - 0 5 5 8 - 0 3 0 A 8 K 1
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 6 - 0 3 0 A 8 U 1
2 RESISTOR,FXD CMFSN, 1 . 5 K ~ 1 0 x 9 l / 8 N ( 8 1 3 4 9 1
7 4 5 - 2 3 4 7 - 0 0 0 A8R2
2 RESISTCR,FXD CWPSN, 4 7 OHMSI 1 0 % ~1/8W ( 8 1 3 4 9 1
7 4 5 - 2 2 9 2 - 0 0 0 ASR3
2 PUB-MECH ASSY
3 ,
COIJTACT E LEC
3 CONTACT E LEC
3 HOUSING,COt:N A 8 P 1
Rellised 1 5 October l ! / X O
arts list 523-0769256
Scans by ArtekMedia © 2008
Store/Recnll Assembly A9
F~gure22
I-
FIG- UNITS USABLE
ITEM PART N O ,zw, DESCRIPTION PER ON
z ASSY CODE
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM o
-
Z ASSY CODE
+
z UNITS U S A B L E
FIG- w PER ON
PART N O n DESCRIPTION
ITEM ASSY CODE
z
2 INTEGRATED C I R C U I T LOGIC GATE ( 1 8 3 2 4 ) 3 5 1 - 1 5 2 3 - 0 9 0
AS'U11
2 INTEGRATED C I R C U I T ( 3 4 3 3 5 ) 3 5 1 - 1 5 2 9 - 0 4 0 A9U12
2 INTEGRATED C I P C U I T ( E S D S ) ( 1 4 9 3 6 ) 3 5 1 - 6 5 3 0 - 0 1 0 A9U18
( E F F TO REV LTR A )
2 INTEGRATED C I R C U I T ( E S D S ) ( 1 4 9 3 6 ) 3 5 1 - 8 5 3 0 - 0 2 0 A9U18
( E F F REV LTR A )
2 SOCKET,IC ( 2 3 3 8 0 ) 2 2 0 - 0 0 7 5 - 0 6 0 A9XU18
2 CAPACITOR,FXD CER D I E L , O.lUF, FORfllOZ, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A9C14
2 INTEGRATED C I R C U I T F L I P FLOP ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 4 0
A9U13
2 RESISTOR,FXD CtlPSNs 10Kp 1 0 % ~1/4W ( 8 1 3 4 9 )
7 4 5 - 0 7 8 5 - 0 0 0 A9R6
2 INTEGRATED C I R C U I T ( 0 4 7 1 3 ) 3 5 1 - 7 6 1 6 - 0 2 0 A9U24
2 CAPACITOR,FXO CER D I E L , O . l U F , PORtllO%, lOOV ( 8 1 3 4 9 )
9 1 3 - 5 0 1 9 - 4 4 0 A9C6
2 SEMICCKD DEVICE ( 0 3 5 0 8 ) 3 5 3 - 3 6 4 4 - 0 1 0 A9CR3
2 CAFACITOR,FXO ELCTLT, 10UFs 10%. 2 0 V ( 8 1 3 4 9 )
1 8 4 - 9 0 8 6 - 4 6 0 A9C4
2 INTEGRATED C I R C U I T LOGIC GATE ( 1 6 3 2 4 ) 3 5 1 - 1 5 2 3 - 1 1 0
ACU3
2 INTEGDATED C I R C U I T F L I P FLOP ( 0 4 7 1 3 ) 3 5 1 - 1 5 2 5 - 0 4 0
A9U7
2 C I R C U I T CARD- MECH
3 CONTACT 9 E LEC
3 CONTACT, ELEC
3 HOUS1t:G yCCt4N A 9 P 1
3 COt4TACT,ELEC
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM o
Z ASSY CODE
+
z UNITS USABLE
FIG-
ITEM PART NO W
DESCRIPTION PER ON
Z ASSY CODE
lLk--'
DETAIL A
kl DETAIL A
Chassis Assembly A6
Figure 24
I-
UNITS USABLE
FIG- z
w PER ON
ITEM PART N O a DESCRIPTION
Z ASSY CODE
UNITS USABLE
FIG-
ITEM PART N O 5n DESCRIPTION PER ON
Z ASSY CODE
I-
FIG- UNITS USABLE
PART N O z
w DESCRIPTION PER ON
ITEM a
Z ASSY CODE
Re?~ised15 October. 1Y K O
parts list 523-0769256 Scans by ArtekMedia © 2008
3. NUMERICAL INDEX
I
FIG- TTL FIG- TTL
PART NUMBER ITEM PART NUMBER ITEM REQ
REQ
NUMERICAL INDEX
NUMERICAL INDEX I I
NUMERICAL INDEX
NUMERICAL INDEX
NLlMERlCAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NLlMERlCAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
I
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
NUMERICAL INDEX
- -
914-3098-640 10-57
10-62
10-68
10-70
10-72
10-86
12-22
12-23
12-26
12-27
16-3
16-10
16-13
16-17
16-35
16-36
25-2
25-16
25-18
25-25
25-29
25-34
25-42
25-43
25-52 38
914-3098-710 10-62A AR
914-3098-720 10-62A AR
914-3105-320 10-18 1
917-1222-000 8-81 1
917-1256-010 10-13
10-77
25-13
25-23
25-36 5
917-1256-020 16-4
16-39 2
917-1256-030 16-24
25-22 2
922-0583-030 10-77 1
922-6100-040 15-10
15-80
15-81 3
922-6119-010 10-42
10-44
10-46
10-48
10-50
10-52
10-54
10-56 8
933-0264-130 11-106 1
933-0264-200 11-102 1
933-1039-230 7-62
7-63
7-67
7-68
7-137
7-138
7-142
7-143 8
933-1084-250 11-159 1
933-1084-370 11-30 1
Rockwell
International
Collins 479s-6A
VORII LS Signal Generator diagrams
I Collins Government Avionics Division
a
$
Pnnled in USA 523-0769121-101118 $
1 Serptember 1978 B
1st Revision, 15'0ctober 1980 g
list of illustrations p
3
L
0
3
9
Figure Page 3
4
1 Front Panel Assembly Al, Schematic Diagram ............................................................ 3
2 Controller/Audio Assembly A2, Schematic Diagram ....................................................... 13
3 Controller/Audio Assembly A2, CPU Board Assembly A2A1, Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Controller/Audio Assembly A2, Analog Board Assembly A2A2, Schematic Diagram .......................... 23
5 Controller/Audio Assembly A2, TDM Board A2A3, Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 RF Modulator Assembly A3, Schematic Diagram .......................................................... 39
7 RF Modulator Assembly A3, RF Strip Line Assembly A3A1, Schematic Diagram ............................ 43
8 RF Modulator Assembly A3, Demodulator/ALC Board Assembly A3A2, Schematic Diagram .................. 47
9 RF Modulator Assembly A3, Counter-I/O Board Assembly A3A3, Schematic Diagram ........................ 51
10 Synthesizer Assembly A4, Schematic Diagram ........................................................... 57
11 Power Supply Assembly A5, Schematic Diagram ......................................................... 63
12 Backplane Assembly A7, Interconnect Diagram ........................................................... 67
13 Remote Tune Assembly A8, Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14 Chassis Wiring Harness, Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I
15 Store/Recall Assembly A9 (479s-6A CPN 622-4127-002, -003 Only), Schematic Diagram ...................... 79
16 IEEE-488/1978 Bus Interface Assembly A10 (CPN 601-5883-001) (479s-6A CPN 622-4127-003,
-004 Only), Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
17 IEEE-488/1978 Bus Interface Assembly A10 (CPN 601-2309-001) (479s-6A CPN 622-4127-003, -004
Only), Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Scans by ArtekMedia © 2008
List of .Effective Pages 'The asterisk indicates pages changed. added. or deleted by t h e current change .
1 15 Oct 80 1 thru 10
) -
Scans by ArtekMedia © 2008
diagrams
1 . CONFIGURATION STATUS CONTROL For example, a unit is marked REV F and falls
between REV E and REV H on the schematic changes
Collins Government Avionics Division of Rockwell page. The electrical configuration of the unit is the
International uses a 2-character maximum alphabetic same a s units with REV E.
identifier for identifying the configuration status of a
unit or subassembly. The alphabetic identifier is 2. CONFIGURATION EFFECTIYITY
preceded by the letters REV (revision) and starts
with - if no changes have been processed. The first Refer to the schematic changes page preceding each
change is identified a s A, the second a s B, continuing subassembly schematic for any subassembly changes
through Z to AA, AB, and ultimately ZZ. The that may have occurred and the corresponding iden-
alphabetic identifier is not a serial number because tifier covering each change.
many units or subassemblies may exist with t h e same
identifier. Incorporation of design changes in a unit ) Note (
or subassembly t h a t is returned to Rockwell-Collins Configuration history before 1 September
for repair by a customer or that is removed from the 1978 is not recorded in this section.
company's finished goods inventory is defined a s
rework. At the time of rework, the unit or sub- Listed below a r e the units/subassemblies with the
assembly is re-marked to reflect the design level to latest identifier (change) covered by this document.
which it is upgraded. This is done by leaving the
original marking on the unit or subassembly and ad- COLLINS
ding the letters RWK (rework), followed by the PART LATEST
LlNIT/SUBASSEMBLY NUMBER EFFECTIVITY
alphabetic identifier of the latest change incorporated
in the rework. A reworked unit may not contain all A1 REV G
design changes made to the reworked identifier, but AlAl REV H
does contain all changes required to make unit opera- A1A2 REV E
tion identical to a newly manufactured unit with the A2 REV G
A2A1 REV H
same identifier. For example, unit one is marked A2A2 REY L
REV B - RWK F and unit two is marked REV F. A2A3 REV R
This indicates t h a t both units are a t the design level A3 REV G
of revision F. Unit one is reworked and may not look A3A1 REV P
exactly the same a s unit two. A3A2 REV Y
A3A3 RE3' H
A4 REV J
Whenever possible, t h e alphabetic identifier is A4A1 REV G
marked on the unit or subassembly approximately A4A2 with board 637-2718-001 REV E
two spaces after the 10-digit part number. When this .44A2 with hoard 634-9681-001 REV R
is not practicable, it is marked a s close a s possible to, A5 REV L
A5A1 REV F
but not immediately following, the part number. As A5A2 REV C
an example, in a subassembly with high parts densi- A5A3 REV B
ty, the 10-digit part number may appear on one side A5A4 REV B
of the subassembly, the alphabetic identifier on the Wiring Harness REV K
A7 REV C
other.
A8 REV D
A9 REV E
Only alphabetic identifiers that result in schematic A10 RE\' F
changes are covered in this section. If a unit or sub- A10 REF -
assembly has an identifier t h a t falls between iden-
tifiers on the schematic changes pages, the electrical
configuration is represented by the earlier identifier.
3. SCHEMATIC DIAGRAMS
SCHEMATIC CHANGES
-
I/O WR
SPARES
i
J
VAC IN H OUT 54
OUT 55
S54
VAC IN L
VAC L (SW)
VAC H (SW)
4
2
I
P I 0 FRONT
PANEL
I
I
I.--- -
diagrams 523-0769 121
Scans by ArtekMedia © 2008
IAW TEST A
I---------
--------- - _
P/O DISPLAY BOARD A I A 2
P I 0 KEYBOARD DRIVER
BOARD AlAl
diagrams 523-0769 121
Scans by ArtekMedia © 2008
- - - - - - - - ------------ -7
P/O DISPLAY BOARD A I A 2
I
I
+5 v DC +5 v DC +5 V DC +5 v DC +5 v DC I
DS2 14 OS3 14 OS4 14
+5 V D C 0 +5 v DC
o b c d e f g o b c d e f g o b c d e f g
\
m
I.Y
r-
9 r - ~ m : m ! n ~ !n
(U r-
*) 2 S : , " ! ~ Z : kr;:xzaa n" LO
*) a
$
. a
C)
+5 v DC
P I 0 KEYBOARD / DRIVER
BOARD AlAl
diagrams 523-0769 121
Scans by ArtekMedia © 2008
- -- -- - -
P/O DlSRAY BOARD A I A 2
- ------------------ 1
1 DSlO
+ 5 v a
114
--.) el-lc
L-• d
EACH EACH
w m
P t n ( a om ( o ~m r - -r +w
w w ~ ~ N
r- N
m E Z ~ F F S E m a
m m
r-Y mN
L O m
P7 m z~ ~ N
8 s s s g a s s .- =
% m ~~~~~~~ -
,-
7,r-
- ::2ZP:2
. - r r r r r r
P/O D I S P L A Y BOARD A I A 2
i NOTES :
1. M E S S OTHERWISE SPECIFIED. RESISTANCE VALUES ARE U W S
AN2 CAPACITANCE VALUES ARE I N MICROFARADS.
_ - ~ - -
P/O
- - - -
DISPLAY BOARD A I A 2
- - - -
Scans by ArtekMedia © 2008
NOTES:
I
I
2 PARTIAL REFEREHE EllGNAT l a i I R E S-
DESIGMTION, PREFIX WITH W I T ARD /OR
FOR C W L E T E
ASSEMBLY DESIGNATION.
+
OS12 14
+5 v Dc 6 0
'Z:; ef 1
1-1 2cb1
L-* d
a b c d e f g
10
7 8
OUT
+5v@402 2.l: +5vKA:
OUT 4C
OUT 40
DAC
€ 0 ENABLE 30 ED ENABLE
vcxo (
I L S ENABLE
+ 1 5 V DC OUT
- 1 5 V DC OUT
ANALCG RTN
SPARE
5 ,
, > 5 )ANALOG
CNALCG RTN 6 RTN
V I ) 6
. , 8 , -WIR SUPPLY ASSY A5
t 5 V DC RTN 9
'4
10 /,
V
A0
51
48
- A1
A2
36 ,
,
Scans by ArtekMedia © 2008
A6
A7
= 00
58
! > 58 01
2 Dl I
45
= 02
49
BUS FRONT PANEL ASSY A l .
= 03
RF MODULATOR ASSY A 3 ,
53
AN0 BACKPLANE A 7
55
= D5
56
= 06
54
07
20,
FRONT PANEL ASSY A1,
I/OR
- RF MODULATOR ASSY A 3 .
17
I /O RD - ! <17( 1 V I- AND BACKPLANE A 7
I
rn~
15
+'5 <I 16
- 4 1 6 <I 18
I
)19** '
-
I 1 NM I
2'0 I
22
0
230
2 4 p,
>
I 24 RSVD
RSVD
HO CONNECT ION 25
28
BACKPLANE A 7
29
3' 0
32
34
37
-37 <t 3 8 0
40
44
47
KEY -+< 47
- , n.. I -
. <, .i .--.
.-
+ 1 5 V DC OUT
-15 v DC OUT
ANALOG RTN
SPARE
5 ,
,
ANALOG RTN 6
V
7 ,
,
8 )= PNR SUPPLY ASSY A 5
V
t 5 V 3C RTN 9 ,
V
10
V
11
12
+ 5 V DC 13
14
52
AD
51
A1
A2
36
A5
43 ,
Y A6
30 ,-,
Y A7
46 ,
= DO
58
Dl 58 <!
Dl
45
02 I
49
49 03 DATA
/ BUS FRONT PANEL ASSY A l ,
= 03
R F M O D U L A T O R ASSY A 3 ,
53
AND BACKPLANE A 7
55
Scans by ArtekMedia © 2008
= 05
56
= 06
54
07
-- 20
I/D I R 20
FRONT PANEL ASSY A l ,
R F MODULATOR ASSY A 3 ,
17
I /O RD 17 AND B A C K P L A N E A 7
15
+15 1
16
18
I
> 1 9 + f i '
Y -
1 I NMI
21 I
2 2 0
23 0
2 4A
>
I 24 &-RSVD
I RSVO
HO CONNECT l ON 25
28
BACKPLANE A 7
29
31 0
32
34
37
4 3 7 <! 3 8 0
40
44
47
KEY -47 <1 I
w,, > 50 % WT
-
WAIT
SPARE
41
57
i
I - - - -
Scans by ArtekMedia © 2008 diaarams 523-076912 1
SCHEMATIC CHANGES
-
RESET
SPARES
TEST
16 H z CLK ENBL
-
NM I
-
NSRp
-
WAIT
BUSAK
diagrams 523-0769 12 1
Scans by ArtekMedia © 2008
A
P/O CPU BOARD A2A1 1.
NOTES :
-
MA15
NC
NC
MICROCIRCUIT 8T97
1 6 15 114 113112 111110 19
VCC
GND
1 12 1314 151 6 1718
MICROCIRCUIT INCRMTION
SCHEMATIC CHANGES
R ~ t ~ i s e1.5
r i October 1980
Scans by ArtekMedia © 2008
NOTES:
1
AUX OUT LOW
EO ENABLE
@ %;:I
VALES
ANALOG BOARD A 2 A 2
9 @ Ly;;:
5 KEY
@ ALL DC
6 SPARE
DAC A
ILS E l ENABLE
R13
VOR E l ENABLE
E2 LEVEL ADJ R115 470 kfl
470 k f l
7 COHWSITE MONITOR HlGH
VOR E l VOR E l
PHASE ADJ GAIN AOJ U2A 8 COMPOSITE MONITOR LOW
R14 1 13
DAC B 0
12
ILS
C6 BAUdlCE
R16
2700 R20
6800 PF pR7 R22 R23 R4
17.4 kfl - 5 k f l P 15kfl 68.1kfl 5kn 15
SPARES
GAlN ADJ
RlOO RlOl 'I -LC10
806 kfl 806 kfl C9 2200 pF
0.01 -
VOR E2 ENABLE
ILS E2 ENABLE
DAC C
..
R26
10 kfl
:"I1 kfl 2" 100 k f l
+15 V DC 12 VDC R1
L1 I
220 PF
-
- AD.J@&
390 1N752A = R65
5.6 V +12 V
-15 v oc
TUNE HlGH
TUNE LOW
ANALOG RTN
diagrams 523-0769 121
Scans by ArtekMedia © 2008
R103 P/O P2
47 I
10 AUX WT HlGH NOTES :
9 AUX OUT LOW 1 UNLESS OTHERWISE SPEC I F IU). RESl STANCE V A L E S ARE I N W ,
1
-
- O CAPACITANCE VALLEI LR I N MI CRWARAOS. YO I W T Y E E
V A L E S ARE I N M I C R M N W S .
470 k f l
ANALOG BOARD A 2 A 2
2 PARTIAL REFERENCE DESIGNATIONS ARE StKMN. FOR C M V E T E
O CESIGNATIDI. PREFIX WITH UNIT ASGWLY DESlGNATlCN.
@ 5 KEY ALL DC VOLTAGES ARE NCMINAL.
47 pF 6 SPARE
7
UNFILTERED COMPOSITE
. COMWS ITE HlGH
COMPOSITE LOW
R13
R115 470 k f l
470 k n
MONITOR HlGH
/OR E l VOR E l
WAS€ AOJ GAIN AJ3J U2A MONITOR LOW
11
7
2
k k , k 1 13 O
12
I LS
B A W E
-p- - . I>-l -
-
u3B
10
l P F Z ~ 7 R22 R23 R4
- 5 k n a
/
15kfl 68.1kfl 5kfl
- 15
"b
I 1
2
@=ILS E l I
-
- PDO
\1 GAlN ADJ
HlGH
LOW
S C H E M A T I C CHA,VGES
A2 Disconnected ~ 1 0 5 - 9 / ~ 1 0 6 - 1 line
0 REV P
from ~ 7 5 - 3 / ~ 1 0 1 - 4
line, and
reconnected ~ 1 0 5 - 9 / ~ 1 0 6 - 1 0line
to U100-12 to improve digital timing
characteristics.
CARRY INH ( 2 )
FMINCK(1) FM l NCK
I1 I
-
I
m ( 1 ) OSC
DACACK( 1 ) DACACK
DACBCK( 1 ) OACBCK
-
L F M N
COD-CO4, COO-CO4,
C06.C07(1) CD6 , C 0 7
ENABLEB
-
A
CARRY
TDM GENERATOR
PHASE GENERATOR
DATA BUFFER
FM l NCK FMINCK(3)
I - I I I I
-
OSC OSC(3)
OACACK DACACK(3)
DACBCK OACBCK( 3 )
H(3)
-
FMWEN m ( 3 )
COO-CO4, COO-CO4,
CD6.CO7
ENPgLEB
- -
A
CC6. C07(3)
ENABLE B I 3 I
CARRY INH(3)
CARRY INH
MEN
1 REGCK( 3 )
m m 3 )
637-8599
TP5-1071-055
P/O TDM BOARD A2A3
FREQUENCY GENERATOR
ACCUMULATOR LOGIC
FMItCK(2) FM l NCK
TO-T4. T O - E , T I D TO-T4, E - R , T I D
OSC(2) m
DACACK( 2 ) DACACK
DACBCK(2) DACBCK
H(2)
- -
FPWN(2) FMWEN
REGCK(2 I
COO-CO4. C06. C 0 7 ( 2 )
mmI3 ( 2 )
- COD-CO4, C06. C07
tNABLE B
-
A
I
FM l NCK ENABLE A ( 4 )
TO-T4, ~ - ~ , T ~ o TO-T4. E-~,T~D
4)
'dSZ:
DACACK DACACK( 4 )
DACBCK OACBCK(4)
I TO-T4, ~ - ~ %l YH T( I4 D, ( ~ )
-
FMEN m ( 4 1
FM GENERATOR
diaarams 523-0769 121
Scans by ArtekMedia © 2008
MICROCIRCUIT INFORMATION
POWER ( V [
P/O TDM BOARD A2A3 U NO TYPE
+151+5 I(
U1 SPARE
U2 1 7489 116 1
U3 / RES ARRAY 1 1 14 1
TO ANALOG t f 5 v DC
CARD
RES ARRAY
74LS175
ANALOG CARO
GtQ
NOTES :
HES ARRAY
M L E S S OTHERWISE SPECIFIED; RESISTANCE V A L E S
@ ARE I N M S . AND CAPACITANCES VALUES ARE I N 74LS175
MICROFARADS. U46 74586
74LSO2
74LS74
RES ARRAY (150C RES ARRAY ( 4 7 0 0 US3 RES A W A Y
Revised
diaarams 523-0769 12 1
Scans by ArtekMedia © 2008
MICROCIRCUIT INFORMATIOE(
P/O T D M BOARD A 2 A 3
J3-77
TO ANALOG +15 v DC
CARD
---I::::
LOG l C GND
10
-
JI-ll JI-28 J2-34 J2-36
ANALOG CARD
GNI
18
NOTES :
SCHEMATIC CHANGES
0 I
X
RF INPUT
K
0
r
00
X
00
x r
m V)
V) m
m
-4 -4
m
- m
-
-4 -I m m
0 --I -4
-- -- - 0 I
W
L 4
Scans by ArtekMedia © 2008
n
71
-
z
w
C
- 4I
7)
r - C
-4 0
2 2 2
O W 0 -4
N
W
0 -
- m
Z
C
D
4
0
n
-
1 R F F
2 VCXO SELECT
3 PHU)CK
4 10 MHz-2 I
5 OlMHz-8
6 0 1 Miz-4
7 1 0 MHz-4
8 10 MHz-8
9 10 H z - 1
0
-4 10 1 MHz-2
VI 11 100 M z LSB
2 12 100 Mia MS8
m
2 13 1 mz-1
V)
m
- 14 1 Hz-8
N
m 15 1 Hz-4
I)
16 25 kHz MSB
17 0 1 MHz-2
18 0.1 MHz-1
19 25 kHz LSB
20 +24 V DC
21 +9 V DC
22 SPARE
23 SPARE
24 SPARE
25 GNO
Z E Z Z G ULl U2l
x x a o
A vcxo 88x4,;<<
n- 2
sz On X X
-I
\
L
W
-------
9
1-- - I
diagrams 523-0769121
Scans by ArtekMedia © 2008
TO SYNTHESIZER
SCHERZATIC CH.4NGE.S
SCHEMATIC CHANGES
VCXO NNE
15 V RETURN
EX7 MOD IN
m
VCXO SELECT
RTTZK
10 w - 2
0.1 H+L-8
0.1 w - 4
10 w - 4
10 M - 8
10 w - 1
1 mz-2
100 mz-LSB
100 mz-HSB
1 mz-1
1 m - 8
1 w - 4
2 5 kHz-HSB
0.1 m z - 2
0 1 M*-1
25 kHz-LSB
+24 V DC
+9 v X
SPARE
SPARE
SPARE
G R W
diagrams 523-0769 12 1
Scans by ArtekMedia © 2008
+24 V DC
t15 V LC
-15 V oc
VARIABLE FREO
CONT VOLTAGE
15 V RETURN
P/O J3 NOTES :
1 W S S OTERWISE SPECIFIED RESISTANCE VALES
+15 V DC t15 V OC O AFE I N hUI. C A P A C I T U X VALES ARE I N MICRO-
FARADS, I W T A N C E VALES ARE I N M l C K H N ? Y S .
-15 V OC -15 V LC AH) TRANS1S T m TYPES ARE m2222A.
R45
2 PARTIAL REFERENCE DESIGNATIONS ARE SHCIM; FOR
15 V RETURN
O CaPLTTE CESlGNATIO( PFEFlX WITH W I T UOm
A S S E M Y DESIGMTION.
MICROCIRCUIT INFORMATION
Ma)
FR
VCXO SELECT VCXO SELECT
Fmxl7 RI-C[IER
10 F M - 2 10 w - 2
0.1 M*-8 0.1 F M - 8
0.1 w - 4 0.1 F M - 4
10 w - 4 10 F M - 4
10 w - 8 10 FM-8
10 w - 1 10 m z - 1
1 mz-? 1 mz-2
100 m z - L S B 100 m - L S B
100 Mi:-HSB 100 m - P G B
1 mz-1 1 FM-1
1 M - 8 1 FM-8
1 mz-4 1 mz-4
25 k k - H S B 25 k k - H S B
0.1 k - 2 0 1 m-2
0 1 m - 1 0.1 m-1
25 kHz-LSB 25 k k - L S B
+24 V LC +24 V M:
+9 v X +9 v DC
SPARE SPARE
DEMO3 OUT
SPARE SPARE
SPARE
G R W
RF LEVEL BIT
diagrams 523-076912 1
Scans by ArtekMedia © 2008
P/O J4
*9 v X
$24 V DC
PI0 J1
"1"
NOTES :
MICROCIRCUIT INFORMTION:
SCHEMATIC CHA.YGES
SPARE
diaarams 523-0769121
Scans by ArtekMedia © 2008
- - - - - - - - - - - - - --
0 -- E
P I 0 REGULATOR /DIVIDER BOARD A4A1A1
635-8516-001 1 ~r
36
9 C39
T;"r.'--
70 pF R35 33 pF
L4
430
-
- -
-
- I P I 0 SYNTHESIZER ASSY A 4
L- - - - - - -
Q8 R47
2N3879 1 %
- - -
+5va I
a a
?$E47 C53
47
R56
270
Q12
2~3879
R54
.47
&+PI 7 O - - - - I
6%
a a a a
U20
-
4
v+ vC
VWT
6
- ~
C27
0 . 0 i0-
C28
- C29
k 0~. 0 0 1 & 0 . 0 0 1 $,I C31
l o .
C33
1 i P 2F I
I-1 "REF CL lo
_1 -
IN"4"&7 I b
$5; T-
NlNV
CS
INV
2
- O I
A
-0
I V- COW R55 t C52
I E R BOARD I & 19 T? -
-
68
1 7 z -
P/O SYNTHESIZER I
- U7
P
NOTES :
ASSY A4 t 2 0 v OC 3.2 MHz TCXO ASSY
"k IN I l4 U6 1. I
2 A4 C A
t 5 VOC 623-5856-001 B 2- A . A x (
C5
0.1
- C4
TO.1
W
-
- I L O B C
11
B
200 kHz 1
B
.;
-
kHz CLOCK
\
2. f
[
-
-
- - - -1
- -
---- R01 R02 - 11 25 kHz
R01
12
R02
13
, -
I I
+5 v DC
+20 v OC ------
637-2718-001 +20 V M:
PHASE-FMQ DlSCR
+20 v DC
'03 R3
(PA) (VCO) TESrSEL
C9
-BAN0 3
diagrams 523-076912 1
Scans by ArtekMedia © 2008
NOTES :
I I I 1
I I
LOSS OF LOCK DETECTOR
LOCK FREQUENCY I-
I +5 v M:
- I -
I -
I u T P u - r AMPL BOARD A4AZ
diaarams 523-0769121
Scans by ArtekMedia © 2008
--------
NOTES :
3.2 MHz TCXO ASSY
3.2 MHz IN 1 . UNLESS OTHERWISE SPECIFIED. RESISTANCE VALUES ARE IN m,
A4 CAPACITANCE VALUES ARE IN MICROFARADS, AM] INDUCTANCE
623-5856-001 VALUES ARE I N MICROHENRYS.
--
U 2. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN; FOR COMPLETE
DESIGNATION, PREF l X WITH UNIT ANl/OR ASSEMBLY DESIGNATION.
I
-----
----- - - , - -
- -
I 0 l c ID-
---
VCO-BUFFER A4A3
LEVEL 2
f
I
53
L1
108-152 MHz
R5
L3
10
1C l O
-
-
470
511 C15
Ql 8
2N5109
\I
3~ CRI C1 I
FD-700 R10
\I
-
- C7 0
ENABLE 2
+20 V DC
LEVEL 1
ENABLE i
LEVEL 3
ENABLE 3
R F OUTPUT
vct
GROUND
+20 v DC
GROUND
Rc~iis~r!
1.5 October 1980 62C/62D
Scans by ArtekMedia © 2008 diagrams 523-076912 1
SCHEMATIC CHANGES
SCHEMATIC C H A Y G E S
FREQ C W O N
NOTES :
1. .
lMLESS OTHEFiW l SE SPEC I F I ED RES l STANCE
VALUES ARE I N CHMS AN) CAPACITANCE VALLES
ARE IFI MICROFARADS.
2. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN
FOR CCMPLETE DESIGNATION PREFIX WITH UNIT
AND/OR ASSY DESIGNATION.
MICROCIRCUIT INFORMATION
U NO 1
I
TYPE II VCC GND SPARE
U1 1 74LS138 1 16 1 8 1 7,9,10
U2 1 74LS32 1 14 1 7 1 SECT ION D
14 SECT l ON D
MODE SELECT A
NAV DISABLE
LOC/GS ENERGIZE
MODE SELECT B
COM DISABLE
TIMING TRIGGER
SCHEMATIC CHARTGES
-- - - - -- - - -
P / o P 8 r
BACK PLANE A7
I
-------- -
1 15VAC (mpfl)15vAc REMOTE TUNE A 8
I RELAY GND
+15 V DC
-15 V M: -15 v 3C
+5 V RTN +5 V RTN
I@ fiFlw2 TUNE
A3
RF
5 V J C +
12 V LX RTN MODULATOR
A5 A3
+12 v M: (
(
SPARE
)O
-
DEMOD OUT
+15 V DC
-15 V M: P/O P4 I A N A L o G A 1z- -
I I I 1 KEY
SPARE -
IP/OP4
COMPOS I TE 4 1 ~ C a P m l T F O J T AUXW
L 15
vcxo u {; - >
b
4
I I
vcxo T u w MCN I TOR
C-sITE {~k-fi1 -
@
CPU A2A1
i
KEY ATTENUATOR AGATI
ANALOG SHLD
+15 V M: +15 V M:
-15 v M: -15 V DC
1 5 V RTN 15 V RTN
2-
t 9 V M:
9 V RTN 4-
D V RTN
8-
1 2 4 V RTN 1 39 1 44
+24 V DC
16-
32 -
64 -
SPARE
--
5 V RTN
A Pr--
diagrams 523-07691 21
Scans by ArtekMedia © 2008
NOTES :
R e ~ ~ i s e15
d October 1980
Scans by ArtekMedia © 2008 diagrams 523-0769 12 1
SCHEMATIC CH.4NGES
I
REVISION DESCRIPTION OF REVISION SERVICE EFFECTIVITY
IDENTIFICATION AND REASON FOR CHANGE BULLETIN
AC POWER
(
aeo
A01
641 1681
TP5-4784-024
SCHEMATIC CHANGES
GND
diagrams 523-0769121
Scans by ArtekMedia © 2008
NOTES :
-
-
ATN
-
€
-
0I
REN
DAV
DAC
IFC
sm
SCHE,MATZC C H A N G E S
NOTES:
@ UNLESS
ARE I N OHMS,
OTHERWISE
AND INDUCTANCE
S P E C I F I E DVALUES
R E S I SARE
T A N IN
C EMICRO-
VALUES
HENRYS.