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VHDL report week 3

CHAPTER 6:
4 to 1 multiplexer
We have 4 inputs called A,B,C,D and also S0 and S1 which depends on the value of S0 and S1 we have
different lesd on and each state of S0 and S1 represent one of the inputs (A or B or C or D).

It photo that I attached below it is shown more clear:

Figure 1https://allaboutfpga.com/vhdl-4-to-1-mux-multiplexer/
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VHDL report week 3
Negin Shiran 452598
VHDL report week 3

1 to 4 demultiplexer

In this the demultiplexer, the output value is decided by the input S0 and S1 because their bit value will
decide the output.
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VHDL report week 3

Connect the two descriptions in a block diagram and give a good simulation:
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VHDL report week 3

CHAPTER 7
When is a tristate needed?
The basic concept of the third state, high impedance (Hi-Z), is to effectively remove the device's
influence from the rest of the circuit. If more than one device is electrically connected to another
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VHDL report week 3

device, putting an output into the Hi-Z state is often used to prevent short circuits, or one device
driving high (logical 1) against another device driving low (logical 0).

CHAPTER 8
1-Gating the clock is not advisable because of the glitch which can occur. The clock tree of the chips are
specifically built to handle anything such as logically control, delay, … It is not recommend to arbitrarily
gating the clock.

2-The first one is the asynchronous reset, clock. When reset is “1”, regardless of clock state, the output
Q3 will be set to “0”. The second one is the synchronous. When the reset is set, it has to wait for the
clock come in then it changes the state to “0”.
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VHDL report week 3