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Dashboard / Courses / Lahore Region / Riphah College of Science and Technology / B.Sc. Electrical Engineering / FALL-2020
/ Digital Logic Design SEC A / 28 December - 3 January / Quiz 5
Shukraan Mubarik
Select one:
a. synchronous, Q1a
b. asynchronous, Q1c
c. synchronous, Q1d
d. asynchronous, Q1b
Response history
Step Time Action State Marks
Select one:
a. synchronous BCD decade counter
b. BCD-to-decimal decoder
Response history
Step Time Action State Marks
Select one:
a. 11
b. 0110
c. 7
d. 4
Response history
Step Time Action State Marks
Select one:
a. 010
b. 110
c. 101
d. 011
Response history
Step Time Action State Marks
Select one:
a. 4 MHz
b. 800 Hz
c. 210.5 kHz
d. 20 kHz
Response history
Step Time Action State Marks
Select one:
a. 5
b. 1 or 4
c. 3
d. 2
Response history
Step Time Action State Marks
Select one:
a. The counter is working correctly.
The correct answer is: The counter is defective; an open exists somewhere
between TC of CTR0 and CTEN of CTR1.
Response history
Step Time Action State Marks
Select one:
a. 5041
b. 5040
c. 5039
d. 5038
Response history
Step Time Action State Marks
Select one:
a. next-state table
b. state diagram
Response history
Step Time Action State Marks
Select one:
a. Waveform d
b. Waveform b
c. Waveform a
d. Waveform c
Response history
Step Time Action State Marks
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