Professional Documents
Culture Documents
2020-2021
A PROJECT REPORT ON
SUBMITED BY:
1) PATIL SHUBHAM NANASO (16)
2) PAWAR TEJAS GOPAL (17)
3) SAWALE KARAN YUVRAJ (18)
(Computer Dept.)
Page 1 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
CERTIFICATE:
This is to certify that:
▪ Roll No: 16
▪ Roll No: 17
▪ Roll No: 18
Diploma in Computer Engineering, has satisfactorily completed the project work under mini
project report on, Project Name:” Study of De mux” under my guidance and supervision,
this is part of partial fulfilment of the requirement for submission of Maharashtra State
Board of Technical Education, Mumbai during Semester third of Academic year 2020-2021.
Page 2 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
Index:
SR.NO PARAMETES PAGE
NO
1 Action Plan 04
2 Introduction 05
3 Demultiplexer (Demux) 06
4 What is Demultiplexer? 06
5 1-to-2 Demultiplexer 07
6 1-to-4 Demultiplexer 09
7 1-to-8 Demultiplexer 11
10 Applications of Demultiplexer 16
11 Acknowledgement 17
12 References 18
Page 3 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
ACTION PLAN
Page 4 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
Introduction
A demultiplexer (or demux) is a device that takes a single
input line and routes it to one of several digital output lines. A
demultiplexer of
n
2 outputs has n select lines, which are used to select which
output line to send the input. A demultiplexer is also called a
data distributor.
Demultiplexers can be used to implement general purpose
logic. By setting the input to true, the demux behaves as a
decoder.
The reverse of the digital demultiplexer is the digital multiplexer
Page 5 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
Demultiplexer (Demux)
The action or operation of a demultiplexer is opposite to that of the
multiplexer. As inverse to the MUX, demux is a one-to-many circuit. With
the use of a demultiplexer, the binary data can be bypassed to one of its
many output data lines.
What is Demultiplexer?
The process of getting information from one input and transmitting the
same over one of many outputs is called demultiplexing. A demultiplexer is
a combinational logic circuit that receives the information on a single input
and transmits the same information over one of 2n possible output lines.
The bit combinations of the select lines control the selection of specific
output line to be connected to the input at given instant. The below figure
illustrates the basic idea of demultiplexer, in which the switching of the
input to any one of the four outputs is possible at a given instant.
Demultiplexers are also called as data distributors, since they transmit the
same data which is received at the input to different destinations.
Page 6 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
1-to-2 Demultiplexer
A 1-to-2 demultiplexer consists of one input line, two output lines and one
select line. The signal on the select line helps to switch the input to one of
the two outputs. The figure below shows the block diagram of a 1-to-2
demultiplexer with additional enable input.
In the figure, there are only two possible ways to connect the input to
output lines, thus only one select signal is enough to do the demultiplexing
operation. When the select input is low, then the input will be passed to Y0
and if the select input is high then the input will be passed to Y1.
Page 7 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
The truth table of a 1-to-2 demultiplexer is shown below in which the input
is routed to Y0 and Y1 depends on the value of select input S. In the table
output Y1 is active when the combination of select line and input line are
active high, i.e., S F = 11.
From the above truth table, the logic diagram of this demultiplexer can be
designed by using two AND gates and one NOT gate as shown in below
figure. When the select lines S=0, AND gate A1 is enabled while A2 is
disabled.
Then, the data from the input flows to the output line Y1. Similarly, when
S=1, AND gate A2 is enabled and AND gate A1 is disabled, thus data is
passed to the Y0 output.
Page 8 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and
S0) and four outputs (Y0 to Y3). The input data goes to any one of the four
outputs at a given time for a particular combination of select lines.
The truth table of this type of demultiplexer is given below. From the truth
table it is clear that, when S1=0 and S0= 0, the data input is connected to
output Y0 and when S1= 0 and s0=1, then the data input is connected to
output Y1.
Similarly, other outputs are connected to the input for other two
combinations of select lines.
Page 9 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
From the table, the output logic can be expressed as min terms and are
given below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select
lines.
Page 10 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
1-to-8 Demultiplexer
The below figure shows the block diagram of a 1-to-8 demultiplexer that
consists of single input D, three select inputs S2, S1 and S0 and eight
outputs from Y0 to Y7.
Page 11 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
The truth table for this type of demultiplexer is shown below. The input D is
connected with one of the eight outputs from Y0 to Y7 based on the select
lines S2, S1 and S0.
From this truth table, the Boolean expressions for all the outputs can be
written as follows.
From these obtained equations, the logic diagram of this demultiplexer can
be implemented by using eight AND gates and three NOT gates as shown
in below figure. The different combinations of the select lines, select one
AND gate at given time , such that data input will appear at a particular
output.
Page 12 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
With a 3-bit storage latch, this IC combines the 3-to-8 decoder function.
Page 13 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
For example, if the application needs 32 output lines from a DEMUX, then
we cascade two 1:16 demultiplexers or three 1:8 demultiplexers. Therefore,
by cascading the two or more demultiplexers, a large demultiplexer can be
implemented.
In the above figure, the highest significant bit A of the selection inputs are
connected to the enable inputs such that it is complemented before
connecting to one DEMUX and to the other it is directly connected.
By this configuration, when A is set to zero, one of the output lines from Y0
to Y3 is selected based on the combination of select lines B and C.
Similarly, when A is set to one, based on the select lines one of the output
lines from Y4 to Y7 will be selected.
Page 14 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
From the above table, the full subtractor output D can be written as
D = f (A, B, C)
= ∑m (1, 2, 4, 7)
Page 15 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
Applications of Demultiplexer
Since the demultiplexers are used to select or enable the one signal out of
many, these are extensively used in microprocessor or computer control
systems such as
Page 16 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
Acknowledgement:
We take this opportunity to express sincere thanks to our project
guide. Ms. Nikam.R. A Under whose guidance our project is
done.
We also thanks to all the Computer department teachers for their
valuable guidance, and timely suggestions without which we
could not complete this project work.
Only because of our staff inspiration and instructions we
could achieve satisfactory completion of project work.
Last but not least, we wish to thanks all of those who have helped us
directly or indirectly in this project work.
Page 17 of 18
COMPUTER ENGINEERING DIGITAL TECHNIQUE
References: -
Page 18 of 18