Lab Assignment 2

Introduction to Modelsim

1 What is ModelSim?
ModelSim is a multi-language HDL simulation environment by Mentor Graph-
ics, for simulation of hardware description languages such as VHDL, Verilog
and SystemC, and includes a built-in C debugger. ModelSim can be used in-
dependently, or in conjunction with Intel Quartus Prime, Xilinx ISE or Xilinx
Vivado. Simulation is performed using the graphical user interface (GUI), or au-
tomatically using scripts. ModelSim PE Student Edition is intended for use by
students in pursuit of their academic coursework and basic educational projects.

2 Installation
1. Download the Modelsim Student Edition by visiting the following link:
https://www.mentor.com/company/higher_ed/modelsim-student-edition

The lab manual is exclusively for the students of the University of Engineering and Tech-
nology, Lahore. ©2020 UET Lahore.

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2. After clicking Download Student Edition, you will be redirected to the next
page where you have to fill in your information as shown in figure below.
Make sure you use a valid email because you will receive the license file
through that email.

3. Click on Submit. Then accept the user agreement on the next page.
4. After clicking the Submit button, you will receive an email which will
provide you with a link to download the software. When you click on that
link, your browser will start downloading the setup file.
5. After the download completion, run the installation file. Make sure you
complete the software installation successfully.
6. After completion of installation a web page will open with a license request
form as shown in figure below.

7. Fill the licence request form and submit it. After submission, you will
receive an email with licence (student licence.dat) attached to it.

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 8. Save the downloaded licence file in the Modeltech pe edu 10.4a folder
in the C drive or the directory where you installed the software.

Note: If you do not receive the license file then you will need to uninstall the
ModelSim Software and then follow the above steps again. You have to start
from the first step again because otherwise you will not receive the file again.

3 Getting Started with ModelSim

A simple logic circuit shown in Figure 1 is simulated in the ModelSim with step
by step instructions.

Figure 1: A simple logic circuit

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 Make a folder containing Verilog and test bench file. The Verilog code for
the given logic circuit and the testbench code are given below.

// V e r i l o g code f o r t h e c i r c u i t o f F i g u r e 1
module myLogicFunction ( output y , i n p u t a , b , c ) ;
a s s i g n y = ( a && b ) | | c ;
endmodule

// Testbench code f o r t h e c i r c u i t o f F i g u r e 1
‘ t i m e s c a l e 1 ns /10 ps // time−u n i t = 1 ns
// p r e c e s i o n = 10 ps
module tb myLogicFunction ;
reg a , b , c ;
localparam period = 10;
myLogicFunction UUT( y , a , b , c , d ) ;
i n i t i a l // E x e c u t e s o n l y once
begin
// Values f o r a , b and c
a = 0; b = 0; c = 0;
#p e r i o d ; // w a i t f o r p e r i o d

a = 0; b = 0; c = 1;
#p e r i o d ;

a = 0; b = 1; c = 0;
#p e r i o d ;

a = 0; b = 1; c = 1;
#p e r i o d ;

a = 1; b = 0; c = 0;
#p e r i o d ;

a = 1; b = 0; c = 1;
#p e r i o d ;

a = 1; b = 1; c = 0;
#p e r i o d ;

a = 1; b = 1; c = 1;
#p e r i o d ;
end
endmodule

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Following steps helps to create a project in ModelSim.

1. Click on File, select New and then Select Project as shown in Figure 2.

Figure 2: Creating a new project.

2. After that a window will open as shown in Figure 3, browse the Project
Location to the folder containing the verilog code and the test bench
code. Then click on OK.

Figure 3: Create Project window.

3. A new window will open as shown in Figure 4, select Add Existing File.

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 Figure 4: Add items to the Project window.

4. After that, a window Add file to Project will open as shown in Figure 5.
Click on Browse and select the Verilog and textbench code file as shown
in Figure 6 then click on Open and then click OK.

Figure 5: Add File to the Project window.

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 Figure 6: Adding verilog and test bench file to project.

5. The two files will be added to ModelSim project as shown in Figure 7.

Figure 7: ModelSim project created.

6. Click on compile all. If there are no errors in the code, the transcript
will show no errors.

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 Figure 8: Compiling on ModelSim.

7. Then Click on Simulate. A start simulation window will open. Expand

the work tab and select the testbench file (in our case tb myLogicFunction).
And click OK. This is shown in Figure 9.

Figure 9: Start Simulation dialog box.

8. ModelSim will load the simulation on the window.

9. Check if the Objects dark blue box is appearing in the window as shown in

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 Figure 10. If this box does not appear click on View and select Objects.

Figure 10: Objects box (dark blue box) in the upper right corner.

10. Right click on any one of the object and then click on Add to then select
Wave and select Signals in region. This is shown in the following Figure
11.

Figure 11: Objects box (dark blue box) in the upper right corner.

11. The Wave window will appear. Select the run length (80 ns) as shown
below.

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 Figure 12: Selecting Run Length (80ns).

12. Click on Run. The simulation waveform will appear on the screen. We
can scroll to check the output of y for all the various inputs as shown in
Figure 13.

Figure 13: Output wave-forms of the logic circuit.

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4 Lab Tasks
Task 1: Write a Verilog code for the following logic circuit and then simulate
on the ModelSim. You should write the testbench code by yourself to simulate
this circuit. Make sure to include all the possible input combinations in the
testbench.

Figure 14: Logic circuit for Task 1

Task 2: Draw the logic circuit corresponding to the following Verilog code.
Clearly label all the nodes.

// V e r i l o g code f o r t h e c i r c u i t o f Task 2
module Task2 ( output out , i n p u t a , b , c , d , s0 , s 1 ) ;
w i r e sobar , s1bar , T1 , T2 , T3 , T4 ;
not ( s0bar , s 0 )
not ( s1bar , s 1 ) ;
and ( T1 , a , s0bar , s 1 b a r ) ;
and ( T2 , b , s0bar , s 1 )
and ( T3 , c , s0 , s 1 b a r ) ;
and ( T4 , d , s0 , s 1 ) ;
o r ( out , T1 , T2 , T3 , T4 ) ;
endmodule

5 Instructions
a) A written report is required for this lab. The report should include the
following:

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 • Answers to all the questions
• A snapshot of simulation waveform for the Task 1. Make sure they are
clearly visible by choosing appropriate time scale (you must include your
registration number on the top right side of snapshot)

• A snapshot of the notepad++ window showing the testbench code for

task 1 (you must include your registration number on the top right side
of snapshot)
• A clear picture of the circuit for task 2 drawn on the paper by hand or by
any software (you must include your registration number on the top right
side of snapshot)
b) The collaboration between students is encouraged, but blind copying or shar-
ing the simulation and report is not allowed. I can randomly ask a student during
the teams meeting session to explain about his/her work. If you are unable to
explain anything in your work, it will be assumed you have copied it and you
may be awarded a zero grade for the lab. So make sure you know everything
that you have done. I am least concerned about how you have learnt something
as long as you have learnt it well.

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