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PRODUCTION DATA – May 23, 2017
Applications
Interior light modules
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Functional Diagram
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Pin Configuration
Pin Description
No Name Type Description
1 GND HV_S Analog ground
LIN ground
LED ground
2 LIN_M HV_A_IO LIN bus line (direction towards master)
3 LIN_S HV_A_IO LIN bus line (direction away from master)
4 VS HV_S Battery supply voltage
5 OUT0 AD_IO LED driver channel 0 & GPIO0
6 OUT1 AD_IO LED driver channel 1 & GPIO1
7 OUT2 AD_IO LED driver channel 2 & GPIO2
8 DB AD_IO Debug interface (GPIO3 and analog input)
EP Exposed Connect to ground
Pad
Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
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Figure 1: Typical leakage current IOUTn,LEAK at pins OUTn. Figure 2: Typical current in sleep mode at pin VS
The IC is in normal mode and the pull-up and pull-down
resistors as well as the LED driver are disabled.
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
3 Electrical Characteristics
(5.0V < VVS < 28V, -40°C < TAMB < +125°C, unless otherwise noted. Typical values are at VVS = 12.0V and TAMB =
+25°C. Positive currents flow into the device pins.)
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Note: The auto-addressing functions have limited ground shift tolerance compared to normal LIN operation.
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3.6.2.2 EEPROM
Table 3.6.2.2-1: Timings
No. Description Condition Symbol Min Typ Max Unit
1 Read access time*) fSYS = 4 MHz tREAD_4MHz 2 us
2 Read access time*) fSYS = 24 MHz tREAD_24MHz 1 us
3 2 x 16 bit page erase time tERASE 4.2 9.0 ms
4 16 bit word program time tPROG 4.2 9.0 ms
5 Data retention of the EEPROM cells*) DREE 15 100 years
6 Endurance of the EEPROM cells*) ENEE 100 k
cycles
7 Cumulative programming events*) 1) write_disturb 12.6 106
*)
Not tested in production
1)
When an address is programmed, the unselected addresses can be subject to a write disturb stress. While a single write disturb event is not a
concern, the cumulative effect of write disturb events can potentially cause bit-flips on the unselected addresses.
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
4 Functional Description
4.1 LIN Transceiver with Slave Node Position Detection (SNPD)
4.1.1 LIN Transceiver; pins LIN_M, LIN_S, GND
4.1.1.1 Characteristics
The LIN bus physical interface is implemented as a LIN 2.2a standard high-voltage single wire interface according
to ISO 9141 for baud rates from 2.4kBds to 20.4kBds. The LIN bus Interface can be operated in Master or Slave
mode. The LIN bus has two logical values. The dominant state - bus voltage near GND - represents logical LOW
level and the recessive state - bus voltage near VS - represents logical HIGH level. In the recessive state, the bus
is pulled high by an internal pull-up resistor and a diode in series, thus no external pull-up components are required
for slave applications. Master applications require an additional external pull-up resistor and a series diode. The
LIN protocol output data stream is converted into the LIN bus signal through a current limited, wave-shaping low-
side driver with control as outlined by the LIN Physical Layer Specification Revision 2.2a. The receiver converts the
data stream from the bus.
The LIN transceiver can handle a bus voltage swing from +40V down to ground and survives -27V. The device also
prevents current flow through the LIN pin to the supply pin in case of a ground shift / loss or supply voltage discon-
nection.
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In sleep mode the LIN block requires a very low quiescent current by using a special wake up comparator allowing
the remote wake up via the LIN bus. The sleep mode can be activated during recessive or dominant level of the
LIN bus line.
To transmit data via LIN bus, the LIN transmitter must be activated. Therefore, bit PHY_CONFIG.lin_on must be
set to H.
The auto-addressing feature added to the normal LIN bus functionality allows slave devices to detect their relative
position within a bus system. The internal hardware extensions needed for that purpose are a shunt resistor
between nodes LIN_M and LIN_S, a pull-up current source and a circuitry that allows to measure the differential
voltage across the shunt resistor. The slaves within such a bus system have to be connected as a daisy-chain. Fig-
ure 4.1.2-1 shows such a bus architecture.
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On the left side of the schematic, the ECU is terminating the LIN bus. Next to it, there is a group of addressable
slaves, each of them having its own auto-addressing circuitry. Finally, shown on the right side of the schematic,
there may be some standard LIN bus transceivers without auto-addressing capability. They may be mixed up with
the addressable slaves in any possible position.
The start of the addressing sequence is initialized by the ECU with a command sent to the slaves telling them that
the addressing sequence starts with the next break field. During the next break field, each slave starts its auto-ad-
dressing sequence. The sequence is divided up in measuring the offset current on the bus line, measuring the bus
load and, depending on the bus load, switching on the current source for the detection of the last not addressed
slave in the line.
Figure 4.1.2-2: LIN BSM auto-addressing block schematic of a single LIN slave
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The different parts can be controlled by software via the registers of the LIN_CTRL Module (e.g. PHY_CONFIG
register). See chapter 4.4.6.8 for details. The ADC can be controlled by the ADC Control Module.
The software can either manage the auto-addressing sequence by accessing the LIN_CTRL registers and following
the sequence shown in the flow chart diagram (Figure 4.1.2-3) or it can enable the implemented auto-addressing
state machine (recommended).
The state machine will step through the flow chart and will automatically set up the pull-up configurations and trig-
ger the ADC measurements as well as calculating the measurement differences and compare the results to
thresholds. Before enabling the state machine, the software has to configure the FSM control registers:
• PHY_CONFIG
• LIN_AA_CONFIG_MODES0 & LIN_AA_CONFIG_MODES1
• LIN_AA_I_DIFF_THD_1 & LIN_AA_I_DIFF_THD_2
The following flowchart shows the command sequence executed during every synch break within the auto-address-
ing process.
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START
All slaves
detect break field
Y Slave already
addressed ?
N
Step 2
Measure bus current ISHUNT1
Step 3
switch on pull-up configuration1
(pre-selection phase)
Step 4
Measure bus current ISHUNT2
Calculate difference
Step 5
IDIFF21 = ISHUNT2 - ISHUNT1
N
Switch off all LIN pull-up switch on pull-up configuration2
sources, wait for end of step 6 (selection phase)
Step 6
Measure bus current ISHUNT3
Calculate difference
Step 7
IDIFF31 = ISHUNT3 - ISHUNT1
N
Slave saves NAD contained
in auto-addressing command
Master
checks: all slaves N
addressed ?
STOP
In order to assure that the different steps of the auto-addressing sequence are executed synchronously by all the
slaves, a timing scheme for the break field is defined. The time reference is the bit time T BIT,SLAVE. The following tim-
ing diagram shows the requested timing for the different steps executed during the break field.
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The LIN auto-addressing measurement scheme is shown in Figure 4.1.2-5. The LIN auto-addressing amplifier has
to be enabled at least tAA,en before it is used. First, the amplifiers auto-zeroing has to be enabled for a time t >
tAA_AZ,act. When auto-zeroing has been finished, the amplifier is settling in t AA,set. After the settling time has elapsed,
the measurements can be done for a time tAA,meas. A new auto-zero sequence has to initiated after this time.
Note: When using the auto-addressing state machine all timings are handled by the FSM. The timings are based
on actual configured baud rate.
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The analog multiplexer is used to measure several voltages with the integrated ADC. Therefore, the selected chan-
nel is buffered and then applied to the ADC input. The channels which can be selected are listed in Table 4.2.2-1
with their ratio from the output voltage to the input voltage.
Note: To measure the forward voltage of the LEDs, the pull-up resistor at the corresponding pin has to be enabled.
The IC has an internal power mode and wake-up logic. This logic includes a state machine which can be controlled
by the microcontroller. Furthermore, another timer is included in the logic. This timer can be used as wake-up timer.
Additionally, the LIN receiver signal is evaluated to detect a wake-up request via LIN (see 4.1.1.3 for further inform-
ation).
Figure 4.3-1 shows the states and the state transitions. After power up, the IC is in NORMAL mode. To go to
SLEEP mode or STANDBY mode, the register POWER.sleep respectively POWER.standby has to be written with
1. If both registers are written at the same time the transition to SLEEP mode is prioritized.
Once in SLEEP or STANDBY mode, the IC can be woken up by LIN or by the wake-up timer. This leads to a trans-
ition to NORMAL mode. All blocks necessary for normal function are enabled during this transition.
The microcontroller can now select the power mode by writing to register POWER in the system state module. Both
states, SLEEP mode and STANDBY mode, behave in the same way except that in STANDBY mode the core regu-
lator stays enabled to maintain the state of the microcontroller, thus the boot process is not needed. The system
clock oscillator and the watchdog clock oscillator are disabled in STANDBY mode.
The wake-up timer is enabled if the timer configuration in register POWER is not 0x00 and the state is either
SLEEP or STANDBY. See chapter 4.3.1 for additional notes on SLEEP and STANDBY mode. If the wake-up timer
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is enabled, the wake-up logic will count upwards from zero to the defined value with a period of T WU_timer. When the
configured value is reached, a transition to NORMAL mode is initiated.
To protect the IC, the integrated temperature sensor monitors the temperature in NORMAL mode to detect over-
temperature events. In case of a junction temperature greater than T J,OT,high, the IC goes into OVER-TEMPERAT-
URE mode. This mode is equivalent to SLEEP mode. The transition to NORMAL mode is only initiated, if the junc-
tion temperature falls below TJ,OT,low.
STANDBY Mode:
When switching to STANDBY mode it is mandatory to additionally enter the CPU HALT mode for a clean CPU
state during STANDBY. See chapter 4.4.5 for details. Be sure to enable interrupts, e.g. SYS_STATE wake-up
event interrupts to be able to recover from CPU HALT after wake-up.
Recommended procedure:
a) configure and enable wake-up interrupts
b) configure wake-up source, e.g. wake-up timer and set STANDBY bit in SYS_STATE.POWER register
c) set HALT bit in CPU status register
Note:The API function is based on function code implemented in a ROM section of the memory located at address
0x0002:
go_to_standby():
BIS #0x0018, R2
NOP
NOP
RET
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Figure 4.4-1: Digital Part Block Diagram (Note: Only 128Bytes of EEPROM memory are usable by customer)
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OTP Programming
All memory cells in the macro are initially manufactured as "0"s and their state may be changed from a "0" to a "1"
using the write (program) operation. Once programmed, it is not possible to reverse a "1" to a "0". Programming is
done one cell at a time.
During program operation the "1"s in the data input word, are "burned" into the addressed memory location. "0"s in
the data input word mask programming in the corresponding bit locations.
Programming is completely controlled by a state machine which can be accessed via the OTP_CTRL module. See
OTP_CTRL register description for details.
The state machine verifies the programmed bit location and, if necessary, repeats programming by inserting "soak
pulses".
The status of the latest word programming can be determined by accessing the OTP_CTRL.PROG_STATUS
register.
4.4.3.3 EEPROM
The EEPROM instance is controlled by the EEPROM_CTRL module.
4.4.3.4 SRAM
• Size: 1.25K byte
• Byte write support
• Per byte parity protection
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• The CPU executes the OTP memory start up code which is usually used to initialize the micro controller
analog part calibration registers.
• The CPU returns to ROM start up code
• The CPU fetches the user program reset vector which is located at address 0xFFFE in the OTP memory
which also enables the JTAG interface for CPU debugging
• The CPU starts executing the user program
An OTP boot vector is valid if:
• it's value is even (bit 0 == 0)
• it points into first 0x80 bytes of OTP memory
• 16 bit CPU
• MSP430 binary code compatible
• Harvard architecture with AHBL data and instruction bus interfaces
• RISC architecture with 27 instructions and 7 addressing modes
• Orthogonal architecture: every instruction usable with every addressing mode
• Full register access including program counter, status registers, and stack pointer
• 16 x 16-bit register
• 64 KByte linear address space
• 16-bit native data bus width
• Constant generator provides six most used immediate values and reduces code size
• Direct memory-to-memory transfers without intermediate register holding
• Word and byte addressing and instruction formats
• IAR development IDE compatible JTAG debug interface
• Several C compilers are available
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Interrupts
The embedded H430 IP core does not contain a primary interrupt controller. It has only a IRQ request signal and
an address, pointing to a vector table in memory, which contains addresses of the interrupt handlers.
Therefore the H430 IP does not support a fixed number of interrupts. Any number fitting reasonable in the 64k
memory range is supported.
All interrupts can be enabled or disabled with the GIE bit in the status register.
You can nest interrupt handlers by disabling the current source and setting the GIE bit back to 1.
The H430 is byte-addressed, and Little-Endian. Word operands must be located at even addresses.
Most instructions have a byte/word bit, which selects the operand size. Appending ".B" to an instruction makes it a
byte operation. Appending ".W" to an instruction, to make it a word operation, is also legal. However, since it is also
the default behavior, if you add nothing, it is generally omitted.
A byte instruction with a register destination clears the high 8 bits of the register to 0. Thus, the following would
clear the top byte of the register, leaving the lower byte unchanged:
MOV.B Rn,Rn
Mostly the on-chip peripherals support only one bus size, e.g. the data width of the processor. These peripherals
must be accesses only with the supported access mode and with correct alignment. Any other access may produce
an undefined behavior.
When performing a word access, address bit 0 is undefined and has to be ignored.
CPU States
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After setting the halt bit in the CPU status register the following instruction will be executed, then halt mode will be
entered. A good idea is to use the following sequence to ensure a later wake up.
BIS #0x18, SR ; sets halt flag and enables interrupts for wake up
NOP ; needed for correct halt entry behavior
• An interrupt will force the CPU to exit the halt mode. The CPU will enter the interrupt service routine directly.
• After the interrupt routine has been finished the CPU will NOT return to previous halt mode.
• A system reset (e.g. by the watchdog) will restart the device and therefore exit the halt mode.
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V: Overflow bit
This bit is set when the result of an arithmetic operation overflows the signed-variable range.
N: Negative bit
This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative.
Word operation: N is set to the value of bit 15 of the result
Byte operation: N is set to the value of bit 7 of the result
Z: Zero bit
This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0.
C: Carry bit
This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred.
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As Modes
Ad Modes
The only addressing mode that uses an extension word is the indexed mode.
The destination operand in a two-operand instruction has only one addressing mode bit, which selects either
register direct or indexed. Register indirect can obviously be faked up with a zero index.
When r0 (the program counter) is used as a base address, indexed mode provides PC-relative addressing. This is,
in fact, the usual way that the H430 assembler accesses operands when a label is referred to.
@r0 just specifies the following instruction word, but @r0+ specifies that word and skips over it. In other word, an
immediate constant! You can just write #1234 and the assembler will specify the addressing mode properly.
r1, the stack pointer, can be used with any addressing mode, but @r1+ always increments by 2 bytes, even on a
byte access.
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Register Direct
Register Indexed
Register Indirect
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All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W extensions.
Byte instructions are used to access byte data or byte peripherals. Word instructions are used to access word data
or word peripherals. If no extension is used, the instruction is a word instruction.
The source and destination of an instruction are defined by the following fields:
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These basically perform dst = src op dst operations. However, MOV doesn't fetch the destination, and CMP and
BIT do not write to the destination. All are valid in their 8 and 16 bit forms.
The status flags are set by RRA, RRC, SXT, and RETI.
The status flags are NOT set by PUSH, SWPB, and CALL.
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Emulated Instructions
There are a number of zero- and one-operand pseudo-operations that can be built from these two-operand forms.
These are usually referred to as "emulated" instructions:
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Relative Jumps
Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jump
range is from -511 to +512 words relative to the PC value at the jump instruction. The 10-bit program-counter offset
is treated as a signed 10-bit value that is doubled and added to the program counter:
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Description
The Vector Interrupt System is a two stage interrupt handling structure. The first stage is located inside the interrupt
capable digital modules. The second stage collects all module interrupts and provides a single interrupt signal to
the CPU. All module interrupts provided to the main interrupt controller are level interrupts.
The Vector Interrupt Control (VIC) logic - included in every module and the main interrupt controller - is built as fol-
lows:
The incoming interrupt sources are latched by hold elements if the interrupt source is classified to be an "event".
"level" interrupt sources are not latched to hold elements. "event" interrupt sources are usually conditions which are
active for a very short time and they need to be latched to be handled. Their latched status flag has to be cleared
by the interrupt handling routine. "level" interrupt sources are usually slow signals and their status changes by the
interrupt handling itself which removes the interrupt condition.
The unmasked interrupt status can be read via the IRQ_STATUS register. Writing to the IRQ_STATUS register
clears all "event" status bits which are written as one. The value of IRQ_MASK bit wise makes the interrupt status.
The IRQ_MASK register can be written directly or modified using the IRQ_VENABLE and IRQ_VDISABLE
registers. These two registers implement a fast vector based mask modification possibility.
The masked interrupt status is converted to an integer value and compared with the value of the IRQ_VMAX
register. It defines a maximum interrupt vector level for the outgoing interrupt.
The IRQ_VNO register implements the possibility to read the current interrupt vector of the highest priority. Low
vector numbers have high priority. This value can be used for a fast table based interrupt routine entry. A write
access to the IRQ_VNO register clears the interrupt status bit of the written vector.
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Features
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Features
• Unsigned/signed multiplication (MPY / MPYS)
• Unsigned/signed MAC (multiply and accumulate) operation (MAC / MACS)
• Using the old result and adding the new product
• 16*16, 8*16, 16*8, and 8*8 bit input data width
• 32/33 bit output data width
• 1 system clock cycle calculation time
• No CPU wait states (no NOP required)
The type of operation to be performed is selected by writing the first operand to one of the following four registers.
Writing the first operand does not start the operation. The first operand (and thus the type of operation) may remain
constant for more than one operation. Writing the second operand starts the operation.
SumLo stores the low word of the result, SumHi stores the high word of the result, and SumExt stores information
about the result.
For signed operations, results are provided in 2's complement format. The sum extension register SUMEXT allows
calculations with results exceeding the 32-bit range. This read-only register holds the most significant part of the
result (bits 32 and higher). The register simplifies multiple word operations, because straightforward additions can
be performed without conditional jumps.
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Note: This configuration when changed by software will take affect not earlier than 30ms after
digital core start up. This guarantees a JTAG availability of at least 30ms after digital core start
up. If 2nd level JTAG access signature was written correctly during this time, this register config-
uration will not take affect and device will stay in debug mode.
used by hardware to allow JTAG access to CPU and instruction memory content
used by hardware to allow JTAG access to CPU and instruction memory content
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used by hardware to allow JTAG access to CPU and instruction memory content
used by hardware to allow JTAG access to CPU and instruction memory content
Table 4.4.6.5-14: Register OSC_5V_CONTROL (0x18) 5V digital part oscillator control register
MSB LSB
Content - - - - - - - - - - - - - - - 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R R R R R R R R R R R R R R W
Bit Description 0 : do_meas -
1: do a 5V digital part oscillator frequency measurement (count system oscillator cycles fitting into
two 5V digital part oscillator cycles)
Table 4.4.6.5-15: Register OSC_5V_STATUS (0x1A) 5V digital part oscillator status register
MSB LSB
Content - - - - - - - 8 7:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R R R R R R R R R R R R R R R
Bit Description 8 : busy - 1 : measurement in progress
7:0 : meas_val - number of system oscillator cycles fitting into two 5V digital part oscillator cycles
Note: measurement is triggered by OSC_5V_CONTROL.do_meas
Note: meas_val is invalid when busy = 1
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Features
• 2 timers
• Pre-divider with:
• Reload value
• Trigger reload possible by software
• Event when zero
• Counter with:
• Reload value
• Trigger reload possible by software
• Can be started / stopped
• Automatic reload possible, otherwise counter stops when reaching zero (single shot mode)
• Event when zero
Using the timers:
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
config
compare_evt
LIN TIMER compare_val
RXD data
data(8) data(8)
dat data(8)
RESYNC
HYST full
eot_evt data_stb RX DMA
fe_evt run
RECEIVER
prty_evt
RX FIFO(1)
brk10_evt
brk11_evt
DATA BUS
read
LIN RX CTRL
brk_evt
sync_err_evt pid_prty_evt
LIN RX BREAK sync_ov_evt conc_brk_evt
rx_2bit_times LIN RX SYNC sync_byte_evt classic_chksum
pid_evt
pid(8)
FRAC DIV Tbit_brk_cnt
config
LIN_AA adc_trigger
FSM adc_data
phy_control
LIN
CHECKSUM
Functional Description
General function can be derived from Register description.
The concurrent break error flag will only be handled during header processing. The software has to handle occur-
ring concurrent breaks during data transmission (unexpected break event during transfer).
Note: Since concurrent break measurement is based on the actual baud_rate and concurrent break measurement
is also enabled during sync byte measurement the actual baud_rate must not exceed 10 times (respectively 11
times when LIN mode is set) the expected baud rate of the external sci. Otherwise low bits of the sync byte are
detected as breaks and sync break measurement will be canceled:
Condition: Actual baud_rate < 11 times expected external baud_rate
Example: When setting internal baud_rate = 115200 concurrent baud measurement works with external
baud_rates down to 10472 baud. The external baud_rate = 9600 baud cannot be synchronized.
Concurrent break measurement supports the LIN requirement of interrupting ongoing frames by a new break/sync
header.
DMA
Start DMA transfer by writing a length to the LENGTH register. Set a valid base address to the DMA_ADDRESS
register before. Write access to the Address register during DMA operation will be ignored.
The LENGTH register will be decremented, the ADDRESS register will be incremented with each transferred data.
If an error occurs the DMA finish flag will be raised and the DMA controller will stop operation and has to be restar-
ted by accessing the LENGTH register.
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Check DMA_LENGTH register and SCI error flags when DMA finished flag is set to check if the DMA transfer abor-
ted abnormally. Possible error cases are:
• For TXD: transmitter disabled, bus error
• For RXD: receiver disabled, bus error
SCI flags are not suppressed during DMA operation. The FIFO_full flags will be handled by the DMA controller.
Reading/writing of the DATA_IO register is prohibited during DMA operation.
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FRAC[00000] = 0/32 = 0
FRAC[00001] = 1/32 = 0.03125
FRAC[00010] = 2/32 = 0.0625
...
FRAC[10000] = 16/32 = 0.5
...
FRAC[11111] = 31/32 = 0.96875
The divider can be used to achieve divisor values between 1 and 2047.96875. The baud divisor
fractional part can be used to fine tune the baud rate in 1/32 steps of the divisor.
Use the following formula to calculate the SCI baud rate:
Note: The 16 bit baud divisor value represents the number of system clock cycles of two bit
lengths. The result of a SYNC byte measurement(see below) can directly be written to the baud
rate register.
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
MSB LSB
3 : header_processing - enable header processing
0: function disabled
1: enable receive header processing: BREAK/SYNC sequence will be detected, PID will be
received and validated, SYNC byte will not be forwarded to receive FIFO, PID byte can be option-
ally be forwarded. PID reception initializes the checksum calculation and generates a header
event.
Note: Recommended for LIN communication
Note: RX unit is disabled during sync byte reception to avoid data reception and framing errors.
2 : break_thd - break detection threshold length
0: break detection threshold 9.5 x TBit (UART mode)
1: break detection threshold 11 x TBit (LIN mode)
Note: use msk_brk_err in UART_CONFIG to avoid frame/parity error generation during break
recognition.
1 : collision - TXD collision detection
0: collision detection disabled
1: collision detection enabled while transmitting
Note: if a collision is detected the transmit process will be aborted immediately, an ongoing DMA
transfer will be stopped
Note: only applicable when operating in single line mode (LIN)
Note: Recommended for LIN communication
0 : autobaud - LIN auto setup new baud rate after reception of valid LIN BREAK/SYNC sequence
0: disabled
1: enabled
Note: Recommended for LIN communication
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MSB LSB
4 : sync_invalid
Write 1 to clear flag
related to header_err interrupt
flag will be raised when receiver unit is in unexpected state after sync byte measurement
Note: only applicable when header_processing is enabled in LIN_CONFIG register
3 : sync_ov - Sync byte overflow
Write 1 to clear flag
related to header_err interrupt
flag will be raised when sync byte counter overflows, e.g. when time between two edges is too
long
Note: LIN header processing will be stopped when overflow error occurs
2 : sync_err - Sync byte error
Write 1 to clear flag
related to header_err interrupt
flag will be raised when sync byte plausibility check failed
Note: only applicable when sync_validation is enabled in LIN_CONFIG register
Note: LIN header processing will be stopped when error occurs
Note: In error case the RX unit is potentially out of sync. All incoming data should be refused until
next break/sync sequence
1 : parity_err - UART parity error
Write 1 to clear flag
related to receiver_err interrupt
flag will be raised when a parity error is detected
Error flag can be suppressed during break with UART_CONFIG.mask_brk_err
0 : frame_err - UART frame error
Write 1 to clear flag
related to receiver_err interrupt
flag will be raised when no stop bit is present. Break signals will generate a frame error. Error flag
can be suppressed during break with UART_CONFIG.mask_brk_err
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Note: As long as timer_prepare is >0 no compare events will be generated, this allows preload-
ing of the timer compare register.timer_prepare works only with timer_enable=1
1 : clk_src - timer_clk_base
Timer counts with
0: 16 x baud rate
1: 1µs clock
0 : enable - Timer Enable
0: timer not running(reset counter to 0)
1: timer running
timer counter is incremented by timer_clk_base
Note: a disabled timer can be auto enabled when a valid break signal is detected and the
'break_restart' bit is set
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4 : bus_err (level) - bus error occurred, see ERROR register for details
3 : sci_timer_ov (event) - SCI timer overflow
2 : sci_timer_cmp (event) - SCI timer compare
1 : rxd_rising (event) - rising edge of RXD signal
0 : rxd_falling (event) - falling edge of RXD signal
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TXD
LIN_M LINSCI
RXD
LIN_S LIN PHY
WITH
AUTO ADDRESSING linsci_rxd Tbit_brk_cnt
config
phy_control LIN_CTRL result
pull-up config WITH AA FSM irq
adc_trigger
adc_data
ADC
The auto-addressing sequence specified in chapter 4.1.2 is supported by a dedicated hardware block.
Features of the hardware support are:
• Automated pull-up configuration handling dependent on the position within the auto-addressing break.
• Position within the break is monitored by a T bit counter
• Pull-up configuration registers LIN_AA_CONFIG_MODESx
• Hardware driven trigger of a the ADC measurement of the shunt current
• Supports two times and four times ADC oversampling
• Hardware driven auto zero signal management
• Calculation of current difference and comparison against threshold values(register LIN_AA_I_DIFF_THD)
• Generation of aa_finished interrupt event when an auto-addressing sequence successfully finished
• Set/reset of aa_store_nad flag which has to be handled by software
• Handling of short auto-addressing breaks (auto abort auto-addressing sequence)
• Handling of errors during auto-addressing sequence
• In case of measurement timeout errors the device behaves like not pre-selected
Enable the hardware support with the PHY_CONFIG.aa_fsm_enable bit.
Set bit PHY_CONFIG.aa_addressed when the device is already addressed.
Use bits PHY_CONFIG.aa_restore_eob and PHY_CONFIG.aa_st5_mid_wait to configure the sequence timing.
Note: When auto-addressing hardware is enabled each falling edge of the RXD signal leads to a start of the auto-
addressing sequence, including the change of the pull-up configuration.
Warning: Since the auto-addressing hardware triggers ADC measurements with high priority the ADC measure-
ments of the currently running application can be delayed.
Note: Software has to consider that shunt measurement has to be finished within the given time in a measurement
step.
This time is limited by:
• Amplifier parameter tAA,meas
• Measurement time window, e.g. 3 x Tbit (baud rate dependent), whereof tAA_AZ,act + tAA,set is used for autozero.
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Since ongoing ADC conversion cannot be interrupted by the auto-addressing ADC trigger, a huge configured
sampling extension can delay the start of the AA measurement and can therefore lead to an aa_adc_timout_evt
error. In addition the sampling extension for the AA measurement must not exceed the given time window. Con-
sider the oversampling config bit PHY_CONFIG.aa_oversampling.
The software has to handle the aa_addressed bit and has to evaluate the resulting aa_store_nad flag.
The hardware follows the auto-addressing sequence in chapter Figure 4.1.2-3 and the timing diagram in chapter
Figure 4.1.2-4.
The following diagram shows the states of the FSM which reflects the sequence:
Reset
STEP0
From all states except STEP6
If (RXD=1)
If AA enabled and falling RXD
reset Tbit counter
STEP1
If end of 1xTbit
Start measurement of ishunt1
If aa_addressed==1
STEP2
Dependent on the current state of the auto-addressing FSM different pull-up configurations are valid:
1. Default Mode: The default configuration is valid in states STEP0 and STEP7. It is also valid when the auto-ad-
dressing hardware is disabled.
2. Offset Mode: The offset mode configuration is valid in states STEP1, STEP2 and in ALL OFF state. It is used to
measure the offset current on the bus and to disable all pull-up sources when the device is already addressed.
3. Pre-Selection Mode: The pre-selection configuration is valid states STEP3 and STEP4. It is used to selected
the last 3-4 not addressed devices on a bus.
4. Selection Mode: The selection configuration is valid in states STEP5 and STEP6. It is used to select the last
not addressed device on the bus.
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Note: When auto-addressing is implemented completely software driven use the default mode setting to set up the
pull-up configuration for the different phases. In that case the ADC measurement can be triggered by writing to the
LIN_AA_ADC_RESULT register. This is only allowed when the AA FSM is disabled (aa_fsm_enable=0) and when
the amplifier is enabled by software (aa_amp_on=1). A finished ADC conversion will be signaled by
aa_adc_valid_evt interrupt.
Note: Auto-addressing can be implemented partial software driven. Use the configuration bits
PHY_CONFIG.aa_st4_sw_wait and CONTROL.aa_st4_sw_proceed to stop the FSM at STEP4 and wait for soft-
ware intervention. The software has the possibility to decide if the the FSM should proceed with STEP5 or with
state ALLOFF. If no software interaction occurs the FSM will step to state ALLOFF.
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Table 4.4.6.8-6: Register LIN_AA_ADC_RESULT (0x08) Auto Addressing averaged ADC input
MSB LSB
Content - - - - 11:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description 11:0 : value - ADC result of I_shunt measurement
read: Averaged result of ADC measurement (two or four times oversampling depending on
aa_oversampling), Value is valid when aa_adc_valid=1. A valid result is signaled by
aa_adc_valid_evt event.
Note: Consider inconsistency of value when measurement is in progress e.g. triggered by the AA
FSM
write: write access triggers i_shunt ADC measurement, use for software driven AA, e.g. when
PHY_CONFIG.aa_disable_adc_trig is set.
Note: To start the measurement the aa_amp_on must be set and the measurement status must
be IDLE
Table 4.4.6.8-9: Register LIN_AA_I_SHUNT_1 (0x14) Auto Addressing I shunt measurement result
MSB LSB
Content - - - - 11:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R R R R R R R R R R R R R R R
Bit Description 11:0 : i_shunt_1 - Result of latest I_SHUNT_1 measurement
Note: i_shunt value will be updated within STEP2 of the LIN Auto-Addressing FSM.
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Features
• 4 IOs ( ports )
• Interrupt capable
• Positive IO signal edge interrupt
• Negative IO signal edge interrupt
• IO [0] is connected to LED0 pin
• IO [1] is connected to LED1 pin
• IO [2] is connected to LED2 pin
• IO [3] is connected to PWM3 / debug pin
Note: When going to standby or sleep, the LED drivers have to be disabled.
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Note: If IO is used as output(GPIO or PWM), the corresponding output driver has to be enabled
in the PWM.CONTROL register.
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Note: IO state can also be read throught this register when PWM module is selected by SELECT
register and related GPIO.DATA_IE bits are set.
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Features:
• DMA based memory read access
• Concurrent CRC calculation
• CPU starts CRC calculation by writing start address value
• Application can run in parallel with little performance loss. See CONFIG register description. The duration of
the CRC calculation depends on the CONFIG and LENGTH register values.
• CCITT-CRC-16 compatible
• Algorithm parameters:
• Generator polynomial = 0x1021
• Check sum initial value = 0xFFFF
Equivalent C code:
int n, b;
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Writing this register starts CRC calculation and CRC_STATUS.state changes to 0. When CRC
calculation has been finished, CRC_STATUS.state changes to 1 or 2.
Note: This value has to be set by Software before starting CRC calculation.
If calculated CRC sum does not match this value, a maskable reset will be asserted.
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With every CRC module DMA read access the CRC check sum will be "extended" by the read 16
bit data word.
To less influence the CPU performance, CRC calculation read accesses can be done with spa-
cing.
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Features
• PWM based trigger to start ADC conversion
• Variable PWM trigger to ADC channels assignment
• Register based conversion trigger
• ADC result data DMA to a 10 word memory area
• 10 result data update interrupts
• Configurable DMA base address
• ADC data valid status
• Valid, when related PWM channel was ON during ADC sampling
• ADC channel 0 has highest priority
• ADC channel 9 has lowest priority
• ADC conversions will be done in order of their priority
• All trigger events will be halted until the corresponding conversion is executed
The cyclic trigger is automatically generated inside the ADC_CTRL module if the cyclic measurement mode is
used.
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Note: When bits in the ORed PWMx_CONFIG are change from '1' to '0' the related pending conversion flags are
cleared immediately.
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Figure 4.4.6.11-3: ADC timing, here a PWM triggered conversion is shown when no ADC conversion is in progress
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At the moment the ADC samples an ADC channel the status bit related to this ADC channel is set
to 1 when ALL configured (enabled by PWMx_CONFIG) PWM channels are active (ON) other-
wise the status bit is cleared to 0.
When an ADC channel is only configured (enabled) in one PWMx_CONFIG register, the status
bit is set to 1 when the related PWM channel is active at the moment the ADC samples and
cleared to 0 otherwise.
Delayed PWM triggers will be scheduled and "executed" in order of their priority. It may be hap-
pen that a conversion is done some system clock cycles later than determined by the trigger
delay. The valid flag is set after a conversion when the related PWM output was active during the
ADC conversion else it is cleared.
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extend ADC sample time by given number of ADC half clock cycles
extend ADC sample time by given number of ADC half clock cycles
extend ADC sample time by given number of ADC half clock cycles
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Features
• 3x Low-side LED driver configuration and 1x digital output configuration (GPIO3)
• 4 x 8 bit pre-scaler
• 4 x 16 bit PWM channel with independent period length, pulse start and pulse stop timestamps
• External PWM signal polarity configuration
• Period, pulse start and pulse stop interrupts per channel
• PWM channel related trigger delay (timestamp) configuration (see ADC_CTRL module)
• Pre-scaler, period, pulse start, pulse stop, polarity and ADC_CTRL.trigger_delay configurations will be loaded
into active (current) registers with channel related period event
• START-STOP cases
• start < stop : PWM pulse length > 0
• ON at start
• OFF at stop
• start == stop : PWM pulse length = 0
• 0% ON
• start == 0, stop == period
• 100% ON
• start > stop : PWM pulse length > 0 (inverted pulse form behaviour)
• OFF at stop
• ON at start
Please note: The picture shows the none continuous transition at 0 where (stop-start) changes its sign.
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POLARITY.pwm_term:
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Figure 4.4.6.12-4: PWM output behavior in relation to the setting of start and stop(1)
Figure 4.4.6.12-5: PWM output behavior in relation to the setting of start and stop(2)
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ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Features:
• Read mode and read speed configuration
• OTP programming configuration
• OTP programming state machine control
Note: The READ_CONFIG and PROG_CONFIG registers can only be written once. A write access protects their
contents. Usually they will be set during boot procedure.
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Table 4.4.6.13-5: Register WDATA0 (0x08) OTP write data [15:0] register
MSB LSB
Content 15:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description 15:0 : data - OTP write data bits [15:0]
Note: If WDATA0 register is not written since last WADDR write, it's content will be cleared to 0
at WADDR write and it will not be used in the programming process. This makes possible to write
a 16 bit word in case of an already written 16 bit word at the other address of the corresponding
32 bit word.
Table 4.4.6.13-6: Register WDATA1 (0x0A) OTP write data [31:16] register
MSB LSB
Content 15:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description 15:0 : data - OTP write data bits [31:16]
Note: If WDATA1 register is not written since last WADDR write, it's content will be cleared to 0
at WADDR write and it will not be used in the programming process. This makes possible to write
a 16 bit word in case of an already written 16 bit word at the other address of the corresponding
32 bit word.
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Table 4.4.6.13-9: Register BIT_SOAK_STATUS (0x16) OTP bit soak status register
MSB LSB
Content - - - - - - - - - - 5 4:0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R R R R R R R R R R R R R R R
Bit Description 5 : take - 1 : increment soak count of bit "soak_bit" by 1 (program software has to evaluate this for
getting soak count information)
Note: protect bits can only be set. Once set they cannot be cleared again.
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0 : no protection
1 : 128 byte (0x0080)
2 : 256 byte (0x0100)
3 : 384 byte (0x0180)
4 : 512 byte (0x0200)
5 : 1024 byte (0x0400)
6 : 1536 byte (0x0600)
7 : 2048 byte (0x0800)
Note: Once written, this register cannot be changed anymore. This register will usually be initial-
ized during boot process (device calibration).
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Features:
• EEPROM memory erase and write access is protected by a special handling sequence
• To erase or write access the EEPROM this sequence has to be used by software
• This sequence is necessary to lower the risk of accidental EEPROM erase or write
• 1. Increment lock counter 9 times => lock_counter == 9
• 2. Configure LOCK_L/LOCK_U register(s) if needed
• LOCK_L/LOCK_U bits can only be configured when lock_counter == 9
• 3. Increment lock counter 2 times => lock_counter == 11
• 4. Configure LOCK_U_FREEZE register if needed
• LOCK_L_FREEZE/LOCK_U_FREEZE bits can only be configured when lock_counter == 11
• 5. Increment lock counter => lock_counter == 12
• 6. Set needed MODE bits
• MODE bits can only be configured when lock_counter == 12
• 7. Increment lock counter => lock_counter == 13
• 8. Write data to memory area OR do erase mode dummy write to memory area
• 9. Read STATUS until STATUS.busy == 0
• When writing LOCK_CNT with 0 value, MODE, LOCK_CNT (lock_counter) and LOCK_L/LOCK_U will be reset
to their default or frozen state
Note: Erased data words should be programmed before they are erased again. Violating this constraint will result in
unnecessary bit-cell stress.
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The status is self timed and depends on the IP and may vary between devices and over voltage,
temperature and time.
To be sure that a started erase or program operation has been finished poll STATUS.busy until
it's 0.
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Note: Lock bits can only be changed (set or cleared) when related LOCK_FREEZE bit is 0.
Note: Lock bits can only be changed (set or cleared) when related LOCK_FREEZE bit is 0.
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Note: Freeze bits can only be set. Once set they cannot be cleared again.
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Note: Freeze bits can only be set. Once set they cannot be cleared again.
0 : OFF
1 : ON
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5.2 Latch-up
Latch-up performance is validated according JEDEC standard JESD 78D.
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5.3 EMC
The device fulfils the OEM EMC requirements specified in the "Hardware Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications", V1.3, dated 04.05.2012
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6 Package Reference
The E521.36 is available in a Pb free, RoHs compliant, SO8ep plastic package according to JEDEC MS-012-F,
variant BA. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020C with
a soldering peak temperature of 260°C.
Note: Thermal resistance junction to ambient Rth,ja is typ. 45 K/W, based on JEDEC standard JESD-51-2, JESD-51-
5 and JESD-51-7.
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E52136B
XXXXC
YWWR@
Table 6.1.1-1: Top Side
where
Signature Explanation
E52136B Elmos project number
XXXX Production lot number
C Assembler code
YWW Year and week of assembly
R Mask revision code
@ Elmos internal code
Table 6.1.1-2: Marking of the Devices
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7 General
7.1 WARNING - Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability
to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products, to observe
standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor AG Product
could cause loss of human life, body injury or damage to property. In development your designs, please ensure that
Elmos Semiconductor AG products are used within specified operating ranges as set forth in the most recent
product specifications.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
8 Contact Info
Table 8-1: Contact Information
Headquarters Phone: +49 (0) 231 / 75 49-100
ELMOS Semiconductor AG Fax: +49 (0) 231 / 75 49-149
Heinrich-Hertz-Str. 1, sales-germany@elmos.com
D-44227 Dortmund (Germany)
www.elmos.com
Sales and Application Support Office North America Phone: +1 (0) 248 / 8 65 32 00
ELMOS NA. Inc. Fax: +1 (0) 248 / 8 65 32 03
32255 Northwestern Highway, Suite 220 sales-usa@elmos.com
Farmington Hills, MI 48334 (USA)
Sales and Application Support Office Korea and Japan Phone: +82 (0) 31 / 7 14 11 31
ELMOS Korea sales-korea@elmos.com
B-1007, U-Space 2, #670 Daewangpangyo-ro, Sampyoung-dong,
Bunddang-gu, Sungnam-si Kyounggi-do
463-400 Republic of Korea
Sales and Application Support Office Singapore Phone: +65 (0) 690 / 8 12 61
ELMOS Semiconductor Singapore Pte Ltd. Fax: +65 (0) 6570 / 5906
3A International Business Park, sales-singapore@elmos.com
#09-13 ICON@IBP, Singapore 609935
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.