2017 International Conference on Recent Advances in Electronics and Communication Technology
Design and Implementation of
High Speed FPGA for
Under & Over Voltage Protective Relay
1 2
Venkateshmurthy.B.S
Research Scholar, Dept. of Electrical Engineering,
Jain University, Bangalore, India
bsvmurthy364@gmail.com
+917204384964
ABSTRACT: In this paper we present a novel
approach based on FPGA for the protection of power
system based technology from under/over voltage. It
has been always a matter of challenge to design the
system with optimal power usage and protection from
excessive voltage. Considering Power system, it has
become very much necessary to have an additional
system which is smart and capable of having
intelligence to take the predefined decision based on
the applied input. Keeping this context in mind a
FPGA based low power system has been proposed in
the paper that is solely responsible for the execution
of the complete power protection system. The
Solution suggested here is optimal and low cost
intelligent solution as compared to the present
systems that are currently used in the industry.
Design is made to provide the system with over
voltage and under voltage protection. It is capable of
providing protection against sudden transit.
KEY WORDS: FPGA, Voltage calculation, power
utilization, Surg, over voltage, under voltage,
protection.
INTRODUCTION:
FPGA technology has taken over almost all the high
speed and image processing application based project
due to its ability to deliver high speed and at the same
time its proficiency in executing the complex
algorithm. Another major advantage of FPGA is its
low power consuming ability. A small study on
various other devices such as DSP, High Speed
processor, and Microprocessors has proven that use
of all the above component makes an application
978-1-5090-6701-5/17 $31.00 © 2017 IEEE
DOI 10.1109/ICRAECT.2017.25
Dr.K.R.Nataraj
Professor & HOD, Dept of ECE, SJBIT.
Bangalore, India
nataraj.sjbit@gmail.com
+919916065415
faster compact, more efficient and reliable as
compared to the conventional one that makes use of
solid state components. Over all study of all the
previous system and the advantages of FPGA has
inspired us to do some novel work in control of
power system based applications using FPGA.
To bring the system in to the use for real time
application we have done a study on the components
need to be used for the system. After finalizing the
FPGA as a main processing element we have
concentrated on an interface module which will
protect the system and be an actual point of contact
for the FPGA and Design to be protected. After a
detailed study on relays it was finalized that the
numerical relays are the best in the industry for this
kind of applications. It has been studied that these
numerical relays are provided with inbuilt
transducers that are capable of sampling the analog
signal at the mentioned rate and produce an
equivalent digital output of required bits. This
provision of numerical relays reduces lot of physical
hardware component on board and also the cost is
optimized. The data provided by these relays can be
further used buy the processing element to implement
the algorithm and provided relay with specific
command to produce the corresponding results.
These relays have given a rise to a complete new era
for the development of control system based on these
relays. Lot of research is being done on making these
relays more intelligent and active in taking the
decision. Various people are trying with
implementation of Artificial Neural Network(ANN)
and Fuzzy logic based system on the relay unit to
make it more efficient and reduce the hardware
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complexibility at the same time maintain the
advantage of low power and low prize.
Our work mainly concentrate on usage of these relays
to acquire data and make it available in digital format
for the usage in FPGA for processing based on
algorithm developed in the system.
PREVIOUS WORK
Below shows the basic block diagram for the system
based on DSP that has been implemented in the past
using Numerical Relay. As shown in the figure 1. It
consists of power supply for the entire unit to power
up the section. It comprises numerous input and
output block that are responsible to the perfect
transfer of the data at the point of interface. The main
component of the system is DSP block or the
microprocessor block. It can be more than one as
they perform certain dedicated task only.
Figure1. DSP Based Block Diagram of a Numerical
Relay
The number of processors is more due to various
operation that needs to be implemented for example
the implementation of algorithm is done by one and
the other is used for the control action numerical
relay where as other can be used for the interface
with the input and output block. Other DSP or
Microprocessor are used for performing any
dedicated logic or are associated for HMI (Human
Machine Interface). Then system has an internal bus
interface for efficient communication among the
devices. This is built for the reduction on physical
parameters such as connecting wire. Dedicated
PCB’s are used for implementation of such a design.
This reduces the overall hardware and improves the
performance of the system. The design has been
implemented so that the system is at good speed.
While the development has been is was very
necessary to implement the design in such a way that
the system of noise free and do not reduce the
operation speed of the executing system. The care has
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been taken in the system in such a way that the there
is an isolation in input and output block. The Optical
isolation technique has in introduced for digital input
and outputs in the design in order to keep the internal
circuit away from the transients. In the same manner
the care has also been taken to provide the isolation
to the analog circuit. A Precision transformer has
been used to perform the isolation for the analog
input. These isolation are very much necessary to be
provided in order to harmful transients and also to
maintain the accuracy. The system has been designed
to take care for the input signal to look smooth and
not exceed the given amplitude in the situation with
over power supply voltage. This design helps the
designer to take care at the time when input signal
looks distorted or not even during the over voltage at
the input.
In order to reduce the cost of the system a single
Numerical relay has been used with a high speed
multiplexer that is used to take to multiple input to
the system without using multiple relays. To perform
the operation on the input voltage it is very much
necessary to bring the input signal in the necessary
computational form to do so dedicated sine and
cosine filter with the required frequency response has
been incorporated to extract the necessary component
such as real and imaginary elements.
The basic problem with the present system is the total
physical hardware requirement is very has as there
are dedicated processors for each operations which
increases the cost of the system. Also it reduces the
overall speed of operation as multiple processors will
take their own time to perform the operation and if
the design is sequential then the situation gets worst.
To overcome the drawbacks of the system we
propose the system which will take all the advantages
of the previous system and will incorporate a new
design that will be advantageous from all the
technical point and financial point also it will
improve the system performance and efficiency.
PROPOSED SYSTEM
Below shows the simplified basic block diagram for
the system that will be developed based on FPGA for
the over and under voltage protection. As we can see
from the block diagram the application unit or the
system that needs to have an over and under voltage
protection is connected to the signal conditioning
system in order to generate the necessary digital
signal for processing in FPGA.
Application Signal
System Conditioning
Physical FPGA for
Control Unit Algorithm
Figure2. Top Level Block diagram for FPGA
based control system
The data acquired by FPGA goes through an
algorithm implemented to calculate the cutoff for the
system to be protected from over and under voltage
protection. Based on the processed data the control
signal are generated and given as an input to relay
unit to perform the action of cut off the unit and
protect the same without any manual interference.
Figure3. Automated System
Above shows the block diagram for the generalized
automated system used for the protection. The block
diagram describe the use of Isolators for protecting
the circuit from the transit also the design is
connected to a computer to collect the data and keep
for the future use. The use of Numerical relays in the
system has simplified the operation of the design. As
discussed in the previous system it was generated
based on traditional concept of open delta VT
connection. With the use of numerical relay the
voltage and current can be derived easily in the form
of (Va, Vb, Vc) and (Ia, Ib, Ic) respectively. With the
ease of having all the digital data all the traditional
and additional circuit can be easily eliminated and an
efficient system can be built. While modifying the
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design the care has to be taken that the accuracy and
speed of operation should not be affected. Hence,
implementing the design on FPGA is the best
solution to overcome the present problems and give
the best possible solution. Below shows the block
diagram for final implementation blocks for the
control system. The design is implemented on FPGA
and so that whole system can be easily incorporated
on single chip. The biggest challenge while
implementation is about the various interfaces such
as digital convertors and algorithm implementation
for generation of control signal for the relay logic and
communication with data base and feedback from the
system.
Figure4. Functional block diagram of delay relay
The whole architecture has been divided in to three
main parts mainly first is the digital architecture
based on FPGA implementation. This block is further
sub divided in to three main divisions that is memory
unit that act as an temporary storage for the system.
The data is stored from the memory and also new
data that is given as an input to the design. Next
important block is digital filter which is used for the
removal of unwanted signal to enter the algorithm
process. Final block in FPGA design is algorithm and
relay logic. This block is heart of the system the main
decision is based on this block to perform the control
logic. Other main block of the system is interface of
the system with various analog and digital
connections to the design. The whole system is
powered by power supply which is the third and last
block of the system.
FPGA
FPGA is used as a replacement element to DSP and
Microprocessor for enormous advantages. FPGA
gives a next generation programmable logic. It comes
with large numbers of advantages such as efficeient
device utilization, high speed of operation, stand
alone system, better power utilization, better power
utilization, compact, etc. The greatest advantage with
FPGA is that they are end user programmable and
there is not restriction by the manufacture in terms of
programming such as various DSP’s or Controllers or
processors. This flexibility makes these device hot
cake and favorite among the designers. FPGA mainly
comprises of three main configurable components:
(i) IOBs –input/output blocks at the perimeter
(ii) CLBs- configurable logic blocks as a core array
(iii) large number of resources for interconnection
`
Figure5. Internal Structure of FPGA
The fig .5 shows the basic internal structure of FPGA
chip. The major block in the structure is CLB this
large number of CLB enables the end user to design
without any restriction or limitation as in other
programmable device. The advantage comes to the
picture when there is large possibility of
interconnection of each CLB to other based on the
huge interconnection module. Due to sufficient
availability of the Input and output block there is no
limitation to number of inputs and outputs for
specific application. Summing the entire internal
component it is clear that these features of FPGA
makes it most liking component as a programmable
unit in the design.
DATA ACQUISATION BLOCK
The proposed architecture comprises of data
available in different format. It is always necessary to
convert the data in the necessary format for the
internal processing. The data at end application is in
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analog format and the data required for the
processing of system by FPGA should be in digital
format. Hence it is very much necessary for the
converting the analog data from the end application
in to the digital format for the processing. To perform
this operation the system has been designed to
interface an analog to digital converter to the FPAG.
Main operation performed by this unit is to take the
data in analog format from the end application of the
end system and convert in equivalent digital format
and provide it to the FPGA for further processing. To
perform the above mentioned task an state machine
with following flow chart has been implemented.
Figure6 . Flow Chart for DA block
Figure 6 demostrate the basic flow chart for the
interface module implemented in FPGA for the
communication with ADC. When the system starts
initialization of the input and other parameters is
done. After that the channel is selected by FPGA
from which the analog signal needs to be converted.
Then the start of signal is send to the ADC to initiate
the process of conversion. This process basically
needs some time so the FPGA enters in the wait state
and do not perform any operation. It basically waits
for the response from the ADC, once the end of
conversion signal is received from the ADC the data
available on the data output of ADC is captured is
transferred to the FGPA for further processing. The
data generated by the ADC is just the binary
equivalent of the input analog signal and needs
further processing on it so that it can be either used
for the algorithm or for display. The above mentioned
description has been coded in verilog HDL and
synthesize on Xilinx ISE 14.1 for device utilization.
Below shows the design summary for the unit.
Figure7. Design Summary for DA block
Also the design has been verified for the functional
behavior in model-sim. A dedicated test bench has
been developed to check the behavioral functional of
the developed code. And it is found be perfent in
operations. Figure8 shows the simulation output
obtained by the code.
Figure8. Simulation results for Data Acquisition
CONLUSION:
FPGA based system will be providing an ultimate
solution to the present power system based
application by providing them with efficient and
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improved protection from over/under voltage loss.
The system will be comparatively faster in response
and the overall power consumption will come done
for the entire system. Also it can be concluded that
the cost for the entire system will be less as compared
with present solid state component based system.
Performance in terms of speed of execution and
power consumption will be reduced. Usage of
Numerical Relay has reduced the design complexity
as inbuilt transducers can be used for data conversion
from analog to digital. Also cost in terms of
individual transducer and relay has also been
reduced. The entire system is more efficient as it is
complete digital execution. The performance has
been improved and design complexity has been
reduced.
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