Compal La-8131p, La-8133p r1.0 Schematics

1 2 3 4 5
Compal Confidential
Model Name : QILE1 & QILE2
File Name : LA-8131P, LA-8133P
BOM P/N:
A
QILE1: A
4319GG39L01 : SMT MB A8131 QILE1 DIS-N13P
4319GG39L02 : SMT MB A8131 QILE1 DIS GPU-N13M
4319GG39L03 : SMT MB A8131 QILE1 UMA
QILE2:
4319GJ39L01 : SMT MB A8133 QILE2 DIS-N13P
4319GJ39L02 : SMT MB A8133 QILE2 DIS GPU-N13M
4319GJ39L03 : SMT MB A8133 QILE2 UMA
Compal Confidential
B B
M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
GPU nVIDIA N13M-GE1 / N13P-GL
C
2012-01-11 C
REV:1.0
D D
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8133P
Friday, January 13, 2012 Sheet 1 of 58
1 2 3 4 5
A B C D E
ZZZ
LA8131P
DA_PCB
DA80000QL00 nVIDIA N13M-GE1
DDR3*4
VRAM 256M*16/
128M*16/64M*16 Intel
1
nVIDIA N13P-GL Memory Bus 1
DDR3*8 PCI-E X16 Ivy Bridge Dual Channel

VRAM 256M*16/ 1.5V DDR3 1600MHz
DDR3-SO-DIMM X2
rPGA 989 Socket Page 11~12
128M*16/64M*16 Page 24~32
37.5mm * 37.5mm
HDMI Connector Page 4~10

HDMI
Page 34 FDI x8
DMI x4
(UMA) 100MHz 2Channel Speaker
100MHz Page 35
5GB/s
CRT Connector 2.7GT/s
RGB Digital MIC
Page 33 HD Audio Audio Codec
Page 35
Intel CX20671-21Z CODEC
LVDS Connector LVDS

2
Page 32
Panther Point Page 35 Audio combo Jack 2
Page 35
PCI-E FCBGA 989 Sub-Board
Card Reader 25mm*25mm USB 2.0
cable CMOS Camera Page 32
Realtek RTS5229 HM76
SPI ROM USB 3.0
Page 36 SPI
BIOS 8M+4M SATA USB PORT 2.0 x 1(charger)
Page 13 Page 13~21
Realtek Page 39
RTL8111F(Giga) cable
Sub-Board
Page 40 LPC BUS Finger Printer
UPEK TCS5DA6C0 Page 40
RJ45 CONN EC TPM

ENE KBC9012 Page 40
3
Page 40 USB PORT 3.0 x 3 3
Page 41 Page 37
Sub-Board
Track Point G-Sensor
Page 39 Page 36 SATA3.0 HDD CONN Page 36
PCI Express USB(BT)

Click Pad Int.KBD Thermal Sensor SATA ODD CONN Page 36
Mini card Page 39 Page 39 Fintek F75303M Page 39
Slot 1 Page 38 PCI-E(WLAN) m-SATA CONN Page 38
WLAN/WiMAX/BT
PCI Express USB
Mini card SATA

4 Slot 2 Page 38
4
WWAN/mSATA
SIM Card Security Classification Compal Secret Data

Title
Page 38 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Block Diagram
Custom 1.0
Date:
LA-8133P
A B C D E
1 2 3 4 5
Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+5VS Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
A +5VALW +CPU_CORE A
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +1.5V +VGA_CORE
+3VM
+3VALW +VCC_GFXCORE_AXG
+1.05VM
+1.8VS
State +0.75VS
+1.05VS BOARD ID Table
Board ID PCB Revision
0 0.1
1 0.2
S0
O O O O O 2 0.3
M3 Supported
3 0.4
S3 O 4 0.5
O O O X M3 Supported
5 0.6
S5 S4/AC O 6
O O X X M3 Supported
7
S5 S4/ Battery only
X X X X
B B
S5 S4/AC & Battery
don't exist
X X X X
USB Port Table BOM Structure Table
3 External BTO Item BOM Structure
USB 2.0 Port USB Port Connector CONN@
EC SM Bus1 address EC SM Bus2 address 0 45 LEVEL 45@
UHCI0
1 USB 3.0 Port (Left Side) Unpop @
Device Address Device Address
Smart Battery 0001 011X b Thermal Sensor Fintek F75303M 1001_101xb
2 USB 3.0 Port (Left Side) nVidia DIS@
UHCI1
3 USB 3.0 Port (Left Side) INTEL DD3 M3 M3@
EHCI1
4 SIM Card Slot 3G@
USB3.0 UHCI2
5 Camera Intel UMA UMA@
PCH SM Bus address 6 VRAM Option X76@
UHCI3
7 Intel SBA SBA@
Device Address
DDR DIMM0 1001 000Xb
8 Intel AOAC AOAC@
UHCI4
DDR DIMM2 1001 010Xb
9 USB Port (Right Side) TPM TPM@
10 Mini Card(WLAN/BT) GPU N13M N13M@
EHCI2 UHCI5
11 FPR GPU N13P N13MP
C
12 Mini Card(WWAN) C
UHCI6
13 Blue Tooth
SMBUS Control Table

WLAN Thermal
SOURCE VGA BATT KE9012 SODIMM WWAN Sensor PCH
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB9012 X X X X X X V
+3VS
+3VALW
SMBCLK
SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
+3VALW
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X +3VS
V X
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
A A
JCPU1A CONN@
J22 PEG_COMP R1 1 2 24.9_0402_1% +1.05VS PEG_ICOMPI and RCOMPO signals should be shorted and routed
PEG_ICOMPI
PEG_ICOMPO J21 with - max length = 500 mils - typical impedance = 43 mohms
(15) DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 PEG_ICOMPO signals should be routed with - max length = 500 mils
(15) DMI_CRX_PTX_N1 B25 DMI_RX#[1] - typical impedance = 14.5 mohms
(15) DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] (22)
(15) DMI_CRX_PTX_N3 B24 K33 PCIE_CRX_GTX_N0
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N1
PEG_RX#[1] M35
(15) DMI_CRX_PTX_P0 B28 L34 PCIE_CRX_GTX_N2
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N3
(15) DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35
(15) DMI_CRX_PTX_P2 A24 J32 PCIE_CRX_GTX_N4
DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N5
(15) DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N6
PEG_RX#[6] PCIE_CRX_GTX_N7
(15) DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PCIE_CRX_GTX_N8
(15) DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PCIE_CRX_GTX_N9 PEG Static Lane Reversal - CFG2 is for the 16x
D21 E34 PCIE_CRX_GTX_N10
E32 PCIE_CRX_GTX_N11
PEG_RX#[11] PCIE_CRX_GTX_N12
G22 D33 1: Normal Operation; Lane # definition matches
(15)
(15)
(15)
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
D22
F20
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
D31
B33
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N14
CFG2 * socket pin map definition
PCIE_CRX_GTX_N15
PCI EXPRESS* - GRAPHICS

(15) DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32
PCIE_CRX_GTX_P[0..15] (22) 0:Lane Reversed
J33 PCIE_CRX_GTX_P0
PEG_RX[0] PCIE_CRX_GTX_P1
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P2
(15) FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P4
(15) FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PCIE_CRX_GTX_P5
F18 G31 PCIE_CRX_GTX_P6
Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P7
C20 F30 PCIE_CRX_GTX_P8
D18 E35 PCIE_CRX_GTX_P9
E17 E33 PCIE_CRX_GTX_P10
B (15) FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] B
F32 PCIE_CRX_GTX_P11
PEG_RX[12] D34
A22 E31 PCIE_CRX_GTX_P13
(15) FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PCIE_CRX_GTX_P14
E20 B32 PCIE_CRX_GTX_P15
(15) FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] (22)
B20 M29 PCIE_CTX_GRX_C_N0 C1 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N0
(15) FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N1 C2 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N1
D19 M31 PCIE_CTX_GRX_C_N2 C3 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N2
F17 L32 PCIE_CTX_GRX_C_N3 C4 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N3
L29 PCIE_CTX_GRX_C_N4 C5 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N4
PEG_TX#[4] PCIE_CTX_GRX_C_N5 C6 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N5
(15) FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
(15) FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_C_N6 C7 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N6
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_C_N7 C8 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N7
PEG_TX#[7] J30 1 2
(15) FDI_INT H20 J28 PCIE_CTX_GRX_C_N8 C9 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N9 C10 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N9
PEG_TX#[9] H29 1 2
(15) FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N10 C11 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N10
FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_C_N11 C12 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N11
(15) FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2
F27 PCIE_CTX_GRX_C_N12 C13 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N12
PEG_TX#[13] D28 1 2
+1.05VS F26 PCIE_CTX_GRX_C_N14 C15 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_N14
PEG_TX#[15] E25 1 2
R2 1 2 24.9_0402_1% EDP_COMP A18 eDP_COMPIO PCIE_CTX_GRX_P[0..15] (22)
A17 M28 PCIE_CTX_GRX_C_P0 C17 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P0
R3 @ eDP_ICOMPO PEG_TX[0]
1 2 10K_0402_5% B16 eDP_HPD# PEG_TX[1] M33 PCIE_CTX_GRX_C_P1 C18 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P1
M30 PCIE_CTX_GRX_C_P2 C19 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_C_P3 C20 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P3
PEG_TX[3] L31 1 2
C15 L28 PCIE_CTX_GRX_C_P4 C21 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P4
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_C_P5 C22 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P5
D15 eDP_AUX# PEG_TX[5] K30 1 2
K27 PCIE_CTX_GRX_C_P6 C23 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P6
eDP
PEG_TX[6] PCIE_CTX_GRX_C_P7 C24 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P7
PEG_TX[7] J29 1 2
eDP_COMPIO and ICOMPO signals C17 J27 PCIE_CTX_GRX_C_P8 C25 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P8
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P9 C26 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P9
F16 H28 1 2
should be shorted near balls C16
eDP_TX[1] PEG_TX[9]
G28 PCIE_CTX_GRX_C_P10 C27 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P10
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P11 C28 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P11
C and routed with typical G15 eDP_TX[3] PEG_TX[11] E28 1 2 C
F28 PCIE_CTX_GRX_C_P12 C29 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P12
impedance <25 mohms C18
PEG_TX[12]
D27 PCIE_CTX_GRX_C_P13 C30 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P13
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_C_P14 C31 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P14
E16 eDP_TX#[1] PEG_TX[14] E26 1 2
D16 D25 PCIE_CTX_GRX_C_P15 C32 1 2 DIS@ 0.1U_0402_10V7K PCIE_CTX_GRX_P15
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
Nvidia support PCIE Gen2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR(1/7)
Size Document Number
DMI,FDI,PEGRev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
JCPU1B
A A
A28 CLK_CPU_DMI_R R4 1 @ 2 0_0402_5%

BCLK CLK_CPU_DMI (14)
C26 A27 CLK_CPU_DMI#_R R7 1 @ 2 0_0402_5%
MISC
CLOCKS
(18) H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# (14)
R8 1 @ 2 10K_0402_5% AN34 SKTOCC# R9

DPLL_REF_CLK A16 1 2 1K_0402_5%
A15 R10 1 2 1K_0402_5% +1.05VS
DPLL_REF_CLK#
H_CATERR# AL33 CATERR#
+1.05VS
THERMAL
H_PECI AN33 R8
(18,41) H_PECI PECI SM_DRAMRST# H_DRAMRST# (6)
Processor Pullups
DDR3
MISC
R5 1 2 62_0402_5% H_PROCHOT# H_PROCHOT# R12 1 2 56_0402_5% H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R13 1 2 140_0402_1%
(41) H_PROCHOT# PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP1 R14 1 2 25.5_.402_1%
SM_RCOMP[1] SM_RCOMP2 R15
SM_RCOMP[2] A4 1 2 200_0402_1%
DDR3 Compensation Signals
H_THRMTRIP# AN32
(18) H_THRMTRIP# THERMTRIP#
P+ AP29 XDP_PRDY# PU/PD for JTAG signals

PRDY# XDP_PREQ#
P+ PREQ# AP27
+1.05VS
P+ AR26 XDP_TCK R21 1 2 51_0402_5%
TCK XDP_TMS R17
P+ AR27 1 2 51_0402_5%
PWR MANAGEMENT
TMS
JTAG & BPM

H_PM_SYNC AM34 P+ AP30 XDP_TRST# R22 1 2 51_0402_5%
(15) H_PM_SYNC PM_SYNC TRST#
B B
P+ AR28 XDP_TDI R18 1 2 51_0402_5%
TDI XDP_TDO R19
TDO AP26 1 2 51_0402_5%
R23 1 @ 2 0_0402_5% H_CPUPWRGD_R AP33
(18) H_CPUPWRGD UNCOREPWRGOOD +3VS
R6 1 2 10K_0402_5%
C33 @1 2 220P_0402_50V7K R24 1 2 1K_0402_5%
AL35 XDP_DBRESET#
DBR# XDP_DBRESET# (15)
PM_SYS_PWRGD_BUF R25 1 2 130_0402_5% PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
AT28 XDP_BPM#0
BPM#[0] XDP_BPM#1
BPM#[1] AR29
AR30 XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3
AR33 RESET# BPM#[3] AT30
P+ AP32 XDP_BPM#4
BPM#[4] XDP_BPM#5
BPM#[5] AR31
AT31 XDP_BPM#6
BPM#[6] XDP_BPM#7
BPM#[7] AR32
CONN@
C C
+3VS +3VALW +1.5V_CPU_VDDQ +3VS +1.05VS
1 Buffered reset to CPU 1

1
1
C34 @ C35
0.1U_0402_16V4Z R33 0.1U_0402_16V4Z R34
200_0402_5% 75_0402_5%
2 2
2
2
5
R35 @ U1 @ R36
5
10K_0402_5% 74AHC1G09GW_TSSOP5 1 43_0402_1%

P
NC
1 2 1 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
P
B PM_SYS_PWRGD_BUF Y
O 4 (17) PCH_PLTRST# 2 A
G
1
2 U2
(15) PM_DRAM_PWRGD A
G
SN74LVC1G07DCKR_SC70-5 R38
3
1
0_0402_5%
3
R37 @
39_0402_5% For 26 Pin XDP Conn.
2
@
1 2
R26 1 @ 2 1K_0402_1%
(18) H_CPUPWRGD
R27 1 @ 2 0_0402_5%
D (15,41) PBTN_OUT#
Q1 R28 1 @ 2 1K_0402_1%
(7) XDP_CFG0
2 2N7002K_SOT23-3 R29 1 @ 2 0_0402_5%
(9) RUN_ON_CPU1.5VS3# (15) SYS_PWROK
G @ R30 1 @ 2 0_0402_5%
(14) CLK_XDP_CLK
S R31 1 @ 2 0_0402_5%
(14) CLK_XDP_CLK#
PLT_RST# R32 1 @ 2 1K_0402_1%
(14,17,22,36,38,40,41) PLT_RST#
3
D D
PM_DRAM_PWRGD R214 1 2 0_0402_5% PM_SYS_PWRGD_BUF

Title
PM,XDP,CLKRev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
JCPU1C CONN@ JCPU1D CONN@
(11) DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 (11) (12) DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 (12)
A
SA_CLK#[0] AA6 M_CLK_DDR#0 (11) SB_CLK#[0] AD2 M_CLK_DDR#2 (12) A
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA (11) SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB (12)
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 (11) A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 (12)
DDR_A_D5 C6 AB5 DDR_B_D5 A8 AD1
SA_DQ[5] SA_CLK#[1] M_CLK_DDR#1 (11) SB_DQ[5] SB_CLK#[1] M_CLK_DDR#3 (12)
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA (11) SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB (12)
DDR_A_D7 C3 DDR_B_D7 D8
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# (11) K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# (12)
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# (11) SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# (12)
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 (11) N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 (12)
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4
DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] M_ODT1 (11) SB_DQ[30] SB_ODT[1] M_ODT3 (12)
DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
B
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33] B
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
AH5 SA_DQ[36] DDR_A_DQS#[0..7] (11) AN3 SB_DQ[36] DDR_B_DQS#[0..7] (12)
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN1 SB_DQ[38] SB_DQS#[1] F3
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D39 AP2 K6 DDR_B_DQS#2
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AT5 SB_DQ[42] SB_DQS#[5] AP9
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
AH8 SA_DQ[44] SA_DQS#[7] AM15 AP6 SB_DQ[44] SB_DQS#[7] AP15
DDR_A_D45 AH9 DDR_B_D45 AN8
AL9 SA_DQ[46] AR6 SB_DQ[46]
DDR_A_D47 AL8 DDR_B_D47 AR5
AP11 SA_DQ[48] DDR_A_DQS[0..7] (11) AR9 SB_DQ[48] DDR_B_DQS[0..7] (12)
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
AL14 SA_DQ[60] DDR_A_MA[0..15] (11) AT12 SB_DQ[60] DDR_B_MA[0..15] (12)
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
C
(11) DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 (12) DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2 C
AF10 V1 DDR_A_MA8 AA7 T5 DDR_B_MA8
(11) DDR_A_BS1 SA_BS[1] SA_MA[8] (12) DDR_B_BS1 SB_BS[1] SB_MA[8]
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
(11) DDR_A_BS2 SA_BS[2] SA_MA[9] (12) DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
(11) DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 (12) DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
(11) DDR_A_RAS# SA_RAS# SA_MA[14] (12) DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
(11) DDR_A_WE# SA_WE# SA_MA[15] (12) DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
+1.5V
R39 1 @ 2 0_0402_5%
1
R40
1K_0402_5% R41
1K_0402_5%
S
3 1 DDR3_DRAMRST#_R 1 2
(5) H_DRAMRST# DDR3_DRAMRST# (11,12)
2
1
D D
Q2
BSS138_NL_SOT23-3
G
2
R42
4.99K_0402_1%
2
R43 1 @ 2 0_0402_5% DRAMRST_CNTRL

(14) DRAMRST_CNTRL_PCH DRAMRST_CNTRL (9)
1
C36
0.047U_0402_16V4Z
Title
2
DDRIII Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
CFG Straps for Processor

CFG2
1
A R45 A
1K_0402_1%
@
2
JCPU1E CONN@
PEG Static Lane Reversal - CFG2 is for the 16x
AH27 1: Normal Operation; Lane # definition matches

(5) XDP_CFG0 AK28
AK29
CFG[0]
CFG[1]
VCC_DIE_SENSE
VSS_DIE_SENSE AH26 R173 1
T2
@ 2 0_0402_5% CFG2 * socket pin map definition
CFG2 AL26 CFG[2]
AL27 CFG[3] 0:Lane Reversed
CFG4 AK26 L7
CFG5 CFG[4] RSVD28
AL29 CFG[5] RSVD29 AG7
CFG6 AL30 P+ AE7
CFG7 CFG[6] RSVD30
AM31 CFG[7] RSVD31 AK2
AM32 CFG4
CFG[8]
AM30 W8
CFG
+CPU_CORE +VCC_GFXCORE_AXG CFG[9] RSVD32
AM28 CFG[10]
1
AM26 CFG[11]
AN28 CFG[12] RSVD33 AT26
AN31 AM33 @ R50
CFG[13] RSVD34
1
AN26 AJ27 1K_0402_1%

R48 R46 CFG[14] RSVD35
AM27
2
49.9_0402_1% CFG[15]
49.9_0402_1% AK31 CFG[16]
AN29 CFG[17]
2
RSVD37 T8 Display Port Presence Strap

B RSVD38 J16 B
VCC_AXG_VAL_SENSE AJ31 H16
R176 @ VAXG_VAL_SENSE RSVD39
1 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 G16 1 : Disabled; No Physical Display Port
R179 1 @ 2 100_0402_1%
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ33
AH33
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
RSVD40
CFG4 * attached to Embedded Display Port
R47 1 2 49.9_0402_1% VSS_AXG_VAL_SENSE 0 : Enabled; An external Display Port device is
AJ26 RSVD5 RSVD_NCTF1 AR35 connected to the Embedded Display Port
R49 1 2 49.9_0402_1% VSS_VAL_SENSE AT34
RESERVED
RSVD_NCTF2
RSVD_NCTF3 AT33
RSVD_NCTF4 AP35
RSVD_NCTF5 AR34
CFG6
F25 CFG5
RSVD8
F24 RSVD9
1
F23 RSVD10
D24 B34 @ R51 @ R52
RSVD11 RSVD_NCTF6 1K_0402_1% 1K_0402_1%
G25 RSVD12 RSVD_NCTF7 A33
G24 RSVD13 RSVD_NCTF8 A34
E23 B35
2
RSVD14 RSVD_NCTF9
D23 RSVD15 RSVD_NCTF10 C35
C30 RSVD16
A31 RSVD17
B30 RSVD18
B29 RSVD19
D30 RSVD20 RSVD51 AJ32
B31 RSVD21 RSVD52 AK32
A30 RSVD22 PCIE Port Bifurcation Straps
C29 RSVD23
AN35 11: (Default) x16 - Device 1 functions 1 and 2 disabled
J20
B18
RSVD24
RSVD25
BCLK_ITP
BCLK_ITP# AM35
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2
C
disabled C
01: Reserved - (Device 1 function 1 disabled ; function
J15 RSVD27 RSVD_NCTF11 AT2 2 enabled)
RSVD_NCTF12 AT1
RSVD_NCTF13 AR1 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
KEY B1
CFG7
1
@ R53
TYCO_2013620-2_IVY BRIDGE 1K_0402_1%
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
0: PEG Wait for BIOS for training
D D

Title
RSVD,CFG Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+CPU_CORE +1.05VS
JCPU1F POWER CONN@
97A 8.5A
AG35 VCC1
AG34 VCC2 VCCIO1 AH13
A AG33 VCC3 VCCIO2 AH10 A
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF32 VCC14 VCCIO13 H14
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12
PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD32 VCC24 VCCIO23 E14
AD30 VCC26
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC30 VCC36 VCCIO34 B14
B
AC29 VCC37 VCCIO35 B12 B
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48 +1.05VS +1.05VS
AA27 VCC49
AA26 VCC50
Y35
CORE SUPPLY
VCC51
Y34 VCC52
Y33 VCC53
1
Y32 VCC54 1 1
Y31 C37 R54 R55 C38
VCC55 0.1U_0402_16V4Z 130_0402_5% 75_0402_5% 0.1U_0402_16V4Z
Y30 VCC56
Y29 VCC57 2 2
Y28 Place the PU
2
VCC58
Y27 VCC59
Y26 resistors close to VR
VCC60
V35 VCC61
V34 AJ29 H_CPU_SVIDALRT# R56 1 2 43_0402_1%
SVID
VCC62 VIDALERT# VR_SVID_ALRT# (52)
V33 AJ30 H_CPU_SVIDCLK R57 1 @ 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK (52)
V32 AJ28 H_CPU_SVIDDAT R58 1 @ 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT (52)
V31 VCC65
V30 VCC66
V29 VCC67
V28 VCC68
V27 VCC69
V26 VCC70
U35 VCC71
C U34 VCC72
C
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VSSSENSE_R R174 @1 2 100_0402_1% VCCSENSE_R
VCC78
U27 VCC79
U26 VCC80
R35 +CPU_CORE
VCC81
R34 VCC82
R33 VCC83
1
R32 VCC84
R31 Trace Impedance = 27 ~ 33 ohm R59 Place the PU
VCC85 100_0402_1%
R30 VCC86
R29 Trace Length Match < 25 mils resistors close to CPU
VCC87
R28
SENSE LINES
2
VCC88 VCCSENSE_R R60 @
R27 VCC89 VCC_SENSE AJ35 1 2 0_0402_5% VCCSENSE (52)
R26 AJ34 VSSSENSE_R R61 1 @ 2 0_0402_5%
VCC90 VSS_SENSE VSSSENSE (52)
P35 VCC91 +1.05VS
P34 VCC92
1
P33 R64 1 2 10_0402_1%
VCC93 VCCIO_SENSE R62
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE (50)
P31 A10 VSSIO_SENSE 100_0402_1%
VCC95 VSS_SENSE_VCCIO
P30 VCC96
P29
2
VCC97
1
P28 VCC98
P27 R63
VCC99 10_0402_1%
P26 VCC100
2
D D

Title
PWR,BYPASS Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
M3 Support R67 1 @ 2 0_0402_5%
Q3 +VREF_DQ_DIMMA
BSS138_NL_SOT23-3
+VCC_GFXCORE_AXG
D
+V_DDR_REFA_R 3 1
1
2
R79
G
2
R65 1K_0402_1%
10_0402_1% @ DRAMRST_CNTRL
2
1
A A
VCC_AXG_SENSE (52)
R73 1 @ 2 100_0402_1% R71 1 @ 2 0_0402_5%
+VCC_GFXCORE_AXG
JCPU1G
POWER CONN@
VSS_AXG_SENSE (52)
Q6
BSS138_NL_SOT23-3
+VREF_DQ_DIMMB
1
+V_SM_VREF should
33A
D
R66 have 10 mil trace width +V_DDR_REFB_R 3 1
AT24 AK35 10_0402_1%
SENSE
LINES
VAXG1 VAXG_SENSE
1
AT23 VAXG2 VSSAXG_SENSE AK34
+1.5V_CPU_VDDQ +1.5V R108
G
AT21
2
VAXG3 1K_0402_1%
AT20 VAXG4
AT18 @
VAXG5
1
AT17 DRAMRST_CNTRL (6)
2
VAXG6 R68 @ R69
AR24 VAXG7
AR23 1K_0402_5% R70 1 @ 2 0_0402_5% 100_0402_5%
VAXG8
AR21 VAXG9 from 1PCS 2N7002 dual channel change to BSS138 2pCS
AR20
2
VAXG10 +V_SM_VREF_CNT +V_SM_VREF
AR18 VAXG11 SM_VREF AL1 3 1
AR17 Q4
VAXG12
C39
0.1U_0402_16V4Z
AP24 AP2302GN-HF_SOT23-3
VREF
VAXG13
1
AP23 1 @
VAXG14 R72 @ R74 +1.5V_CPU_VDDQ +1.5V
AP21 VAXG15 +V_DDR_REFA_R 1K_0402_5% 2 RUN_ON_CPU1.5VS3 100_0402_5%
AP20 VAXG16 SA_DIMM_VREFDQ B4
AP18 D1 +V_DDR_REFB_R @
VAXG17 SB_DIMM_VREFDQ 2 C47
AP17 1 2 0.1U_0402_10V7K
2
VAXG18
AN24 VAXG19
AN23 VAXG20
AN21 C53 1 2 0.1U_0402_10V7K
VAXG21 +1.5V
AN20 VAXG22 +1.5V_CPU_VDDQ
AN18 10A
DDR3 -1.5V RAILS

VAXG23 @ JP1 C54
AN17 VAXG24 1 2 0.1U_0402_10V7K
AM24 AF7 1 2
GRAPHICS
VAXG25 VDDQ1
AM23 VAXG26 VDDQ2 AF4
C40
10U_0603_6.3V6M
C41
10U_0603_6.3V6M
C42
10U_0603_6.3V6M
C43
10U_0603_6.3V6M
C44
10U_0603_6.3V6M
C45
10U_0603_6.3V6M
C46
330U_D2_2V_Y
AM21 AF1 1 PAD-OPEN 4x4m C55 1 2 0.1U_0402_10V7K
VAXG27 VDDQ3
B
AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1 B
AM18 AC4 +
VAXG29 VDDQ5
AM17 VAXG30 VDDQ6 AC1
AL24 VAXG31 VDDQ7 Y7
2 2 2 2 2 2 2
AL20 VAXG34 VDDQ10 U7
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
AK21 P1 +VCCSA
VAXG39 VDDQ15
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
C48
10U_0603_6.3V6M
C49
10U_0603_6.3V6M
C50
10U_0603_6.3V6M
C51
10U_0603_6.3V6M
C52
330U_D2_2V_Y
AJ23 VAXG44 1
AJ21 VAXG45 1 1 1 1
AJ20 +
AJ18
VAXG46 6A
VAXG47 @ @
AJ17 VAXG48 VCCSA1 M27
2 2 2 2 2
SA RAIL
AH24 VAXG49 VCCSA2 M26

AH23 VAXG50 VCCSA3 L26
AH21 VAXG51 VCCSA4 J26
AH17 VAXG54 VCCSA7 H26
VCCSA8 H25
+1.5V_CPU_VDDQ Source
1.8V RAIL
+1.8VS_VCCPLL
VCCSA_SENSE H23 +VCCSA_SENSE (49)
+1.8VS
C
1.5A R75 1 @ 2 0_0402_5% C
R76 1 2 0_0805_5% B6 VCCPLL1 +3VALW +VSB +1.5V +1.5V_CPU_VDDQ
A6 C22
MISC
VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 (49)

C56
C57
C58
C59
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
330U_D2_2V_Y
1 A2 C24 @ J2
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 (49)
1 1 1 1 2
+ +3VS
PAD-OPEN 4x4m
@ A19 H_VCCP_SEL R77 1 @ 2 0_0402_5% R78 1 2 10K_0402_5% Q5
2 2 2 2 VCCIO_SEL AP4800BGM-HF_SO-8
IVY Bridge drives VCCIO_SEL low
1
TYCO_2013620-2_IVY BRIDGE 8 1
R82
VCCP_PWRCTRL:0 R80
100K_0402_5%
R81
82K_0402_1%
7 2
6 3
1
@ 5 1
C60
2
Sandy Bridge is NC for A19 0.1U_0402_10V6K
4
@
VCCP_PWRCTRL:1 R201 2
2 220_0402_5%
RUN_ON_CPU1.5VS3 1 2
1
Q11 15K_0402_5%
1
D R85 1
(24,42,50,51) SUSP R83 1 @ 2 0_0402_5% 2
G @ C61
1
S
1
2
0.047U_0603_25V7K
R84 1 @ 2 0_0402_5% D
(41) CPU1.5V_S3_GATE
2
2N7002K_SOT23-3
330K_0402_5%
Q12 D 2 RUN_ON_CPU1.5VS3#
2 G
G S Q7
2N7002K_SOT23-3
(24,41,42,46,48,50,51) SUSP# R86 1 @ 2 @ S 2N7002K_SOT23-3
3
3
0_0402_5%
D D
RUN_ON_CPU1.5VS3#
Vaxg (5) RUN_ON_CPU1.5VS3#
‧ Can connect to GND if motherboard only

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
‧ VAXG can be left floating in a common Security Classification Compal Secret Data
Title
motherboard design (Gfx VR keeps VAXG from Issued Date 2011/07/12 Deciphered Date 2012/07/01
floating) if the VR is stuffed THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR(6/7)
PWR Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
A A
JCPU1H CONN@ JCPU1I CONN@
AT35 VSS1 VSS81 AJ22

AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
B
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28 B
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216
AL13 VSS64 VSS145 W35 H1 VSS222
C AL10 VSS65 VSS146 W34 G35 VSS223
C
AL7 VSS66 VSS147 W33 G32 VSS224
AK33 VSS69 VSS150 W30 G23 VSS227
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE
D D

Title
VSS Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
DDR_A_DQS#[0..7] (6)
DDR_A_DQS[0..7] (6)
+1.5V
DDR_A_D[0..63] (6)
DDR_A_MA[0..15] (6)
1
R2001
1K_0402_1%
+1.5V +1.5V
2
A JDIMM1 A
+VREF_DQ_DIMMA +VREF_DQ_DIMMA 1 2 Layout Note:
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4 Place near
C2001
2.2U_0603_6.3V6K
C2002
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
1
1 1 DDR_A_D1 7 8 JDIMM1
R2003 DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10
1K_0402_1% 11 12 DDR_A_DQS0
DM0 DQS0 +1.5V
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6
15 16
2
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
C2003
0.1U_0402_10V6K
C2004
0.1U_0402_10V6K
C2005
0.1U_0402_10V6K
C2006
0.1U_0402_10V6K
23 DQ9 DQ13 24 1 1 1 1
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# (6,12) 2 2 2 2
31 VSS11 VSS12 32
All VREF traces should DDR_A_D10 33 34 DDR_A_D14
35 36
have 10 mil trace width 37
DQ11 DQ15
38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 DQ16 DQ20 40
DQ17 DQ21
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 +1.5V
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
C2007
10U_0603_6.3V6M
C2008
10U_0603_6.3V6M
C2009
10U_0603_6.3V6M
C2010
10U_0603_6.3V6M
C2011
10U_0603_6.3V6M
C2012
10U_0603_6.3V6M
C2013
10U_0603_6.3V6M
C2014
330U_D2_2V_Y
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56 1 1 1 1 1 1 1 1
DDR_A_D25 DQ24 DQ29 +
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3 @
VSS22 DQS#3 DDR_A_DQS3 2 2 2 2 2 2 2 @
63 DM3 DQS3 64
2
65 VSS23 VSS24 66
B
DDR_A_D27 DQ26 DQ30 DDR_A_D31 B
69 DQ27 DQ31 70
71 VSS25 VSS26 72
(6) DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA (6)

CKE0 CKE1
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
(6) DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
(6) M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1 M_CLK_DDR1 (6)
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 +0.75VS
(6) M_CLK_DDR#0 103 CK0# CK1# 104 M_CLK_DDR#1 (6) +1.5V
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 (6)
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
(6) DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# (6)
C2017
C2018
C2019
C2020
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
111 VDD13 VDD14 112
1
(6) DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# (6) 1 1 1 1 Layout Note:
DDR_A_CAS# WE# S0# M_ODT0 R2004
(6) DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 (6) Place near
117 118 1K_0402_1%
DDR_A_MA13 VDD15 VDD16 M_ODT1 JDIMM1.203,204
119 A13 ODT1 120 M_ODT1 (6)
DDR_CS1_DIMMA# 2 2 2 2
(6) DDR_CS1_DIMMA# 121 122
2
S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CA
NCTEST VREF_CA
127 VSS27 VSS28 128
C2015
C2016
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
DDR_A_D32 129 130 DDR_A_D36
C 131 DQ33 DQ37 132 1 1 C
1
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 R2005
DDR_A_DQS4 DQS#4 DM4 1K_0402_1%
137 DQS4 VSS31 138
DDR_A_D38 2 2
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39
2
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_A_D44
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
193 DQ59 DQ63 194
195 VSS51 VSS52 196
197 SA0 EVENT# 198
+3VS 199 200 SMB_DATA_S3
D VDDSPD SDA SMB_DATA_S3 (12,14,38,39) D
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 (12,14,38,39)
+0.75VS 203 VTT1 VTT2 204 +0.75VS
C2021
C2046
C2022
R2006
R2007
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
10K_0402_5%
10K_0402_5%
205 G1 G2 206
1
<Address: 00> 1 1 1
TYCO_2-2013310-1
CONN@
DIMM_A Reserve H:4.0mm 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2
Title
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRIII
DIMMA Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+1.5V DDR_B_DQS#[0..7] (6)
DDR_B_DQS[0..7] (6)
1
DDR_B_D[0..63] (6)
R2008
1K_0402_1%
DDR_B_MA[0..15] (6)
2
+1.5V +1.5V
JDIMM2
A +VREF_DQ_DIMMB +VREF_DQ_DIMMB 1 2 A
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4
C2024
2.2U_0603_6.3V6K
C2023
0.1U_0402_16V4Z
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
1 1 7 DQ1 VSS3 8
1
9 10 DDR_B_DQS#0 Layout Note:
R2010 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12 Place near
1K_0402_1% 13 14
2 2 DDR_B_D2 VSS5 VSS6 DDR_B_D6 JDIMM2
15 DQ2 DQ6 16
2
DQ3 DQ7 +1.5V
19 VSS7 VSS8 20
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
C2025
0.1U_0402_10V6K
C2026
0.1U_0402_10V6K
C2027
0.1U_0402_10V6K
C2028
0.1U_0402_10V6K
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# (6,11) 1 1 1 1
31 VSS11 VSS12 32
35 DQ11 DQ15 36
2 2 2 2
37 VSS13 VSS14 38
All VREF traces should DDR_B_D16 39 40 DDR_B_D20
41 42
have 10 mil trace width 43
DQ17 DQ21
44
DDR_B_DQS#2 VSS15 VSS16
45 DQS#2 DM2 46
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 VSS18 DQ22 50
DDR_B_D18 51 52 DDR_B_D23 +1.5V
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 DQ24 DQ29 58
C2029
10U_0603_6.3V6M
C2030
10U_0603_6.3V6M
C2031
10U_0603_6.3V6M
C2032
10U_0603_6.3V6M
C2033
10U_0603_6.3V6M
C2034
10U_0603_6.3V6M
C2035
10U_0603_6.3V6M
C2036
330U_D2_2V_Y
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62 1 1 1 1 1 1 1 1
63 64 DDR_B_DQS3
DM3 DQS3 +
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30 @
DDR_B_D27 DQ26 DQ30 DDR_B_D31 2 2 2 2 2 2 2 @
69 DQ27 DQ31 70
B 2 B
71 VSS25 VSS26 72
(6) DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB (6)

CKE0 CKE1
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
(6) DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94 Layout Note:
DDR_B_MA1 97
A3 A2
98 DDR_B_MA0 Place near
A1 A0 JDIMM2.203,204
99 VDD9 VDD10 100
(6) M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3 M_CLK_DDR3 (6)
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
(6) M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 (6) +1.5V
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 (6)
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
(6) DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# (6)
1
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_CS2_DIMMB# R2011 +0.75VS
(6) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (6)
(6) DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 (6) 1K_0402_1%
CAS# ODT0
117 VDD15 VDD16 118
DDR_B_MA13 119 120 M_ODT3 M_ODT3 (6)
2
A13 ODT1
C2039
C2040
C2041
C2042
C2045
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
(6) DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 VDD17 VDD18 124 1 1 1 1 1
125 126 +VREF_CB @
NCTEST VREF_CA
127 VSS27 VSS28 128
C2037
C2038
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37 2 2 2 2 2
131 DQ33 DQ37 132 1 1
1
C 133 VSS29 VSS30 134 C
DDR_B_DQS#4 135 136 R2012
DDR_B_DQS4 DQS#4 DM4 1K_0402_1%
137 DQS4 VSS31 138
DDR_B_D38 2 2
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39
2
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_B_D44
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
153 154 DDR_B_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
+3VS +3VS 173 174 DDR_B_D54
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
C2043
C2044
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
DDR_B_D56 181 182 DDR_B_D61

DQ56 DQ61
1
1 1 DDR_B_D57 183 184

R2013 DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
10K_0402_5% 187 188 DDR_B_DQS7
DM7 DQS7
189 VSS49 VSS50 190
2 2 DDR_B_D58 DDR_B_D62
191 192
2

193 DQ59 DQ63 194
195 VSS51 VSS52 196
197 SA0 EVENT# 198
199 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 (11,14,38,39)
201 202 SMB_CLK_S3
D SA1 SCL SMB_CLK_S3 (11,14,38,39) D
+0.75VS 203 VTT1 VTT2 204 +0.75VS
1
205 G1 G2 206
R2014
10K_0402_5% FOX_AS0A626-U2SN-7F
CONN@
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRIII
DIMMB Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
PCH_RTCX1
W=20mils W=20mils
R87 1 2 10M_0402_5% PCH_RTCX2
+RTCVCC +RTCBATT
Y1
R106
1 2 1K_0402_5%
1 2
18P_0402_50V8J
32.768KHZ_12.5PF_CM31532768DZFT
1
1 1 1
C64 C179 CLRP1
C63 11/14 18P_0402_50V8J 1U_0402_6.3V6K SHORT PADS
2
2 2 2
CMOS
A A
SHORT PADS
JCMOS1
1 U3A
1
C62
+RTCVCC 1U_0402_6.3V6K PCH_RTCX1 A20 P+ C38 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 (38,40,41)
@ P+ A38 LPC_AD1
LPC_AD1 (38,40,41)
2
2 FWH1 / LAD1
LPC
PCH_RTCX2 C20 P+ B37 LPC_AD2
+RTCVCC RTCX2 FWH2 / LAD2 LPC_AD2 (38,40,41)
P+ C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 (38,40,41)
R88 1 2 20K_0402_5% PCH_RTCRST# D20
R90 SM_INTRUDER# RTCRST# LPC_FRAME#
1 2 1M_0402_5% FWH4 / LFRAME# D36 LPC_FRAME# (38,40,41)
R89 1 2 20K_0402_5% PCH_SRTCRST# G22
R91 SRTCRST# +3VS
1 2 330K_0402_5% PCH_INTVRMEN P+ LDRQ0# E36
RTC
1 SM_INTRUDER# K22 P+ K36
INTRUDER# LDRQ1# / GPIO23
1
SHORT PADS
JME1
C66 R92 2 10K_0402_5%
INTVRMEN 1U_0402_6.3V6K PCH_INTVRMEN C17 V5 SERIRQ
1
INTVRMEN SERIRQ SERIRQ (40,41)
：Integrated VRM enable
H： @
*
2
2
：Integrated VRM disable
L：
AM3 SATA_DTX_C_PRX_N0
SATA0RXN SATA_DTX_C_PRX_N0 (36)
(INTVRMEN should always be pull high.) HDA_BIT_CLK N34 AM1 SATA_DTX_C_PRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_PRX_P0 (36)
AP7 SATA_PTX_C_DRX_N0 C67 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0 HDD
SATA 6G
SATA0TXN SATA_PTX_DRX_N0 (36)
HDA_SYNC L34 P- AP5 SATA_PTX_C_DRX_P0 C68 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 (36)
ME HDA_SPKR T10 P- AM10 SATA_DTX_C_PRX_N1

+3VS (35) HDA_SPKR SPKR SATA1RXN SATA_DTX_C_PRX_N1 (36)
AM8 SATA_DTX_C_PRX_P1
SATA1RXP SATA_DTX_C_PRX_P1 (36)
HDA_RST# K34 AP11 SATA_PTX_C_DRX_N1 C69 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N1 ODD
HDA_RST# SATA1TXN SATA_PTX_DRX_N1 (36)
R93 1 @ 2 1K_0402_5% HDA_SPKR AP10 SATA_PTX_C_DRX_P1 C70 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 (36)
HIGH= Enable ( No Reboot ) (35) HDA_SDIN0 HDA_SDIN0 E34 P- AD7 SATA_DTX_C_PRX_N2
HDA_SDIN0 SATA2RXN SATA_DTX_C_PRX_N2 (38)
LOW= Disable (Default) AD5 SATA_DTX_C_PRX_P2
* G34 HDA_SDIN1 P- SATA2RXP
SATA2TXN AH5 SATA_PTX_C_DRX_N2 C71 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N2
SATA_DTX_C_PRX_P2 (38)
SATA_PTX_DRX_N2 (38) m-SATA
AH4 SATA_PTX_C_DRX_P2 C72 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P2
SATA2TXP SATA_PTX_DRX_P2 (38)
C34 HDA_SDIN2 P-
IHDA
SATA3RXN AB8
B
A34 HDA_SDIN3 P- SATA3RXP AB10 B
SATA3TXN AF3
+3V_PCH AF1
+3VS R94 @ SATA3TXP
(41) ME_FLASH 1 2 0_0402_5% HDA_SDOUT A36 HDA_SDO P-
R95 @ 2 1K_0402_5% HDA_SDOUT
SATA
1 SATA4RXN Y7
SATA4RXP Y5
R202 1 2 10K_0402_5% WLBT_OFF_5# (38) WLBT_OFF_5#
WLBT_OFF_5# C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
SATA4TXP AD1
9/27 +3V_PCH R209 1 @ 2 10K_0402_5% PCH_GPIO13 N32 HDA_DOCK_RST# / GPIO13
HDA_SDO SATA5RXN Y3
Y1
SATA5RXP
ME debug mode,this signal has a weak internal PD SATA5TXN AB3
Low = Disabled (Default) R96 1 2 51_0402_5% PCH_JTAG_TCK J3 P- AB1
* High = Enabled [Flash Descriptor Security Overide]
JTAG_TCK SATA5TXP +1.05VS_PCH
PCH_JTAG_TMS H7 P+ Y11
JTAG_TMS SATAICOMPO
JTAG
PCH_JTAG_TDI K5 P+ Y10 SATA_COMP R97 1 2 37.4_0402_1% +1.05VS_VCC_SATA
JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1 JTAG_TDO
SATA3RCOMPO AB12
+3V_PCH +1.05VS_SATA3
AB13 SATA3_COMP R98 1 2 49.9_0402_1%
R99 SATA3COMPI
1 2 1K_0402_5% HDA_SYNC
This signal has a weak internal pull-down SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 R100 1 2 750_0402_1%
SPI_CLK SATA3RBIAS
SPI_SB_CS0# Y14
On Die PLL VR Select is supplied by SPI_CS0# +3VS
1.5V when sampled high SPI_SB_CS1# T1
* SPI_CS1#
SPI
P3 PCH_SATALED# R101 1 2 10K_0402_5%
1.8V when sampled low SATALED#
Prevent back drive issue.
Needs to be pulled High for Huron River platfrom SPI_SI V4 P- V14 PCH_GPIO21 R102 1 2 10K_0402_5%
SPI_MOSI SATA0GP / GPIO21
SPI_SO_R U3 P+ P+ P1 ODD_DET# R103 1 2 10K_0402_5%
SPI_MISO SATA1GP / GPIO19
ODD_DET# (36)
C C
PANTHER-POINT_FCBGA989
R107
33_0402_5%
1 2 HDA_BIT_CLK +5VS
(35) HDA_BITCLK_AUDIO
8MB+4MB SPI ROM FOR 5M ME(SBA)

2
G
R241
9/22
& Non-share ROM.
33_0402_5% +3VS_SPI +3VS +3VM
HDA_SYNC_R HDA_SYNC @
(35) HDA_SYNC_AUDIO 1 2 3 1
R110 1 2 0_0402_5%
if not supply SBA function R110 mount , R112 @
S
Q8 if supply SBA function R110 @,R112 mount

1
R109 BSS138_NL_SOT23-3 R112 1 SBA@ 2 0_0402_5%

33_0402_5%
HDA_RST# R303
(35) HDA_RST#_AUDIO 1 2
1M_0402_5% U6
U6 4M +3VS_SPI
SPI_SB_CS1# R336 1 2 0_0402_5% CS1# 1 8
2
R111 SPI_SO_R R343 1 CS# VCC

2 33_0402_5% SPI_SO1 2 DO(IO1) HOLD#(IO3) 7 SPI_HOLD#1
33_0402_5% SPI_WP#1 3 6 SPI_CLK1 R339 1 2 33_0402_5% SPI_CLK_PCH_R SPI_WP#1 R104 1 2 3.3K_0402_5%
HDA_SDOUT WP#(IO2) CLK SPI_SI1 R338 1
(35) HDA_SDOUT_AUDIO 1 2 4 GND DI(IO0) 5 2 33_0402_5% SPI_SI
SPI_HOLD#1 R105 1 2 3.3K_0402_5%
W25Q16BVSSIG_SO8
SPI_WP# R334 1 2 3.3K_0402_5%
+3VS_SPI
C76 1 2 22P_0402_50V8J HDA_BITCLK_AUDIO SPI_HOLD# R335 1 2 3.3K_0402_5%
C191 1 2 0.1U_0402_16V4Z
C77 @1 2 22P_0402_50V8J HDA_SDOUT_AUDIO SPI_CLK_PCH_R R119 @ 2 33_0402_5% C78 @1 2 22P_0402_50V8J
U5
U5 8M 1
SPI_SB_CS0# R340 1 2 0_0402_5% CS# 1 8 Reserve for EMI please close to U3

SPI_SO_R R337 1 CS# VCC
2 33_0402_5% SPI_SO_L 2 DO HOLD# 7 SPI_HOLD# R342 33_0402_5%
SPI_WP# 3 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R
WP# CLK SPI_SI_R SPI_SI SPI_CLK_PCH_R C84
4 GND DI 5 1 2 1 2 22P_0402_50V8J
R341 33_0402_5%
+3V_PCH +3V_PCH +3V_PCH W25Q32BVSSIG_SO8 C85 1 2 22P_0402_50V8J
D 9/28 RF modify D
1
EON Reserve for RF please close to U5, U6

R120 @ R121 @ R122 @
200_0402_5% 200_0402_5% 200_0402_5% 8M:SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P
4M:SA00004LI00 S IC FL 32M EN25Q32B-104HIP SOP 8P
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
R123 @
100_0402_1%
R124 @
100_0402_1%
R125 @
100_0402_1%
Title
PCH (1/9) SATA,HDA,SPI, LPC
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+3V_PCH
PCH_SMBCLK R128 1 2 2.2K_0402_5%
PCH_SMBDATA R129 1 2 2.2K_0402_5%
U3B PCH_SML0CLK R130 1 2 2.2K_0402_5%
PCIE_PRX_DTX_N1 BG34 PCH_SML0DATA R131 1 2 2.2K_0402_5%

(36) PCIE_PRX_DTX_N1 PERN1
PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11
(36) PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11
Card Reader C86 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 AV32 PCH_SML1CLK R126 1 2 2.2K_0402_5%
(36) PCIE_PTX_C_DRX_N1 PETN1
C79 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
(36) PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SML1DATA R132 1 2 2.2K_0402_5%
PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA
(38) PCIE_PRX_DTX_N2 PERN2 SMBDATA
PCIE_PRX_DTX_P2 BF34 PCH_HOT# R133 1 2 10K_0402_5%
(38) PCIE_PRX_DTX_P2 PERP2
Wireless LAN C82 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BB32
(38) PCIE_PTX_C_DRX_N2 PETN2
A C83 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 PCH_GPIO11 R135 1 2 10K_0402_5% A
(38) PCIE_PTX_C_DRX_P2 PETP2
SMBUS
A12 DRAMRST_CNTRL_PCH
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH (6)
BG36 DRAMRST_CNTRL_PCH R127 1 2 1K_0402_5%
PERN3 PCH_SML0CLK
BJ36 PERP3 SML0CLK C8
AV34 PCH_GPIO47 R138 1 2 10K_0402_5%
PETN3 PCH_SML0DATA
AU34 PETP3 SML0DATA G12
PCIE_PRX_DTX_N4 BF36
(40) PCIE_PRX_DTX_N4 PERN4
PCIE_PRX_DTX_P4 BE36
(40) PCIE_PRX_DTX_P4 PERP4
PCIE LAN C80 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
(40) PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 +3VS
C81 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BB34
(40) PCIE_PTX_C_DRX_P4 PETP4
E14 PCH_SML1CLK
SML1CLK / GPIO58
PCI-E*
BG37 PERN5
BH37 M16 PCH_SML1DATA R136 2.2K_0402_5%
PERP5 SML1DATA / GPIO75
2
AY36 PETN5 1 2 +3VS
BB36 PETP5 PCH_SMBDATA 6 1 SMB_DATA_S3
SMB_DATA_S3 (11,12,38,39)
BJ38 PERN6
BG38 Q9A 2N7002KDWH_SOT363-6
PERP6
P+/P-
Controller
AU36 PETN6 CL_CLK1 M7
R137 2.2K_0402_5%
DDR, WALN, WWAN
AV36 PETP6
5
1 2 +3VS
Link
BG40 PERN7 P+/P- CL_DATA1 T11
BJ40 PCH_SMBCLK 3 4 SMB_CLK_S3 SMB_CLK_S3 (11,12,38,39)
PERP7
AY40 PETN7
BB40 P10 Q9B 2N7002KDWH_SOT363-6
PETP7 CL_RST1#
BE38 PERN8
BC38 PERP8
AW38 PETN8
AY38 +3VS
PETP8 DIS@
M10 PCH_GPIO47 R139 1 @ 2 0_0402_5% Pull up at EC side.
PEG_A_CLKRQ# / GPIO47 GPU_CLKREQA (22)
R147 1 @ 2 0_0402_5% CLK_CARD# Y40 R140 1 @ 2 10K_0402_5%
(36) CLK_PCIE_CARD# CLKOUT_PCIE0N
2
Card Reader R149 1 @ 2 0_0402_5% CLK_CARD Y39
B (36) CLK_PCIE_CARD CLKOUT_PCIE0P DIS@ B
AB37 R144 1 @ 2 0_0402_5%
CLKOUT_PEG_A_N DIS@ CLK_PCIE_VGA# (22)
CARD_CLKREQ# R151 1 @ 2 0_0402_5% PCH_SML1DATA EC_SMB_DA2
CLOCKS
(36) CARD_CLKREQ# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA (22) 6 1 EC_SMB_DA2 (22,39,41)
Q10A 2N7002KDWH_SOT363-6
R141 1 @ 2 0_0402_5% CLK_MINI1# AB49 AV22 CLK_CPU_DMI# EC, VGA, Theraml
(38) CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# (5)
5
R142 1 @ 2 0_0402_5% CLK_MINI1 AB47 AU22 CLK_CPU_DMI
(38) CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI (5)
Wireless LAN
(38) WLAN_CLKREQ1# WLAN_CLKREQ1# M1 PCH_SML1CLK 3 4EC_SMB_CK2 EC_SMB_CK2 (22,39,41)
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
AM13 Q10B 2N7002KDWH_SOT363-6
CLKOUT_DP_P
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 CLK_BUF_CPU_DMI# R148 1 2 10K_0402_5%
PCH_GPIO20 CLKIN_DMI_N CLK_BUF_CPU_DMI R150 10K_0402_5%
V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 1 2
R145 1 @ 2 0_0402_5% CLK_LAN# Y37 BJ30 CLKIN_DMI2# R152 1 2 10K_0402_5%

(40) CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_GND1_N
PCIE LAN R146 1 @ 2 0_0402_5% CLK_LAN Y36 BG30 CLKIN_DMI2 R153 1 2 10K_0402_5%
(40) CLK_PCIE_LAN CLKOUT_PCIE3P CLKIN_GND1_P R168 33_0402_5% C89 22P_0402_50V8J
(40) LAN_CLKREQ# LAN_CLKREQ# A8 CLK_BUF_ICH_14M 1 @ 2 @ 1 2
PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M# R154 10K_0402_5%
CLKIN_DOT_96N G24 1 2
E24 CLK_BUF_DREF_96M R155 1 2 10K_0402_5%
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
+3VS Y45 R169 33_0402_5% C90 22P_0402_50V8J
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R156 10K_0402_5% CLK_PCI_LPBACK @ @ 1
CLKIN_SATA_N AK7 1 2 1 2 2
R170 1 2 10K_0402_5% WLAN_CLKREQ1# PCH_GPIO26 L12 AK5 CLK_BUF_PCIE_SATA R157 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
R162 1 2 10K_0402_5% PCH_GPIO20 Reserve for EMI please close to U60
V45 K45 CLK_BUF_ICH_14M R158 1 2 10K_0402_5%
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
+3V_PCH PCH_GPIO44 L14 P+ H45 CLK_PCI_LPBACK XTAL25_IN
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK (17)
R177 1 2 10K_0402_5% CARD_CLKREQ# XTAL25_OUT R161 1 2 1M_0402_5%
C AB42 V47 XTAL25_IN C
R175 1 LAN_CLKREQ# CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT Y2
2 10K_0402_5% AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
+1.05VS_PCH 25MHZ_20PF_ X3G025000DK1H
R181 1 2 10K_0402_5% PCH_GPIO26 PCH_GPIO56 E6 PEG_B_CLKRQ# / GPIO56 +1.05VS_VCCDIFFCLKN 1 1 3 3
R182 1 2 10K_0402_5% PCH_GPIO44 Y47 XCLK_RCOMP R160 1 2 90.9_0402_1%
XCLK_RCOMP GND GND
V40 CLKOUT_PCIE6N 1 1
R159 1 2 10K_0402_5% PCH_GPIO56 V42 CLKOUT_PCIE6P C87 2 4 C88
R183 1 2 10K_0402_5% PCH_GPIO45 PCH_GPIO45 T13 18P_0402_50V8J 18P_0402_50V8J
PCIECLKRQ6# / GPIO45 2 2
11/14
R184 1 @ 2 10K_0402_5% ON_ODD_DET V38 P- K43 PCH_GPIO64
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
V37 CLKOUT_PCIE7P
P- F47 PCH_GPIO65
ON_ODD_DET CLKOUTFLEX1 / GPIO65
(36) ON_ODD_DET K12 PCIECLKRQ7# / GPIO46 P+
P- H47 LAN_25M R163 1 @ 2 22_0402_5%
CLKOUTFLEX2 / GPIO66 PCH_LAN_25M (40)
R164 1 @ 2 0_0402_5% CLK_BCLK_ITP# AK14
(5) CLK_XDP_CLK# CLKOUT_ITPXDP_N +3VS
R165 1 @ 2 0_0402_5% CLK_BCLK_ITP AK13 P- K49 PCH_GPIO67
(5) CLK_XDP_CLK CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 (18)
+3VS
1
R172
10K_0402_5%
@
U8
2
1 NC VCC 8
2 NC WP 7 ROM_WP 1
PLT_RST# 3 6 SMB_CLK_S3 C91
(5,17,22,36,38,40,41) PLT_RST# PROT# SCL
4 5 SMB_DATA_S3 0.1U_0402_16V4Z
GND SDA
PCA24S08D_SO8 2
EEPROM SA00004MK00
EEPROM SA00004ML00
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PCH (2/8)
PCIE, SMBUS, CLK Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
U3C
(4) DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 (4)

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
(4) DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 (4)
A (4) DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 (4) A
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
(4) DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 (4)
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 (4)
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
(4) DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 (4)
(4) DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 (4)
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
(4) DMI_CTX_PRX_P2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 (4)
(4) DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 (4)
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 (4)
(4) DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 (4)
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 (4)
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 (4)
DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 (4)
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
(4) DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 (4)
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 (4)
(4) DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
(4) DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18
(4) DMI_CRX_PTX_P3 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT (4)
+1.05VS_PCH
BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 (4)
+1.05VS_VCC_EXP
R186 1 2 49.9_0402_1% DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 (4)
R188 1 2 750_0402_1% RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 (4)
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 (4)
within 500mil of the PCH
+RTCVCC
A18 DSWODVREN
DSWVRMEN
DSWODVREN R185 1 2 330K_0402_5%
System Power Management

T8 SUSACK#_R C12 P+ E22 PCH_DPWROK_R R189 1 @ 2 0_0402_5% PCH_RSMRST#_R
SUSACK# DPWROK R187 @
1 2 330K_0402_5%
B B
R193 1 @ 2 0_0402_5% XDP_DBRESET#_R K3 B9 WAKE# R194 1 @ 2 0_0402_5% PCIE_WAKE# (40) DSWODVREN - On Die DSW VR Enable
(5) XDP_DBRESET# SYS_RESET# WAKE#
H：Enable
* L：Disable
SYS_PWROK P12 N3 PM_CLKRUN#
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# (40)
(41) PCH_PWROK PCH_PWROK R197 1 2 0_0402_5% PCH_POK_R L22 G8

R198 1 @ PWROK SUS_STAT# / GPIO61
2 0_0402_5%
R200 1 2 0_0402_5% APWROK L10 N14 SUSCLK +3V_PCH

(41) PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK (41)
T11 WAKE# R192 1 2 10K_0402_5%

PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
(5) PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# (41)
PCH_GPIO29 R195 1 @ 2 10K_0402_5%
T12 +3VS
R203 1 @ 2 0_0402_5% PCH_RSMRST#_R C21 H4 PM_SLP_S4#
(41) EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# (41)
T13 PM_CLKRUN# R196 1 2 8.2K_0402_5%

SUSWARN# K16 F4 PM_SLP_S3#
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# (41)
R199 1 @ 2 10K_0402_5%
E20 P+ G10 PCH_SLPA#

(5,41) PBTN_OUT# PWRBTN# SLP_A# PCH_SLPA# (41)
EC team suggestion
T14 South Bridge side must have
D3 1 2 AC_PRESENT_R H20 P- G16 PM_SLP_SUS# pull-low 10K on this pin(GPIO32)
(40,41,44) ACIN ACPRESENT / GPIO31 SLP_SUS# PM_SLP_SUS# (41)
RB751V-40_SOD323-2
Use CLKRUN# Requires a 8.2- k weak
T15 pull-up resistor to Vcc3_3S
PCH_GPIO72 H_PM_SYNC
E10 BATLOW# / GPIO72 P+ PMSYNCH AP14 H_PM_SYNC (5)
RI# A10 K14 PCH_GPIO29

RI# SLP_LAN# / GPIO29
Can be left NC when
PANTHER-POINT_FCBGA989 IAMT is not support on
C the platfrom C
+3VS
U9
5
+3VS
VCC
R204 1 @ 2 200_0402_5% PM_DRAM_PWRGD PCH_PWROK 1 IN1 SYS_PWROK
OUT 4 SYS_PWROK (5)
2
GND
(52) VGATE IN2
+3V_PCH
1
3
MC74VHC1G08DFT2G_SC70-5 R211
R305 1 @ 2 200_0402_5% PM_DRAM_PWRGD 100K_0402_5%
R205 1 2 10K_0402_5% SUSWARN#
2
D D
R206 1 2 200K_0402_5% AC_PRESENT_R
R207 1 2 10K_0402_5% PCH_GPIO72
R208 1 2 10K_0402_5% RI#
R210 1 2 10K_0402_5% PCH_RSMRST#_R

Title
DMI,FDI,PM, Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
A A
100K_0402_5% 1 2 R253
U3D
0_0402_5% 1 @ 2 R252 PCH_ENBKL J47 P- AP43
(41) ENBKL L_BKLTEN SDVO_TVCLKINN
(32) PCH_ENVDD M45 L_VDD_EN P- SDVO_TVCLKINP AP45
(32) PCH_PWM P45 L_BKLTCTL P- SDVO_STALLN AM42

P- SDVO_STALLP AM40
(32) EDID_CLK T40 L_DDC_CLK
(32) EDID_DATA K47 L_DDC_DATA P- P- SDVO_INTN AP39
P- SDVO_INTP AP40
+3VS 2.2K_0402_5% 1 2 R212 CTRL_CLK T45
2.2K_0402_5% L_CTRL_CLK
1 2 R213 CTRL_DATA P39 L_CTRL_DATA
2.37K_0402_1% 1 2 R215 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK HDMICLK_NB (34)
AF36 LVD_VBG P- SDVO_CTRLDATA M39 HDMIDAT_NB (34)
LVD_VREF AE48
0_0402_5% @ LVD_VREFH
B
1 2 R217 AE47 LVD_VREFL DDPB_AUXN AT49 B
DDPB_AUXP AT47
DDPB_HPD AT40 PCH_DPB_HPD (34)
(32) LVDS_ACLK# AK39 LVDSA_CLK#
LVDS
(32) LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 PCH_DPB_N0 (34)
DDPB_0P AV40 PCH_DPB_P0 (34) HDMI D2
(32) LVDS_A0# AN48 LVDSA_DATA#0 DDPB_1N AV45 PCH_DPB_N1 (34)
(32) LVDS_A1# AM47 LVDSA_DATA#1 DDPB_1P AV46 PCH_DPB_P1 (34) HDMI D1
Digital Display Interface

(32) LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 PCH_DPB_N2 (34)
AJ48 LVDSA_DATA#3 DDPB_2P AU47 PCH_DPB_P2 (34) HDMI D0
DDPB_3N AV47 PCH_DPB_N3 (34)
(32) LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 PCH_DPB_P3 (34) HDMI CLK
(32) LVDS_A1 AM49 LVDSA_DATA1
(32) LVDS_A2 AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P- DDPC_CTRLDATA P42
(32) LVDS_BCLK# AF40 LVDSB_CLK#

(32) LVDS_BCLK AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
(32) LVDS_B0# AH45 LVDSB_DATA#0 DDPC_HPD AT38
(32) LVDS_B1# AH47 LVDSB_DATA#1
(32) LVDS_B2# AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
(32) LVDS_B0 AH43 LVDSB_DATA0 DDPC_1P AY45
(32) LVDS_B1 AH49 LVDSB_DATA1 DDPC_2N BA47
(32) LVDS_B2 AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
+3VS DAC_BLU N48 M43

(33) DAC_BLU CRT_BLUE DDPD_CTRLCLK
DAC_GRN P49 P- DDPD_CTRLDATA M36
(33) DAC_GRN CRT_GREEN
R218 1 2 2.2K_0402_5% CRT_DDC_CLK DAC_RED T49
(33) DAC_RED CRT_RED
C C
R219 1 2 2.2K_0402_5% CRT_DDC_DATA AT45
DDPD_AUXN
CRT
CRT_DDC_CLK T39 AT43
(33) CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41
(33) CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
R220 1 2 150_0402_1% DAC_BLU BB43
CRT_HSYNC DDPD_0N
(33) CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
R221 1 2 150_0402_1% DAC_GRN CRT_VSYNC M49 BF44
(33) CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
R222 1 2 150_0402_1% DAC_RED BF42
1K_0402_0.5% DDPD_2N
1 2 R223 CRT_IREF T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
D D

Title
LVDS,CRT,DP,HDMI Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+3VS
U3E
R225 AY7
PCI_PIRQB# RSVD1
1 8 RSVD2 AV7
2 7 PCI_PIRQC# BG26 AU3
PCI_PIRQD# TP1 RSVD3
3 6 BJ26 TP2 RSVD4 BG4
4 5 PCI_PIRQA# BH25 TP3
BJ16 TP4 RSVD5 AT10
8.2K_8P4R_5% BG16 BC8
TP5 RSVD6
AH38 TP6
R228 AH37 AU2
PCH_GPIO52 TP7 RSVD7
1 8 AK43 TP8 RSVD8 AT4
2 7 PCH_GPIO5 AK45 AT3
3 6 C18 TP10 RSVD10 AT1
4 5 PCH_GPIO53 N30 AY3
TP11 RSVD11
A H3 TP12 RSVD12 AT5 A
8.2K_8P4R_5% AH12 AV3
TP13 RSVD13
AM4 TP14 RSVD14 AV1
R227 AM5 BB1
ODD_DA# TP15 RSVD15
1 8 Y13 TP16 RSVD16 BA3
2 7 PCH_GPIO4 K24 BB5
3 6 L24 TP18 RSVD18 BB3
4 5 AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD
8.2K_8P4R_5% BD4
RSVD21
RSVD22 BF6
R230 1 2 8.2K_0402_5% PCH_GPIO55
B21 TP21 RSVD23 AV5
R231 1 2 8.2K_0402_5% PCH_GPIO50 M20 AV10
TP22 RSVD24
AY16 TP23
R246 1 2 8.2K_0402_5% PCH_GPIO54 BG46 AT8
TP24 RSVD25
RSVD26 AY5
RSVD27 BA2
BE28 USB3Rn1
(37) USB3_RX1_N BC30 USB3Rn2 RSVD28 AT12
(37) USB3_RX2_N BE32 USB3Rn3 RSVD29 BF3
(37) USB3_RX3_N BJ32 USB3Rn4
BC28 USB3Rp1 PCH HM65 config not support USB port 6 & 7.
(37) USB3_RX1_P BE30 USB3Rp2
R244 1 @ 2 8.2K_0402_5% PCH_GPIO54 BF32
(37) USB3_RX2_P USB3Rp3
(37) USB3_RX3_P BG32 USB3Rp4 USBP0N C24
R232 1 @ 2 8.2K_0402_5% PCH_GPIO50 AV26 A24
USB3Tn1 USBP0P USB20_N1
(37) USB3_TX1_N BB26 USB3Tn2 USBP1N C25 USB20_N1 (37)
R234 1 @ 2 100K_0402_5% PCH_PLTRST# AU28 B25 USB20_P1 USB 3.0
(37) USB3_TX2_N USB3Tn3 USBP1P USB20_P1 (37)
AY30 C26 USB20_N2
(37) USB3_TX3_N USB3Tn4 USBP2N USB20_N2 (37)
AU26 A26 USB20_P2 USB 3.0
USB3Tp1 USBP2P USB20_P2 (37)
AY26 K28 USB20_N3
(37) USB3_TX1_P USB3Tp2 USBP3N USB20_N3 (37)
AV28 H28 USB20_P3 USB 3.0
(37) USB3_TX2_P USB3Tp3 USBP3P USB20_P3 (37)
B (37) USB3_TX3_P AW30 USB3Tp4 USBP4N E28 B
USBP4P D28
C28 USB20_N5
USBP5N USB20_N5 (32)
A28 USB20_P5 CMOS Camera (LVDS)
USBP5P USB20_P5 (32)
USBP6N C29
P- USBP6P B29
PCI_PIRQA# K40 N28
R243 1 @ PIRQA# USBP7N
2 1K_0402_5% PCH_GPIO51 PCI_PIRQB# K38 PIRQB# USBP7P M28
PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30
G30 USB20_N9
DIS@ R254 1 @ 2 0_0402_5% PCH_GPIO50 C46 E30 USB20_P9 USB 2.0
(22) DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 (39)
USB
Boot BIOS Strap bit1 BBS1 DIS@ R348 1 @ 2 0_0402_5% PCH_GPIO52 C44 C30 USB20_N10
(51) NVDD_PWR_EN DIS@ REQ2# / GPIO52 USBP10N USB20_N10 (38)
R264 1 @ 2 0_0402_5% PCH_GPIO54 E40 A30 USB20_P10 Mini Card(WLAN/BT)
(22,24) DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 (38)
GPIO51 GPIO19 Boot BIOS L32 USB20_N11
PCH_GPIO51 D47 P+ K32 USB20_P11 FingerPrint
Destination PCH_GPIO53 GNT1# / GPIO51 USBP11P USB20_N12
USB20_P11 (40)
Bit11 Bit10 E42 GNT2# / GPIO53 P+ USBP12N G32 USB20_N12 (38)
PCH_GPIO55 F46 P+ E32 USB20_P12 Mini Card(WWAN)
GNT3# / GPIO55 USBP12P USB20_P12 (38)
0 1 Reserved C32 USB20_N13
A32 USB20_P13 Bluetooth Module OC[0..3] use for EHCI 1
USBP13P USB20_P13 (38)
1 0 PCI R332 1 @ 2 0_0402_5% PCH_GPIO2 G42 OC[4..7] use for EHCI 2
(38) BT_DET# PIRQE# / GPIO2
ODD_DA# G40 Within 500 mils22.6_0402_1%
(36) ODD_DA# PIRQF# / GPIO3 +3V_PCH
1 1 SPI (Default) PCH_GPIO4 USBRBIAS R247 1
* PCH_GPIO5
C42
D44
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS# C33 2
0 0 LPC R233
B33 USB_OC0# 1 8
USBRBIAS USB_OC1#
(41) PCI_PME# K10 PME# P+ 2 7
USB_OC2# 3 6
PCH_PLTRST# C6 A14 USB_OC0# (To USB S/B) USB_OC3# 4 5
(5) PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# (37)
K20 USB_OC1#
OC1# / GPIO40 USB_OC1# (37)
R245 1 @ 2 1K_0402_5% PCH_GPIO55 B17 USB_OC2# 10K_8P4R_5%
R248 22_0402_5% CLK_PCI0 OC2# / GPIO41 USB_OC3# R235
(14) CLK_PCI_LPBACK 1 2 H49 CLKOUT_PCI0 P- OC3# / GPIO42 C16
CLK_PCI_EC R249 1 2 22_0402_5% CLK_PCI1 H43 P- L16 USB_OC4# USB_OC4# 1 8
(41) CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# (39)
R250 1 2 22_0402_5% CLK_PCI2 J48 P- A16 USB_OC5# USB_OC5# 2 7
(38,40) CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
A16 swap overide Strap/Top-Block R350 1 2 22_0402_5% CLK_PCI3 K42 P- D14 USB_OC6# USB_OC6# 3 6
(40) CLK_PCI_TPM CLKOUT_PCI3 OC6# / GPIO10
C Swap Override jumper TPM@ H40 P- C14 USB_OC7# USB_OC7# 4 5 C
CLKOUT_PCI4 OC7# / GPIO14
Low=A16 swap 10K_8P4R_5%
override/Top-Block PANTHER-POINT_FCBGA989
PCI_GNT3# Swap Override enabled
High=Default *
RF Boris Tsai suggests

10P_0402_50V8J 1 2 C119 CLK_PCI_TPM
10P_0402_50V8J @ 1 2 C92 CLK_PCI_LPBACK

R251 1 2 0_0402_5%
10P_0402_50V8J 1 2 C93 CLK_PCI_EC

+3VS
5
U11
PCH_PLTRST# 1
P
B
Y 4 PLT_RST# (5,14,22,36,38,40,41)
2 A
G
@ R255
3
TC7SH08FUF_SSOP5 100K_0402_5%
2
D D

Title
PCI, USB, NVRAM Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable
R265 1 @ 2 1K_0402_5% PCH_GPIO28
U3F +3VS
GPIO28
On-Die PLL Voltage Regulator PCH_GPIO0 T7 P+ C40 ODD_EN# ODD_EN# R256 1 2 8.2K_0402_5%
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# (36)
This signal has a weak internal pull up
A PCH_GPIO1 A42 P+ P+ B41 PCH_GPIO69 R260 1 @ 2 8.2K_0402_5% A
TACH1 / GPIO1 TACH5 / GPIO69
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable PCH_GPIO6 H36 TACH2 / GPIO6 P+ P+ TACH6 / GPIO70 C41 PCH_GPIO70
EC_SCI# E38 P+ P+ A40 PCH_GPIO71 +3VS

(41) EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
R274 1 @ 2 1K_0402_5% EC_SMI#
EC_SMI# C10 P+ PCH_GPIO70 R258 2 1 10K_0402_5%
(41) EC_SMI# GPIO8
PCH_GPIO12 C4 R262 1 @ 2 10K_0402_5%
LAN_PHY_PWR_CTRL / GPIO12
+3VS EC_WAKE# R178 1 @ 2 0_0402_5% PCH_GPIO15 G2 P- P4
GPIO15 A20GATE GATEA20 (41)
R280 1 @ 2 10K_0402_5% P- AU16 PCH_PECI_R R267 1 @ 2 0_0402_5% +3VS
PECI H_PECI (5,41)
R282 1 2 10K_0402_5% WLBT_OFF_51# PCH_GPIO16 U2 SATA4GP / GPIO16 KB_RST# PCH_GPIO71 R257 2
RCIN# P5 KB_RST# (41) 1 10K_0402_5%
GPIO
DGPU_PWROK D40 AY11 H_CPUPWRGD R263 1 @ 2 10K_0402_5%
+3V_PCH (24,51) DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD (5)
CPU/MISC
PCH_GPIO22 T5 AY10 R278 1 2 390_0402_5% H_THRMTRIP#
SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# (5)
R288 1 2 10K_0402_5% VGA_THRMTRIP# (22) +3VS
R290 1 @ 2 10K_0402_5% PCH_GPIO24 PCH_GPIO24 E8 P+ T14
GPIO24 INIT3_3V#
INIT3_3V
R167 1 2 0_0402_5% PCH_GPIO27 DF_TVS GATEA20 R272 1 2 10K_0402_5%
(41) EC_WAKE# E16 GPIO27 P+ P- DF_TVS AY1
This signal has weak internal
+3VS PCH_GPIO28 KB_RST# R276 1 2 10K_0402_5%
P8 GPIO28 P+ PU, can't pull low
TS_VSS1 AH8
R285 1 @ 2 10K_0402_5% BT_ON# K1
(38) BT_ON# STP_PCI# / GPIO34
R284 1 2 10K_0402_5% PCH_GPIO37 AK11
3G_DET# TS_VSS2 +1.8VS
(38) 3G_DET# K4 GPIO35
TS_VSS3 AH10
WLBT_OFF_51# V8 P-
+3VS (38) WLBT_OFF_51# SATA2GP / GPIO36
TS_VSS4 AK10 Intel schematic reviwe recommand.
1
PCH_GPIO37 M5 P-
SATA3GP / GPIO37 R226
R269 1 2 10K_0402_5% PCH_GPIO0 PCH_GPIO38 N2 P37 2.2K_0402_5%
B SLOAD / GPIO38 NC_1 B
R270 1 2 10K_0402_5% PCH_GPIO1 3G_OFF# M3
(38) 3G_OFF#
2
SDATAOUT0 / GPIO39
R266 1 2 10K_0402_5% PCH_GPIO6 PCH_GPIO48 V13 BG2 T18 DF_TVS R229 1 2 1K_0402_5% H_SNB_IVB# (5)
SDATAOUT1 / GPIO48 VSS_NCTF_15
R344 1 @ 2 10K_0402_5% EC_SCI# PCH_GPIO49 V3 BG48 T19
R293 1 @ SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
(38) mSATA_PCH 2 0_0402_5% DMI Termination Voltage
R275 1 2 10K_0402_5% PCH_GPIO16 PCH_GPIO57 D6 BH3 T20
R294 1 GPIO57 VSS_NCTF_17
(41) mSATA_DETEC# 2 10K_0402_5% Set to Vcc when HIGH
R268 1 2 10K_0402_5% DGPU_PWROK BH47 T21 NV_CLE
VSS_NCTF_18
Set to Vss when LOW
R277 1 2 10K_0402_5% PCH_GPIO22 T22 A4 BJ4 T23
VSS_NCTF_1 VSS_NCTF_19
CLOSE TO THE BRANCHING POINT
R346 1 2 10K_0402_5% BT_ON# GPIO34 T24 A44 BJ44
VSS_NCTF_2 VSS_NCTF_20 T25
R283 1 2 10K_0402_5% 3G_DET# T26 A45 BJ45 T27
NCTF
R287 1 2 10K_0402_5% 3G_OFF# T28 A46 BJ46 T29
R289 1 2 10K_0402_5% PCH_GPIO48 T30 A5 BJ5 T31
R291 1 2 10K_0402_5% PCH_GPIO49 T32 A6 BJ6 T33
T34 B3 C2 T35
+3V_PCH T36 B47 C48 T37
T38 BD1 D1 T39
R345 1 VSS_NCTF_9 VSS_NCTF_27
2 10K_0402_5% EC_SMI#
T40 BD49 D49 T41
R271 1 PCH_GPIO12 VSS_NCTF_10 VSS_NCTF_28
2 10K_0402_5%
T42 BE1 E1 T43
2 1K_0402_5% PCH_GPIO15
T44 BE49 E49 T45
C 2 10K_0402_5% PCH_GPIO28 C
T46 BF1 F1 T47
R292 1 @ VSS_NCTF_13 VSS_NCTF_31
2 10K_0402_5% PCH_GPIO57
T48 BF49 F49 T49
For Edge code setting
PCH_GPIO69 PCH_GPIO38 PCH_GPIO67 Function
0 0 0 Optimus
0 0 1 Reserved
0 1 0 DIS
0 1 1 UMA
+3VS
1
R259 R330 R311

10K_0402_5% 10K_0402_5% 10K_0402_5%
D D
@ UMA@ UMA@
2
PCH_GPIO69
PCH_GPIO38
(MB_ID_2)
PCH_GPIO67
(MB_ID_1)
PCH_GPIO67 (14) (MB_ID_0)
1
R261 R329 R286

10K_0402_5% 10K_0402_5%
DIS@
10K_0402_5%
DIS@
Title
PCH (6/9) GPIO, CPU, MISC
2
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+VCCADAC +3VS
+VCCADAC MBK1608221YZF_2P 1 2 L1
C94
0.01U_0402_16V7K
C99
0.1U_0402_10V7K
C100
10U_0603_6.3V6M
C160
10U_0603_6.3V6M
1 1 1 1
@
2 2 2 2
A A
+1.05VS +1.05VS_PCH U3G POWER
JP2 1300mA
1 2 +1.05VS_PCH AA23 U48
VCCCORE[1] 1mA VCCADAC
AC23 VCCCORE[2] +3VS
C95
10U_0603_6.3V6M
C96
1U_0402_6.3V6K
C97
1U_0402_6.3V6K
C98
1U_0402_6.3V6K
PAD-OPEN 4x4m AD21
CRT
VCCCORE[3]
1 1 1 1 AD23 VCCCORE[4] VSSADAC U47
AF21
VCC CORE
VCCCORE[5]
AF23 VCCCORE[6]
AG21 +1.8VS
2 2 2 2 VCCCORE[7]
AG23 VCCCORE[8]
AG24 VCCCORE[9] 1mAVCCALVDS AK36
AG26 +VCCTX_LVDS 0.1UH_MLF1608DR10KT_10%_1608 1 2 L2
VCCCORE[10]
AG27 AK37 0.1uH inductor, 200mA
VCCCORE[11] VSSALVDS
C101
0.01U_0402_16V7K
C102
0.01U_0402_16V7K
C103
22U_0805_6.3V6M
AG29 VCCCORE[12]
AJ23 VCCCORE[13] 1 1 1
LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37
AJ27 VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38
2 2 2
AJ31 VCCCORE[17]
+1.05VS_PCH 40mA VCCTX_LVDS[3] AP36
+1.05VS_VCCDPLLEXP
VCCTX_LVDS[4] AP37
+1.05VS_PCH AN19 VCCIO[28] +3VS
T50 +VCCAPLLEXP BJ22 VCCAPLLEXP
This pin can be left as no connect in VCC3_3[6] V33
HVCMOS
AN16 VCCIO[15]
On-Die VR enabled mode (default). 1
AN17 C104
VCCIO[16] 0.1U_0402_10V7K
VCC3_3[7] V34
+1.05VS_PCH
B +1.05VS_VCC_EXP 2 B
AN21 VCCIO[17] +VCCAFDI_VRM
AN26 VCCIO[18]
C105
10U_0603_6.3V6M
C106
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
AN27 3709mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
1 1 1 1 1
AP21 +1.05VS_PCH
VCCIO[20] +VCCP_VCCDMI
AP23 VCCIO[21] VCCDMI[1] AT20
2 2 2 2 2
+1.05VS
DMI
AP24 VCCIO[22]
VCCIO
1
AP26 75mA VCCCLKDMI AB36 C110
VCCIO[23] 1U_0402_6.3V6K
1
AT24 C111
+3VS VCCIO[24] 1U_0402_6.3V6K 2
2
AN33 VCCIO[25]
AN34 AG16 +1.8VS
VCCIO[26] VCCDFTERM[1] +VCCPNAND
1
C112
0.1U_0402_10V7K BH29 AG17 +VCCPNAND 0_0805_5% 1 @ 2 R300
VCC3_3[3] 2mA VCCDFTERM[2]
DFT / SPI
2 1
C113
AJ16 1U_0402_6.3V6K
VCCDFTERM[3]
+VCCAFDI_VRM 2
AP16 VCCVRM[2]
VCCDFTERM[4] AJ17
Place C167 Near BG6 pin +3VM +3VS
+1.05VS_VCCAPLL_FDI BG6 VccAFDIPLL
+3V_VCCPSPI R166 1 SBA@ 2 0_0402_5%
1
+1.05VS_PCH AP17
@ C114 VCCIO[27] +3V_VCCPSPI R302 @
C 10mA VCCSPI V1 1 2 0_0402_5% C
FDI
1U_0402_6.3V6K
2
AU20 VCCDMI[2] 1
C115 11/16
+1.05VS_VCCDPLL_FDI 1U_0402_6.3V6K
+VCCP_VCCDMI PANTHER-POINT_FCBGA989
2
+1.5VS +VCCAFDI_VRM
R304 1 2 0_0603_5% +VCCAFDI_VRM
D D
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

Title
PWR Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec
+1.05VS
+3VALW Have internal VRM
R307 1 @ 2 0_0603_5% +VCCACLK
+5VALW +5VALW_PCH
R308 1 2 0_0603_5% +VCCPDSW @

+1.05VS_PCH R309 1 2 0_0603_5%
U3J POWER
If platform does not support 1
A Deep S4/S5 then tie to VccSus3_3. C118 AD49 N26 +1.05VS_PCH A
0.1U_0402_10V7K VCCACLK VCCIO[29]
1
P26 C120
+3VS 2 VCCIO[30] 1U_0402_6.3V6K
T16 VCCDSW3_33mA
VCCIO[31] P28
+3V_PCH 2 +1.05VS_VCCUSBCORE
+3VS C121 @ +PCH_VCCDSW
1 2 V12 DCPSUSBYP VCCIO[32] T27
C116
10U_0603_6.3V6M
C117
1U_0402_6.3V6K
0.1U_0402_10V7K T29
VCCIO[33]
1 1 T38 VCC3_3[5] 1
C122
+1.05VS_PCH C123 @ 2 1 +VCCAPLL_CPY_PCH T23 0.1U_0402_10V7K
119mA VCCSUS3_3[7]
BH23 VCCAPLLDMI2
2 2 10U_0603_6.3V6M 2 11/16
VCCSUS3_3[8] T24
AL29 VCCIO[14]
VCCSUS3_3[9] V23
USB
+VCCDPLL_CPY 1
C124 @ +VCCSUS1 C125 +3V_PCH +5VALW_PCH
1 2 AL24 DCPSUS[3] VCCSUS3_3[10] V24
0.1U_0402_10V7K
1U_0402_6.3V6K P24 +1.05VS_PCH
VCCSUS3_3[6]
1
2
AA19 D4 R315
VCCASW[1] +1.05VS_PCH +1.05VS_VCCAUPLL RB751V-40_SOD323-2 10_0402_5%
VCCIO[34] T26
AA21 VCCASW[2]
903mA
1
2
AA24 M26 +PCH_V5REF_SUS +PCH_V5REF_SUS
VCCASW[3] 1mA V5REF_SUS C132 @ 1
+1.05VS AA26 1U_0402_6.3V6K +3V_PCH C126
Clock and Miscellaneous

@ VCCASW[4] +VCCA_USBSUS 2 0.1U_0402_10V7K
DCPSUS[4] AN23
R316 1 2 0_0805_5% +1.05VM_VCCASW AA27 VCCASW[5] +3V_PCH 2
VCCSUS3_3[1] AN24
C127
1U_0402_6.3V6K
C128
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
C130
22U_0805_6.3V6M
C131
22U_0805_6.3V6M
AA29 VCCASW[6] 1
+1.05VM
1 1 1 1 1
SBA@ AA31 C133 11/16
R349 1 VCCASW[7]
2 0_0805_5% 0.1U_0402_10V7K
B
+PCH_V5REF_RUN 2 B
AC26 P34
2 2 2 2 2 VCCASW[8] 1mA V5REF
if not supply SBA R316 mount , R349 @ AC27
+3VS +5VS
VCCASW[9]
if supply SBA R316 @,R349 mount VCCSUS3_3[2] N20 +3V_PCH
PCI/GPIO/LPC
AC29 VCCASW[10] 1
1
N22 C134
VCCSUS3_3[3] 1U_0402_6.3V6K D5 R318
AC31 VCCASW[11]
+1.05VS_PCH P20 RB751V-40_SOD323-2 10_0402_5%
L4 VCCSUS3_3[4] 2 +3VS
AD29 VCCASW[12]
1 2 +1.05VS_VCCA_A_DPL P22
2
10UH_LB2012T100MR_20% VCCSUS3_3[5] +PCH_V5REF_RUN
AD31 VCCASW[13]
C136 1 C137 1
1 W21 AA16 C135
220U_B2_2.5VM_R35 + 1U_0402_6.3V6K VCCASW[14] VCC3_3[1] 1U_0402_6.3V6K
1 1
W23 W16 C141 C140
VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K 0.1U_0402_10V7K 2
2 2
W24 VCCASW[16] VCC3_3[4] T34
2 2
W26 VCCASW[17]
L5 W29
+1.05VS_VCCA_B_DPL VCCASW[18]
1 2 1
10UH_LB2012T100MR_20% W31 AJ2 C142
C138 C139 VCCASW[19] VCC3_3[2] 0.1U_0402_10V7K
1
1 W33 VCCASW[20]
220U_B2_2.5VM_R35 + 1U_0402_6.3V6K 2 +1.05VS_PCH
VCCIO[5] AF13
C143 1 2 +VCCRTCEXT
N16 DCPRTC
2 2 0.1U_0402_10V7K
VCCIO[12] AH13
1 +1.05VS_SATA3
+VCCAFDI_VRM Y49 AH14 Place C199 Near AK1 pin C145
VCCVRM[4] VCCIO[13] +VCCSATAPLL 1U_0402_6.3V6K
+VCCAFDI_VRM 1
C147 2
VCCIO[6] AF14
C 1 +1.05VS_VCCA_A_DPL BD47 75mA 10U_0603_6.3V6M C
VCCADPLLA
SATA
C144 AK1 @ +VCCAFDI_VRM
1U_0402_6.3V6K +1.05VS_VCCA_B_DPL VCCAPLLSATA 2
BF47 VCCADPLLB
75mA
2 +VCCAFDI_VRM
VCCVRM[1] AF11
+1.05VS_PCH AF17 +1.05VS_PCH
VCCIO[7]
AF33 VCCDIFFCLKN[1]
AF34 VCCDIFFCLKN[2]
55mA VCCIO[2] AC16
AG34 VCCDIFFCLKN[3]
+1.05VS_PCH AC17 +1.05VS_VCC_SATA
VCCIO[3]
1 1
C146 AG33 AD17 C148
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4] 1U_0402_6.3V6K
+1.05VS 2 2
V16 DCPSST
R328 1 2 0_0603_5% +1.05VS_SSCVCC T17 T21

DCPSUS[1] VCCASW[22]
1 V19 DCPSUS[2]
Ensure independent power C149 +VCCSST +1.05VM_VCCASW
MISC
1U_0402_6.3V6K V21
routing for SSC and DIFFCLKN +1.05VM_VCCSUS VCCASW[23]
2
CPU
2 1 BJ8 V_PROC_IO
1mA
VCCASW[21] T19
C150 C151
0.1U_0402_10V7K 1U_0402_6.3V6K
1 2 +3V_PCH
@
A22 P32
RTC
VCCRTC 10mA VCCSUSHDA

HDA
+1.05VS_PCH
+V_CPU_IO +1.05VS_PCH PANTHER-POINT_FCBGA989

1
C152
C153
C154
4.7U_0603_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
C158
1 1 1 0.1U_0402_16V4Z
D +RTCVCC 2 D
11/16
2 2 2
C155
C156
C157
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1
2 2 2 Security Classification Compal Secret Data

Title
PWR Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
U3H U3I
H5 VSS[0]
AY4 VSS[159] VSS[259] H46
AA17 VSS[1] VSS[80] AK38 AY42 VSS[160] VSS[260] K18
A AA33 VSS[4] VSS[83] AK46 B11 VSS[163] VSS[263] K46 A
AA34 VSS[5] VSS[84] AK8 B15 VSS[164] VSS[264] K7
AB11 VSS[6] VSS[85] AL16 B19 VSS[165] VSS[265] L18
AC19 VSS[13] VSS[92] AL27 F45 VSS[172] VSS[272] M12
AC2 VSS[14] VSS[93] AL31 BB12 VSS[173] VSS[273] P16
AC21 VSS[15] VSS[94] AL33 BB16 VSS[174] VSS[274] M18
AC34 VSS[18] VSS[97] AM11 BB24 VSS[177] VSS[277] M30
AC48 VSS[19] VSS[98] AM14 BB28 VSS[178] VSS[278] M32
AD10 VSS[20] VSS[99] AM36 BB30 VSS[179] VSS[279] M34
AD19 VSS[24] VSS[103] AM46 BC14 VSS[183] VSS[283] M46
AD24 VSS[25] VSS[104] AM7 BC18 VSS[184] VSS[284] M8
AD26 VSS[26] VSS[105] AN2 BC2 VSS[185] VSS[285] N18
AD27 VSS[27] VSS[106] AN29 BC22 VSS[186] VSS[286] P30
AD33 VSS[28] VSS[107] AN3 BC26 VSS[187] VSS[287] N47
AD34 VSS[29] VSS[108] AN31 BC32 VSS[188] VSS[288] P11
AD36 VSS[30] VSS[109] AP12 BC34 VSS[189] VSS[289] P18
AD37 VSS[31] VSS[110] AP19 BC36 VSS[190] VSS[290] T33
AD40 VSS[35] VSS[114] AP38 BD46 VSS[194] VSS[294] P7
AD42 VSS[36] VSS[115] AP4 BD5 VSS[195] VSS[295] R2
AD43 VSS[37] VSS[116] AP42 BE22 VSS[196] VSS[296] R48
B
AD45 VSS[38] VSS[117] AP46 BE26 VSS[197] VSS[297] T12 B
AD46 VSS[39] VSS[118] AP8 BE40 VSS[198] VSS[298] T31
AD8 VSS[40] VSS[119] AR2 BF10 VSS[199] VSS[299] T37
AE2 VSS[41] VSS[120] AR48 BF12 VSS[200] VSS[300] T4
AE3 VSS[42] VSS[121] AT11 BF16 VSS[201] VSS[301] W34
AF10 VSS[43] VSS[122] AT13 BF20 VSS[202] VSS[302] T46
AF12 VSS[44] VSS[123] AT18 BF22 VSS[203] VSS[303] T47
AD14 VSS[45] VSS[124] AT22 BF24 VSS[204] VSS[304] T8
AD16 VSS[46] VSS[125] AT26 BF26 VSS[205] VSS[305] V11
AF16 VSS[47] VSS[126] AT28 BF28 VSS[206] VSS[306] V17
AF19 VSS[48] VSS[127] AT30 BD3 VSS[207] VSS[307] V26
AF31 VSS[53] VSS[132] AT46 BG17 VSS[212] VSS[312] V39
AF38 VSS[54] VSS[133] AT7 BG21 VSS[213] VSS[313] V43
AF4 VSS[55] VSS[134] AU24 BG33 VSS[214] VSS[314] V7
AF42 VSS[56] VSS[135] AU30 BG44 VSS[215] VSS[315] W17
AF46 VSS[57] VSS[136] AV16 BG8 VSS[216] VSS[316] W19
AF5 VSS[58] VSS[137] AV20 BH11 VSS[217] VSS[317] W2
AG19 VSS[61] VSS[140] AV38 BH19 VSS[220] VSS[320] Y12
AG2 VSS[62] VSS[141] AV4 H10 VSS[221] VSS[321] Y38
AH11 VSS[65] VSS[144] AW14 BH33 VSS[224] VSS[324] Y46
AH3 VSS[66] VSS[145] AW18 BH35 VSS[225] VSS[325] Y8
AH36 VSS[67] VSS[146] AW2 BH39 VSS[226] VSS[328] BG29
AH39 VSS[68] VSS[147] AW22 BH43 VSS[227] VSS[329] N24
AH40 VSS[69] VSS[148] AW26 BH7 VSS[228] VSS[330] AJ3
AH42 VSS[70] VSS[149] AW28 D3 VSS[229] VSS[331] AD47
AH46 VSS[71] VSS[150] AW32 D12 VSS[230] VSS[333] B43
AH7 VSS[72] VSS[151] AW34 D16 VSS[231] VSS[334] BE10
C AJ19 VSS[73] VSS[152] AW36 D18 VSS[232] VSS[335] BG41 C
AJ21 VSS[74] VSS[153] AW40 D22 VSS[233] VSS[337] G14
AJ24 VSS[75] VSS[154] AW48 D24 VSS[234] VSS[338] H16
AJ33 VSS[76] VSS[155] AV11 D26 VSS[235] VSS[340] T36
AJ34 VSS[77] VSS[156] AY12 D30 VSS[236] VSS[342] BG22
AK12 VSS[78] VSS[157] AY22 D32 VSS[237] VSS[343] BG24
AK3 VSS[79] VSS[158] AY28 D34 VSS[238] VSS[344] C22
D38 VSS[239] VSS[345] AP13
PANTHER-POINT_FCBGA989 D42 M14
VSS[240] VSS[346]
D8 VSS[241] VSS[347] AP3
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
D D

Title
VSS Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+3VS_VGA
OVERT# R1408 1 DIS@ 2 10K_0402_5%
THERM#_VGA R1410 1 DIS@ 2 10K_0402_5%
VGA_GPIO12 R1409 1 DIS@ 2 10K_0402_5%
VGA_BL_PWM R1413 1 DIS@ 2 10K_0402_5%
U1401A VGA_ENVDD R1411 1 DIS@ 2 10K_0402_5%

PCIE_CTX_GRX_N[0..15]
(4) PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P0 AN12 Part 1 of 7 VGA_ENBKL R1412 1 @ 2 10K_0402_5%
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 PEX_RX0 GPU_VID4
A
(4) PCIE_CTX_GRX_P[0..15] AM12 PEX_RX0_N GPIO0 P6 GPU_VID4 (51) A
PCIE_CTX_GRX_P1 AN14 M3 GPU_VID3 VGA_GPIO15 R1414 1 DIS@ 2 100K_0402_5%
PCIE_CRX_GTX_N[0..15] PEX_RX1 GPIO1 GPU_VID3 (51)
PCIE_CTX_GRX_N1 AM14 L6 VGA_BL_PWM
(4) PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2
PCIE_CTX_GRX_P2 AP14 P5 VGA_ENVDD R1429 1 @ 2 0_0402_5%
PCIE_CRX_GTX_P[0..15] PEX_RX2 GPIO3 DPRSLPVR_VGA (51)
PCIE_CTX_GRX_N2 AP15 P7 VGA_ENBKL
(4) PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4
PCIE_CTX_GRX_P3 AN15 L7 GPU_VID1
PEX_RX3 GPIO5 GPU_VID1 (51)
PCIE_CTX_GRX_N3 AM15 M7 GPU_VID2
PEX_RX3_N GPIO6 GPU_VID2 (51) +3VS_VGA
PCIE_CTX_GRX_P4 AN17 N8
PCIE_CTX_GRX_N4 PEX_RX4 GPIO7 OVERT#
AM17 PEX_RX4_N GPIO8 M1
PCIE_CTX_GRX_P5 AP17 M2 THERM#_VGA
PCIE_CTX_GRX_N5 PEX_RX5 GPIO9
AP18 PEX_RX5_N GPIO10 L1 VGA_THRMTRIP# (18)
1
PCIE_CTX_GRX_P6 AN18 M5 GPU_VID0
GPU_VID0 (51)
GPIO
PCIE_CTX_GRX_N6 PEX_RX6 GPIO11 VGA_GPIO12 D2414 VGA_AC_DET
AM18 PEX_RX6_N GPIO12 N3 2 1 VGA_AC_DET (41,51)
3
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5 R1423
PEX_RX7 GPIO13 GPU_VID5 (51)
PCIE_CTX_GRX_N7 AM20 N4 RB751V-40_SOD323-2 DIS@ 10K_0402_5%
PCIE_CTX_GRX_P8 PEX_RX7_N GPIO14 VGA_GPIO15 DIS@ Q1401B
AP20 P2
2
PCIE_CTX_GRX_N8 PEX_RX8 GPIO15 VGA_GPIO16 R1430 1 @
AP21 PEX_RX8_N GPIO16 R8 2 0_0402_5% DPRSLPVR_VGA (51) 5 2N7002KDWH_SOT363-6
PCIE_CTX_GRX_P9 AN21 M6 DIS@
PEX_RX9 GPIO17
6
PCIE_CTX_GRX_N9 AM21 R1
4
PCIE_CTX_GRX_P10 PEX_RX9_N GPIO18
AN23 PEX_RX10 GPIO19 P3
PCIE_CTX_GRX_N10 AM23 P4
PCIE_CTX_GRX_P11 PEX_RX10_N GPIO20 OVERT#
AP23 PEX_RX11 GPIO21 P1 2
PCIE_CTX_GRX_N11 AP24 DIS@ Q1401A
PCIE_CTX_GRX_P12 PEX_RX11_N 2N7002KDWH_SOT363-6
AN24
1
PCIE_CTX_GRX_N12 PEX_RX12
AM24 PEX_RX12_N
PCIE_CTX_GRX_P13 AN26
AM26 PEX_RX13_N
PCIE_CTX_GRX_P14 AP26
AP27 PEX_RX14_N
PCIE_CTX_GRX_P15 AN27 AK9
PCIE_CTX_GRX_N15 PEX_RX15 DACA_RED
AM27 PEX_RX15_N DACA_GREEN AL10
+3VS_VGA
DIS@ DACA_BLUE AL9
DACs
PCIE_CRX_GTX_P0 C1401 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P0 AK14
PCIE_CRX_GTX_N0 C1402 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N0 PEX_TX0
B
1 2 AJ14 PEX_TX0_N DACA_HSYNC AM9 B
PCIE_CRX_GTX_P1 C1403 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P1 AH14 AN9
PCIE_CRX_GTX_N1 C1404 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N1 PEX_TX1 DACA_VSYNC
1 2 AG14 PEX_TX1_N
PCIE_CRX_GTX_N2 C1406 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N2 PEX_TX2 R1448 1 DIS@
1 2 AJ15 PEX_TX2_N DACA_VDD AG10 2 10K_0402_5%
5
PCI EXPRESS
PCIE_CRX_GTX_P3 C1407 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P3 AL16 AP9
PCIE_CRX_GTX_N3 C1409 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N3 PEX_TX3 DACA_VREF Q1402B DIS@
1 2 AK16 PEX_TX3_N DACA_RSET AP8
PCIE_CRX_GTX_P4 C1410 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P4 AK17 I2CS_SCL 4 3
PEX_TX4 EC_SMB_CK2 (14,39,41)
PCIE_CRX_GTX_N4 C1411 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N4 AJ17
PCIE_CRX_GTX_P5 C1412 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_P5 PEX_TX4_N 2N7002KDWH_SOT363-6
1 2 AH17 PEX_TX5
PCIE_CRX_GTX_N5 C1413 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N5 AG17
PCIE_CRX_GTX_P6 C1414 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_P6 PEX_TX5_N +3VS_VGA R1442 1 @
1 2 AK18 PEX_TX6 2 0_0402_5%
PCIE_CRX_GTX_N6 C1415 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N6 AJ18
PCIE_CRX_GTX_P7 C1416 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_P7 PEX_TX6_N
1 2 AL19 PEX_TX7
2
PCIE_CRX_GTX_N7 C1417 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N7 AK19 R4 I2CA_SCL R1452 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_P8 C1418 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_P8 PEX_TX7_N I2CA_SCL I2CA_SDA R1460 1 DIS@
1 2 AK20 PEX_TX8 I2CA_SDA R5 2 2.2K_0402_5% Q1402A DIS@
PCIE_CRX_GTX_N8 C1419 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_N8 AJ20 I2CS_SDA 1 6
PEX_TX8_N EC_SMB_DA2 (14,39,41)
PCIE_CRX_GTX_P9 C1420 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL R1406 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_N9 C1421 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N9 PEX_TX9 I2CB_SCL I2CB_SDA R1407 1 DIS@
1 2 AG20 PEX_TX9_N I2CB_SDA R6 2 2.2K_0402_5% 2N7002KDWH_SOT363-6
I2C
PCIE_CRX_GTX_N10 C1423 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N10 PEX_TX10 I2CC_SCL R1402 1 DIS@
1 2 AJ21 PEX_TX10_N I2CC_SCL R2 2 2.2K_0402_5% R1443 1 @ 2 0_0402_5%
PCIE_CRX_GTX_P11 C1424 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P11 AL22 R3 I2CC_SDA R1403 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_N11 C1425 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N11 PEX_TX11 I2CC_SDA
1 2 AK22 PEX_TX11_N
PU AT EC SIDE, +3VS AND 4.7K
PCIE_CRX_GTX_P12 C1426 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P12 AK23 T4 I2CS_SCL R1404 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_N12 C1427 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N12 PEX_TX12 I2CS_SCL I2CS_SDA R1405 1 DIS@
1 2 AJ23 PEX_TX12_N I2CS_SDA T3 2 2.2K_0402_5%
PCIE_CRX_GTX_P13 C1428 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P13 AH23
PCIE_CRX_GTX_N13 C1429 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N13 PEX_TX13
1 2 AG23 PEX_TX13_N
PCIE_CRX_GTX_N14 C1431 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N14 PEX_TX14 R1436 1 DIS@
1 2 AJ24 PEX_TX14_N 2 10M_0402_5%
PCIE_CRX_GTX_P15 C1432 DIS@ 1 2 0.1U_0402_10V7K PCIE_CRX_C_GTX_P15 AL25
PCIE_CRX_GTX_N15 C1433 DIS@ 0.1U_0402_10V7K PCIE_CRX_C_GTX_N15 PEX_TX15 DIS@
1 2 AK25 PEX_TX15_N 60mA Y1401
AD8 +PLLVDD R1428 1 @ 2 0_0402_5%
PLLVDD XTALIN XTAL_OUT
AJ11 PEX_WAKE_N 1 1 3 3
CLK_PCIE_VGA SP_PLLVDD AE8 45mA GND GND
C
(14) CLK_PCIE_VGA AL13 PEX_REFCLK 1 1 C
CLK_PCIE_VGA# AK13 AD7 45mA +SP_PLLVDD C1441 C1442
(14) CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD 2 4
CLK_REQ_GPU# 18P_0402_50V8J 18P_0402_50V8J
CLK
AK12 PEX_CLKREQ_N DIS@ DIS@
@ PEX_TSTCLK_OUT XTALIN 2 27MHZ 16PF X3G027000FG1H-HX 2
Differential signal 1
R1432
2
200_0402_1% PEX_TSTCLK_OUT#
AJ26
AK26
PEX_TSTCLK_OUT XTAL_IN H3
H2 XTAL_OUT
PEX_TSTCLK_OUT_N XTAL_OUT
PLT_RST_VGA# AJ12 J4 XTALOUT R1433 1 DIS@ 2 10K_0402_5%
PEX_TERMP PEX_RST_N XTAL_OUTBUFF XTALSSIN R1435 1 DIS@
1 2 AP29 PEX_TERMP XTAL_SSIN H1 2 10K_0402_5%
R1434 DIS@ 2.49K_0402_1%
Internal Thermal Sensor
Under GPU(below 150mils)
N13P-PES-A1_FCBGA908
DIS@ 150mA L1402 DIS@
+SP_PLLVDD 1 2 +1.05VS_VGA
SA000056B30 BLM18PG330SN1_2P
C1443
C1444
C1445
C1446
22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
S IC N13M-GE1-B-A1 FCBGA 908P GPU A39 180ohms (ESR=0.2) Bead
1 1 1 1
SA000051A40
DIS@
DIS@
DIS@
DIS@
S IC N13P-GL-A1 FCBGA 908P GPU A39 2 2 2 2
10K_0402_5%
R1444
DIS@ L1403 DIS@
+3VS_VGA +3VS_VGA 1 2 +PLLVDD 1 2
(17,24) DGPU_PWR_EN +1.05VS_VGA
BLM18PG181SN1D_2P
+3VS_VGA
C1448
C1449
0.1U_0402_10V7K
22U_0805_6.3V6M
1 30 ohms @100MHz (ESR=0.05)
C2154 1 1
0.1U_0402_16V4Z
1
R1437 1 2 DIS@
D 2 D
DIS@
DIS@
@ 0_0402_5% R1438 11/17 R1445
10K_0402_5% 10K_0402_5%
Under GPU 2 2 Near GPU
2
@ DIS@
5
U1402
G
2
PLT_RST# 1
P
(5,14,17,36,38,40,41) PLT_RST# B
4 PLT_RST_VGA# 1 3 CLK_REQ_GPU#
Y (14) GPU_CLKREQA
DGPU_HOLD_RST# 2
D
(17) DGPU_HOLD_RST# A
G
1
1
TC7SH08FUF_SSOP5 C2108 Q2414 DIS@

3
DIS@ R1441 0.1U_0402_16V4Z 2N7002K_SOT23-3 R1446

10K_0402_5% 10K_0402_5% Title
DIS@ 2
1 @ 2 @
N13X-PCIE/DAC/GPIO
2
R1447 0_0402_5% Size Document Number Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
U1401D
Part 4 of 7
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28
AN5 IFPA_TXD1 NC AJ4
AM5 IFPA_TXD1_N NC AJ5
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15
NC
AJ6 IFPA_TXD3 NC D19
AH6 IFPA_TXD3_N NC D20
A
NC D23 A
NC D26
AJ9 IFPB_TXC NC H31
AH9 IFPB_TXC_N NC T8
AP6 IFPB_TXD4 NC V32
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N
AK8 IFPB_TXD7
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA (51)
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA (51)
AJ2 IFPC_L1_N
AH3 IFPC_L2 trace width: 16mils
AH4 IFPC_L2_N
AG5 differential voltage sensing.
IFPC_L3
AG4 IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE R1449 1 DIS@ 2 10K_0402_5%
IFPD_L0 TESTMODE
AM2 IFPD_L0_N
AM3 IFPD_L1 JTAG_TCK AM10 T1401
AM4 IFPD_L1_N JTAG_TDI AM11 T1402
AL3 IFPD_L2 JTAG_TDO AP12 T1403
AL4 IFPD_L2_N JTAG_TMS AP11 T1404
AK4 AN11 R1450 1 DIS@ 2 10K_0402_5%
IFPD_L3 JTAG_TRST_N
AK5 IFPD_L3_N
LVDS/TMDS
B
AD2 IFPE_L0 B
AD3 IFPE_L0_N
AD1 IFPE_L1 SERIAL
AC1 DIS@
IFPE_L1_N ROM_CS R1453
AC2 IFPE_L2 ROM_CS_N H6 1 2 10K_0402_5% +3VS_VGA
AC3 H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK (31)
AC4 H5 ROM_SI
IFPE_L3 ROM_SI ROM_SI (31)
AC5 H7 ROM_SO
IFPE_L3_N ROM_SO ROM_SO (31)
AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5 IFPF_L1_N GENERAL
AD4 IFPF_L2
AD5 L2 R1530 1 DIS@ 2 10K_0402_5%
IFPF_L2_N BUFRST_N
AG1 IFPF_L3
AF1 L3 R1531 1 DIS@ 2 10K_0402_5% +3VS_VGA
IFPF_L3_N CEC
J1 R1532 1 DIS@ 2 40.2K_0402_1%
MULTI_STRAP_REF0_GND
AG3 IFPC_AUX_I2CW_SCL
AG2 IFPC_AUX_I2CW_SDA_N
J2 STRAP0
STRAP0 STRAP0 (31)
J7 STRAP1
STRAP1 STRAP1 (31)
AK3 J6 STRAP2
IFPD_AUX_I2CX_SCL STRAP2 STRAP2 (31)
AK2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 (31)
J3 STRAP4
STRAP4 STRAP4 (31)
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N
C C
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-LVDS/HDMI/DP/THM
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
U1401E
+1.5VS_VGA +1.05VS_VGA
Under GPU(below 150mils) Near GPU Part 5 of 7
3.5A 2000mAUnder GPU(below 150mils) Near GPU
AA27 FBVDDQ_0 PEX_IOVDD_0 AG19
AA30 FBVDDQ_1 PEX_IOVDD_1 AG21
C1483
0.1U_0402_10V7K
C1484
0.1U_0402_10V7K
C1485
0.1U_0402_10V7K
C1486
0.1U_0402_10V7K
C1487
0.1U_0402_10V7K
C1488
0.1U_0402_10V7K
C1489
0.1U_0402_10V7K
C1490
0.1U_0402_10V7K
C1479
1U_0603_10V6K
C1480
1U_0603_10V6K
C1456
4.7U_0603_6.3V6K
C1457
4.7U_0603_6.3V6K
C1458
10U_0805_6.3V6M
C1459
10U_0805_6.3V6M
C1460
10U_0805_6.3V6M
C1461
10U_0805_6.3V6M
C1465
1U_0402_6.3V6K
C1466
1U_0402_6.3V6K
C1467
1U_0402_6.3V6K
C1468
1U_0402_6.3V6K
C1469
4.7U_0603_6.3V6K
C1470
4.7U_0603_6.3V6K
C1471
10U_0603_6.3V6M
C1472
10U_0603_6.3V6M
C1473
10U_0603_6.3V6M
C1474
10U_0603_6.3V6M
C1475
22U_0805_6.3V6M
C1476
22U_0805_6.3V6M
C1477
22U_0805_6.3V6M
C1478
22U_0805_6.3V6M
AB27 FBVDDQ_2 PEX_IOVDD_2 AG22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AB33 FBVDDQ_3 PEX_IOVDD_3 AG24 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AC27 FBVDDQ_4 PEX_IOVDD_4 AH21
AD27 FBVDDQ_5 PEX_IOVDD_5 AH25
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
AE27 FBVDDQ_6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AF27 FBVDDQ_7
AG27 FBVDDQ_8 PEX_IOVDDQ_0 AG13
B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15
A E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25 A
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15 For N13P-GT/N13E-GE +3VS_VGA
E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18 Under GPU(below 150mils)
H10 AH26
rise 1.5v system source voltage to 1.55-1.57V H11
FBVDDQ_15
FBVDDQ_16
PEX_IOVDDQ_7
PEX_IOVDDQ_8 AH27 +PEX_PLLHVDD R1459 1 @ 2 0_0402_5%
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
C1493
0.1U_0402_10V7K
C1494
4.7U_0603_6.3V6K
C1495
4.7U_0603_6.3V6K
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27
H14 AL27 1 1 1
POWER
FBVDDQ_19 PEX_IOVDDQ_11
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
+1.05VS_VGA
DIS@
DIS@
DIS@
H18 FBVDDQ_22 L1404 DIS@ 2 2 2
H19 FBVDDQ_23 120mA
H20 +PEX_PLLVDD 1 2
FBVDDQ_24 BLM18PG121SN1D_0603
H21 FBVDDQ_25 PEX_PLL_HVDD AH12
C1500
0.1U_0402_10V7K
C1501
1U_0603_10V6K
C1502
4.7U_0805_10V4Z
H22 FBVDDQ_26 120ohms @100MHz (ESR=0.18)
H23 FBVDDQ_27 1 1 1
H24 L1405
FBVDDQ_28
H8 FBVDDQ_29 PEX_SVDD_3V3 AG12
DIS@
DIS@
DIS@
H9 FBVDDQ_30 2 2 2
L27 FBVDDQ_31
M27 FBVDDQ_32
N27 AG26 +PEX_PLLVDD @
FBVDDQ_33 PEX_PLLVDD
P27 FBVDDQ_34 0_0603_5%
R27 FBVDDQ_35 Place near balls
T27 FBVDDQ_36
T30 FBVDDQ_37 VDD33_0 J8
T33 FBVDDQ_38 VDD33_1 K8
+3VS_VGA
V27 FBVDDQ_39 VDD33_2 L8 Place near balls Place near GPU
W27 M8 @
FBVDDQ_40 VDD33_3 +VDD33 R1461 1
W30 FBVDDQ_41 2 0_0603_5%
W33 DIS@
FBVDDQ_42
C1507
0.1U_0402_10V7K
C1506
0.1U_0402_10V7K
C1496
0.1U_0402_10V7K
C1497
0.1U_0402_10V7K
C1498
1U_0402_6.3V6K
C1499
4.7U_0603_6.3V6K
Y27 FBVDDQ_43
AH8 +IFPAB_PLLVDD R1462 1 DIS@ 2 10K_0402_5% 1 1 1 1 1 1
IFPAB_PLLVDD
IFPAB_RSET AJ8
+1.5VS_VGA 10_0402_5% 1 @ 2 R1463 FB_VDDQ_SENSE
B B
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
AG8 +IFPAB_IOVDD R1471 1 DIS@ 2 10K_0402_5%
IFPA_IOVDD 2 2 2 2 2 2
IFPB_IOVDD AG9
F1 FB_VDDQ_SENSE
10_0402_5% 1 @ 2 R1464 FB_VSS_SENSE
AF7 +IFPC_PLLVDD R1465 1 DIS@ 2 10K_0402_5%
IFPC_PLLVDD
F2 FB_GND_SENSE IFPC_RSET AF8
+1.5VS_VGA
AF6 +IFPC_IOVDD R1467 1 DIS@ 2 10K_0402_5%
R1468 1 DIS@ IFPC_IOVDD
2 40.2_0402_1% J27 FB_CAL_PD_VDDQ
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD R1469 1 DIS@ 2 10K_0402_5% +5VALW
R1470 1 DIS@ IFPD_PLLVDD
2 42.2_0402_1% H27 FB_CAL_PU_GND IFPD_RSET AN2
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD R1472 1 DIS@ 2 10K_0402_5%
IFPD_IOVDD
1
R1473 1 DIS@ 2 51.1_0402_1% H25 FB_CAL_TERM_GND R1545
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD R1474 1 DIS@ 2 10K_0402_5% 100K_0402_5%
IFPEF_PLVDD DIS@
IFPEF_RSET AD6
FB_CAL_xTERM_GND 51.1Ohm
2
Place near balls AC7 +IFPE_IOVDD R1466 1 DIS@ 2 10K_0402_5% DGPU_PWROK#
IFPE_IOVDD DGPU_PWROK# (51)
IFPF_IOVDD AC8
1
D
R1544 1 DIS@ 2 10K_0402_5% 2 Q1411
(18,51) DGPU_PWROK
N13P-PES-A1_FCBGA908 G 2N7002K_SOT23-3
S DIS@
1
DIS@
3
R1546
100K_0402_5%
@
2
C C
+3VS to +3VS_VGA
+1.5V to +1.5VS_VGA +5VALW +3VS +3VS_VGA
+1.5V +1.5VS_VGA J1401 @
+VSB J1402 @ 1 2
1 2
1 1 2 2
JUMP_43X79
C1513
C1512
C1627
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
JUMP_43X79
1 1 1
1
Q1404 DIS@ Q1405 DIS@
1
AO4430L_SO8 R1475 AO3413_SOT23-3

DIS@
DIS@
R1536 8 1 @ 100K_0402_5% C1511 DIS@

2 2 2
D
100K_0402_5% 7 2 DIS@ 3 1 1 2
DIS@ 6 3
1
5 10U_0603_6.3V6M
2
R1533
G
2
R1539 R1476 470_0603_5%
4
470_0603_5% DGPU_PWR_EN# 1 DIS@ 2 @

R1538 1 DIS@ 2 0_0402_5% @ 10K_0402_5%
1 2
1
R1477 1 @ 2 0_0402_5%
(9,41,42,46,48,50,51) SUSP#
1 2
1
R1542 1 @ 2 0_0402_5% D
(9,42,50,51) SUSP
C1515
0.1U_0402_10V7K
D R1478 1 @ 2 0_0402_5% 2 Q1406 D R1479 @
(17,22) DGPU_PWR_EN
C1516
0.1U_0603_25V7K
DGPU_PWROK# R1541 1 @ 2 0_0402_5% 2 Q1410 D R1540 @ DIS@ G 2N7002K_SOT23-3 1 2 1 2 DGPU_PWR_EN#

(51) DGPU_PWROK# DIS@ G 2N7002K_SOT23-3 1 2 1 2 DGPU_PWROK# S DIS@ Q1407 G 10K_0402_5%
C1521
0.1U_0402_10V7K
S DIS@ G 0_0402_5% 2N7002K_SOT23-3 S
3
1
DIS@
Q1408 S R1480 DIS@ @ 1
3
3
2
DIS@
R1537 2N7002K_SOT23-3 R1543 @ 100K_0402_5%

3
D
100K_0402_5% 2 @ SUSP D
1 2
@ 0_0402_5% @
2
2
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-POWER
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
U1401F
+VGA_CORE U1401G +VGA_CORE
Part 6 of 7
Place near balls A2 GND_0 GND_100 D2
A Part 7 of 7 V17 AA17 D31 A
VDD_56 GND_1 GND_101
AA12 VDD_0 VDD_57 V18 AA18 GND_2 GND_102 D33
C1636
47U_0805_4V6
AA14 VDD_1 VDD_58 V20 AA20 GND_3 GND_103 E10
AA16 VDD_2 VDD_59 V22 1 AA22 GND_4 GND_104 E22
AA19 VDD_3 VDD_60 W12 AB12 GND_5 GND_105 E25
DIS@
2
AB13 VDD_6 VDD_63 W19 AB19 GND_8 GND_108 F28
AB15 VDD_7 VDD_64 W21 AB2 GND_9 GND_109 F7
AB17 VDD_8 VDD_65 W23 AB21 GND_10 GND_110 G10
AB18 VDD_9 VDD_66 Y13 A33 GND_11 GND_111 G13
AB20 VDD_10 VDD_67 Y15 AB23 GND_12 GND_112 G16
AB22 VDD_11 VDD_68 Y17 AB28 GND_13 GND_113 G19
AC12 VDD_12 VDD_69 Y18 AB30 GND_14 GND_114 G2
AC19 VDD_15 AB7 GND_17 GND_117 G28
AC21 VDD_16 AC13 GND_18 GND_118 G3
AC23 VDD_17 XVDD_1 U1 AC15 GND_19 GND_119 G30
M12 VDD_18 XVDD_2 U2 AC17 GND_20 GND_120 G32
POWER
M16 VDD_20 XVDD_4 U4 AA13 GND_22 GND_122 G5

M21 VDD_22 XVDD_6 U6 AC22 GND_24 GND_124 K2
M23 VDD_23 XVDD_7 U7 AE2 GND_25 GND_125 K28
N13 VDD_24 XVDD_8 U8 AE28 GND_26 GND_126 K30
N15 VDD_25 AE30 GND_27 GND_127 K32
N17 VDD_26 AE32 GND_28 GND_128 K33
N18 VDD_27 XVDD_9 V1 AE33 GND_29 GND_129 K5
N20 VDD_28 XVDD_10 V2 AE5 GND_30 GND_130 K7
N22 VDD_29 XVDD_11 V3 AE7 GND_31 GND_131 M13
P12 VDD_30 XVDD_12 V4 AH10 GND_32 GND_132 M15
P14 VDD_31 XVDD_13 V5 AA15 GND_33 GND_133 M17
B
P19 VDD_33 XVDD_15 V7 AH16 GND_35 GND_135 M20 B
P23 VDD_35 AH2 GND_37 GND_137 N12
R13 VDD_36 AH22 GND_38 GND_138 N14
R15 VDD_37 XVDD_17 W2 AH24 GND_39 GND_139 N16
GND
T12 VDD_42 XVDD_22 W8 AH33 GND_44 GND_144 N28
T14 VDD_43 AH5 GND_45 GND_145 N30
T16 VDD_44 AH7 GND_46 GND_146 N32
T19 VDD_45 XVDD_23 Y1 AJ7 GND_47 GND_147 N33
T21 VDD_46 XVDD_24 Y2 AK10 GND_48 GND_148 N5
T23 VDD_47 XVDD_25 Y3 AK7 GND_49 GND_149 N7
U13 VDD_48 XVDD_26 Y4 AL12 GND_50 GND_150 P13
U17 VDD_50 XVDD_28 Y6 VDD33 AL15 GND_52 GND_152 P17
U22 VDD_53 tIFPx_IOVDD AL2 GND_55 GND_155 P22
V13 VDD_54 AL20 GND_56 GND_156 R12
V15 VDD_55 XVDD_31 AA1 IFPx_IOVDD AL21 GND_57 GND_157 R14
XVDD_32 AA2 AL23 GND_58 GND_158 R16
XVDD_35 AA5 tNVVDD AL28 GND_61 GND_161 R23
XVDD_36 AA6 NVVDD AL30 GND_62 GND_162 T13
XVDD_37 AA7 AL32 GND_63 GND_163 T15
XVDD_38 AA8 AL33 GND_64 GND_164 T17
tFBVDDQ AL5 GND_65 GND_165 T18
AM13 GND_66 GND_166 T2
FBVDDQ AM16 GND_67 GND_167 T20
N13P-PES-A1_FCBGA908 AM19 T22
GND_68 GND_168
AM22 GND_69 GND_169 AG11
C DIS@ tPEX_VDD AM25 GND_70 GND_170 T28 C
AN1 GND_71 GND_171 T32
PEX_VDD AN10 GND_72 GND_172 T5
AN13 GND_73 GND_173 T7
AN16 GND_74 GND_174 U12
tIFPy_IOVDD AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16
IFPy_IOVDD AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 W18
NV Recommended Power On Sequencing Order B34
B4
GND_89
GND_90
GND_189
GND_190 W20
W22
GND_91 GND_191
B7 GND_92 GND_192 W28
X=A and B C10 GND_93 GND_193 Y12
Y=C,D,E and F C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32
D D
DIS@

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-VGA
CORE, GND Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
FBA_D[0..63] FBC_D[0..63]
(27,28) FBA_D[0..63] (29,30) FBC_D[0..63]
(27,28) FBA_DQM[7..0] (29,30) FBC_DQM[7..0]
(27,28) FBA_DQS[7..0] FBA_MA[15..0] (27,28) (29,30) FBC_DQS[7..0] FBC_MA[15..0] (29,30)
(27,28) FBA_DQS#[7..0] FBA_BA[2..0] (27,28) (29,30) FBC_DQS#[7..0] FBC_BA[2..0] (29,30)
PU for X16 mode PU for X16 mode Mode D - Mirror Mode Mapping
U1401B U1401C
DATA Bus
Part 2 of 7 Part 3 of 7
A FBA_D0 L28 U30 FBA_CS0#_L FBC_D0 G9 D13 FBC_CS0#_L Address 0..31 32..63 A
FBA_D0 FBA_CMD0 FBA_CS0#_L (27) FBB_D0 FBB_CMD0 FBC_CS0#_L (29)
FBA_D1 M29 T31 FBC_D1 E9 E14
FBA_D2 FBA_D1 FBA_CMD1 FBA_ODT_L FBC_D2 FBB_D1 FBB_CMD1 FBC_ODT_L
L29 FBA_D2 FBA_CMD2 U29 FBA_ODT_L (27) G8 FBB_D2 FBB_CMD2 F14 FBC_ODT_L (29) FBx_CMD0 CS0#_L
FBA_D3 M28 R34 FBA_CKE_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D3 FBA_CMD3 FBA_CKE_L (27) FBB_D3 FBB_CMD3 FBC_CKE_L (29)
FBA_D4 N31 R33 FBA_MA14 FBC_D4 F11 B12 FBC_MA14 FBx_CMD1
FBA_D5 FBA_D4 FBA_CMD4 FBA_RST# FBC_D5 FBB_D4 FBB_CMD4 FBC_RST#
P29 FBA_D5 FBA_CMD5 U32 FBA_RST# (27,28) G11 FBB_D5 FBB_CMD5 C14 FBC_RST# (29,30)
FBA_D6 R29 U33 FBA_MA9 FBC_D6 F12 B14 FBC_MA9 FBx_CMD2 ODT_L
FBA_D7 FBA_D6 FBA_CMD6 FBA_MA7 FBC_D7 FBB_D6 FBB_CMD6 FBC_MA7
P28 FBA_D7 FBA_CMD7 U28 G12 FBB_D7 FBB_CMD7 G15
FBA_D8 J28 V28 FBA_MA2 FBC_D8 G6 F15 FBC_MA2 FBx_CMD3 CKE_L
H29 FBA_D9 FBA_CMD9 V29 F5 FBB_D9 FBB_CMD9 E15
FBA_D10 J29 V30 FBA_MA4 FBC_D10 E6 D15 FBC_MA4 FBx_CMD4 A14 A14
H28 FBA_D11 FBA_CMD11 U34 F6 FBB_D11 FBB_CMD11 A14
FBA_D12 G29 U31 FBA_BA0 FBC_D12 F4 D14 FBC_BA0 FBx_CMD5 RST RST
FBA_D13 FBA_D12 FBA_CMD12 FBA_WE# FBC_D13 FBB_D12 FBB_CMD12 FBC_WE#
E31 FBA_D13 FBA_CMD13 V34 FBA_WE# (27,28) G4 FBB_D13 FBB_CMD13 A15 FBC_WE# (29,30)
FBA_D14 E32 V33 FBA_MA15 FBC_D14 E2 B15 FBC_MA15 FBx_CMD6 A9 A9
FBA_D15 FBA_D14 FBA_CMD14 FBA_CAS# FBC_D15 FBB_D14 FBB_CMD14 FBC_CAS#
F30 FBA_D15 FBA_CMD15 Y32 FBA_CAS# (27,28) F3 FBB_D15 FBB_CMD15 C17 FBC_CAS# (29,30)
FBA_D16 C34 AA31 FBA_CS0#_H FBC_D16 C2 D18 FBC_CS0#_H FBx_CMD7 A7 A7
FBA_D16 FBA_CMD16 FBA_CS0#_H (28) FBB_D16 FBB_CMD16 FBC_CS0#_H (30)
FBA_D17 D32 AA29 FBC_D17 D4 E18
FBA_D18 FBA_D17 FBA_CMD17 FBA_ODT_H FBC_D18 FBB_D17 FBB_CMD17 FBC_ODT_H
B33 FBA_D18 FBA_CMD18 AA28 FBA_ODT_H (28) D3 FBB_D18 FBB_CMD18 F18 FBC_ODT_H (30) FBx_CMD8 A2 A2
FBA_D19 C33 AC34 FBA_CKE_H FBC_D19 C1 A20 FBC_CKE_H
FBA_D19 FBA_CMD19 FBA_CKE_H (28) FBB_D19 FBB_CMD19 FBC_CKE_H (30)
FBA_D20 F33 AC33 FBA_MA13 FBC_D20 B3 B20 FBC_MA13 FBx_CMD9 A0 A0
F32 FBA_D21 FBA_CMD21 AA32 C4 FBB_D21 FBB_CMD21 C18
FBA_D22 H33 AA33 FBA_MA6 FBC_D22 B5 B18 FBC_MA6 FBx_CMD10 A4 A4
H32 FBA_D23 FBA_CMD23 Y28 C5 FBB_D23 FBB_CMD23 G18
FBA_D24 FBA_MA5 FBC_D24 FBC_MA5 FBx_CMD11 A1 A1
MEMORY INTERFACE
P34 FBA_D24 FBA_CMD24 Y29 A11 FBB_D24 FBB_CMD24 G17
FBA_D25 P32 W31 FBA_MA3 FBC_D25 C11 F17 FBC_MA3
FBA_D25 FBA_CMD25 FBB_D25 FBB_CMD25
MEMORY INTERFACE B
FBA_D26 P31 Y30 FBA_BA2 FBC_D26 D11 D16 FBC_BA2 FBx_CMD12 BA0 BA0
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA1 FBC_D27 FBB_D26 FBB_CMD26 FBC_BA1
P33 FBA_D27 FBA_CMD27 AA34 B11 FBB_D27 FBB_CMD27 A18
FBA_D28 L31 Y31 FBA_MA12 FBC_D28 D8 D17 FBC_MA12 FBx_CMD13 WE# WE#
L34 FBA_D29 FBA_CMD29 Y34 A8 FBB_D29 FBB_CMD29 A17
FBA_D30 L32 Y33 FBA_RAS# FBC_D30 C8 B17 FBC_RAS# FBx_CMD14 A15 A15
FBA_D30 FBA_CMD30 FBA_RAS# (27,28) FBB_D30 FBB_CMD30 FBC_RAS# (29,30)
FBA_D31 L33 V31 FBC_D31 B8 E17
FBA_D32 FBA_D31 FBA_CMD31 FBC_D32 FBB_D31 FBB_CMD31
AG28 FBA_D32 F24 FBB_D32 FBx_CMD15 CAS# CAS#
FBA_D33 AF29 FBC_D33 G23
FBA_D34 FBA_D33 FBC_D34 FBB_D33
B
AG29 FBA_D34 E24 FBB_D34 FBx_CMD16 CS0#_H B
FBA_D35 AF28 R32 FBC_D35 G24 C12
FBA_D36 FBA_D35 FBA_CMD_RFU0 FBC_D36 FBB_D35 FBB_CMD_RFU0
AD30 FBA_D36 FBA_CMD_RFU1 AC32 D21 FBB_D36 FBB_CMD_RFU1 C20 FBx_CMD17
FBA_D37 AD29 FBC_D37 E21
AC29 FBA_D38 G21 FBB_D38 FBx_CMD18 ODT_H
FBA_D39 AD28 FBC_D39 F21
FBA_D39 FBB_D39
A
FBA_D40 AJ29 R28 R1509 1 @ 2 60.4_0402_1% +1.5VS_VGA FBC_D40 G27 G14 R1510 1 @ 2 60.4_0402_1% +1.5VS_VGA FBx_CMD19 CKE_H
FBA_D41 FBA_D40 FBA_DEBUG0 R1511 1 @ FBB_D40 FBB_DEBUG0
AK29 FBA_D41 FBA_DEBUG1 AC28 2 60.4_0402_1% FBC_D41 D27 FBB_D41 FBB_DEBUG1 G20 R1512 1 @ 2 60.4_0402_1%
FBA_D42 AJ30 FBC_D42 G26 FBx_CMD20 A13 A13
AK28 FBA_D43 E27 FBB_D43
FBA_D44 AM29 FBC_D44 E29 FBx_CMD21 A8 A8
FBA_D45 FBA_D44 FBA_CLK0 FBC_D45 FBB_D44 FBC_CLK0
AM31 FBA_D45 FBA_CLK0 R30 FBA_CLK0 (27) F29 FBB_D45 FBB_CLK0 D12 FBC_CLK0 (29)
FBA_D46 AN29 R31 FBA_CLK0# FBC_D46 E30 E12 FBC_CLK0# FBx_CMD22 A6 A6
FBA_D46 FBA_CLK0_N FBA_CLK0# (27) FBB_D46 FBB_CLK0_N FBC_CLK0# (29)
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D47 D30 E20 FBC_CLK1
FBA_D47 FBA_CLK1 FBA_CLK1 (28) FBB_D47 FBB_CLK1 FBC_CLK1 (30)
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D48 A32 F20 FBC_CLK1# FBx_CMD23 A11 A11
FBA_D48 FBA_CLK1_N FBA_CLK1# (28) FBB_D48 FBB_CLK1_N FBC_CLK1# (30)
FBA_D49 AN32 FBC_D49 C31
AP30 FBA_D50 C32 FBB_D50 FBx_CMD24 A5 A5
FBA_D51 AP32 FBC_D51 B32
AM33 FBA_D52 FBA_WCK01 K31 D29 FBB_D52 FBB_WCK01 F8 FBx_CMD25 A3 A3
FBA_D53 AL31 L30 FBC_D53 A29 E8
FBA_D54 FBA_D53 FBA_WCK01_N FBC_D54 FBB_D53 FBB_WCK01_N
AK33 FBA_D54 FBA_WCK23 H34 C29 FBB_D54 FBB_WCK23 A5 FBx_CMD26 BA2 BA2
FBA_D55 AK32 J34 FBC_D55 B29 A6
AD34 FBA_D56 FBA_WCK45 AG30 B21 FBB_D56 FBB_WCK45 D24 FBx_CMD27 BA1 BA1
FBA_D57 AD32 AG31 FBC_D57 C23 D25
AC30 FBA_D58 FBA_WCK67 AJ34 A21 FBB_D58 FBB_WCK67 B27 FBx_CMD28 A12 A12
FBA_D59 AD33 AK34 FBC_D59 C21 C27
AF31 FBA_D60 B24 FBB_D60 FBx_CMD29 A10 A10
FBA_D61 AG34 FBC_D61 C24
AG32 FBA_D62 B26 FBB_D62 FBx_CMD30 RAS# RAS#
FBA_D63 AG33 J30 FBC_D63 C26 D6
FBA_D63 FBA_WCKB01 FBB_D63 FBB_WCKB01
FBA_WCKB01_N J31 FBB_WCKB01_N D7
FBA_DQM0 P30 J32 FBC_DQM0 E11 C6
FBA_DQM1 FBA_DQM0 FBA_WCKB23 FBC_DQM1 FBB_DQM0 FBB_WCKB23
F31 FBA_DQM1 FBA_WCKB23_N J33 E3 FBB_DQM1 FBB_WCKB23_N B6
FBA_DQM2 F34 AH31 FBC_DQM2 A3 F26
M32 FBA_DQM3 FBA_WCKB45_N AJ31 C9 FBB_DQM3 FBB_WCKB45_N E26
C FBA_DQM4 AD31 AJ32 FBC_DQM4 F23 A26 C
AL29 FBA_DQM5 FBA_WCKB67_N AJ33 F27 FBB_DQM5 FBB_WCKB67_N A27
FBA_DQM6 AM32 T1405 FBC_DQM6 C30
FBA_DQM7 FBA_DQM6 FBC_DQM7 FBB_DQM6
AF34 FBA_DQM7 A24 FBB_DQM7
FBA_DQS0 M31 E1 R1513 1 DIS@ 2 10K_0402_5% FBC_DQS0 D10
FBA_DQS1 FBA_DQS_WP0 FB_CLAMP FBC_DQS1 FBB_DQS_WP0
G31 FBA_DQS_WP1 D5 FBB_DQS_WP1
FBA_DQS2 E33 +FB_PLLAVDD FBC_DQS2 C3
FBA_DQS3 FBA_DQS_WP2 FBC_DQS3 FBB_DQS_WP2
M33 FBA_DQS_WP3 B9 FBB_DQS_WP3
FBA_DQS4 AE31 K27 C1622 1 2 DIS@ 0.1U_0402_10V7K FBC_DQS4 E23 H17 +FB_PLLAVDD
FBA_DQS5 FBA_DQS_WP4 FB_DLL_AVDD FBC_DQS5 FBB_DQS_WP4 FBB_PLL_AVDD
AK30 FBA_DQS_WP5 E28 FBB_DQS_WP5
C1623
0.1U_0402_10V7K
FBA_DQS6 AN33 Place close to ball FBC_DQS6 B30
FBA_DQS7 FBA_DQS_WP6 FBC_DQS7 FBB_DQS_WP6
AF33 FBA_DQS_WP7 A23 FBB_DQS_WP7 1
FBA_PLL_AVDD U27 +FB_PLLAVDD
FBA_DQS#0 M30 FBC_DQS#0 D9
FBA_DQS_RN0 FBB_DQS_RN0
C1624
C1625
C1626
0.1U_0402_10V7K
1U_0402_6.3V6K
22U_0805_6.3V6M
DIS@
FBA_DQS#1 H30 FBC_DQS#1 E4
FBA_DQS#2 FBA_DQS_RN1 FBC_DQS#2 FBB_DQS_RN1 2
E34 FBA_DQS_RN2 1 1 1 B2 FBB_DQS_RN2
FBA_DQS#3 M34 H26 FBC_DQS#3 A9
FBA_DQS#4 FBA_DQS_RN3 FB_VREF FBC_DQS#4 FBB_DQS_RN3
AF30 FBA_DQS_RN4 D22 FBB_DQS_RN4
DIS@
DIS@
DIS@
FBA_DQS#5 AK31 FBC_DQS#5 D28

FBA_DQS#6 FBA_DQS_RN5 2 2 2 FBC_DQS#6 FBB_DQS_RN5
AM34 FBA_DQS_RN6 A30 FBB_DQS_RN6
Place close to ball
FBA_DQS#7 AF32 FBC_DQS#7 B23
FBA_DQS_RN7 FBB_DQS_RN7
Place close to ball Place close to BGA

N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908
DIS@ DIS@
30ohms (ESR=0.01) Bead

D P/N;SM010007W00 D
+1.05VS_VGA +FB_PLLAVDD
L1414 DIS@
600mA
1 2 +FB_PLLAVDD
FBMA-L11-160808300LMA25T_2P
Place close to BGA Security Classification Compal Secret Data

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-MEM
Interface Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Lower 32 bits FBA_MA[15..0] (26,28)
FBA_BA[2..0] (26,28)
FBA_D[0..63] (26,28)
FBA_DQM[7..0] (26,28)
FBA_DQS[7..0] (26,28)
A A
FBA_DQS#[7..0] (26,28)
U1406 U1407
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19

VREFCA DQL0 FBA_D1 VREFCA DQL0 FBA_D20
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 FBA_D7 F2 FBA_D17
DQL2 DQL2
1
FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)

R1481 FBA_MA1 A0 DQL3 FBA_D6 FBA_MA1 A0 DQL3 FBA_D16
P7 A1 DQL4 H3 Group0 (IN3) P7 A1 DQL4 H3
1.1K_0402_1% FBA_MA2 P3 H8 FBA_D3 FBA_MA2 P3 H8 FBA_D23
DIS@ FBA_MA3 A2 DQL5 FBA_D5 FBA_MA3 A2 DQL5 FBA_D18
N2 G2 N2 G2
FBA_MA4 P8
A3 DQL6
H7 FBA_D2 FBA_MA4 P8
A3 DQL6
H7 FBA_D22 Mode D - Mirror Mode Mapping
2
+FBA_VREF0 FBA_MA5 A4 DQL7 FBA_MA5 A4 DQL7

P2 A5 P2 A5
FBA_MA6 R8 FBA_MA6 R8
A6 A6
C1522
0.01U_0402_16V7K
FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10 DATA Bus

A7 DQU0 A7 DQU0
1
1 FBA_MA8 T8 C3 FBA_D25 FBA_MA8 T8 C3 FBA_D15

R1482 FBA_MA9 A8 DQU1 FBA_D28 FBA_MA9 A8 DQU1 FBA_D8
R3 A9 DQU2 C8 R3 A9 DQU2 C8 Address 0..31 32..63
1.1K_0402_1% FBA_MA10 L7 C2 FBA_D26 FBA_MA10 L7 C2 FBA_D13 Group1 (TOP)
A10/AP DQU3 A10/AP DQU3
DIS@
DIS@ FBA_MA11 R7 A7 FBA_D31 Group3 (BOT) FBA_MA11 R7 A7 FBA_D9 FBx_CMD0 CS0#_L

2 FBA_MA12 A11 DQU4 FBA_D24 FBA_MA12 A11 DQU4 FBA_D12
N7 A2 N7 A2
2
FBA_MA13 A12 DQU5 FBA_D30 FBA_MA13 A12 DQU5 FBA_D11

T3 A13 DQU6 B8 T3 A13 DQU6 B8 FBx_CMD1
FBA_MA14 T7 A3 FBA_D27 FBA_MA14 T7 A3 FBA_D14
FBA_MA15 A14 DQU7 FBA_MA15 A14 DQU7
M7 A15/BA3 +1.5VS_VGA
M7 A15/BA3 +1.5VS_VGA
FBx_CMD2 ODT_L
FBx_CMD3 CKE_L
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD4 A14 A14
FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD5 RST RST
VDD K8 VDD K8
B VDD N1 VDD N1 FBx_CMD6 A9 A9 B
FBA_CLK0 FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
(26) FBA_CLK0 CK VDD CK VDD
FBA_CLK0# K7 R1 FBA_CLK0# K7 R1 FBx_CMD7 A7 A7
(26) FBA_CLK0# CK VDD CK VDD
FBA_CKE_L K9 R9 FBA_CKE_L K9 R9
(26) FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1
FBx_CMD8 A2 A2
R1483
160_0402_1% FBA_ODT_L K1 A1 FBA_ODT_L K1 A1 FBx_CMD9 A0 A0
(26) FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
DIS@ FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8
(26) FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD10 A4 A4
(26,28) FBA_RAS#
2
FBA_CAS# RAS VDDQ FBA_CAS# RAS VDDQ FBA_ODT_L

(26,28) FBA_CAS# K3 CAS VDDQ C9 K3 CAS VDDQ C9
FBA_CLK0# FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD11 A1 A1
(26,28) FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 FBA_CKE_L FBx_CMD12 BA0 BA0
FBA_DQS0 VDDQ FBA_DQS2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9 FBx_CMD13 WE# WE#
DQSU VDDQ DQSU VDDQ
1
R1484 R1485 FBx_CMD14 A15 A15
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5%
FBA_DQM3 DML VSS FBA_DQM1 DML VSS DIS@ DIS@
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD15 CAS# CAS#
E1 E1
2
VSS VSS
VSS G8 VSS G8 FBx_CMD16 CS0#_H
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2
FBA_DQS#3 DQSL VSS FBA_DQS#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 FBx_CMD17
VSS M1 VSS M1
VSS M9 VSS M9 FBx_CMD18 ODT_H
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD19 CKE_H
(26,28) FBA_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD20 A13 A13
FBx_CMD21 A8 A8
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R1486 R1487 L1 B9 R1488 L1 B9 FBx_CMD22 A6 A6
10K_0402_5% 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
DIS@ DIS@ L9 D8 DIS@ L9 D8 FBx_CMD23 A11 A11
NCZQ1 VSSQ NCZQ1 VSSQ
C E2 E2 C
2
2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD24 A5 A5
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 FBx_CMD25 A3 A3
VSSQ G9 VSSQ G9
FBx_CMD26 BA2 BA2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD27 BA1 BA1
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
DIS@ DIS@ FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
U1406 SIDE U1407 SIDE
C1541
C1526
C1527
C1528
C1529
C1537
C1531
C1532
C1533
C1534
C1530
C1524
C1525
C1535
C1536
C1538
C1539
C1540
C1545
C1546
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-VRAM
A Lower Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Memory Partition A - Upper 32 bits
A A
U1409 U1408
+1.5VS_VGA
FBA_D[0..63] (26,27)
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
VREFCA DQL0 FBA_D34 VREFCA DQL0 FBA_D58
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_MA[15..0] (26,27)
1
F2 FBA_D37 F2 FBA_D60
R1489 FBA_MA0 DQL2 FBA_D35 FBA_MA0 DQL2 FBA_D59
N3 A0 DQL3 F8 N3 A0 DQL3 F8 FBA_BA[2..0] (26,27)
1.1K_0402_1% FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3)
DIS@ FBA_MA2 A1 DQL4 FBA_D32 FBA_MA2 A1 DQL4 FBA_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8 FBA_DQM[7..0] (26,27)
FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2
+FBA_VREF1 FBA_MA4 A3 DQL6 FBA_D33 FBA_MA4 A3 DQL6 FBA_D57

P8 A4 DQL7 H7 P8 A4 DQL7 H7 FBA_DQS[7..0] (26,27)
FBA_MA5 P2 FBA_MA5 P2
A5 A5
C1547
0.01U_0402_16V7K
FBA_MA6 R8 FBA_MA6 R8
A6 A6 FBA_DQS#[7..0] (26,27)
1
1 FBA_MA7 R2 D7 FBA_D45 FBA_MA7 R2 D7 FBA_D55

R1490 FBA_MA8 A7 DQU0 FBA_D42 FBA_MA8 A7 DQU0 FBA_D51
T8 A8 DQU1 C3 T8 A8 DQU1 C3
1.1K_0402_1% FBA_MA9 R3 C8 FBA_D46 FBA_MA9 R3 C8 FBA_D54
A9 DQU2 A9 DQU2
DIS@
DIS@ FBA_MA10 L7 C2 FBA_D41 FBA_MA10 L7 C2 FBA_D49

2 FBA_MA11 A10/AP DQU3 FBA_D47 FBA_MA11 A10/AP DQU3 FBA_D52
R7 A7 Group5 (TOP) R7 A7 Group6 (BOT)
2
FBA_MA12 A11 DQU4 FBA_D43 FBA_MA12 A11 DQU4 FBA_D50

N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBA_MA13 T3 B8 FBA_D44 FBA_MA13 T3 B8 FBA_D53
FBA_MA14 T7
A13
A14
DQU6
DQU7 A3 FBA_D40 FBA_MA14 T7
A13
A14
DQU6
DQU7 A3 FBA_D48 Mode D - Mirror Mode Mapping
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
DATA Bus
FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 D9 N8 D9 Address 0..31 32..63
B
FBA_CLK1 FBA_BA2 BA1 VDD FBA_BA2 BA1 VDD B
M3 BA2 VDD G7 M3 BA2 VDD G7
VDD K2 VDD K2 FBx_CMD0 CS0#_L
VDD K8 VDD K8
1
VDD N1 VDD N1 FBx_CMD1

R1491 FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
(26) FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1 FBx_CMD2 ODT_L
(26) FBA_CLK1# CK VDD CK VDD
DIS@ FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
(26) FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD3 CKE_L
2
FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1 FBx_CMD4 A14 A14

(26) FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
(26) FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1 FBx_CMD5 RST RST
(26,27) FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
(26,27) FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2 FBx_CMD6 A9 A9
(26,27) FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 FBx_CMD7 A7 A7
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD8 A2 A2
FBx_CMD9 A0 A0
FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD10 A4 A4
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD11 A1 A1
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 DQSL VSS FBA_DQS#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 FBx_CMD12 BA0 BA0
VSS M1 VSS M1
FBA_CKE_H M9 M9 FBx_CMD13 WE# WE#
VSS VSS
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9 FBx_CMD14 A15 A15
(26,27) FBA_RST# RESET VSS RESET VSS
FBA_ODT_H T1 T1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD15 CAS# CAS#
FBx_CMD16 CS0#_H
1
1
C J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 C
R1492 R1493 R1494 L1 B9 R1495 L1 B9 FBx_CMD17
10K_0402_5% 10K_0402_5% 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
DIS@ DIS@ DIS@ L9 D8 DIS@ L9 D8 FBx_CMD18 ODT_H
E2 E2
2
2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD19 CKE_H
VSSQ F9 VSSQ F9
VSSQ G9 VSSQ G9
FBx_CMD21 A8 A8
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD22 A6 A6
DIS@ DIS@ FBx_CMD23 A11 A11
FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
FBx_CMD26 BA2 BA2
FBx_CMD27 BA1 BA1
+1.5VS_VGA +1.5VS_VGA U1408 SIDE
U1409 SIDE FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
C1549
C1555
C1551
C1552
C1554
C1553
C1556
C1557
C1558
C1559
C1560
C1561
C1562
C1567
C1566
C1565
C1568
C1569
C1570
C1571
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBx_CMD30 RAS# RAS#
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D

Title
A Upper Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Memory Partition C - Lower 32 bits

FBC_D[0..63] (26,30)
FBC_MA[15..0] (26,30)
FBC_BA[2..0] (26,30)
FBC_DQM[7..0] (26,30)
FBC_DQS[7..0] (26,30)
A A
FBC_DQS#[7..0] (26,30)
+1.5VS_VGA
U1410 U1411
1
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16

R1496 VREFCA DQL0 FBC_D3 VREFCA DQL0 FBC_D21
1.1K_0402_1% F2 FBC_D7 F2 FBC_D18
N13P@ FBC_MA0 DQL2 FBC_D0 FBC_MA0 DQL2 FBC_D17
N3 A0 DQL3 F8 Group0 (IN3) N3 A0 DQL3 F8
FBC_MA1 P7 H3 FBC_D5 FBC_MA1 P7 H3 FBC_D20 Group2 (IN1)
2
FBC_MA2 A1 DQL4 FBC_D1 FBC_MA2 A1 DQL4 FBC_D23

P3 H8 P3 H8
+FBB_VREF0 FBC_MA3 N2
A2
A3
DQL5
DQL6 G2 FBC_D6 FBC_MA3 N2
A2
A3
DQL5
DQL6 G2 FBC_D19 Mode D - Mirror Mode Mapping
FBC_MA4 P8 H7 FBC_D2 FBC_MA4 P8 H7 FBC_D22
A4 DQL7 A4 DQL7
C1572
0.01U_0402_16V7K
FBC_MA5 P2 FBC_MA5 P2
A5 A5
1
1 FBC_MA6 R8 FBC_MA6 R8 DATA Bus

R1497 FBC_MA7 A6 FBC_D28 FBC_MA7 A6 FBC_D8
R2 A7 DQU0 D7 R2 A7 DQU0 D7
1.1K_0402_1% FBC_MA8 T8 C3 FBC_D27 FBC_MA8 T8 C3 FBC_D15 Address 0..31 32..63
A8 DQU1 A8 DQU1
N13P@
N13P@ FBC_MA9 R3 C8 FBC_D31 FBC_MA9 R3 C8 FBC_D11

2 FBC_MA10 A9 DQU2 FBC_D25 FBC_MA10 A9 DQU2 FBC_D12
L7 C2 L7 C2 FBx_CMD0 CS0#_L
2
FBC_MA11 A10/AP DQU3 FBC_D29 FBC_MA11 A10/AP DQU3 FBC_D9

R7 A11 DQU4 A7 Group3 (BOT) R7 A11 DQU4 A7 Group1 (TOP)
FBC_MA12 N7 A2 FBC_D24 FBC_MA12 N7 A2 FBC_D13 FBx_CMD1
FBC_MA13 A12 DQU5 FBC_D30 FBC_MA13 A12 DQU5 FBC_D10
T3 A13 DQU6 B8 T3 A13 DQU6 B8
FBC_MA14 T7 A3 FBC_D26 FBC_MA14 T7 A3 FBC_D14 FBx_CMD2 ODT_L
FBC_MA15 A14 DQU7 FBC_MA15 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+1.5VS_VGA +1.5VS_VGA FBx_CMD3 CKE_L
FBC_BA0 M2 B2 FBC_BA0 M2 B2 FBx_CMD4 A14 A14
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
B
N8 BA1 VDD D9 N8 BA1 VDD D9 B
FBC_BA2 M3 G7 FBC_BA2 M3 G7 FBx_CMD5 RST RST
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 FBx_CMD6 A9 A9
FBC_CLK0 FBC_CLK0
310mA VDD N1
FBC_CLK0 VDD N1
(26) FBC_CLK0 J7 CK VDD N9 J7 CK VDD N9 FBx_CMD7 A7 A7
FBC_CLK0# K7 R1 FBC_CLK0# K7 R1
(26) FBC_CLK0# CK VDD CK VDD
FBC_CKE_L K9 R9 FBC_CKE_L K9 R9 FBx_CMD8 A2 A2
(26) FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1
R1498 FBx_CMD9 A0 A0
160_0402_1% FBC_ODT_L K1 A1 FBC_ODT_L K1 A1
(26) FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
N13P@ FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8 FBx_CMD10 A4 A4
(26) FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1
(26,30) FBC_RAS#
2
FBC_CAS# RAS VDDQ FBC_CAS# RAS VDDQ

(26,30) FBC_CAS# K3 CAS VDDQ C9 K3 CAS VDDQ C9 FBx_CMD11 A1 A1
FBC_CLK0# FBC_WE# L3 D2 FBC_WE# L3 D2
(26,30) FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 FBx_CMD12 BA0 BA0
VDDQ F1 VDDQ F1
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2 FBx_CMD13 WE# WE#
FBC_DQS3 DQSL VDDQ FBC_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
FBx_CMD14 A15 A15
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9 FBx_CMD15 CAS# CAS#
FBC_DQM3 DML VSS FBC_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 FBx_CMD16 CS0#_H
VSS G8 VSS G8
FBC_DQS#0 G3 J2 FBC_DQS#2 G3 J2 FBx_CMD17
FBC_DQS#3 DQSL VSS FBC_DQS#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 FBx_CMD18 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 FBx_CMD19 CKE_H
FBC_RST# T2 P9 FBC_RST# T2 P9 FBC_ODT_L
(26,30) FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1 FBx_CMD20 A13 A13
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
FBC_CKE_L FBx_CMD21 A8 A8
1
1
C J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 FBx_CMD22 A6 A6 C
1
R1535 R1534 L1 B9 R1499 L1 B9

NC/CS1 VSSQ NC/CS1 VSSQ
1
10K_0402_5% 243_0402_1% J9 D1 243_0402_1% J9 D1 FBx_CMD23 A11 A11
N13P@ N13P@ NC/CE1 VSSQ N13P@ NC/CE1 VSSQ R1500 R1501
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 10K_0402_5% 10K_0402_5% FBx_CMD24 A5 A5
2
2
VSSQ VSSQ N13P@ N13P@
E8 E8
2
VSSQ VSSQ
F9 F9 FBx_CMD25 A3 A3
2
VSSQ VSSQ
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 FBx_CMD28 A12 A12
N13P@ N13P@
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
C1573
C1574
C1579
C1580
C1575
C1576
C1577
C1581
C1582
C1583
C1587
C1592
C1585
C1586
C1591
C1588
C1593
C1594
C1595
C1596
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D

Title
C Lower Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Memory Partition C - Upper 32 bits

FBC_D[0..63] (26,29)
FBC_MA[15..0] (26,29)
FBC_BA[2..0] (26,29)
FBC_DQM[7..0] (26,29)
FBC_DQS[7..0] (26,29)
A A
FBC_DQS#[7..0] (26,29)
U1413 U1412
+FBB_VREF1 M8 E3 FBC_D39 +FBB_VREF1 M8 E3 FBC_D60

+1.5VS_VGA VREFCA DQL0 FBC_D33 VREFCA DQL0 FBC_D57
F2 FBC_D38 F2 FBC_D63
FBC_MA0 DQL2 FBC_D32 FBC_MA0 DQL2 FBC_D58
N3 A0 DQL3 F8 N3 A0 DQL3 F8
1
FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) FBC_MA1 P7 H3 FBC_D61 Group7 (IN3)

R1502 FBC_MA2 A1 DQL4 FBC_D35 FBC_MA2 A1 DQL4 FBC_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% FBC_MA3 N2 G2 FBC_D37 FBC_MA3 N2 G2 FBC_D62
N13P@ FBC_MA4 A3 DQL6 FBC_D34 FBC_MA4 A3 DQL6 FBC_D59
P8 A4 DQL7 H7 P8 A4 DQL7 H7
FBC_MA5 P2 FBC_MA5 P2
2
+FBB_VREF1 FBC_MA6 A5 FBC_MA6 A5

R8 A6 R8 A6
FBC_MA7 R2 D7 FBC_D47 FBC_MA7 R2 D7 FBC_D54
A7 DQU0 A7 DQU0
C1597
0.01U_0402_16V7K
FBC_MA8 T8 C3 FBC_D43 FBC_MA8 T8 C3 FBC_D51

A8 DQU1 A8 DQU1
1
1 FBC_MA9 R3 C8 FBC_D46 FBC_MA9 R3 C8 FBC_D55

R1503 FBC_MA10 A9 DQU2 FBC_D42 FBC_MA10 A9 DQU2 FBC_D49
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
1.1K_0402_1% FBC_MA11 R7 A7 FBC_D40 Group5 (TOP) FBC_MA11 R7 A7 FBC_D52 Group6 (BOT)
A11 DQU4 A11 DQU4
N13P@
N13P@ FBC_MA12 N7 A2 FBC_D45 FBC_MA12 N7 A2 FBC_D50

2 FBC_MA13 T3
A12 DQU5
B8 FBC_D44 FBC_MA13 T3
A12 DQU5
B8 FBC_D53 Mode D - Mirror Mode Mapping
2
FBC_MA14 A13 DQU6 FBC_D41 FBC_MA14 A13 DQU6 FBC_D48

T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7 DATA Bus
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
Address 0..31 32..63
FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 FBx_CMD0 CS0#_L
FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 FBx_CMD1
B VDD K8 VDD K8 B
VDD N1 VDD N1 FBx_CMD2 ODT_L
FBC_CLK1 J7 N9 FBC_CLK1 J7 N9
(26) FBC_CLK1 CK VDD CK VDD
FBC_CLK1 FBC_CLK1# K7 R1 FBC_CLK1# K7 R1 FBx_CMD3 CKE_L
(26) FBC_CLK1# CK VDD CK VDD
FBC_CKE_H K9 R9 FBC_CKE_H K9 R9
(26) FBC_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
FBx_CMD4 A14 A14
1
R1504 FBC_ODT_H K1 A1 FBC_ODT_H K1 A1 FBx_CMD5 RST RST

(26) FBC_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
160_0402_1% FBC_CS0#_H L2 A8 FBC_CS0#_H L2 A8
(26) FBC_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
N13P@ FBC_RAS# J3 C1 FBC_RAS# J3 C1 FBx_CMD6 A9 A9
(26,29) FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
(26,29) FBC_CAS#
2
FBC_WE# CAS VDDQ FBC_WE# CAS VDDQ

(26,29) FBC_WE# L3 WE VDDQ D2 L3 WE VDDQ D2 FBx_CMD7 A7 A7
FBC_CLK1# E9 E9
VDDQ VDDQ
VDDQ F1 VDDQ F1 FBx_CMD8 A2 A2
FBC_DQS4 F3 H2 FBC_DQS7 F3 H2
FBC_DQS5 DQSL VDDQ FBC_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 FBx_CMD9 A0 A0
FBx_CMD10 A4 A4
FBC_DQM4 E7 A9 FBC_DQM7 E7 A9
FBC_DQM5 DML VSS FBC_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 FBx_CMD11 A1 A1
VSS E1 VSS E1
VSS G8 VSS G8 FBx_CMD12 BA0 BA0
FBC_DQS#4 G3 J2 FBC_DQS#7 G3 J2
FBC_DQS#5 DQSL VSS FBC_DQS#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 FBx_CMD13 WE# WE#
VSS M1 VSS M1
FBC_ODT_H M9 M9 FBx_CMD14 A15 A15
VSS VSS
VSS P1 VSS P1
FBC_RST# T2 P9 FBC_RST# T2 P9 FBx_CMD15 CAS# CAS#
(26,29) FBC_RST# RESET VSS RESET VSS
FBC_CKE_H T1 T1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 FBx_CMD16 CS0#_H
1
FBx_CMD17
1
1
R1505 R1506 J1 B1 J1 B1
10K_0402_5% 10K_0402_5% R1507 NC/ODT1 VSSQ R1508 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 FBx_CMD18 ODT_H
N13P@ N13P@ 243_0402_1% J9 D1 243_0402_1% J9 D1
N13P@ NC/CE1 VSSQ N13P@ NC/CE1 VSSQ
C L9 D8 L9 D8 FBx_CMD19 CKE_H C
2

E2 E2
2
2
VSSQ VSSQ
VSSQ E8 VSSQ E8 FBx_CMD20 A13 A13
VSSQ F9 VSSQ F9
VSSQ G9 VSSQ G9
FBx_CMD22 A6 A6
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 FBx_CMD23 A11 A11
N13P@ N13P@ FBx_CMD24 A5 A5
FBx_CMD25 A3 A3
FBx_CMD26 BA2 BA2
+1.5VS_VGA +1.5VS_VGA FBx_CMD27 BA1 BA1
FBx_CMD28 A12 A12
C1602
C1598
C1599
C1604
C1605
C1603
C1606
C1607
C1608
C1609
C1610
C1611
C1612
C1616
C1617
C1613
C1618
C1619
C1620
C1621
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
FBx_CMD29 A10 A10
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FBx_CMD30 RAS# RAS#
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
N13P@
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D D

Title
C Upper Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
R1516 ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
1
R1514 R1515 R1516 R1517 R1518 ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
45.3K_0402_1% 34.8K_0402_1% 10K_0402_5% 20K_0402_1% 20K_0402_1%
DIS@ @ N13P@ @ @ ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
2
4.99K_0402_1% STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
STRAP0 N13M@
(23) STRAP0
STRAP1 SD034499180 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
(23) STRAP1
STRAP2
(23) STRAP2
STRAP3 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
(23) STRAP3
A STRAP4 A
(23) STRAP4
R1520 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
1
CHANGE_GEN3
R1519 R1520 R1521 R1522 R1523
4.99K_0402_1% 34.8K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 10K_0402_5%
@ N13M@ @ N13M@ N13M@ 45.3K_0402_1%
N13P@ Pull-up to
2
SD034453280 Resistor Values Pull-down to Gnd
+3VS_VGA
5K 1000 0000
10K 1001 0001
+3VS_VGA 15K 1010 0010
20K 1011 0011
25K 1100 0100
1
1
30K 1101 0101
R1524 R1525 R1526
15K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 35K 1110 0110
@ @ N13M@
45K 1111 0111
2
2
N13M @ N13M Mount
N13P @ N13P @
ZZZ1 ZZZ2 ZZZ3 ZZZ4
ROM_SI
(23) ROM_SI
ROM_SO SUB_VENDOR 3GIO_PADCFG XCLK_417
(23) ROM_SO
ROM_SCLK
(23) ROM_SCLK
0 No VBIOS ROM 3GIO_PADCFG[3:0] 0 277MHz (Default)
Hynix Samsung Hynix Samsung
1
1
B B
H2G@ S2G@ H1G@ S1G@ 1 BIOS ROM is present (Default) 0110 Notebook Default 1 Reserved
R1527 R1528 R1529 X7635439L01 X7635439L02 X7635439L03 X7635439L04
15K_0402_1% 29.4K_0402_1% 15K_0402_1%
X76@ DIS@ N13P@
FB_0_BAR_SIZE SLOT_CLK_CFG
2
N13M Mount 2 N13M @

N13P Mount N13P Mount 0 Reserved 0 GPU and MCH don't share a common reference clock
1 Reserved 1 GPU and MCH share a common reference clock (Default)
2 256MB (Default) SMBUS_ALT_ADDR VGA_DEVICE

GPU FB Memory gDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
3 Reserved 0 0x9E (Default) 0 3D Device (Class Code 302h)
Samsung K4W1G1646G-BC11
900MHz PD 10K PD 15K PD 20K PU 45K PD 45K PU 10K NC NC
USER Straps 1 0x9C (Multi-GPU usage) 1 VGA Device (Default)
64Mx16 PU 45K(ES)
User[3:0]
Hynix H5TQ1G63DFR-11C PCIE_MAX_SPEED PEX_PLL_EN_TERM
1000-1100 Customer defined
64Mx16 PU 45K(ES) 0 Limit to PCIE Gen1 0 Disable (Default)
N13P-GL
Samsung K4W2G1646C-HC11 1 PCIE Gen 2/3 Capable 1 Enable
128Mx16 PU 45K(ES)
C Hynix H5TQ2G63BFR-11C C

128Mx16 PU 45K(ES)
X76
GPU FB Memory gDDR3 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
Samsung K4W1G1646G-BC11
900MHz PD 30K PU 5K PD 20K PU 45K PD 35K PU 5K PD 5K PD 10K
64Mx16
Hynix H5TQ1G63DFR-11C
64Mx16
N13M-GE1
Samsung K4W2G1646C-HC11
128Mx16
Hynix H5TQ2G63BFR-11C
D D
128Mx16
9/27 X76
from 15K to 5K

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL N13X-MISC
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
LCD POWER CIRCUIT

LCD/LED PANEL Conn.
+LCDVDD +5VALW +3VS Q2102 +LCDVDD +LCDVDD_CONN
PN:SP01000XE00
W=60mils Place closed to JLVDS1
W=60mils
1
A 3 1 1 2 +3VS +LEDVDD B+ A
R2101 R2102 1 FBMA-L11-201209-221LMA30T_0805
150_0603_1% 100K_0402_5% C2101 L2102 R2108 @
C2109
0.1U_0402_16V4Z
C2124
4.7U_0805_10V4Z
4.7U_0805_10V4Z 1 2
1 1 1
2
2 AP2301GN-HF_SOT23-3 C2103 0_0805_5%
0.1U_0402_16V4Z
3
2 2 2 1 1
C2113 C2112
4.7U_0805_25V6-K 680P_0402_50V7K
5 R2103 1 2 220K_0402_5% 10/06 @
Q2415B 2 2
2N7002KDWH_SOT363-6 1
4
C2107 JLCD1
0.1U_0402_16V4Z (20 MIL)
6 40 40
2
39 39
Q2415A 9/19 Del R1010 38
PCH_ENVDD 2N7002KDWH_SOT363-6 38
(16) PCH_ENVDD 2 37 37
36 36
11/14 DISPOFF# 35
1
35
1
INVPWM 34
@ R2106 34
+3VS_CMOS 33 33
100K_0402_5% 32 32
31 31
(35) DMIC_CLK 30
2
30
(35) DMIC_1_2 29 29
+3VS 28 28
A LOGO RED LIGHT LOGO_LED# 27
(36,41) LOGO_LED# 27
+3VALW R1209 1 2 4.99K_0402_1% +3VALW_LOGO 26
USB20_N5 26
(17) USB20_N5 25 25
CMOS USB20_P5 24
(17) USB20_P5 24
(16) LVDS_ACLK 23 23
(16) LVDS_ACLK# 22 22
B
21 21 B
(16) LVDS_A2 20 20
(16) LVDS_A2# 19 19
(16) LVDS_A1 18 18
(16) LVDS_A1# 17 17
(16) LVDS_A0 16 16
(16) LVDS_A0# 15 15
14 14
(16) LVDS_BCLK 13 13
(16) LVDS_BCLK# 12 12
+3VS
(16) LVDS_B2 11 11
(16) LVDS_B2# 10 10
(16) LVDS_B1 9 9
(16) LVDS_B1# 8 8
1
(16) LVDS_B0 7 7 G6 46
R2113 6 45
(16) LVDS_B0# 6 G5
4.7K_0402_5% EDID_DATA 5 44
(16) EDID_DATA 5 G4
@ EDID_CLK 4 43
(16) EDID_CLK 4 G3
@ D2101 +3VS 3 42
2
3 G2
2 1 +LCDVDD_CONN 2 2 G1 41
1 1
RB751V-40_SOD323-2
STARC_107K40-000001-G2
R2114 @ +3VS
(41) BKOFF# 1 2 0_0402_5% DISPOFF# CONN@
R2118 1 2 10K_0402_5% INVPWM

1
R2115 R2116 C2116 1 2 220P_0402_50V7K INVPWM

10K_0402_5% 10K_0402_5%
@ C2125 @ 1 2 1000P_0402_50V7K INVPWM
2
C2117 1 2 220P_0402_50V7K DISPOFF#
C C
+3VS +3VS
R2104 1 2 2.2K_0402_5% EDID_CLK
CMOS Camera Conn

1
R2105 1 2 2.2K_0402_5% EDID_DATA

R2154 1 1
4.7K_0402_5% C2110 C2111
@ 10P_0402_50V8J 10P_0402_50V8J +3VS +3VS_CMOS
@ D2102 @ @ Q2105 (20 MIL)
2
2 2 AP2301GN-HF_SOT23-3 CMOS SUSPEND 2.4mA

2 1
(20 MIL) @
RB751V-40_SOD323-2 3 1 1 2 0_0603_5%
R2150
R2107 @ +3VALW
(16) PCH_PWM 1 2 0_0402_5% INVPWM
1 1
2
C2114 @ C2115
0.1U_0402_16V4Z 10U_0603_6.3V6M
1
1 2 2
R2153 R2137 C2123
10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z
@ @ @
2
2
R2119 1 2 4.7V
(41) CMOS_ON#
150K_0402_5%
1
C2118
0.1U_0402_16V4Z
2
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL LVDS Connector
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
W=40mils
+5VS +R_CRT_VCC +CRT_VCC
D2105 F2101
2 1.1A_6V_SMD1812P110TF W=40mils
1 1 2
A 3 A
RB491D_SOT23-3
C2119
0.1U_0402_16V4Z
1
CRT Connector
2 PN:DC060002L10
DAC_RED L2104 1 2 FCM1608CF-121T03_2P RED JCRT1

(16) DAC_RED
6
T16 11
DAC_GRN L2105 1 2 FCM1608CF-121T03_2P GREEN 1
(16) DAC_GRN
7
12
DAC_BLU L2106 1 2 FCM1608CF-121T03_2P BLUE 2
(16) DAC_BLU
8
C2120
10P_0402_50V8J
C2121
10P_0402_50V8J
C2122
10P_0402_50V8J
C2126
10P_0402_50V8J
C2127
10P_0402_50V8J
C2128
10P_0402_50V8J
13
1
1
1 1 1 1 1 1 3
R2120 R2121 R2122 9
150_0402_1% 150_0402_1% 150_0402_1% 14 16
4 17
2 2 2 2 2 2
10
2
15
1
5
R314 R319
CONN@ 0_0603_5% 0_0603_5%
TE_2041480-1
2
L2109 1 2 FCM1608CF-121T03_2P JVGA_HS
+CRT_VCC CRT_DDC_DAT_CONN
B B
C2129 1 2 0.1U_0402_16V4Z R2123 1 2 1K_0402_5% L2110 1 2 FCM1608CF-121T03_2P JVGA_VS
5
CRT_DDC_CLK_CONN
C2132
100P_0402_50V8J
C2133
68P_0402_50V8J
P
OE#
CRT_HSYNC 2 4 CRT_HSYNC_1 1 1 1 1 1
(16) CRT_HSYNC A Y C2130 C2131 C2134
G
U2101 10P_0402_50V8J 10P_0402_50V8J 68P_0402_50V8J

74AHCT1G125GW_SOT353-5 @ @ @ @
3
2 2 2 2 2 R115 1 @ 2 0_0402_5%
+CRT_VCC
C2135 1 2 0.1U_0402_16V4Z 5 R2127 1 2 1K_0402_5% R116 1 @ 2 0_0402_5%
1
R117 1 @ 2 0_0402_5%
P
OE#
CRT_VSYNC 2 4 CRT_VSYNC_1
(16) CRT_VSYNC A Y
G
U2102 R118 1 @ 2 0_0402_5%

74AHCT1G125GW_SOT353-5
3
D2103
D2110 JVGA_VS 3 6 JVGA_HS
BLUE RED I/O2 I/O4
3 I/O2 I/O4 6
2 GND VDD 5 +R_CRT_VCC

2 GND VDD 5 +R_CRT_VCC
C C
CRT_DDC_CLK_CONN 1 4 CRT_DDC_DAT_CONN
GREEN I/O1 I/O3
1 I/O1 I/O3 4
AZC099-04S.R7G_SOT23-6
+3VS +R_CRT_VCC
+3VS
1
R2124 R2125
4.7K_0402_5% 4.7K_0402_5%
2
2
C2152
C2153
100P_0402_50V8J
100P_0402_50V8J
CRT_DDC_DATA 1 6 CRT_DDC_DAT_CONN
(16) CRT_DDC_DATA
1 1
2N7002KDWH_SOT363-6 Q2107A
5
Chip Conn
2 2 CRT_DDC_CLK CRT_DDC_CLK_CONN
(16) CRT_DDC_CLK 4 3
D D
2N7002KDWH_SOT363-6 Q2107B
9/27 ESD

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL CRT Connector
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
A A
+3VS
1
R2126
1M_0402_5%
2
G
Q2109
2
2N7002K_SOT23-3
(16) PCH_DPB_HPD 3 1
1
1
R2129 C2137
20K_0402_5% 220P_0402_50V7K
ESD request @
Common mode choke 90ohm on these singals
2
HDMI Connector
2
Compal PN: SM070000K00
Vendor PN: WCM-2012-900T
PN:DC232001K10
+HDMI_5V +HDMI_5V_OUT
(16) PCH_DPB_P3 .1U_0402_16V7K 1 2 C2145 HDMI_CLK+ R2128 1 @ 2 0_0402_5% HDMI_R_CK+ W=40mils JHDMI1
D2106 HDMI_HPD 19
F2102 HP_DET
1 1 2 2 +5VS 2 W=40mils 18 +5V
1 +HDMI_5V 1 2 17
L2111 WCM-2012HS-900T HDMI_SDATA DDC/CEC_GND
3 16 SDA
4 RB491D-YS_SOT23-3 1.1A_6V_SMD1812P110TF HDMI_SCLK
4 3 3 15 SCL
1 14 Reserved
(16) PCH_DPB_N3 .1U_0402_16V7K 1 2 C2144 HDMI_CLK- R2130 1 @ 2 0_0402_5% HDMI_R_CK- C2136 13
0.1U_0402_16V4Z HDMI_R_CK- CEC
B
12 CK- GND 20 B
11 CK_shield GND 21
2 HDMI_R_CK+ 10 CK+ GND 22
(16) PCH_DPB_P2 .1U_0402_16V7K 1 2 C2143 HDMI_TX0+ R2131 1 @ 2 0_0402_5% HDMI_R_D0+ HDMI_R_D0- 9 23
R2149 1 @ D0- GND
2 0_0805_5% 8 D0_shield
1 2 HDMI_R_D0+ 7
1 2 HDMI_R_D1- D0+
6 D1-
L2112 WCM-2012HS-900T 5
HDMI_R_D1+ D1_shield
4 4 3 3 4 D1+
HDMI_R_D2- 3
.1U_0402_16V7K D2-
(16) PCH_DPB_N2 1 2 C2142 HDMI_TX0- R2132 1 @ 2 0_0402_5% HDMI_R_D0- 2 D2_shield
+3VS +HDMI_5V HDMI_R_D2+ 1 D2+
(16) PCH_DPB_P1 .1U_0402_16V7K 1 2 C2141 HDMI_TX1+ R2133 1 @ 2 0_0402_5% HDMI_R_D1+ SUYIN_100042GR019M23DZL

CONN@
1 1 2 2
1
L2113 WCM-2012HS-900T footprint check
4 3 R2148 R2143 R2145 R2146
4 3 2.2K_0402_1% 2.2K_0402_1% 2.2K_0402_5% 2.2K_0402_5%
(16) PCH_DPB_N1 .1U_0402_16V7K 1 2 C2140 HDMI_TX1- R2134 1 @ 2 0_0402_5% HDMI_R_D1-
2
2
2
(16) PCH_DPB_P0 .1U_0402_16V7K 1 2 C2139 HDMI_TX2+ R2135 1 @ 2 0_0402_5% HDMI_R_D2+ 1 6 HDMI_SCLK
(16) HDMICLK_NB
Q2111A
1 2 2N7002KDWH_SOT363-6
1 2
5
L2114 WCM-2012HS-900T
Chip Conn
4 3 4 3 HDMI_SDATA
4 3 (16) HDMIDAT_NB
Q2111B
1
(16) PCH_DPB_N0 .1U_0402_16V7K 1 2 C2138 HDMI_TX2- R2136 1 @ 2 0_0402_5% HDMI_R_D2- 2N7002KDWH_SOT363-6
C2146 @ C2147 @
Place closed to JHDMI1 47P_0402_50V8J 47P_0402_50V8J
2
C C
HDMI_TX2- R2144 1 2 680_0402_5% HDMI_GND

HDMI_TX2+ R2152 1 2 680_0402_5%
HDMI_TX1- R2139 1 2 680_0402_5%

HDMI_TX1+ R2140 1 2 680_0402_5%
HDMI_TX0- R2141 1 2 680_0402_5%

HDMI_TX0+ R2142 1 2 680_0402_5%
HDMI_CLK- R2151 1 2 680_0402_5% D2113 D2112 D2108

HDMI_CLK+ R2147 1 2 680_0402_5% HDMI_HPD 1 1 10 9 HDMI_HPD HDMI_R_CK- 1 1 10 9 HDMI_R_CK- HDMI_R_D2- 1 1 10 9 HDMI_R_D2-
HDMI_SDATA 2 2 9 8 HDMI_SDATA HDMI_R_CK+ 2 2 9 8 HDMI_R_CK+ HDMI_R_D2+ 2 2 9 8 HDMI_R_D2+

1
D HDMI_SCLK HDMI_SCLK HDMI_R_D1- HDMI_R_D1- HDMI_R_D0- HDMI_R_D0-

UMA 680_0402_5% Q2110
4 4 7 7 4 4 7 7 4 4 7 7
+3VS 2
G 2N7002K_SOT23-3 +HDMI_5V_OUT 5 5 6 6 +HDMI_5V_OUT HDMI_R_D1+ 5 5 6 6 HDMI_R_D1+ HDMI_R_D0+ 5 5 6 6 HDMI_R_D0+
S
3 3 3 3 3 3
3
8 8 8
9/27 ESD
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HDMI Connector
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier. +3VS FILT_1.65_R C1135 1 2 1U_0402_6.3V6K
An integrated 5 V to 3.3 V Low-dropout Near Pin 29
C1136 1 2 0.1U_0402_16V4Z
voltage regulator (LDO). Layout Note:Path from +5VS to Pin12,
Pin15 must be very low
An integrated 3.3 V to 1.8V Low-dropout resistance (<0.01 ohms)
voltage regulator (LDO).
1
To support Wake-on-Jack or Wake-on-Ring, the CODEC +LDO_OUT_3.3V_R C1133 1 2 4.7U_0603_6.3V6K
VAUX_3.3 & VDD_IO pins must be powerd by a rail that C1121 C1119
A D2417 RB751V-40_SOD323-2 is not removed unless AC power is removed. 0.1U_0402_16V4Z 4.7U_0603_6.3V6K C1134 1 2 0.1U_0402_16V4Z Near Pin 27 A
2
2 1 *DSH page42 has more detail. @
Near Pin 2
AVDD_3.3 pinis output of internal LDO. NOT connect
to external supply.
EC Beep C1141 1 2 @ PC_BEEP_C_R R1120 1 2 33_0402_5% PC_BEEP_C C1111 1 2 0.1U_0402_16V4ZPC_BEEP
(41) BEEP# +5VS
1
0.1U_0402_16V4Z
PC Beep C1116 C1114
1
C1142 2 @ @
ICH Beep (13) HDA_SPKR 1 0.1U_0402_16V4Z 1U_0402_6.3V6K
2
@ C1113 C1112 Near Pin 28
0.1U_0402_16V4Z Near Pin 7 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2
D2416
2 1 10 mils FILT_1.8_R
RB751V-40_SOD323-2 +3VS
1
R1121 C1132 C1130
10K_0402_5% 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
1
Near Pin 3
C1129 C1124
2
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2
Near Pin 26
Sense resistors must be
connected same power
18
29
27
28
26
Combo Jack detect (normal open) that is used for
3
7
2
10K only needed if supply to VAUX_3.3 U1101
is removed during system re-start. VAUX_3.3
AVDD_5V
AVDD_HP
FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3
FILT_1.65
AVDD_3.3
MIC_JD Near Pin 17 @
12 +CLASSD_5V R1122 1 2 0_0805_5% +5VS
R1112 1 @ LPWR_5.0
+3VS 2 4.7K_0402_5% RPWR_5.0 15
Q1103 HDA_RST#_AUDIO 9 17 C1107 1 2 0.1U_0402_16V4Z
(13) HDA_RST#_AUDIO RESET# CLASS-D_REF
1
B D LBSS138LT1G_SOT-23-3 B
2 R1130 1 2 33K_0402_5% EXT_MIC HDA_BITCLK_AUDIO 5 R1113 1 2 5.11K_0402_1% +3VS

(13) HDA_BITCLK_AUDIO BIT_CLK
G 1 HDA_SYNC_AUDIO 8 36 SENSE_A R1114 1 2 20K_0402_1% MIC_JD Port B
(13) HDA_SYNC_AUDIO SYNC SENSE_A
S C1146 R1115 1 2 33_0402_5% 6 R1116 1 2 39.2K_0402_1% PLUG_IN Port A
(13) HDA_SDIN0 PLUG_IN (39)
3
1U_0402_6.3V6K HDA_SDOUT_AUDIO SDATA_IN

(13) HDA_SDOUT_AUDIO 4 SDATA_OUT
35 PORTB C1108 1 2 2.2U_0402_6.3V6M R1133 1 2 100_0402_1% EXT_MIC External MIC
2 PORTB_R EXT_MIC (39)
PLUG_IN 34 1109
PORTB_L
EAPD active low B_BIAS 33 +MICBIASB
PC_BEEP 10
0=power down ex AMP PC_BEEP +MICBIASB
CX_GPIO0 R1129 1 @ 2 33K_0402_5% 1=power up ex AMP 32
C_BIAS EXT_MIC R1132 1
1 PORTC_R 31 2 2K_0402_5% R1128 1 2 4.7K_0402_5%
C1147 30
1U_0402_6.3V6K R1111 PORTC_L
(41) EAPD 1 2 0_0402_5% CX_GPIO0 38 GPIO0/EAPD#
@ R1131 1 2 0_0402_5% 37
2 (41) EC_MUTE# GPIO1/SPK_MUTE#
23 HP_OUTR_R R1117 1 2 39_0402_5% HP_OUTR Headphone
PORTA_R HP_OUTR (39)
22 HP_OUTL_R R1118 1 2 39_0402_5% HP_OUTL
PORTA_L HP_OUTL (39)
R1125 1 2 DMIC_CLK_R 40
(32) DMIC_CLK DMIC_CLK
Internal DMIC FBMA-10-100505-301T_2P 1 24
(32) DMIC_1_2 DMIC_1/2 NC
NC 25 Changed from 5.1ohm to 15ohm
NC 39 for "zi zi"noise.
SPK_L2+ 11
SPK_L1- LEFT+
13 LEFT-
21 AVEE C1122 1 2 0.1U_0402_16V4Z
AVEE FLY_P
Internal SPEAKER FLY_P 19 Near Pin 21
SPK_R2+ 16 20 FLY_N C1110 1 2 C1125 1 2 4.7U_0603_6.3V6K
SPK_R1- RIGHT+ FLY_N
14 RIGHT- 1U_0402_6.3V6K
GND
CX20671-21Z_QFN40_6X6
41
C
Decoupling CAP C
+CLASSD_5V
C1115 1 2 0.1U_0402_16V4Z
Near Pin 12
C1117 1 2 10U_0603_6.3V6M
C1118 1 2 0.1U_0402_16V4Z
Near Pin 15
C1120 @1 2 10U_0603_6.3V6M
EMC request
Internal Speaker
Bead 120ohm on these singals
Compal PN: SM010016720
Vendor PN: FBMA-L11-160808-121LMT
SP02000N010
Rdc < 0.05 ohms
SP02000SM10
Rated Current > 2A
JSPK1
SPK_R1- L1102 1 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ L1103 0_0603_5% SPK_R2+_CONN 1
1 2 2 2
SPK_L1- L1104 1 2 0_0603_5% SPK_L1-_CONN 3
SPK_L2+ L1105 0_0603_5% SPK_L2+_CONN 3
1 2 4 4
SPK_RT_DET# R1134 1 2 0_0402_5% SPK_RT_DET#_R 5
(41) SPK_RT_DET# 5
6
EMI 7
6
GND
C1137
C1138
C1139
C1140
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
Width 20 mil 8 GND
1 1 1 1
C1102 1 2 0.1U_0402_16V4Z E-T_4070K-G06N-00L
C1103 1 2 0.1U_0402_16V4Z
EMI @ @ @ @
CONN@
D 2 2 2 2 D
C1104 1 2 0.1U_0402_16V4Z
HDA_RST#_AUDIO
EMI C1123 @1 2 22P_0402_50V8J
HDA_SYNC_AUDIO C1126 @1 2 22P_0402_50V8J R1102 1 @ 2 0_0402_5%
HDA_SDOUT_AUDIO C1128 @1 2 22P_0402_50V8J R1104 1 @ 2 0_0402_5%
HDA_BITCLK_AUDIO R1123 1 2 33_0402_5% HDA_BITCLK_AUDIO_R C1131 1 2 22P_0402_50V8J R1105 1 @ 2 0_0402_5%

Title
9/28 RF modify THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HD Audio Codec CX20671
GND GND GNDA
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
SATA HDD CONN. Card Reader CONN.

PN:DC010004C00
JHDD1
1
(13) SATA_PTX_DRX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
2
GND
A+
PN:SP01001BF00
(13) SATA_PTX_DRX_N0 3 A-
4 GND
A SATA_DTX_C_PRX_N0 C2401 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N0 5 JCARD1 A
(13) SATA_DTX_C_PRX_N0 B-
SATA_DTX_C_PRX_P0 C2402 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P0 6 +3VS 14
(13) SATA_DTX_C_PRX_P0 B+ 14
7 GND 13 13
+3VS 12
(14) PCIE_PRX_DTX_P1 12
(14) PCIE_PRX_DTX_N1 11 11
8 V33 10 10
9 V33 (14) CLK_PCIE_CARD 9 9
10 V33 (14) CLK_PCIE_CARD# 8 8
11 GND 7 7
(41) HDD_DETECT# 12 GND (14) PCIE_PTX_C_DRX_P1 6 6
13 GND (14) PCIE_PTX_C_DRX_N1 5 5
+5VS @ J2401 14 4
V5 (14) CARD_CLKREQ# 4
1 2 5VS_HDD 15 3
1 2 V5 (5,14,17,22,38,40,41) PLT_RST# 3
16 V5 +3VALW 2 2
JUMP_43X79 17 1
GND (32,41) LOGO_LED# 1
18 Reserved
11/15 del R2414
19 GND GND 23 機機機機
20 24 ACES_87213-1400G
+5VS V12 GND CONN@
21 V12
22 V12
10/06
change PN to SP02000H810
C2403
1000P_0402_50V7K
C2405
1U_0402_6.3V6K
C2406
10U_0603_6.3V6M
SANTA_198202-1
1 1 1 CONN@ footprint: ACES_87213-1400G_14P
@ @
2 2 2 Pin 18 to GND for Gen 3
B B
SATA ODD CONN. APS G-Sensor

PN:SP01000TU10
1
for Edge 15'' R2402
100K_0402_5%
JODD2
SATA_PTX_DRX_P1 SATA_PTX_DRX_P1 1 U2401
(13) SATA_PTX_DRX_P1
2
SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 1
(13) SATA_PTX_DRX_N1 2 2
3 2 12 VOUTX R2403 1 2 56K_0402_5%
3 (41) GS_SELFTEST ST Xout GS_VOUTX (41)
SATA_DTX_C_PRX_N1 C2408 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 SATA_DTX_PRX_N1 4 10 VOUTY R2404 1 2 56K_0402_5%
(13) SATA_DTX_C_PRX_N1 4 +3VS +3VS_GS Yout GS_VOUTY (41)
SATA_DTX_C_PRX_P1 C2409 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P1 SATA_DTX_PRX_P1 5 8
(13) SATA_DTX_C_PRX_P1 5 Zout
6 6
+5VS_ODD ODD_DETECT#_R 7 R2405 1 @ 2 0_0603_5% 14
7 Vs
C2411
C2414
C2412
C2415
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
+5VS_ODD 8 15
8 Vs
C2413
C2410
10U_0603_6.3V6M
.1U_0402_16V7K
9 9 1 1 1 1
+5VS_ODD ODD_DA#_R 10 1 1 1
10 NC
11 11/17 4
R2406 @ GND NC
(17) ODD_DA# 1 2 0_0402_5% ODD_DA#_R 12 GND BOM modify 3 COM NC 9
2 2 2 2
C 5 COM NC 11 C
ACES_88514-104N 2 2
Q2406 6 COM NC 13
CONN@ 7 16
2N7002K_SOT23-3 COM NC
APS_GND
ODD_DETECT#_R LIS34ALTR_LGA16_4X4
D
(13) ODD_DET# 1 3
@ APS_GND @ J2402
9/27 1 2
G
2
2MM
(14) ON_ODD_DET
APS_GND
+VSB +5VS +5VS_ODD +3VS +3VS_GS

Q2402
ODD_DA# C2155 1 2 220P_0402_50V7K AP2301GN-HF_SOT23-3 R2409
R2407 1 @ 2 0_0805_5% @
3 1 1 2
1
C2425
C2407
0.1U_0402_16V4Z
10U_0603_6.3V6M
D
R2408 6 1 1 11/17 1 0_0603_5% 1

S
1
470K_0402_5% 1 5 4 1 C2420
C2416 2 @ R2138 C2417 10U_0603_6.3V6M
2
1U_0402_6.3V6K 1 Q2401 @ 150K_0402_5% C2426 0.1U_0402_16V4Z @
2
2 2 0.01U_0402_16V7K 2 2
G
2 2 @
3
2
SI3456DDV-T1-GE3_TSOP6
R2410
ODD_EN GS_ON# 1 2
(41) GS_ON#
150K_0402_5%
1
D D D
1 1
2 C2419
(18) ODD_EN# 0.1U_0603_25V7K
G R2411 C2418
Q2403 S 1.5M_0402_5% 0.01U_0402_16V7K
2N7002K_SOT23-3 2 2
3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HDD/ODD/Card
reader/G-Sensor Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
USB 3.0 Conn.

+USB_VCCA
C2434
150U_B2_6.3VM_R35M
C2435
470P_0402_50V7K
W=80mils L2403 L2404 L2405 1
USB20_N1 2 1 USB20_N1_C USB3TXDP1 3 4 USB3_TX1_C_P USB3_RX1_P 3 4 USB3_RX1_C_P 1
2 1 3 4 3 4 +
+5VALW +USB_VCCA D2410
USB20_P1 3 4 USB20_P1_C USB3TXDN1 2 1 USB3_TX1_C_N USB3_RX1_N 2 1 USB3_RX1_C_N USB3_TX1_C_P 1 1 10 9 USB3_TX1_C_P
3 4 2 1 2 1 2 2
1000P_0402_50V7K
C2215
Low Active 1 WCM-2012-900T_4P WCM-2012HS-900T WCM-2012HS-900T USB3_TX1_C_N 2 2 9 8 USB3_TX1_C_N
A
C2447
U2405 PN: SM070000K00 x 1 PN: SM070001S00 x 2
USB3_RX1_C_P 4 4 7 7 USB3_RX1_C_P A
1 GND VOUT 8
0.1U_0402_16V4Z 2 USB3_RX1_C_N USB3_RX1_C_N
2 VIN VOUT 7 5 5 6 6
1 2 3 VIN VOUT 6
USB_ON# 4 5 JUSB1 3 3
EN FLG USB_OC0# (17)
C2443 1 2 0.1U_0402_10V6K USB3TXDP1 0_0402_5% 1 @ 2 R2423 USB3_TX1_C_P 9
(17) USB3_TX1_P SSTX+ 8
G547I2P81U_MSOP8 1 1
C2448 D2405 C2442 1 VBUS
(17) USB3_TX1_N 2 0.1U_0402_10V6K USB3TXDN1 0_0402_5% 1 @ 2 R2424 USB3_TX1_C_N 8 SSTX-
1000P_0402_50V7K 1 4 USB20_P1_C 0_0402_5% 1 @ 2 R2420 USB20_P1_C 3 YSCLAMP0524P_SLP2510P8-10-9
I/O1 I/O3 (17) USB20_P1 D+
@ 7
2 +USB_VCCA 0_0402_5% @ USB20_N1_C GND
(17) USB20_N1 1 2 R2419 2 D- GND 10
0_0402_5% 1 @ 2 R2463 USB3_RX1_C_P 6 11
(17) USB3_RX1_P SSRX+ GND
2 GND VDD 5 4 GND GND 12
0_0402_5% 1 @ 2 R2464 USB3_RX1_C_N 5 13
9/27 ESD (17) USB3_RX1_N SSRX- GND
ACON_TARA4-9K1311
3 6 USB20_N1_C CONN@
I/O2 I/O4
PN: SC300001G00 PN:DC23300AS20
D2411
USB3_TX2_C_P 1 1 10 9 USB3_TX2_C_P
L2402 L2406 L2407 USB3_TX2_C_N 2 2 9 8 USB3_TX2_C_N

USB20_N2 2 1 USB20_N2_C USB3TXDP2 3 4 USB3_TX2_C_P USB3_RX2_P3 4 USB3_RX2_C_P
2 1 3 4 3 4 USB3_RX2_C_P USB3_RX2_C_P
B
4 4 7 7 B
+USB_VCCB
W=80mils USB20_P2 3 4 USB20_P2_C USB3TXDN2 2 1 USB3_TX2_C_N USB3_RX2_N2 1 USB3_RX2_C_N USB3_RX2_C_N 5 5 6 6 USB3_RX2_C_N
3 4 2 1 2 1
WCM-2012-900T_4P WCM-2012HS-900T WCM-2012HS-900T 3 3
+5VALW +USB_VCCB
PN: SM070000K00 x 1 PN: SM070001S00 x 2 8

1000P_0402_50V7K
C2216
Low Active 1 JUSB2 YSCLAMP0524P_SLP2510P8-10-9

0.1U_0402_10V6K 1 2 C2511 USB3TXDP2 0_0402_5% 1 @ 2 R2425 USB3_TX2_C_P 9
(17) USB3_TX2_P SSTX+
1 VBUS
U2409
(17) USB3_TX2_N
0.1U_0402_10V6K 1 2 C2446 USB3TXDN2 0_0402_5% 1 @ 2 R2426 USB3_TX2_C_N 8 SSTX-
C2421 2 0_0402_5% @
1 GND VOUT 8 (17) USB20_P2 1 2 R2421 USB20_P2_C 3 D+
0.1U_0402_16V4Z 2 7 7
VIN VOUT 0_0402_5% @ GND
1 2 3 VIN VOUT 6 (17) USB20_N2 1 2 R2422 USB20_N2_C 2 D- GND 10
USB_ON# 4 5 0_0402_5% 1 @ 2 R2465 USB3_RX2_C_P 6 11
(41) USB_ON# EN FLG USB_OC1# (17) (17) USB3_RX2_P SSRX+ GND
4 GND GND 12
G547I2P81U_MSOP8 1 0_0402_5% 1 @ 2 R2466 USB3_RX2_C_N 5 13
(17) USB3_RX2_N SSRX- GND
C2424
1000P_0402_50V7K ACON_TARA4-9K1311
@ D2403 CONN@
2 USB20_P2_C 1 I/O1 I/O3 4
+USB_VCCB
2 5
GND VDD 9/27 ESD PN:DC23300AS20
3 6 USB20_N2_C
I/O2 I/O4
C
PN: SC300001G00 C
+USB_VCCB
D2415
USB3_TX3_C_P 1 1 10 9 USB3_TX3_C_P
C2422
C2423
150U_B2_6.3VM_R35M
470P_0402_50V7K
USB3_TX3_C_N 2 2 9 8 USB3_TX3_C_N
1
L2401 L2408 L2409 1 USB3_RX3_C_P 4 4 7 7 USB3_RX3_C_P
USB20_P3 2 1 USB20_P3_C USB3TXDP3 3 4 USB3_TX3_C_P USB3_RX3_P3 4 USB3_RX3_C_P +
2 1 3 4 3 4 USB3_RX3_C_N USB3_RX3_C_N
5 5 6 6
USB20_N3 USB20_N3_C USB3TXDN3 2 USB3_TX3_C_N USB3_RX3_N2 USB3_RX3_C_N 2 2

3 3 4 4 2 1 1 2 1 1 3 3
WCM-2012-900T_4P WCM-2012HS-900T WCM-2012HS-900T 8
YSCLAMP0524P_SLP2510P8-10-9
PN: SM070000K00 x 1 PN: SM070001S00 x 2
JUSB3
0.1U_0402_10V6K 1 2 C2445 USB3TXDP3 0_0402_5% 1 @ 2 R2461 USB3_TX3_C_P 9
(17) USB3_TX3_P SSTX+
1 VBUS
0.1U_0402_10V6K 1 2 C2444 USB3TXDN3 0_0402_5% 1 @ 2 R2462 USB3_TX3_C_N 8
(17) USB3_TX3_N SSTX-
USB20_P3 0_0402_5% 1 @ 2 R2413 USB20_P3_C 3
(17) USB20_P3 D+
7 GND
USB20_N3 0_0402_5% 1 @ 2 R2412 USB20_N3_C 2 10
(17) USB20_N3 D- GND
0_0402_5% 1 @ 2 R2467 USB3_RX3_C_P 6 11
(17) USB3_RX3_P SSRX+ GND
4 GND GND 12
0_0402_5% 1 @ 2 R2468 USB3_RX3_C_N 5 13
(17) USB3_RX3_N SSRX- GND
ACON_TARA4-9K1311
CONN@
D D
D2401
USB20_P3_C 1 4
I/O1 I/O3
+USB_VCCB PN:DC23300AS20
2 GND VDD 5
9/27 ESD
3 I/O2 I/O4 6 USB20_N3_C Security Classification Compal Secret Data

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL USB 3.0
Connector Rev
PN: SC300001G00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Mini Card Power Rating

Mini-Express Card for WLAN/WiMAX(Half) 9/19
BT Connector
9/19 +3VAUX_BT
Power Primary Power (mA) Auxiliary Power (mA)
Mini-Express Card(WLAN/WiMAX) +3VS +3VALW +3VS_AOAC +1.5VS +3VS_AOAC +1.5VS
Peak Normal Normal
JBT1 70mA
PN:SP07000JP00 +3VS 1000 750 1 1
2 2
C2452
10U_0603_6.3V6M
C2455
0.1U_0402_16V4Z
+3V 330 250 250 (wake enable) 3 USB20_P13_R R2473 1 @ 2 0_0402_5%
3 USB20_P13 (17)
J2403 J2406 1 1 4 USB20_N13_R R2474 1 @ 2 0_0402_5%
1
4 USB20_N13 (17)
JUMP_43X79 JUMP_43X79 +1.5VS 500 375 5 (Not wake enable) 7 5
@ @ G1 5
8 G2 6 6 BT_DET# (17)
2
2 2 ACES_50224-00601-001
2
JMINI2 CONN@
A WLAN_WAKE# 1 2 A
(41) WLAN_WAKE# 1 2
3 3 4 4
WLBT_OFF_5# R2434 1 @ 2 0_0402_5% BT_OFF#_R 5 6
(13) WLBT_OFF_5# 5 6
WLAN_CLKREQ1# 7 8 LPC_FRAME#_R
(14) WLAN_CLKREQ1# 7 8 +3VS
9 10 LPC_AD3_R
9 10 LPC_AD2_R +3VAUX_BT
(14) CLK_PCIE_WLAN1# 11 11 12 12
13 14 LPC_AD1_R Q2411 BT@
(14) CLK_PCIE_WLAN1 13 14
15 16 LPC_AD0_R AP2301GN-HF_SOT23-3
15 16
PCI_RST#_R 17 18 3 1
R2427 CLK_PCI_DB_R 17 18 RF_OFF#
(17) BT_DET# 1 2 1K_0402_5% 19 19 20 20 RF_OFF# (41)
C2506 C2507
21 22 PLT_RST# 1 1
21 22 PLT_RST# (5,14,17,22,36,40,41)
1
(14) PCIE_PRX_DTX_N2 23 23 24 24
25 26 @ R2477
(14) PCIE_PRX_DTX_P2
2
25 26 470_0402_5% BT@ BT@
27 27 28 28
SMB_CLK_S3 2 2
29 29 30 30 SMB_CLK_S3 (11,12,14,39)
0.1U_0402_16V4Z
10U_0603_6.3V6M
31 32 SMB_DATA_S3
(14) PCIE_PTX_C_DRX_N2 SMB_DATA_S3 (11,12,14,39)
1 2
31 32
(14) PCIE_PTX_C_DRX_P2 33 33 34 34
35 35 36 36 USB20_N10 (17)
+3VS_AOAC 37 38 BT@ D
37 38 USB20_P10 (17)
39 40 (18) BT_ON# BT_ON# R2109 1 2 2
39 40
9/19 41 41 42 42 9/19 G
43 44 100K_0402_5% S
43 44 @
45 46 1
3
R2432 45 46 +VSB +3VALW +3VS_AOAC C2513 Q2412
47 47 48 48 For AOAC assessment
EC_TX_P80_DATA 1 2 100_0402_1% 49 50
(40,41) EC_TX_P80_DATA 49 50
EC_RX_P80_CLK 1 2 100_0402_1% 51 52 @ BT@
(40,41) EC_RX_P80_CLK 51 52 2 0.1U_0402_16V4Z
R2433 R2485 1 2 0_0805_5% 2N7002K_SOT23-3
1
(18) WLBT_OFF_51# 1 2 R2470 53 GND1 GND2 54
1K_0402_5% R2482
D
470K_0402_5% 6
S
AOAC@ 1 5 4
1
For EC to detect BELLW_80003-7021 C2509 2
2
R2435 CONN@ 1U_0402_6.3V6K 1 Q2400
debug card 100K_0402_5% AOAC@ SI3456DDV-T1-GE3_TSOP6
G
B insert. 2 AOAC@ B
if AOAC enable +3VS_AOAC always ON
3
R2483
if AOAC disable +3VS_AOAC same +3VS Reserve for SW mini-pcie debug card.
2
WLAN_EN 1 2
0_0402_5%
Series resistors closed to KBC side.
1
AOAC@
1
D 1 LPC_FRAME#_R R2449 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# (13,40,41)
2 LPC_AD3_R R2455 1 @ 2 0_0402_5% LPC_AD3
(41) AOAC_WLAN LPC_AD3 (13,40,41)
G R2481 C2501 LPC_AD2_R R2456 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 (13,40,41)
from EC Q2404 S 1.5M_0402_5% .1U_0603_25V7K LPC_AD1_R R2457 1 @ 2 0_0402_5% LPC_AD1
2 LPC_AD1 (13,40,41)
2N7002K_SOT23-3 AOAC@ AOAC@ LPC_AD0_R R2458 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 (13,40,41)
2
AOAC@ PCI_RST#_R R2459 1 @ 2 0_0402_5% PLT_RST#
CLK_PCI_DB_R R2428 1 @ 2 0_0402_5% CLK_PCI_DB
CLK_PCI_DB (17,40)
Mini-Express Card for WWAN/mSATA(Full) 11/15 11/15

R2436
+3VS +3VS_WWAN +1.5VS +3VS_WWAN +1.5VS UIM_DATA 1 @ 2 +UIM_PWR
10K_0402_5%
1
D2406 @
C2451
C2453
C2454
C2456
10U_0603_6.3V6M
47P_0402_50V8J
0.1U_0402_16V4Z
47P_0402_50V8J
@ J2404 3 6
1
JUMP_43X79 I/O2 I/O4

1 1 1 1
PN:SP07000JP00
2
@ @ 2 5 +3VS +3VS
2
JMINI1 2 2 2 2 GND VDD

WLAN_WAKE# R2437 1 @ 2 0_0402_5% 1 2
1 2
3 3 4 4
5 5 6 6 1 I/O1 I/O3 4
7 8 +UIM_PWR
7 8 UIM_DATA AZC099-04S.R7G_SOT23-6 @ D2407
9 9 10 10
11 12 UIM_CLK JSIM1 40mil 3
11 12 UIM_RST +UIM_PWR
C 13 13 14 14 4 GND VCC 1 1 C
15 16 UIM_VPP UIM_VPP 5 2 UIM_RST 2
15 16 UIM_DATA VPP RST UIM_CLK
6 I/O CLK 3
17 18 7 DAN217T146_SC59-3
P23 B+ 17 18 DET
19 19 20 20 3G_OFF# (18)
21 22 PLT_RST# 1 1
SATA_DTX_IRX_P2_R 21 22 3G@ C2457 3G@ C2458
23 23 24 24
SATA_DTX_IRX_N2_R 25 26 8 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
P25 B- 25 26 GND
27 27 28 28 GND 9
P32 A- SMB_CLK_S3 R2439 2 2
29 29 30 30 +3VS 1 3G@ 2 10K_0402_5%
SATA_ITX_DRX_N2_R 31 32 SMB_DATA_S3
SATA_ITX_DRX_P2_R 31 32
33 33 34 34
11/15 35 35 36 36 USB20_N12 (17)
+3VS_WWAN 37 38
37 38 USB20_P12 (17)
39 40 TAITW_PMPAT6-06GLBS7N14H0
39 40 CONN@
41 41 42 42
43 44
(18) 3G_DET#
45
43
45
44
46 46 PN:SP07000LM00
47 47 48 48
49 49 50 50
(18) mSATA_PCH 51 51 52 52
+3VS
53 GND1 GND2 54
A_PRE1 R2460 2 @ 1 4.7K_0402_5%
R2438 2 @ 1 0_0402_5%
BELLW_80003-7021
CONN@ +3VS B_PRE1 R2471 2 @ 1 4.7K_0402_5%
+3VS R2472 2 @ 1 0_0402_5%
PS8520B
PS8520B pin8 B_PRE0 4.7K NC TEST R2475 2 @ 1 4.7K_0402_5%
C2459
C2460
0.1U_0402_16V4Z
0.01U_0402_16V7K
internal pull up 150K pin9 A_PRE0 4.7K NC R2476 2 @ 1 0_0402_5%

1
U2406 1 1
R2440 1 2 4.7K_0402_5% 7 6 R2441 R2442
D EN VCC 4.7K_0402_5% 4.7K_0402_5% D
VCC 10
SATA_PTX_DRX_P2 1 16 @ @
(13) SATA_PTX_DRX_P2 RX_1P VCC 2 2
SATA_PTX_DRX_N2 2 20 PEXTN R352 2 1 0_0402_5%
(13) SATA_PTX_DRX_N2
2
0.01U_0402_16V7K RX_1N VCC PEXTN R353

PS8513B 2 1 4.99K_0402_1%
C2462 1 2 SATA_DTX_PRX_P2 5 9 pin 20 PEXTN 4.99K pull low to GND @
(13) SATA_DTX_C_PRX_P2 TX_2P PE1
C2461 1 2 SATA_DTX_PRX_N2 4 8
(13) SATA_DTX_C_PRX_N2 TX_2N PE2
0.01U_0402_16V7K 3 15 SATA_ITX_DRX_P2_C C2463 1 2 0.01U_0402_16V7K SATA_ITX_DRX_P2_R
GND TX_1P SATA_ITX_DRX_N2_C C2464
13 14 1 2 0.01U_0402_16V7K SATA_ITX_DRX_N2_R
B_PRE1
TEST
17
GND
GND
TX_1N
SATA_DTX_IRX_N2_C C2466 2 0.01U_0402_16V7K SATA_DTX_IRX_N2_R
Title
A_PRE1
18
19
GND RX_2N 12
11 SATA_DTX_IRX_P2_C C2465
1
1 2 0.01U_0402_16V7K SATA_DTX_IRX_P2_R
21
GND
PAD
RX_2P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL WLAN
and WWAN/mSATA Rev
SN75LVCP412ARTJR_QFN20_4X4 Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
INT_KBD Conn. Click pad Track point

PN:SP01001AL00 PN:SP01001CH00
+5VS
JCP1
1 1
R2469 1 2 0_0402_5% 2
PN:SP01000YH00 +5VS
(11,12,14,38) SMB_CLK_S3
TP_DETECT
TP_DATA2
3
2
3 C2508
1
4 4
LEFT C2467 1 2 @100P_0402_50V8J JKB1 TP_CLK2 5 0.1U_0402_16V4Z
KSI1 R2479 5 2
1 1 (11,12,14,38) SMB_DATA_S3 1 2 0_0402_5% 6 6
MIDDLE C2468 1 2 @100P_0402_50V8J KSI7 2 7
KSI[0..7] KSI6 2 CP_RESET# 7 JTP1
A
KSI[0..7] (41) 3 3 (41) CP_RESET# 8 8
A
RIGHT C2469 1 2 @100P_0402_50V8J KSO9 4 TP_CLK 9 11 TP_DATA2 1
KSO[0..17] 4 (41) TP_CLK 9 GND 1
KSI4 5 TP_DATA 10 12 TP_RESET 2
KSO[0..17] (41) 5 (41) TP_DATA 10 GND (41) TP_RESET 2
KSI5 6 MIDDLE 3
KSO0 6 RIGHT 3
7 7 1 1 4 4
KSI2 8 ACES_51522-01001-001 LEFT 5
KSO2 C2470 8 5
1 2 @100P_0402_50V8J KSO1 C2471 1 2 @100P_0402_50V8J KSI3 9 9
C2474 C2475 CONN@ TP_CLK2 6 6
KSO5 10 100P_0402_50V8J 100P_0402_50V8J 7
KSO15 C2472 10 2 2 @ 7
1 2 @100P_0402_50V8J KSO7 C2473 1 2 @100P_0402_50V8J KSO1 11 11
@ 8 8
KSI0 12 9
KSO6 C2476 KSI2 KSO2 12 9
1 2 @100P_0402_50V8J C2477 1 2 @100P_0402_50V8J 13 13 10 10
KSO4 14 11
KSO8 C2478 14 GND
1 2 @100P_0402_50V8J KSO5 C2479 1 2 @100P_0402_50V8J KSO7 15 15 12 GND
KSO8 16
KSO13 C2480 16
1 2 @100P_0402_50V8J KSI3 C2481 1 2 @100P_0402_50V8J KSO6 17 17
ACES_50524-0100N-001
KSO3 18 CONN@
KSO12 C2482 18
1 2 @100P_0402_50V8J KSO14 C2483 1 2 @100P_0402_50V8J KSO12 19 19
KSO13 20
KSO11 C2484 20
1 2 @100P_0402_50V8J KSI7 C2485 1 2 @100P_0402_50V8J KSO14 21 21
KSO11 22
KSO10 C2486 KSI6 KSO10 22
1 2 @100P_0402_50V8J C2487 1 2 @ 100P_0402_50V8J 23 23
KSO15 24
KSO3 C2488 24
1 2 @100P_0402_50V8J KSI5 C2489 1 2 @100P_0402_50V8J 25 25
M1(Left BUTTON) LEFT 26 TP_CLK TP_DATA2
KSO4 C2490 26
1 2 @100P_0402_50V8J KSI4 C2491 1 2 @100P_0402_50V8J M2(Center BUTTON) MIDDLE 27 27
M3(Right BUTTON) RIGHT 28 TP_DATA TP_CLK2
KSI0 C2492 28 +5VS
1 2 @100P_0402_50V8J KSO9 C2493 1 2 @100P_0402_50V8J KSO16 29 29
KSO17 30 30
2
KSO0 C2494 1 2 @100P_0402_50V8J KSI1 C2495 1 2 @100P_0402_50V8J
31 GND1
KSO16 C2496 1 2 @100P_0402_50V8J 32 R2443 1 @ 2 4.7K_0402_5% TP_CLK2
GND2 D2408 D2409
KSO17 C2497 1 2 @100P_0402_50V8J JAE_FL4S030HA3R3000A-DT R2444 1 @ 2 4.7K_0402_5% TP_DATA2 PJDLC05_SOT23-3 PJDLC05_SOT23-3
@ @
CONN@ R2445 1 @ 2 4.7K_0402_5% TP_RESET
B B
CONN PIN define need double check Reserve for ESD. R2446 1 @ 2 0_0402_5% TP_DETECT
1
R2447 1 2 100K_0402_1% CP_RESET#
PN: SCA00000U10 X 2
Fintek thermal sensor

placed near by TOP DDR3 Audio Board
+3VS +3VS
PN:SP011108040
1
R2448
10K_0402_5%
@
U2407
2
EC_SMB_CK2 JAUD1
1 VDD SMCLK 10 EC_SMB_CK2 (14,22,41)
+5VALW 1 1
REMOTE1+ 2 9 EC_SMB_DA2 2
DP1 SMDATA EC_SMB_DA2 (14,22,41) 2
C 1 3 C
C2498
0.1U_0402_16V4Z
REMOTE1- 3 DN1 ALERT# 8 FAN CONN. 4
5
3
4
REMOTE2+ R2450 1 @ 5
4 DP2/DN3 THERM# 7 2 MAINPWON (41,44,45,47) (35) HP_OUTL 6 6
2 0_0402_5%
(35) HP_OUTR 7 7
REMOTE2- 5 6 8
DN2/DP3 GND +5VS 8
(35) EXT_MIC 9 9
(35) PLUG_IN 10 10
F75303M_MSOP10 11 11
Address 1001_101xb (17) USB20_N9 12 12
1
(17) USB20_P9 13 13
R2478 14 14
2nd source 0_0603_5% (17) USB_OC4# 15 15
SA000029210-->EMC1403-2-AIZL-TR @ (41) AOU_EN 16 16
17
2
AOU_CTL1 17
(41) AOU_CTL2 18 18
(41) AOU_CTL3 19 19
20 20
C2499 @ 1 2 1U_0402_6.3V6K AOU_ILIM 21 GND1
BOTTOM DDR3 22 GND2
Close U2407 REMOTE1+
REMOTE1+ ACES_88194-2041
JFAN1
1
C
1
@ C2500 Q2407 +VCC_FAN1
40mil
2 1 1
C2502 2200P_0402_25V7K B MMST3904-7-F_SOT323-3 2 CONN@
(41) EC_TACH
2
2200P_0402_25V7K E 2
(41) EC_FAN_PWM 3
3
2 REMOTE1- REMOTE1- 3
4 4
1 5 G5
C2503 6
1000P_0402_50V7K G6
@ ACES_50273-00401-001
REMOTE2+ 2
1
REMOTE2+
TOP CPU_CORE CONN@
D D
C2504
1
2200P_0402_25V7K C
2 REMOTE2- @ C2505 Q2408
2
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
PN:SP02000U900
2
E
3
REMOTE2-
REMOTE1,2+/-:
Title
Trace width/space:10/10 mil Issued Date 2011/07/12 Deciphered Date 2012/07/01
Trace length:<8" THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL KB/TP/Thermal
Sensor/Audio Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
Power Button Power Button CONN. Finger Print Board
PN:SP01000R400
+3VLP +3VALW
+3VLP
1
1
R114 R113
A R2453 0_0402_5% 0_0402_5% A
100K_0402_5%
@ @
11/21 +3VS
PN:SP01000R400
2
2
JPWR1
1 R2469 JFPB1
ON/OFFBTN# 1
2 2 1 1
J2405 3 3 5 2
ON/OFF (41) 3 G1 (17) USB20_N11 2
1 2 ON/OFFBTN# 1 4 6 3 5
(41) LID_SW# 4 G2 (17) USB20_P11 3 G1
2 51_ON# 4 6
51_ON# (44) 4 G2
2
SHORT PADS ACES_50504-0040N-001
D2412 1 ACES_50504-0040N-001
2
BAV70W_SOT323-3 CONN@ @ D2413 C2512
AZC199-02SPR7G_SOT23-3 0.1U_0402_10V6K
CONN@
1
D 2
1
EC_ON 2 Q2409
(41,47) EC_ON
G 2N7002K_SOT23-3
S
3
1
R2454
100K_0402_5%
2
B B
RJ45 Board
PN:SP01001CB00
TPM
JRJ45
+3VS 1
(14) PCIE_PRX_DTX_N4 1
(14) PCIE_PRX_DTX_P4 2 2
3 3
+3VS +3VALW 4
(14) PCIE_PTX_C_DRX_N4 4
JDB3 (14) PCIE_PTX_C_DRX_P4 5 5
U10 TPM@ 6
C589 1 6
1 SDA VPS 24 2 10U_0603_6.3V6M 1 1 (14) CLK_PCIE_LAN# 7 7
2 10 C645 1 2 0.1U_0402_16V4Z 2 8
SCL VPS 2 (14) CLK_PCIE_LAN 8
3 TPM@ 3 9
VNC 3 (14) LAN_CLKREQ# 9
7 PP VPS1 28 (13,38,41) LPC_FRAME# 4 4 (5,14,17,22,36,38,41) PLT_RST# 10 10
27 SERIRQ 5 11
VPS1 SERIRQ (13,41) (13,38,41) LPC_AD3 5 (41) LAN_WAKE# 11
6 26 LPC_AD0 6 12
DataAvailable VPS1 LPC_AD0 (13,38,41) (13,38,41) LPC_AD2 6 (15) PCIE_WAKE# 12
9 23 LPC_AD1 7 13
AcceptCmd VPS1 LPC_AD1 (13,38,41) (13,38,41) LPC_AD1 7 (14) PCH_LAN_25M 13
C 22 LPC_FRAME# 8 14 C
VPS1 LPC_FRAME# (13,38,41) (13,38,41) LPC_AD0 8 (15,41,44) ACIN 14
4 20 LPC_AD2 PLT_RST# 9 +3VS 15
GND1 VPS1 LPC_AD2 (13,38,41) 9 15
11 17 LPC_AD3 10 16
GND2 VPS1 LPC_AD3 (13,38,41) (17,38) CLK_PCI_DB 10 16
18 GND3 (38,41) EC_TX_P80_DATA 11 11 GND 13 +3VALW 17 17
NC 25 (38,41) EC_RX_P80_CLK 12 12 GND 14 +RTCBATT 18 18
5 21 CLK_PCI_TPM 19
NC NC CLK_PCI_TPM (17) GND
8 NC NC 19 20 GND
12 15 PM_CLKRUN# CLK_PCI_DB ACES_85201-1205N
NC NC PM_CLKRUN# (15)
13 ACES_50506-01841-P01
NC PLT_RST# ME@
14 NC LRESET# 16 PLT_RST# (5,14,17,22,36,38,41)
CONN@
ST33ZP24AR28PVSC TSSOP 28P C5109
12P_0402_50V8J
TPM@
Debug Conn. @
CLK_PCI_TPM R317 1 2 C159 1 2
10_0402_5% 22P_0402_50V8J
TPM@ TPM@
D RF 11/17 D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR Button/Power OK/RJ45
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
+3VALW 3.3V +/- 5%

+3VLP +3VALW +3VALW_EC +3VLP +EC_AVCC Vcc
R2210 100K +/- 1%
1
R310 1 @ 2 0_0603_5% R2210 Board ID min typ
100K_0402_1%
R2213 VAD_BID V AD_BID VAD_BID max Phase
R313 1 2 0_0603_5% 0K +/- 5%
0 0 V 0 V 0 V SVT
2
11/21 BRDID 4.7K +/- 5%
+3VALW_EC 1 0.141 V 0.148 V 0.155 V SIT2
1
+3VALW_EC 8.2K +/- 5%
L2201 1 2 0_0603_5% R2213
2 0.216 V 0.250 V 0.289 V SIT1
+EC_AVCC
C2203
0.1U_0402_16V4Z
C2204
0.1U_0402_16V4Z
C2205
0.1U_0402_16V4Z
C2206
0.1U_0402_16V4Z
C2208
1000P_0402_50V7K
C2207
1000P_0402_50V7K
0_0402_5% 3 18K +/- 5% 0.436 V 0.503 V 0.538 V FVT
1 1 1 1 1 1 1 1
C2201 C2202 33K +/- 5%
4 0.712 V 0.819 V 0.875 V SDV
2
0.1U_0402_16V4Z 1000P_0402_50V7K
A A
2 2 2 2 2 2 2 2
L2202 1 2 0_0603_5% ECAGND SD028330280 S RES 1/16W 33K +-5% 0402
111
125
SD028180280 S RES 1/16W 18K +-5% 0402
22
33
96
67
9
U2201
SD028820180 S RES 1/16W 8.2K +-5% 0402
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
SD028470180 S RES 1/16W 4.7K +-5% 0402
1 21 LOGO_LED
(18) GATEA20 GATEA20/GPIO00 GPIO0F
KB_RST# 2 23 BEEP#
(18) KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# (35)
3 26 ODD_DETECT# LOGO_LED#
(13,40) SERIRQ SERIRQ GPIO12 WLAN_WAKE# (38) LOGO_LED# (32,36)
4 27 ACOFF
(13,38,40) LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF (44,46)
LPC_AD3 5
(13,38,40) LPC_AD3 LPC_AD3
1
LPC_AD2 7 PWM Output
(13,38,40) LPC_AD2 LPC_AD2 D
LPC_AD1 8 63 BATT_TEMP Q2104
+3VALW_EC (13,38,40) LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP (45)
11/21 LPC_AD0 10 LPC & MISC 64 LOGO_LED 2 2N7002K_SOT23-3
(13,38,40) LPC_AD0 LPC_AD0 GPIO39 GS_VOUTX (36)
65 G
ADP_I/GPIO3A ADP_I (45,46)
CLK_PCI_EC 12 AD Input 66 S
(17) CLK_PCI_EC CLK_PCI_EC GPIO3B GS_VOUTY (36)
13 75 BRDID
(5,14,17,22,36,38,40) PLT_RST#
3
R2205 1 PCIRST#/GPIO05 GPIO42
2 47K_0402_5% EC_RST# 37 EC_RST# IMON/GPIO43 76 IMVP_IMON (52)
EC_SCI# 20
(18) EC_SCI# EC_SCII#/GPIO0E +3VALW_EC
1 ADP_PROTECT 38
(45) ADP_PROTECT GPIO1D
DAC_BRIG/GPIO3C 68 AOU_CTL2 (39)
C2210 70
EN_DFAN1/GPIO3D PCH_PWR_EN# (42)
0.1U_0402_10V6K DA Output 71 LID_SW# R2203 1 2 100K_0402_5%
2 IREF/GPIO3E AOU_CTL3 (39) Muxless_STAT
KSI0 55 72 AOU_ILIM
KSI0/GPIO30 CHGVADJ/GPIO3F SPK_RT_DET# (35)
KSI1 56
KSI2 KSI1/GPIO31 +3VS
57 KSI2/GPIO32
C2209 1 2 R2201 1 2 CLK_PCI_EC KSI3 58 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# (35)
22P_0402_50V8J 10_0402_5% KSI4 59 84 USB_ON#
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# (37)
KSI5 60 85 SPK_RT_DET# R2216 1 @ 2 10K_0402_5%
KSI5/GPIO35 CAP_INT#/GPIO4C AOAC_WLAN (38)
RF KSI6 61 PS2 Interface 86
KSI6/GPIO36 EAPD/GPIO4D EAPD (35)
KSI7 62 87 TP_CLK
B KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK (39) B
KSO0 39 88 TP_DATA +3VALW
KSO[0..17] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA (39)
KSO1 40
(39) KSO[0..17] KSO1/GPIO21
KSO2 41
KSI[0..7] KSO3 KSO2/GPIO22
(39) KSI[0..7] 42 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 97 CPU1.5V_S3_GATE (9)
KSO4 43 98 Turbo_V R2217 1 @ 2 47K_0402_5%
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET (22,51)
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99
NTC_V
ME_FLASH (13)
EC_MUTE# R2202 1
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 NTC_V (45) 2 10K_0402_5%
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27 NTC_V R2206 1 @
47 KSO8/GPIO28 2 10K_0402_5%
KSO9 48 119
KSO9/GPIO29 SPIDI/GPIO5B M_PWR_ON (42,55)
KSO10 49 120 AOU_CTL1 HDD_DETECT# R2204 1 2 100K_0402_5%
KSO10/GPIO2A SPIDO/GPIO5C PCH_SLPA# (15)
KSO11 50 SPI Flash ROM 126 BATT_LEN#
KSO11/GPIO2B SPICLK/GPIO58 BATT_LEN# (45)
KSO12 51 128 BM# ADP_PROTECT R2207 1 @ 2 100K_0402_1%
KSO12/GPIO2C SPICS#/GPIO5A BM# (46,47)
KSO13 52
KSO14 KSO13/GPIO2D BM# R2208 1 @
53 KSO14/GPIO2E 2 100K_0402_1%
KSO15 54 73
KSO15/GPIO2F ENBKL/GPIO40 ENBKL (16) +5VALW
KSO16 81 74
KSO16/GPIO48 PECI_KB930/GPIO41 ADP_ID (44)
KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG (46)
90 USB_ON# R2209 1 2 10K_0402_5%
BATT_CHG_LED#/GPIO52 AOU_EN (39)
CAPS_LED#/GPIO53 91 mSATA_DETEC# (18)
EC_SMB_CK1 77 GPIO 92
(45,46) EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 HDD_DETECT# (36) +5VS
EC_SMB_DA1 78 93
(45,46) EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 CP_RESET# (39)
EC_SMB_CK2 79 SM Bus 95 SYSON
(14,22,39) EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON (42,48)
EC_SMB_DA2 80 121 TP_CLK R2211 1 2 4.7K_0402_5%
(14,22,39) EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON (52)
PM_SLP_S4#/GPIO59 127 PM_SLP_S4# (15)
TP_DATA R2212 1 2 4.7K_0402_5%
6 100 BATT_TEMP C2211 1 2 100P_0402_50V8J

(15) PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# (15)
14 101 EC_WAKE# Pull Up (40k)
(15) PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_WAKE# (18)
EC_SMI# 15 102 ACIN C2212 1 2 100P_0402_50V8J
(18) EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V (45)
16 103 H_PROCHOT#_EC R2243 1 @ 2 0_0402_5%
(32) CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT (45)
17 104 MAINPWON_R R2215 1 @ 2 0_0402_5% SA_PGOOD C2510 1 2 0.1U_0402_10V6K
(39) TP_RESET GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON (39,44,45,47)
18 GPO 105 BKOFF#
(36) GS_ON# GPIO0C BKOFF#/GPXIOA08 BKOFF# (32)
ODD_DA# 19 GPIO 106 PBTN_OUT#
(38) RF_OFF# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# (5,15)
C EC_INVT_PWM +VSB_EN 25 107 C
(45) +VSB_EN EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_APWROK (15)
EC_TACH 28 108 SA_PGOOD
(39) EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD (49)
EC_PME# 29
EC_TX_P80_DATA EC_PME#/GPIO15
(38,40) EC_TX_P80_DATA 30 EC_TX/GPIO16
EC_RX_P80_CLK 31 110 ACIN VR_HOT# R2214 1 @ 2 0_0402_5%
(38,40) EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN (15,40,44) (45,52) VR_HOT# H_PROCHOT# (5)
PCH_PWROK 32 112 EC_ON
(15) PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON (40,47)
EC_FAN_PWM 34 114 ON/OFF
(39) EC_FAN_PWM SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF (40)
1
36 GPI 115 LID_SW#
(36) GS_SELFTEST NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# (40) D
116 SUSP# Q2202
SUSP#/GPXIOD05 SUSP# (9,24,42,46,48,50,51)
117 PM_SLP_SUS#_R R2244 1 @ 2 0_0402_5% H_PROCHOT#_EC 2 2N7002K_SOT23-3
GPXIOD06 PM_SLP_SUS# (15)
118 EC_PECI R2245 1 2 43_0402_1% G
PECI_KB9012/GPXIOD07 H_PECI (5,18)
AGND/AGND
EC_RTCX1 122 S
R2221 1 @ XCLKI/GPIO5D
2 0_0402_5% SUSCLK_R +V18R
GND/GND
GND/GND
GND/GND
GND/GND
(15) SUSCLK 123 124
3
XCLKO/GPIO5E V18R
1
GND0
1 C2214
1
C2213 4.7U_0805_10V4Z
20P_0402_50V8
R2223 KB9012QF A3 LQFP 128P_14X14 2
11
24
35
94
113
69
100K_0402_5% 2 +3VALW
2
ECAGND
+3VALW
1
R2220
R2225 1 2 47K_0402_5% KSO1 10K_0402_5%
R2227 1 2 47K_0402_5% KSO2
2
(EC_PME#)
R2228 1 2 2.2K_0402_5% EC_SMB_CK1 R2222 1 @ 2 0_0402_5% LAN_WAKE# (40)
R2230 1 2 2.2K_0402_5% EC_SMB_DA1 EC_RTCX1
R2224 1 @ 2 0_0402_5%
R2229 1 @ 2 10M_0402_5% SUSCLK_R
+3VS
@ EC_PME#
S
Y2202 1 3 PCI_PME# (17)
R2452 1 @ 2 10K_0402_5% EC_FAN_PWM Q2203
D 11/14 D
1 2 2N7002K_SOT23-3
R2451 1 2 10K_0402_5% EC_TACH @
G
32.768KHZ_12.5PF_CM31532768DZFT +3VALW
2
R2236 1 2 2.2K_0402_5% EC_SMB_CK2
R2237 1 2 2.2K_0402_5% EC_SMB_DA2 1 1

C2218 C2219
C2220 @ 1 2 100P_0402_50V8J EC_SMB_CK2 18P_0402_50V8J 18P_0402_50V8J
@ @
C2221 @ 1 2 100P_0402_50V8J EC_SMB_DA2 2 2 Security Classification Compal Secret Data
Title
R2239 1 2 10K_0402_5% PCH_PWROK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL EC ENE-KB9012
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
VL +5VALW
+5VALW TO +5VS +3VALW TO +3VALW(PCH AUX Power)
11/14
1
+5VALW +5VS @ R2308 R2303
U2301 100K_0402_5% 100K_0402_5%
AP4800BGM-HF_SO-8 Short J2301 for PCH VCCSUS3.3
2
8 1 SUSP
(9,24,50,51) SUSP
7 2
C2301
10U_0603_6.3V6M
C2302
10U_0603_6.3V6M
C2303
10U_0805_10V4Z
C2304
10U_0603_6.3V6M
6 3 +3VALW +3V_PCH L
1
1 1 5 1 1
R2304 D
J2301
470_0603_5% 40mil 40mil 2 Q2302
(9,24,41,46,48,50,51) SUSP#
4
@ @ 1 2 G 2N7002K_SOT23-3
2 2 2 2 1 2
A S A
1
C2306
10U_0603_6.3V6M
C2308
1U_0402_6.3V6K
H
3
JUMP_43X79 R2306
1 1
1
@ 10K_0402_5%
20mil 10mil
R2313 Q1409 +3V_PCH@ R2318
+3V_PCH@
+3V_PCH@
+VSB R2301 1 2 150K_0402_5% 1 2 5VS_GATE AO3413_SOT23-3 20K_0402_5%
2
82K_0402_5% D 2 2
D
2 SUSP 3 1 @
2
1
1
C2309 G
D 0.01U_0603_25V7K S Q2303
SUSP 2N7002K_SOT23-3
G
2
2
G @
Q2301 S
2N7002K_SOT23-3 +3V_PCH@
3
(41) PCH_PWR_EN# R171 1 2 0_0402_5%
1
C2322
0.1U_0603_25V7K
@
2
+3VALW TO +3VS
+3VALW U2302 +3VS
AP4800BGM-HF_SO-8 11/21
8 1
C2310
10U_0603_6.3V6M
C2311
10U_0603_6.3V6M
7 2 C2312
10U_0603_6.3V6M
C2313
10U_0603_6.3V6M
1 1 6 3
1
5 1 1
R2309
470_0603_5%
4
2 2 @ @
2 2
2
B B
10mil R2321
R2310 2 470K_0402_5% 3VS_GATE
FOR SBA Function POWER(always mount)
20mil +VSB 1 1 2 3
0_0402_5%
6
5 SUSP +3VALW Q2108 SBA@ +3VM

1
C2314 Q2304B AP2301GN-HF_SOT23-3

SUSP 2 0.01U_0603_25V7K 2N7002KDWH_SOT363-6
4
Q2304A 3 1
2
2N7002KDWH_SOT363-6
1
C2327
10U_0603_6.3V6M
C2329
10U_0603_6.3V6M
1
1
1
2
SBA@ R351 SBA@
SBA@ 390_0402_5%
+3VALW VL 2
2
+1.5V to +1.5VS
2
SBA@
R2320 1 2 47K_0402_5%
3
+1.5V U2303 +1.5VS
AP2301GN-HF_SOT23-3 @ R2324
R2319 1 2 47K_0402_5% M_PWR_ON# 1 2 +3VM_GATE
3 1 10K_0402_5% SBA@ 5 M_PWR_ON#
Q2416B
L
6
C2315
C2317
C2319
C2320
10U_0603_6.3V6M
0.1U_0402_16V4Z
10U_0603_6.3V6M
1U_0402_6.3V6K
2N7002KDWH_SOT363-6
4
1
1 1 1 SBA@
1
1
R2311 C2325
2
470_0603_5% (41,55) M_PWR_ON M_PWR_ON 2 0.1U_0603_25V7K

@ Q2416A SBA@
2
2
2 2 2 2N7002KDWH_SOT363-6
from EC
2
1
SBA@
H 11/14
C 10mil C
R2322
+3VALW R2312 1 2 100K_0402_5% 1 21.5VS_GATE
20mil 0_0402_5%
1
C2321
0.1U_0603_25V7K
D
1 2 SUSP
G
1
S Q2311
D 2N7002K_SOT23-3
3
SUSP# 2 @
(9,24,41,46,48,50,51) SUSP# 2
G
Q2306 S
2N7002K_SOT23-3
3
+1.5V +5VALW
1
+0.75VS +1.05VS +1.8VS

R2317 R2305
470_0603_5% 100K_0402_5%
1
@ @
R2314 R2315 R2316
2
22_0603_5% 470_0603_5% 470_0603_5% SYSON#

@ @
1 2
1 2
1 2
D D
D D D
2 SUSP 2 SUSP 2 SUSP SYSON# 2 5 SYSON
SYSON (41,48)
1
G G G Q2310A Q2310B
S Q2307 S Q2308 S Q2309 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 R2307
1
2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3 @ @ 10K_0402_5%

3
@ @ @
2
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DC Interface
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
1 2 3 4 5
G3 S5 S0
RTC
RTCRST
Screw Hole & FD
EC_111 pin
FD1 FD2 FD3 FD4 EC_ON
@ @ @ @ MAINPWON
1
1
A A
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
+5VALW
H21 H18 H12 +3VALW/VCCDSW

H_4P0N H_4P0N H_2P3
ON/OFF#
@ @ @
1
1
H19 H23 H20 EC_RSMRST#
H_5P2X5P7N H_5P2X5P7N H_2P1N
GPU Screw
H22 PBTN_OUT#
@ @ H_3P3 @
1
H4 H2 H11
H_4P0 H_4P0 H_4P0N SLP_S5#
@
1
@ @ @ SLP_S4#
1
H10 H26
H_2P3 H_2P3 SYSON
@
CPU Screw @ SYSON
1
1
H3 H5 PCH_SLPA#
H7 H_4P0 H_4P0
H_2P3 H25 H27
H_2P3 H_3P5X4P5N M_PWR_ON
@ @
1
@
1
B B
@ @ +3VM
1
1
H8
H9 H_2P3 +1.05VM
H_2P3
@ PCH_APWROK
1
@
1
SLP_S3#
SUSP#
H15
H_2P3 +1.5V_CPU_VDDQ
@ +1.8VS
1
+5VS
H17 H13 H6 H16
H_3P5X4P5N H_2P3 H_2P3 H_2P3 +3VS
@ @ @ @ +1.5VS
1
+0.75VS
+V1.05VS(VCCP)
C C
+VCCSA
SA_PGOOD
VR_ON 99ms
PCH_POK
PCH_CLKOUT
DRAMPWROK
H_CPUPWRGD
CPU_VID
CPU_CORE
VGATE
SYS_PWROK
D D
BUF_PLT_RST# ME and BIOS
activity will continue
SPI
DMI Tralning
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Screw
Hole Rev
Custom 1.0
Date:
LA-8133P
1 2 3 4 5
5 4 3 2 1
ADP_ID
PR101 Precharge detector
10K_0402_1% AC Adapter 90W 65W
15.97V/14.84V FOR
680P_0603_50VK
1 2
+3VALW ADP_ID (41) R(K ohm) open 10
0.1U_0402_16V7K
ADAPTOR
A/D ADP_ID(V) 3.3 1.65
1
PC101
PC102
2011_0929 PR103 Detection voltage >2.64 1.32~1.98 2011_0727
2
for 0ohm change to 270ohm del PreCHG PQ102
TP0610K-T1-GE3_SOT23-3
PR102
PR103 1K_1206_5% PD102
D
JDCIN1
1
270_0402_1%
1 2
VIN VS
1 2 2 1 3 1
D
1 APDIN PR104 LL4148_LL34-2
2
2 APDIN1 1K_1206_5%
3 1 2 1 2
3
4 1 2
4
100K_0402_1%
5 PF101 PL101
5
1
100K_0402_1%
7A_24VDC_429007.WRML SMB3025500YA_2P PR105
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
PR106
PR107
ACES_50312-00541-001 1K_1206_5%
2
1 2
1
@
2
2
2
PC103
PC104
PC105
PC106
100K_0402_1%
1
2011_1230
PR108
DDTC115EUA-7-F_SOT323-3
2011_0818 change JDCIN1 PF101 change to SP040002M00 PQ103
1
from SP04107P030 for HF
1 2
PR109
1M_0402_1% 2
1 2 (41,46) ACOFF PQ104
VINDE-2 VIN DDTC115EUA-7-F_SOT323-3
VS
VIN 2
3
0.01U_0402_25V7K
10K_0805_5%
1
1
PC107
PR111
3
PR110 PR112
84.5K_0402_1% 10K_0402_1%
2
C C
1 2
2
ACIN (15,40,41)
PR113
2
22K_0402_1%
VINDE-1 1 2 3
P
+
0.068U_0603_16V7K
1 PACIN
VINDE-3 2
O PACIN (46) B+
-
G
1
20K_0402_1%
10K_0402_5%
0.1U_0402_16V7K
PU101A
1
LM393DG_SO8 2011_1005 PD103 change PR115

4
PC108
PR114
PC109
PR116
4.99M_0402_1%
PD101 Vin Detector form SCSB715F000(S SCH DIO RB715F UMD3)
to SCSB715F010( S SCH DIO RB715FGT106 UMD3) 2 1
2
LLZ4V3B_LL34-2
Min. typ. Max.
2
PR117
2
10K_0402_5% VL
L-->H 17.430V 17.901V 18.384V VS
150K_0402_1%
0.01U_0402_25V7K
2 1 RTCVREF 3.3V
1
H-->L 16.976V 17.262V 17.728V
100K_0402_1%
PR118
1
1
PR119
PC110
2
VIN
2
PD103 PU101B
8
RB715FGT106_UMD3 LM393DG_SO8
2 5
P
+
2 (39,41,45,47) MAINPWON 1 7
O
887K_0402_1%
61.9K_0402_1%
0.01U_0402_25V7K
PD104 3 6
-
1
(46) ACON
0.1U_0603_25V7K
LL4148_LL34-2
1
1000P_0402_50V7K
PR120
PR121
PC113
4
1
1
PD105 PR122
1
PC111
PC112
LL4148_LL34-2 51ON-1 200K_0402_1%
2
BATT+ 2 1 (46,47) PRECHG 2 1
PRG++ 2
2
1
PR123 PR124
B PQ101 68_1206_5% 68_1206_5% B
2N7002KW_SOT323-3
TP0610K-T1-GE3_SOT23-3
PR125
2
200_0603_5% PR126 PR127
1
CHGRTCP 1 51ON-2 10K_0402_5% D 47K_0402_5%
2 3 1
VS
PQ105
0.22U_0603_25V7K
2 1 2 2 1
G PACIN (46)
RTCVREF
1
1
S
3
2
LTC015EUBFS8TL_UMT3F
PC114
PR128 PC115 2011_1230

100K_0402_1% 0.1U_0603_25V7K PR120 change to SD034619280 61.9K_0402_1% from SD034205380 205K +-1% 0402
PR121 change to SD034887380 887K_0402_1% from SD034511380 511K +-1% 0402 +5VALW
1
PQ106
PR129 2
PR118 change to SD034150380 150K_0402_1% from SD034499380 499K +-1% 0402
2
22K_0402_1%
1 2 51ON-3
(40) 51_ON#
2011_1005 PQ105 change
form SB000006800(2N7002W T/R7 1N SOT-323)
3
to SB000009Q80( 2N7002KW 1N SOT323-3)
1
RTCVREF
PR131
+CHGRTC 200_0603_5%
PU102 ACIN BATT ONLY
PR132 PR133 BIT3021A-ST9_SOT89-3
3.3V Precharge detector Precharge detector
2
PD106
560_0603_5% 560_0603_5%
CHGRTCIN
+RTCBATT 1 2 1 2 1 2 3
VOUT VIN
2 Min. typ. Max. Min. typ. Max.
1
PC117
RB751V-40_SOD323-2 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
1
GND 1U_0805_25V6K
PC116
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
2
10U_0603_6.3V6M 1
2
2011_1005 PQ106 form

A 2011_0805 A
SB301150000
del PD107,PR134,JRTC1 (S TR DTC115EUA NPN (UMT3))
移移HW小小 change to SB00000RM00
2011_0808 PU102 change
form SA00001PE00(APL5156-33DI-TRL) (S TR LTC015EUBFS8TL NPN UMT3F)
2011_0728 del PR130 and +3VLP to SA00002E280(BIT3021A-ST9)
add PR? 1K_0603_5%
change place for R132,R133, +CHGRTC,PD107 Security Classification Compal Secret Data Compal Electronics, Inc.
Title
RTC Battery THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Vin Detector /Pre-charge
Custom 0.4
Date:
LA-8133P
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2 2
3 EC_SMCA
3 EC_SMDA
4
4
5
5
1
D D
6
6
1
7 PC201 PC202
7
100_0402_1%
100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K
2
GND
9
GND PR202
PR201
2011_1128
2
2
Add OTP
@ PR212 and PR206 unmount
SUYIN_200082GR007M211ZR
2011_0823
For KB930 --> Keep PU201 circuit
change 9P JBATT1 PH1 under CPU botten side :
(Vth = 1.25V)
EC_SMB_CK1 (41,46) CPU thermal protection at 93 +-3 degree C
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
Recovery at 56 +-3 degree C
EC_SMB_DA1 (41,46) PH201, PR205, PR211,PQ201,PR208,PR212
1 2 +3VALW
VL
PR203
6.49K_0402_1% 1 2 2011_0801 add PR227, PQ206,
+3VLP
(41,46) ADP_I
21.5K_0402_1%
<BOM Structure> PR227 place port name"ADP_PROTECT"
1
4.42K_0402_1%
12.7K_0402_1%
2.1K_0402_1%
1
D
PR207
1 2 BATT_TEMP (41) A/D 90W : 6.67K
PR205
PR206
PR204 2
1
ADP_PROTECT (41) @
10K_0402_5%
65W : 1.65K PQ206 G
<BOM Structure> PC203 +3VS S S TR 2N7002KW 1N SOT323-3
2
0.1U_0603_16V7K PU201
2
1 8 NTC_V_1
VCC TMSNS1
100K_0402_1%
C OTP_N_002 C
2 GND RHYST1 7 2 1
PR209
PR208
3 6 Turbo_V_1 10K_0402_1%
(41,52) VR_HOT# OT1 TMSNS2
1
PR210 @ PR230
100K_0402_1%_TSM0B104F4251RZ
4 5 ADP_OCP_2 1 2
+3VALW
1
OT2 RHYST2
1
10K_0402_1%
PH201
PQ201 @PR228
@ PR228 0_0402_5%
2
D G718TM1U_SOT23-8 27.4K_0402_1% 0_0402_5%
PR211
2 ADP_OCP_1
2
OTP_N_003
G
S 2N7002KW_SOT323-3
PR229 +3VLP 2 1
2
1 2 1 2 PR232
1
@ PR212 47K_0402_1%
0_0402_5% @ PR231
0_0402_5%
Turbo_V
(41) PROCHOT
(41)
(41)
NTC_V
1 2 2 1 47K_0402_1%
MAINPWON (39,41,44,47)
2011_0731 add circuit for battery learning function PR213 0_0402_5%
2011_1119 change circuit to unmount from mount
2011_0808
2011_1119 PR227,PQ206
P2 Change PQ201,PR209,PR212 to mount from unmount change place
2011_1005
+3VLP +3VALW
0.01U_0402_25V7K
PH201 form SL200000V00

100K +-1% NCP15WF104F03RC 0402
change to SL200000U00
1
PC207
@
2
VMB2 100K +-1% TSM0B104F4251RZ 0402

@ PR222 PR220
2
100K_0402_1% 100K_0402_1%
PR224 @ PR218 @ @
2
768K_0402_1% 10M_0402_5%
1
1 2 BATT_OUT (46)
B PR219 B
10K_0402_1%
8
1 2 PQ204
1
D 2N7002KW_SOT323-3 PQ202
3
P
+ TP0610K-T1-GE3_SOT23-3
1 2
PR221 O G
2
-
G
2
221K_0402_1%@ PU202A S
3
LM393DG_SO8 B+ 3 1
4
VL +VSBP
100K_0402_1%
+3VLP
0.22U_0603_25V7K
@
1
@ PQ205
1
1
D 2N7002KW_SOT323-3
PR214
PC204
2
2 1 2 PC205
2VREF_8205
2
G PR216 0.1U_0603_25V7K
2
@ PR223 PR226 100K_0402_1% @
S
3
2
10K_0402_1% 100K_0402_1% PR215
2@ 1 @ @ 22K_0402_1%
1
RTCVREF
PR217 1 2
1
PR225 @ 1K_0402_5%
10K_0402_1% 1 2
(47) SPOK
@
(41) BATT_LEN#
PR234
1
1K_0402_5% D PJ201
(41) +VSB_EN 1 2 2 PQ203 @ JUMP_43X39
G 2N7002KW_SOT323-3 1 1
+VSBP 2 2 +VSB
1U_0402_6.3V6K
S
3
1
PC206
2
A A
2011_1005 PQ105 change
form SB000006800(2N7002W T/R7 1N SOT-323)
to SB000009Q80( 2N7002KW 1N SOT323-3)

Title
PWR-BATTERY CONN/OTP
Custom 0.4
Date:
LA-8133P
5 4 3 2 1
5 4 3 2 1
2011_0731 PQ304 form SB00000DL00_AO4407A_SO8
change to SB00000I600_SI4459ADY-T1-GE3_SO8
P3
B+ PQ302
AO4407AL_SO8
PQ303
AO4407AL_SO8
2011_1127
change to
PQ304 from SB00000I600_SI4459ADY-T1-GE3_SO8
P2
SB00000N100 AO4423L 1P SO8
Need EC write ChargeOption() bit[8]=1 1 8 8 1
PQ301 2 7 7 2 BATT+
PQ304 3 6 6 3
AO4407AL_SO8 AO4423L 1P SO8 5 5
PR302
VIN 8 1 1 8
0.01_1206_1% B+
7 2 2 7 SH00000AA00
4
6 3 3 6
49.9K_0402_1%
5 5 1 2 1 4 1 2
VIN
1
PR304
PL301 2 3 PR303
4
1UH_PCMB061H-1R0MS_7A_20% PR305 499K_0402_1%
47K_0402_1%
@ 10U_0805_25V6K
@ 10U_0805_25V6K
2200P_0402_50V7K
PQ305
change to SD028470280_47K_0402_5%
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D 1 2 D
47K_0402_5%
1 2
2
1
2
200K_0402_1%
PQ306
0.1U_0603_25V7K
PC308
1
PR301
PC303
PC304
PC305
PC306
PC307
LTA044EUBFS8TL_UMT3F PC302 2011_0805 change net name
2
PC301
PR306
10K_0402_1%
5600P_0402_25V7K 2011_1005 PQ305, PQ306
LTA044EUBFS8TL_UMT3F
form ACOFF to ACOFF-1
1
SD028200380_200K +-5% 0402
3
form SB00000RL00
change to SB00000RL00
2
PR307
2
2
ACN 2
1DISCHG_G-1
2011_0731 PR301 form
2
2ACOFF-1
2011_0731 PC302 form
1SS355_SOD323-2
SE074222K80_2200P 50V K X7R 0402 2011_1005 PQ301,PQ302,PQ303 PR308
1
change to SE075562K80_5600P_0402_25V7K ACP form SB00000DL00_AO4407A_SO8 200K_0402_1%

change to SB00000DL10(S TR AO4407AL 1P SO8 ) 2011_1005 PQ311 change
1
PD302
form SB000006800
1
P2-1 2011_0801 add PR331, PQ317
0.1U_0603_25V7K
(2N7002W T/R7 1N SOT-323)
2 for battery learning to SB000009Q80
1
PQ307 D
( 2N7002KW 1N SOT323-3)
1
+3VALW PC309 PC310 2
1
LTC015EUBFS8TL_UMT3F 2 1 2 G PRECHG (44,47)
2011_1005 PQ307 PR331 1 2 2 1 S
3
3
form SB301150000 20K_0402_1% 2011_0728 numount 2011_1005 PQ312 PD303 PQ309
change to 1 2 PR315,PR316, HW端端PU 0.1U_0603_25V7K change form TPC8037-H 1SS355_SOD323-2 2N7002KW _SOT323-3
6
PQ317 PQ308
0.1U_0603_25V7K
SB00000RM00 to TPC8065-H_1N_SOP-8
3
1
D
150K_0402_1%
2N7002KW _SOT323-3 PC312 LTC015EUBFS8TL_UMT3F
1
D
PR309
PC311
PQ310A @ 2 BATT_OUT (45)
2 2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K BQ24727VCC 2 PACIN
S 2011_0915 del G
3
2
@ @ PR310,PR311 2 1 2011_1005 PQ308 S 2011_1005 PQ309
1
3
VIN PR312,PR313 form SB301150000 form SB301150000
10K_0402_5%
10K_0402_5%
@ H_PROCHOT#,+3VALW change to change to
5
6
7
8
432K_0603_1% SB00000RM00 SB00000RM00
1
P2-2
PQ312
PR315
PR316
10_1206_5%
TPC8065-H_1N_SOP-8
2
C C
PR314
2N7002KDW-2N_SOT363-6
PR317
2011_0829 PQ311
3
PQ310B
change part 2N7002KW _SOT323-3
ACOK
CMPIN
CMPOUT
ACP
ACN
1
1
PR318 PR319 (41,45) ADP_I 4 2011_1207
2
47K_0402_1% 64.9K_0603_1% 21 PR303 change to 499k from 100k
1
PACIN TP
(44) PACIN 1 2 5 1 2 6 ACDET PC314 PR304 change to 10k from 49.9k
PL302
1 2 @ PC313 20 BQ24727VCC-1 1 2 10UH +-20% MMD-10DZ-100M-X1 6A PR320
4
3
2
1
VCC 0.01_1206_1%
(44) ACON 1 2 7 IOUT
PC323 0.1U_0603_25V7K
1U_0603_25V6 BA+
1
PQ313 100P_0603_50V8 19 LX_CHG 1 2 CHG 1 4

LTC015EUBFS8TL_UMT3F (41,45) EC_SMB_DA1 PU301 PHASE
8
change to SD014649280_64.9K_0603_1%
SDA
BQ24737RGRR_VQFN20_3P5X3P5 2 3
PR321 18 DH_CHG
HIDRV
1
2ACOFF-12 (41,45) EC_SMB_CK1
4.7_1206_5%
(41,44) ACOFF 1 9 SCL SA000051W00
5
6
7
8
PR322
10K_0402_5% PR324
PQ314
2011_0818 PR323 2.2_0603_5%
TPC8A03-H_SO8
1
SD00000Z480_66.5K_0603_0.1%
BST_CHG SRP SRN
10U_0805_25V6K
10U_0805_25V6K
add PC323 1 2 10 ILIM BTST 17 1 2 2 1
1
@ PR332 with unmount +3VALW 316K_0402_1%

3
PD301
2
0_0402_5% PC315
LODRV
1
PC316
PC317
PR325 16 2 1 0.047U_0603_25V7M 4
GND
SRN
SRP
24727_SN
REGN
BM
100K_0402_1% 2011_1129
2N7002KW_SOT323-3
2
2011_0731 PR319 form
2011_0830
RB751V-40_SOD323-2 Change 2.2
2
2
@ PQ318
680P_0603_50V7K
11 change PL302
1 12
13
14
15
1
1
D
10_0603_5%
6.8_0603_5%
for height
3
2
1
PR327
2 PC318
(45) BATT_OUT 2011_1127
1
PR326
G PR333 1U_0603_25V6
2
S 2011_0728 add charger @ 0_0402_5% Change from SH00000LI00 4.7u to SH000009R00
3
10UH +-20% MMD-10DZ-100M-X1 6A
PC319
turbo boost function 2011_0829
2
2
2011_0801 add PR332, PQ318 1 2 change part
2
for battery learning PC320 DL_CHG

2011_1122
2
B
2011_1119 change PR332,PQ318 to unmount from mount 0.1U_0603_25V7K B
Add PR333 BM# (41,47)
@ 2 1
PR330
CHGVADJ=(Vcell-4)/0.10627 2011_1210 10K_0402_5%
PR330,PR333 @ for lid wake up from S4
1
Vcell CHGVADJ 2011_1005 PQ313
1
form SB301150000 PC321 @ 2011_0831 PQ314
4V 0V change to 0.1U_0603_25V7K PC322 change form AO4466L
2
SB00000RM00 2 0.1U_0603_25V7K to TPC8A03-H

4.2V 1.882V +3VS
4.35V 3.2935V PQ315 TP0610K-T1-GE3_SOT23-3
3 1 BQ24727VCC
CC=0.25A~3A P2
1
100K_0402_1%
IREF=1.016*Icharge
PR328
IREF=0.254V~3.048V
VCHLIM need over 95mV PR329 2011_1005 PD103 change
2
2 1 form SCSB715F000(S SCH DIO RB715F UMD3)

to SCSB715F010( S SCH DIO RB715FGT106 UMD3)
1
100K_0402_1%
PQ316
LTC015EUBFS8TL_UMT3F 2 FSTCHG
2 1
FSTCHG (41)
3 SUSP#
2011_1005 PQ316 SUSP# (9,24,41,42,48,50,51)
A form SB301150000 A
change to PD304
3
RB715FGT106_UMD3
SB00000RM00

Title
CHARGER
0.4
Date:
LA-8133P
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ402
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118
1U_0603_10V6K
D D
1
PJ403
PC402
+5VALW P 2 1 +5VALW
2
2 1
@ JUMP_43X118
2011_0829
PR406 adj
3.3V OCP PR402 PR403
13K_0402_1% 30K_0402_1%
1 2 1 2
PR404 PR405
RT8205_B+ Typ: 175mA 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2 2011_0826 add
PJ401 +3VLP PQ408 +3VLPP for EMI
FDV301N_NL_SOT23-3~D
B+ 2 1
2 1
ENTRIP2
ENTRIP1
S
D
@ JUMP_43X118 3 1 PR406 PR407 2011_1005 PQ402
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2011_0826 add 137K_0402_1% 71.5K_0402_1%
PC423
PC425
change form TPC8037-H
68P_0402_50V8J
68P_0402_50V8J
PC403
PC410
for EMI (44,46) PRECHG 1 2 1 2
4.7U_0805_10V6K
to TPC8065-H_1N_SOP-8
1
1
PC404
PC405
PC406
PC407
PC408
PC409
G
2
8
7
6
5
5
6
7
8
PU401
2
2
PC411
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C PQ401 2011_0829 C
2200P_0402_50V7K
0.1U_0603_25V7K
TPC8065-H_1N_SOP-8
PQ402
2011_1129
PC424
25 PR407 adj
68P_0402_50V8J
.1U_0402_16V7K
P PAD
PC427 @
AO4466L_SO8
PC401
Change 2.2 5V OCP
2
1
1
PC422
4 4
7 VO2 VO1 24
SPOK (45)
2
2
2011_1127 0.1U_0603_25V7K 8 23 PR409 PC413 2011_0829 change part
PC412 PR408 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
Change PL401 from SH000006J80 to SH00000PG00
1
2
3
3
2
1
4.7UH +-20% PCMB063T-4R7MS 5.5A 1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL401 UG_3V 10
VFB=2.0V 21 UG_5V PL402
4.7UH +-20% PCMB063T-4R7MS 5.5A UGATE2 UGATE1 4.7UH_20%_VMPI1004AR-4R7M-Z01_10A
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
8
7
6
5
1
2011_0826 add LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 LGATE2 LGATE1 19
5
6
7
8
PQ403 2011_1005 for S5
PR401
PR410
for EMI
SKIPSEL
AO4712L_SO8 add PR417 2011_1129
VREG5
PQ404
PR417 Change 2.2
GND
VS
VIN
NC
499K_0402_1% RT8205EGQW _W QFN24_4X4
EN
1 1
2
2
4 1 2
+ PC414 4 + PC415
13
14
15
16
17
18
1
1
150U_B2_6.3VM_R45M PR411 150U_B2_6.3VM_R45M
680P_0603_50V7K
TPC8A03-H_SO8
499K_0402_1%
680P_0603_50V7K
2 2
PC416
PC417
1 2
2
1
2
3
2
2011_1005 PQ403
B+
3
2
1
form SB00000AJ00(S TR AO4712 1N SO8) @
1
100K_0402_1%
1U_0603_10V6K
change to SB00000AJ10(S TR AO4712L 1N SO8) VL
1
PC418
1
PR412
PC419
Typ: 175mA
4.7U_0805_10V6K
B 2011_1215 B
2
Change PR418 to 20.5k SD034205280 2011_0826 ENTRIP1 ENTRIP2 2011_0826
2
2
from 2.2k SD028220180 mount for EMI mount for EMI
RT8205_B+
2012_01_03
6
1
Change PR418 to 47K SD034470280 PQ405B
PQ405A 2N7002KDW -2N_SOT363-6
0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205 +3.3VALWP OCP(min)=5.81A
2
PC420
+5VALWP OCP(min)=8.44A
(40,41) EC_ON
1
PR418
1 2
47K_0402_1%
PR413
100K_0402_1%
2 1
VL
(39,41,44,45) MAINPWON PR414
0_0402_5% 2011_1005 PQ406
2 1 form SB301150000
2011_1122 change to
1
Add PR419,PR420,PC426,PQ407 SB00000RM00
PR420 VS
+3VLP 100K_0402_1% 1 2 2 PQ406
2 1 LTC015EUBFS8TL_UMT3F
PR415
40.2K_0402_1%
1U_0603_10V6K
A A
1
PQ407 100K_0402_1%
1
2012_0103
PR416
PC421
2N7002KW _SOT323-3 @
3
PR419 Change PC421 to 1u SE080105K80 from 4.7u

1
0_0402_5% D
2
2 1 2
2
2
G
S
3
PC426 Title
1
0.1U_0603_25V7K @
6) BM# 2011_1116 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
PR415,PR416=>@ Size Document Number Rev
Custom 0.4
Add PR418 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Date: Friday, January 13, 2012
LA-8133P
Sheet 47 of 58
5 4 3 2 1
A B C D
PJ501
1.5V_B+ 2 2 1 1 B+
2011_1005 PQ501
2200P_0402_50V7K
68P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5
6
7
8
change form TPC8037-H @ JUMP_43X118
1
PC502
PC503
PC504
PC505
PC519
to TPC8065-H_1N_SOP-8
2
4
2011_0826 add
2011_1129 PQ501 for EMI
Change 2.2
TPC8065-H_1N_SOP-8
3
2
1
1
PR502 PC506 PL501 1
100K_0402_1% PU501 2.2_0603_5% 0.22U_0603_16V7K 1UH_+-20%_MMD-10DZ-1R0M-X1A_18A

PR503 1 PGOOD VBST 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP
PR501 2 1 2 9 DH_1.5V 2011_0829
0_0402_5% TRIP DRVH
change part
LX_1.5V
4.7_1206_5%
1 2 3 EN SW 8
1
(41,42) SYSON 1 220U_6.3V_M_F45_R18M_PXK
5
6
7
8
4 VFB V5IN 7 +5VALW
2
@
+
PR504
47K_0402_5%
PQ502 PC508
.1U_0402_16V7K
1
PC501 @
1 PR5062 5 6 DL_1.5V +1.5VP OCP(min)=15.6A
RF DRVL
1
PC507
2
2
PR505
470K_0402_1% 11 1U_0603_10V6K
2
TP PJ502
1000P_0603_50V7K
4
1
2 TPS51212DSCR_SON10_3X3 2 2 1 1
1
VFB=0.7V
PC509
@ JUMP_43X118
2011_1129
3
2
1
2
PR507 change from 11.5K to 11.8K SD034118280 PJ503 +1.5V
TPC8A03-H_SO8 +1.5VP 2 1
2011_0829 2 1
mount for EMI @ JUMP_43X118
PR507
1 2
1 11.8K_0402_1% 2011_1007 PL501

form SH000004S00(S COIL 1.0UH +-20% PCMC104T-
PR508 1R0MN 20A) change to SH00000CN00(S COIL 1UH +-
10K_0402_1%
20% MMD-10DZ-1R0M-X1A 18A)
2
2 2
3 3
2011_0801 JP504 form

43x118 change to 43x79
PU502 PL502
4
PJ504 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW
PG
2 1 PVIN LX +1.8VSP
@ JUMP_43X79 2011_0801 JP505 form
68P_0402_50V8J
9 PVIN LX 3
1
1
680P_0603_50V7K 4.7_1206_5%
43x118 change to 43x79

1
1
PC510 8 PC511 2011_0826 add
SVIN
PR509
22U_0805_6.3VAM PR510 for EMI

20K_0402_1%
2200P_0402_50V7K
68P_0402_50V8J
0.1U_0402_25V6
6
2
FB 2
22U_0805_6.3VAM
22U_0805_6.3VAM
5
1 2
EN
1
PC516
PC518
PC517
NC
NC
PJ505
TP
PC513
PC514
FB=0.6Volt +1.8VSP 2 1 +1.8VS
2 1
(9,24,41,42,46,50,51) SUSP#
PC512
PR511
11
2
1 2 EN_1.8VSP @ JUMP_43X79
2
0_0402_5%
0.1U_0402_10V7K
2
PC515 @
SY8033BDBC_DFN10_3X3 2011_0826
1
PR512 mount for EMI 1.8VSP max current=4A

1M_0402_5%
1.8VSP_FB
2
<BOM Structure>
1
4
PR513 4
10K_0402_1%
2011_0829
2
change and mount

Title
PWR-+1.5VP/+1.8VSP
Custom 0.4
LA-8133P
Sheet 48 of 58
A B C D
5 4 3 2 1
+3VS PR602
1K_0402_5%
2 1
VID [0] VID[1] VCCSA Vout PJ602
+VCC_SAP
100K_0402_5%
0 0 0.9V H_VCCSA_VID1 (9) +VCCSAP 2
2 1
1 +VCCSA
1
TDC 4.2A
@ JUMP_43X118
PR603
0 1 0.8V Peak Current 6A
1 0 0.725V OCP current 7.2A
2 +VCCSA_PWRGD
H_VCCSA_VID0 (9)
1 1 0.675V
PR604
(41) SA_PGOOD
1K_0402_5%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
+VCCSA_VID0
+VCCSA_VID1
+5VALW VCCSA VID is 00 prior to VCCIO stability.
1U_0603_10V6K
2
PC602
PR601 PR605
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2 1.05VS_VCCP_PWRGOOD (50)
PC603
2.2U_0603_10V7K
1 2
2011_0818 change VCCSA of enable name
2011_0826 add
18
17
16
15
14
13
PU601 for EMI
PR606 PC604
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
0_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL601
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND
22U_0805_6.3V6M
0.1U_0402_10V7K
1
PC620
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
68P_0402_50V8J
2200P_0402_50V7K
SW
2200P_0402_50V7K
21 PR607 @
0.1U_0603_25V7K
PGND
1
10U_0805_6.3V6M
10U_0805_6.3V6M
4.7_1206_5%
PC605
PC608
PC609
PC611
PC612
TPS51461RGER_QFN24_4X4
PC607
PC610
9
SW
22
PC613
1 2 2
2
2
VIN
PC601
PC614
PC615
8
SW
23
1
1
2 1 1 VIN PC616
PJ601 7 1000P_0603_50V7K
+3VALW 2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
SW
2011_0826 2011_0929 2011_1012
2
2 1 VIN
mount for EMI del PC606 PC607 PC610 mount for RF
C @ JUMP_43X118 25 C
(22U_0805_6.3V6M)
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
@ PR608
2 1
33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K
0.01U_0402_25V7K
2
2 1 2 1
PR611
PC619
PC618 PR610 0_0402_5%
1
3300P_0402_50V7K 10K_0402_5% 2 1 +VCCSA_SENSE (9)
2011_0801 del +V1.05S_VCCPP circuit

B B
A A

Title
PWR +VCCSAP/1.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.4
LA-8133P
Sheet 49 of 58
5 4 3 2 1
5 4 3 2 1
+1.5V
1
2011_0801 JP701 size form 2011_1127 PU701
PJ701 43x118 change to 43x39 Change from SA00002XR00 to SA00002XR10
1
D JUMP_43X39 D
@
22
PU701
1 VIN NC 8 +3VALW PJ702
+0.75VSP 2 2 1 1 +0.75VS
PC701 2 7
GND NC
1
4.7U_0805_6.3V6K @ JUMP_43X118
1
2011_1119 3 VREF VCNTL 6 PC702
Change PR702 to 49.9K (SD034499280) PR701
2
from 0 (SD028000080) 1K_0402_1% 4 5 1U_0603_10V6K
VOUT NC
9
2
PQ701 TP PJ703
2N7002KW _SOT323-3 APL5336KAI-TRL_SOP8P8 2 1
2 1
PR702 @ JUMP_43X118
.1U_0402_16V7K
+0.75VSP
1
49.9K_0402_1% D +1.05VS_VCCPP PJ704 +1.05VS
10U_0603_6.3V6M
(9,24,42,51) SUSP
PC705
1K_0402_1%
1 2 2 2 2 1 1
10U_0603_6.3V6M
1
1
PC703
PC704
G
2
S PR703 @ JUMP_43X118
0.1U_0402_10V7K
2
1
PC706
2
2011_0801 del PJ705 and "+V1.05S_VCCP"
2011_1005 PQ701 change
C form SB000006800 C
(2N7002W T/R7 1N SOT-323)

to SB000009Q80
Ivy Bridge CPU ES2 Using
( 2N7002KW 1N SOT323-3)
2011_1127
Change PC711 from Sanyo SF000000S80
to panasonic SF000000I80
+1.05VS_VCCPP OCP(min)=20.75A
2011_0926
change part
to TPC8065
PJ706
del PR705 1.05VS_B+ B+
2 1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 1
B+
68P_0402_50V8J
0.1U_0402_25V6
+3VS @ JUMP_43X118
1
PC709
PC710
PC717
100U_25V_M
1
TPCA8065-H_PPAK56-8-5
5
2011_0801 mount
PC707
PC708
PQ702 +
PC711
PR704, PR706
2
2
PR704 2011_0829 PU702 2011_1129 2011_0826 add

2
100K_0402_5% PN error,change Change 2.2 for EMI
4
PR706
1
0_0402_5%
1 2 PR707 PC712
B (49) 1.05VS_VCCP_PWRGOOD +1.05VS_VCCPP B
PU702 2.2_0603_5% 0.22U_0603_16V7K PL701 2011_0929
3
2
1
1 10 BST_1.05VS_VCCP
1 2 1 2 1UH_+-20%_MMD-10DZ-1R0M-X1A_18A PC1166 non-mount
PGOOD VBST
2 1
PR708 TRIP_1.05VS_VCCP 2 9 DH_1.05VS_VCCP
(9,24,41,42,46,48,51) SUSP# 60.4K_0402_1% TRIP DRVH
1
LX_1.05VS_VCCP PQ703
1000P_0603_50V7K 4.7_1206_5%
1 2 3 EN SW 8
5
@ 10K_0402_1%
2
PR710
4 7
.1U_0402_16V7K
+5VALW 1 1 1
VFB V5IN
1
330U_D2_2VM_R9M
330U_D2_2VM_R9M
330U_D2_2VM_R6M
PR709
0_0402_5%
PC1167
PC1168
PC1166
DL_1.05VS_VCCP + + +
PC713
PR711
5 6
2
RF DRVL
75K_0402_1%
470K_0402_1%
2
11 4
1
TP 2 3 2 3 2 3
PR712
PR713
2
TPS51212DSCR_SON10_3X3
1
VFB=0.7V
PC715
2
3
2
1
1U_0603_10V6K
PC716
2
2
2011_1202
PR708 change from 0 to 60.4K 2011_0815 PC1166, PC1167
PC713 mount 2011_1005 PQ805 change PC1168 change place
2011_1007 PR712 form SB00000Q600(TPCA8059-H_PPAK56-8-5) form"+1.05VS"
form 88.7K change to 75K to SB00000Q400(TPCA8057-H_PPAK56-8-5) to"+1.05VS_VCCPP"
1 2
2011_1005 PC1167,PC1168
PR714 2011_1007 PL701 PR716 @ change to 330U_2V_R9M
1
A
4.99K_0402_1% form SH000004S00(S COIL 1.0UH +-20% PCMC104T- 10_0402_5% A
2 1 VCCIO_SENSE (8)
1R0MN 20A) change to SH00000CN00(S COIL 1UH +-
PR715
10K_0402_1% 20% MMD-10DZ-1R0M-X1A 18A)
2

Title
PWR +1.05VS_VCCPP/+0.75VSP
Custom 0.4
LA-8133P
Sheet 50 of 58
5 4 3 2 1
A B C D
+3VS_VGA 2011_1007
N13M-GE1 +1.05VS +1.05VS_VGA
10K_0402_1% PJ801
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
VID: 0110100
+1.05VS 2 1 +1.05VS_VGA
0.85V +5VALW 2 1
8 1
2
2
7 2 @ JUMP_43X118
2
6 3 @
1
PC801 5 PC802 PC803 PR813 2011_0830
10U_0805_10V6K 470_0603_5% +VGA_B+
change P/N
2
2
TPC8A03-H_SO8 PQ802 10U_0805_10V6K 1U_0603_10V6K PJ802
PR801
PR802
PR803
PR804
PR805
PR806
PR807
PR808
PR809
PR810
PR811
PR812
<BOM Structure>
1
2
PR814 <BOM Structure> PR815 2 1 B+
1
0_0402_5% 2 1
20K_0402_1%
@ @ @ @ @ @ PR816 @ 1 2 @ JUMP_43X118
DGPU_PWROK# (24)
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
1
100K_0402_5% D
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
SUSP
PC873
1 2 2 1 2
SUSP (9,24,42,50)
68P_0402_50V8J
1
PC804 PQ803 G
1
PR818 2011_0727 PR816 0.1U_0603_25V7K PR817 @ 2011_0826 add
PC805
PC807
PC808
S
3
2011_1202 0_0402_5% 2N7002KW_SOT323-3 0_0402_5%
PC806
modfiy 10K to 100K. for EMI
2
1 1
Change PR820 from 0 to 147K (24) DGPU_PWROK# 1 2
2
1
D
PC810 mount
5
PD801
(9,24,42,50) SUSP SUSP 1 2 2
G PQ801 PQ804
RB751V-40_SOD323-2 1 2 PR819 @ 2N7002KW_SOT323-3
S
Confirm with HW
3
0_0402_5% 2011_0728 PL801 and PL802
PR820 (SH00000HK00/0.36uH_10X10X4)
147K_0402_1% 2011_1129 4
(17) NVDD_PWR_EN VRON_VGA
change to (SH00000NX00/0.36uH_7X7X4)
1 2 Change 2.2
2011_0727 add PR868 and PD802 del net name (V2N_VGA and LF2_VGA)
place port DPRSLPVR_VGA 1 2 PR821 PC809
RB751V-40_SOD323-2 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5
2011_0819 unmount PR868
3
2
1
@ BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
(22)
(22)
(22)
(22)
(22)
(22)
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
1 PR822 2
(9,24,41,42,46,48,50) SUSP# @0_0402_5% @2 PR823 1 UGATE2_VGA PL802
1 2 47K_0402_5% 0.36UH 20% PDME064T-R36MS1R405 24A
(22) DPRSLPVR_VGA PR868 0_0402_5% 1 2 PHASE2_VGA 1 2 +VGA_CORE
2
@
10K_0402_1% PC810 .1U_0402_16V7K PR825
5
PR824 1 2 DPRSLPVR_VGA+ 0_0402_5%
10K_0402_1%
3.65K_0805_1%
1
1
2011_0727 modfiy net
2
+3VS @ PR827 PQ805 2011_0728 PR830
PR826
10K_0402_1%
1 1
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
1.91K_0402_1% 1_0402_5%
PR829
PR869
del PQ806
CLK_ENABLE#_VGA + +
PC811
PC812
1 2
LGATE2_VGA 4
2
1
HW端端PU 2011_0929 PR827
GPU_VID6
1
2
2
PR831 2 2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
change to @
@1.91K_0402_1% TPCA8057-H_PPAK56-8-5
PR832
PR833
PR834
PR835
PR836
PR837
VSUM-_VGA
3
2
1
2
2011_0815 PQ805 change VSUM+_VGA ISEN2_VGA ISEN1_VGA

(18,24) DGPU_PWROK
1
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
PR838 2011_0830 2011_0826 add
100K_0402_5%
to SB00000Q400(TPCA8057-H_PPAK56-8-5) @ @
change 1% for feedback
+3VS 1 2 for feedback balance
2011_0929 PR839 balance
2
for 47Kohm change to 147Kohm PR839
147K_0402_1%
+VGA_CORE Under VGA Core 2
PR840
@ 100K_0402_5%
1 2 +VGA_CORE Near VGA Core 2011_1007
PC811, PC812
1
+3VS 1 2 PC815
1U_0603_10V6K
form SGA20331E10
40
39
38
37
36
35
34
33
32
31
1 2 PU801
10uF (330U_D2_2V_Y)
(22,41) VGA_AC_DET
2
change to SGA00002680
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PSI#_VGA
RBIAS_VGA
PR841 @ (330U_D2_2.5VY_R9M)
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
1
1
2011_0727 0_0402_5%
PC816
PC817
PC818
PC819
PC820
PC821
PC822
PC823
30 1
BOOT2
1
PC824
PC825
PC826
PC827
del PC814 29
UGATE2
1 28
2
PGOOD PHASE2
2 27
2
PR842 470K_0402_5%_TSM0B474J4702RE PSI# VSSP2 PR843 2
3 26
RBIAS LGATE2 VCCP_VGA 1
1 2 1 2 4 25 2 +5VS
VR_TT# VCCP 0_0402_5%
5 24
4.02K_0402_1% PH802 VW_VGA NTC PWM3
6 23
COMP_VGA VW LGATE1
2011_0727 7 22
FB_VGA COMP VSSP1
mount PR842,PH802 8 21
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
FB PHASE1
1 2ISEN3_VGA 9
ISEN3
1
1
UGATE1
PC829
PC830
PC831
PC832
PC833
PC834
PC835
PC836
PC837
PC838
PC839
PC840
10
BOOT1
ISUM+
ISEN2
ISEN1
ISUM-
VSEN
IMON
PC828 1U_0603_10V6K 2011_0818 mount for

8.06K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41 PC832, PC833, PC834,

@249K_0402_1%
2
2
AGND
PC841
ISL62883CHRTZ-T_TQFN40_5X5
PC835, PC836.
PR844
PR845
11
12
13
14
15
16
17
18
19
20
PR846
2
499_0402_1% PC842
ISUM-_VGA
1 2FB1_VGA1 2
1
VDD_VGA
RTN_VGA
390P_0402_50V7K
PC843 PR849
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
@0.1U_0402_10V7K
100P_0402_50V8J 1.15K_0402_1% @ PR847 IMON_VGA @ PR848
1
0_0402_5% VSEN_VGA 0_0402_5%
PC846
PC844
PC847
PC848
PC852
PC849
PC845
PC853
1 2 1 2
1 2 PR850 0_0402_5% 1 2
11K_0402_1%
+5VS +5VS
0.047U_0402_16V7-K
2
VIN_VGA 1 2
2
1
For 15W one phase

PC851
PR851
ISEN2_VGA +VGA_B+ GPU_IMON

1 2FB2_VGA1 2 PR853
ISEN1_VGA 1_0402_5%
2
3
PC850 PR852 1 2 +VGA_B+ 3
0.22U_0402_10V6K
0.22U_0402_10V6K
1
1
150P_0402_50V8J 33K_0402_1% +5VS

1
1
PC854
PC855
PC856
PC857
1U_0603_10V6K
0.22U_0603_25V7K
PR854
2011_0829 68.1K_0402_1%
2200P_0402_50V7K
2
BOOT1_VGA
change part 2011_0826 add
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
5
2011_0824
PC874
for EMI
68P_0402_50V8J
PR852 form 267K to 33K PQ807
change form 2011_1129
1
PC842 form 680P to 390P
PC858
VSSSENSEVGA to GND Change 2.2
PC859
PC860
PC861
2011_0728 PL801 and PL802
2
VSUM+_VGA UGATE1_VGA 4 (SH00000HK00/0.36uH_10X10X4)
VSUM-_VGA
change to (SH00000NX00/0.36uH_7X7X4)
1 2
@82.5_0402_5%
+VGA_CORE del net name (V1N_VGA and LF1_VGA)

2011_0929 PR857 PC862
1
PR855 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

PR856
PR855.1 net change form
3
2
1
1
10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%
+VGA_CORE to +VGA_COREP
PR858
PL801
(23) VCCSENSE_VGA 1 2 0.36UH 20% PDME064T-R36MS1R405 24A
2
PHASE1_VGA 1 2 +VGA_CORE
2
PR859
0.1U_0603_25V7K
0.1U_0603_25V7K
VSUM_VGA_N001
1
0_0402_5%
5
NTC_VGA
PC863
1
1
330P_0402_50V7K 2011_0728
PC864
PC865
10K_0402_1%
3.65K_0805_1%
2
1
PR861
del PQ809
10K_0402_1%
1 1
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
PR863
PR870
2
1_0402_5% + +
PR862
PC866
PC867
@0.01U_0402_25V7K
LGATE1_VGA 4
@330P_0402_50V7K
2
1
1
PC869
PC870
11K_0402_1%
2
1
PC868 PH801 2 2
PR864
PR865 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ PQ808

0_0402_5%
2
3
2
1
(23) VSSSENSE_VGA 1 2 TPCA8057-H_PPAK56-8-5 VSUM-_VGA
2
Layout Note:
PR866 PR867 Place near Phase1 Choke VSUM+_VGA ISEN1_VGA ISEN2_VGA
10_0402_5% 806_0402_1% 2011_0815 PQ808 change
4 4
For N13M-GE(15W without turbo) 1 2 1 2 form SB00000Q600(TPCA8059-H_PPAK56-8-5) 2011_0826 add
VSUM-_VGA
to SB00000Q400(TPCA8057-H_PPAK56-8-5) 2011_0830 for feedback 2011_1007
@:PR806,PR812,PC823,PC848,PC849,PR832, 2011_0829 change 1% PC866, PC867
PC801,PC802,PQ801,PQ802,PQ803,PR804,
balance
change part for feedback form SGA20331E10
PC805,PC803,PR808,PR809,PR810,PC807, 2011_0830 PC864 form 0.22U to 0.1U
PC804 balance (330U_D2_2V_Y)
N13M-GE1
1
PC872 PC865 form 0.033U to 0.1U change to SGA00002680

OCP: 28.7A
POP:PR815,PC803 0.1U_0402_16V7K (330U_D2_2.5VY_R9M)
form 1K to 806
2
PR816->120K(SD034120380)
PR820->1.69K(SD00000JB80)
PR822->22K(SD034220280)
Title
PR837->866(SD034866080) Issued Date 2011/07/12 Deciphered Date 2012/07/01
PC858->0.1uF(SE026104M80)
PC859->0.068uF(SE026683K80) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - VGA_COREP
PR850->22.1K(SD034221280) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.4
LA-8133P
Sheet 51 of 58
A B C D
5 4 3 2 1
2011_1007 for function test

1. modify PR903 form 1.21K to 8.2K,
2011_0830 2. PC905 form 4700p to 33n,
PC901,PC905,PR901,PR903,PR904 mount 3. PC901 form 680p to 33n,
4. PR904 form 10.7K to 806,
2011_1119 5. PC907 form 330p to 560p
Change PC901,PC905 to 0.033u (SE076333K80) 6. PC909 form 3300p to 1500p
from 0.033u (SE076333KN0) 7. PC904 form 330p to 820p
8. PR911 form 63.4K to 66.5K
9. PR942 form 4.32K to 6.04K
10. PC927 form 3300p to 2200p
11. PC934 330p to 820p
PC901 2011_0829
PR901 0.033U_0402_16V7 PC909 PC902
1200P_0402_50V7K
1 2 FBA3 1 2 change part 1 2
820P_0402_25V7
D PUT COLSE D
75K_0402_1%
10_0402_1% .1U_0402_16V7K
TO GT
1
PR904 1 PR902 2
PC903
PC904
PR905
TRBSTA# 1 2 FBA1 1 2 PH901 Inductor
2P: 24K 24.9K_0402_1% PR906 PC906
1
1
PR903 806_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
8.2K_0402_1% PC905 1P: 24.9K <BOM Structure>
2
PR908 PC907 PC908 2 PR907 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
0.033U_0402_16V7 1 2 FBA2 1 2 1 2 165K_0402_1% <BOM Structure>
10_0402_1% 2P: 1.65K
560P_0402_50V7K PR910 10P_0402_50V8J PC909
1 PR909 2 1 2 COMPA1 1 2 1P: 1K
CSSUMA
1K_0402_1% 5.11K_0402_1% 1500P_0402_50V7K CSREFA
PR911 PC910 TSENSEA
2
1 2 SWN1A 0.047U_0402_16V7K
2P: 21.5K 64.9K_0603_1% PR912 6.98K_0402_1%
1
CSP1A 1 2
1P: 15.8K SWN1A (53)
2
15.8K_0402_1%
PR913
CSCOMPA
1 2 PC911
(9) VCC_AXG_SENSE
2
8.25K_0402_1%
1PR914
0_0402_5% 1000P_0402_50V7K
1
PC912 PH902
PR915
PR916 1000P_0402_50V7K
CSREFA (53)
1
1 2 100K_0402_1%_TSM0B104F4251RZ
(9) VSS_AXG_SENSE
0_0402_5% PC913
1
+3VS
CSP2A
CSP1A
1 2
TRBSTA#
DROOPA
TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K
DIFFA
ILIMA
+1.05VS
1
PR917
10K_0402_1% PR918 2P: 36K
1 2
1P: 26.1K PUT COLSE
26.1K_0402_1% 2011_0829
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
2
2011_0819 +V1.05VS_VCCP +5VS 1 PR919 2 PU901 PR920,PR924,PR931 TO V_GT

C VR_RDYA C
change to +1.05VS 2_0603_5% form 4.7 to 2.2 HOT SPOT
VSNA
VSPA
DIFFA
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
TRBSTA#
6132_PWMA
PC914
1 2 6132_VCC
.1U_0402_16V7K
.1U_0402_16V7K
1 45 PR920 PC917
2.2U_0603_10V7K VCC PWMA BSTA1
2 44 1 2 BSTA1_11 2
VDDBP BSTA +5VS
130_0402_1%
54.9_0402_1%
PR923 VR_RDYA 3 43 2.2_0603_5% 0.22U_0603_25V7K

VRDYA HGA HG1A (53)
1
PR921 2
1 2VR_ON_CPU 4 42
(41) VR_ON EN SWA SW1A (53)
PR922
PC915 PC916 0_0402_5% VR_SVID_DAT1 5 41 PC918

SDIO LGA LG1A (53)
VR_SVID_ALRT# 6 40 BST2 1 PR924 2 BST2_1 1 2 2Phase: @
2
PR927 PR925 VR_SVID_CLK ALERT# BST2 2.2_0603_5% 0.22U_0603_25V7K

7 39 HG2 (53)
SCLK HG2 1Phase: install
1
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 (53)
1
VBOOT NCP6132AMNR2G_QFN60_7X7 SW2

(8) VR_SVID_DAT 1 PR926 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9
ROSC LG2
37 LG2 (53)
PC919 1 phase GFX PR929
CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 2 0_0402_5%
(8) VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 2.2U_0603_10V7K
(8) VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K
2011_0819 +V1.05VS_VCCP PR930 1K_0402_1% VGATE 12 34 1 PR928 2

LG1 (53) +5VS
2
VRDY LG1
1
change to +1.05VS 13 33 0_0402_5% CSP2A

+1.05VS VSN SW1 SW1 (53)
PC920 14 32 PC921
+3VS VSP HG1 HG1 (53)
DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 1 2
CSCOMP
2
DIFF BST1
TRBST#
2.2_0603_5% 0.22U_0603_25V7K
DROOP
CSSUM
DRVEN
CSREF
1
COMP
TSNS
2011_0809
CSP3
CSP2
CSP1
PWM
IOUT
ILIM
1
PR932 PR928 change place
FB
PC936 75_0402_1% PR933 +5VS
47P_0402_50V8J 10K_0402_5%
2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2
1 PR934 2
(41,45) VR_HOT#
2
2P: 41.2K
COMP_CPU
1
FB_CPU 41.2K_0402_1% Option for 3Phase: @
TRBST#
(15) VGATE
PR936 2 phase CPU PR935
DROOP
TSENSE
ILIM_CPU
1 2 VSN 3P: 22p 0_0402_5% 2Phase: install
(8) VSSSENSE 6132_PWM
1
0_0402_5%
IMON
PC922 2P: 10p
2
PR937 1000P_0402_50V7K 2011_0930 CSP3
2
1 2 VSP PC923 add PR954 20k_0402_1%

(8) VCCSENSE
2
PR938 12.4K_0402_1%
0_0402_5% 1 2
.1U_0402_16V7K PR940
IMVP_IMON
B 2011_1005 CSP2 1 2 SWN2 (53) B
1
for Intel add PC836 SE00000D180 (43P_0402_50V8J) PC924 CSP1 6.98K_0402_1% TSENSE
3P: 330p 1 PR939 2 2 1 CSP2 PC925 PR954
1
1K_0402_1% CSP3 0.047U_0402_16V7K 20K_0402_1%

2011_1119 2P: 1000p
2
10P_0402_50V8J @
Change PC936 to 47P (SE071470J80)
2
form 43P (SE00000D180) PR941 PC926 PR942 PC927 CSREF
3P: 21K
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1
PR943 PC928 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K
8.25K_0402_1%
1 2FB_CPU3 1 2 1000P_0402_50V7K 2200P_0402_50V7K PR944
PR945 1
2
10_0402_1% 3P: 6.04K CSP1 1 2
CSREF (53) SWN1 (53)
CSCOMP
1
680P_0402_50V7K 6.98K_0402_1% PH903
PR946 PR947 2P: 4.32K PC929 PR955
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 20K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
1
2
4700P_0402_25V7K
PC930 @
1
2P: 1200p
1
1.21K_0402_1% 9.53K_0402_1% 3P: 2200p 0.047U_0402_16V7K
2
PC931 CSREF
2P: 3300p CSSUM
2
3P: 348 3P: 3.65K PC932

1 2 2011_0930
2P: 1.21K 2P: 9.53K 1200P_0402_50V7K 1 PR948 2 SWN1 add PR955 20k_0402_1%
24.9K_0402_1%
130K_0603_1% PUT COLSE

2
.1U_0402_16V7K
TO VCORE
PC933
3P: 23.7K 1 2 PC934 1 PR950 2 SWN2

PR949
820P_0402_25V7 130K_0603_1% HOT SPOT

1
2P: 24.9K
1 PR951 2NTC_PH201 1 PR952 2
1
75K_0402_1%
PR953 PC935 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH904
PUT COLSE
1K_0402_1% 1000P_0402_50V7K 2 1
3P:
<BOM806
Structure>
TO VCORE
Phase 1 220K_0402_5%_ERTJ0EV224J
2P: 1K <BOM Structure>
A Inductor A
(41) IMVP_IMON

Title
PWR-CPU_CORE1
Custom 0.4
LA-8133P
Sheet 52 of 58
5 4 3 2 1
5 4 3 2 1
2011_0926
2011_0926 2011_0826 add change part 2011_0826 add
change part for EMI 2011_0801 PC1009 form SF22004M210_220U 25V M to TPC8065 for EMI
CPU_B+ 8X10.2 CE-AX change to SF000000S80_100U 25V M CPU_B+
to TPC8065 del PR1002
del PR1001 6.3X7.7 CE-LX and place
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
5
5
PL1002
PC1017
PC1018
68P_0402_50V8J
68P_0402_50V8J
PQ1001 HCB4532VF-800T90_1812 PQ1002 2011_0727
1
PC1001
PC1002
PC1003
PC1005
PC1006
PC1007
PC1004
PC1008
1 2 CPU_B+ chang net name
2011_0727
chang net name
2
4 1 1 4
68U_25V_M_R0.36
68U_25V_M_R0.36
(52) HG1 (52) HG2
+CPU_CORE + + +CPU_CORE
PC1020
PC1009
2011_0815 change PC1009 of place
PL1001 form"CPU_B+" change to "B+"
3
2
1
3
2
1
D 2 2 D
PCMB104T-R36MH1R105_30A_GLUE PL1003
PCMB104T-R36MH1R105_30A_GLUE
(52) SW1 1 4 (52) SW2 1 4
2011_1005 PC1009 change
1
2 3 form SF000000S80 2 3
5
PR1003
(100U 25V M 6.3X7.7 CE-LX ) PQ1004 PR1004
PQ1003 4.7_1206_5% to SF000000W00 4.7_1206_5%
( 68U 25V M 6.3X5.8 ESR0.36 FK)
2
PR1005
4 V1N_CPU2 1 4 V2N_CPU 2 PR1006 1 CSREF
(52) LG1 CSREF (52) (52) LG2
1SNUB_CPU1
SNUB_CPU2
10_0402_1%
10_0402_1%
SWN1 (52) SWN2 (52)
3
2
1
3
2
1
PC1010 2011_1127
Change PL1002 from SM010018210 to SM01000JR00
1
680P_0603_50V7K PC1011
HCB4532VF-800T90 1812 for EOL
2
680P_0603_50V7K
2011_1005 PQ1004 change
2
form SB00000Q600(TPCA8059-H_PPAK56-8-5)
2011_1005 PQ1003 change 2011_1127 to SB00000Q400(TPCA8057-H_PPAK56-8-5)
form SB00000Q600(TPCA8059-H_PPAK56-8-5) Change PL1001,PL1003,PL1004
to SB00000Q400(TPCA8057-H_PPAK56-8-5) from SH00000HK00 to SH00000N900
PCMB104T-R36MH1R105 30A GLUE
C C
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
IccMax=94A IccMax=53A
Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
OCP~110A OCP~65A
2011_0826 add
for EMI CPU_B+
2011_0926
change part
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7K
to TPC8065
68P_0402_50V8J
B del PR1007 B
1
1
PC1019
PC1012
PC1013
PC1014
PC1015
2
2
5
PQ1005
(52) HG1A 4
PL1004
+VCC_GFXCORE_AXG
3
2
1
PCMB104T-R36MH1R105_30A_GLUE
(52) SW1A 1 4
1
TPCA8057-H_PPAK56-8-5 2 3
5
PQ1006 PR1008
V1N_GFX
4.7_1206_5%
2
(52) LG1A 4
SNUB_GFX1
2 PR10091
CSREFA (52)
3
2
1
10_0402_1%
1
PC1016
680P_0603_50V7K SWN1A (52)
2
A A
QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/07/12 Deciphered Date 2012/07/01 Title
R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE2
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.4
LA-8133P
Sheet 53 of 58
5 4 3 2 1
5 4 3 2 1
+CPU_CORE 2011_0727 2011_0727 Below is 458544_CRV_PDDG_0.5 Table 5-8.

chang net name chang net name +CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1101
PC1102 PC1103 PC1104 PC1105
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites
D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1
PC1112
PC1113
PC1114
PC1115
PC1116
PC1117
PC1118
PC1119
@
PC1106 PC1107 PC1108 PC1109 PC1110 PC1111
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 2011_0808 place power name
2 2 2 2 2 2 2 2 2 2 2 2 2 2
change form +V1.05S_VCCP +1.05VS
to +1.05VS
+CPU_CORE 2011_0727 @ @ @
@
+1.05VS
chang net name
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2011_0901 unmount PC1114,PC1115 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 PC1118,PC1119 @
PC1125
PC1126
PC1127
PC1128
PC1129
PC1130
PC1131
PC1132
PC1133
PC1134
PC1135
PC1120 PC1121 PC1122 PC1123 PC1124
2 2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1 1
2 2 2 2 2
PC1136
PC1137
PC1138
PC1139
PC1140
PC1141
PC1142
PC1143
2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1 @ @ @ @ @
PC1149
PC1150
PC1151
PC1152
PC1153
PC1154
PC1155
PC1156
2011_0901 mount PC1140,PC1141
PC1144 PC1145 PC1146 PC1147 PC1148 PC1142,PC1143
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1
330U_D2_2VM_R9M
330U_D2_2VM_R9M
330U_D2_2VM_R9M
@
PC1158
PC1159
PC1160
+ + +
C C
2 3 2 3 2 3 1
330U_D2_2.5VY_R9M
+
PC714
1 1 1 1 1
PC1161 PC1162 PC1163 PC1164 PC1165
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2
2 2 2 2 2 2011_0815 PC1160
change form unmount
2011_0815 del PC1157 to mount
2011_0815 PC714 change place
form "+1.05VS_VCCPP" to "+1.05VS"
1 1 1 1 2011_07929
@ @ @ PC1158 non-mount
PC1169 PC1170 PC1171 PC1172
2011_1005 PC714 change to
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 330uF_2V_R9M
2 2 2 2
+CPU_CORE 2011_0727 2011_1007

chang net name PC714
form SGA00001Q802
(S POLY C 330U 2V M X LESR6M SX H1.9)
change to SGA00002680
1 1 1 1
(330U_D2_2.5VY_R9M)
+ PC1173 + PC1174 + PC1175 + PC1176
330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R9M 330U_D2_2VM_R9M

B 2 3 2 3 2 3 2 3 B
2011_1230
PC1173 unmount
2011_1005
1 @ 1 chang to 330uF_2V_R9M
+ PC1177 + PC1178
2011_1230
470U_D2_2VM_R4.5M 330U_D2_2VM_R9M PC1175,PC1176 change to SGA00006100
2 3 2 3
A A

Title
PWR - PROCESSOR DECOUPLING
0.4
LA-8133P
Sheet 54 of 58
5 4 3 2 1
A B C D
2011_0923 JUMP form 43X79 change to 43X79
1 1
PU1201 PL1201
4
PJ1201 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.05VMP_VIN 10 2 1.05VMP_LX 1 2
+5VALW
PG
2 1 PVIN LX +1.05VMP
68P_0402_50V8J
JUMP_43X39 9 PVIN LX 3
1
PC1201
680P_0603_50V7K 4.7_1206_5%
1
@
PC1202
PC1207 22U_0805_6.3VAM 8 SVIN
PR1201
22U_0805_6.3VAM PR1202
2
6 7.5K_0402_1%
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
1 2
2
EN
1
NC
NC
PJ1202
TP
PC1204
PC1205
FB=0.6Volt +1.05VMP 2 1 +1.05VM
2 1
PC1203
PR1203
11
2
1 2 EN_1.05VMP @ JUMP_43X79
2
(41,42) M_PWR_ON
0_0402_5%
0.1U_0402_10V7K
2
PC1206 @
SY8033BDBC_DFN10_3X3
1
PR1204 1.05VMP max current=1A
1M_0402_5%
1.05VMP_FB
2
1
1
PR1205
10K_0402_1%
2
2 2
3 3
4 4

Title
PWR-+1.05VMP
Custom 0.4
Date:
LA-8133P
A B C D
5 4 3 2 1
D D
C C
B B
A A

Title
PWR-Thermal Protect
1.0
Date:
LA-8133P
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List)

Item Reason for change PG# Modify List Date Phase
1
2
D
3 D
4
5
6
7
8
9
10
11
C
12 C
13
14
15
16
17
B B
A A

Title
PIR (PWR)
Custom 1.0
Date:
LA-8133P
5 4 3 2 1
1 2 3 4 5
Version Change List (P.I.R. List)

Phase Date No. BOM Sch Layout Description function
2011/09/13 No1 V V Add C2325,C2326,C2327,C2328,C2329,R2319,R2324,Q2312 Add SBA function (+3VM) power

2011/09/15 No2 V Del Q2305 Del SYSYON#
2011/09/15 No3 V Add EC pin 119(M_PWR_ON) for SBA function Add SBA function
2011/09/15 No4 V Add EC pin 120(PCH_SLPA#) from PCH to EC for SBA function Add SBA function
2011/09/15 No5 V Add EC pin72 (Muxless_STAT) for GPU STAT Add Muxless_STAT function
2011/09/15 No6 V Del PR310, PR311, PR312, PR313, net name:"H_PROCHOT#", +3VALW. PWR-CHARGER-BQ24727
A A
2011/09/15 No7 V mount PC832
2011/09/15 No8 V V Add R2482,Q2404,C2509,R2481,R2485,Q2400,R2483,C2501 AOAC Function
change net name BT_OFF# to BT_ON# and change PCH EN GPIO from GPIO34 to GPIO36
2011/09/15 No9 V V R280 from @ to mount,R282 from mount to @ BT Function
change net name(Mini-Express) from BT_OFF# to WLBT_OFF#

2011/09/15 No10 V V PCH EN GPIO change to GPIO34 BT Function
change +3VS_WLAN net name to +3VS_AOAC

2011/09/19 No11 V V change +3VS_WWAN net name to +3VS_AOAC AOAC Function
2011/09/19 No12 V V Del R1010 for LVDS CONN plug high voltage LVDS CONN
2011/09/19 No13 V V R1102,R1104,R1105 from @ to mount fix MIC(ECR97236)issue MIC function
2011/09/19 No14 V V Add R2470 for 80 port function 80 port function
2011/09/19 No15 V V Del R2476 Add Q2405 BT Function
Add power schematic 9/15 again modify RF PC423, PC425, PC519, PC620, PC717,
2011/09/20 No16 V V
PC873, PC874, PC424, PC518 PC1017, PC1018, PC1019, PC422, PC516, PC517
modify POWER在VGA的PWM IC 加的加加PR869, PR870
2011/09/22 No17 V V Add U10,C589,C645 for TPM function TPM function

2011/09/22 No18 V V Add R110,R112 for SPI POWER choose(SBA function)
2011/09/23 No19 V V modify power page 44~57(PJ1201 JUMP form 43X79 change to 43X79)
change CPU footprint from TYCO_2013620-2_989P-T to TYCO_2013620-2_989P-T-A39

change PCH footprint from PANTHER-POINT_FCBGA_989P-T to PANTHER-POINT_FCBGA_989P-T-A39
B 2011/09/26 No20 V V change GPU footprint N13P-PES-A1_FCBGA_908P to N13P-PES-A1_FCBGA_908P-A39
B
change VRAM footprint K4W1G1646E-HC12_FBGA_96P to K4W1G1646E-HC12_FBGA_96P-A39
2011/09/26 No21 V V change PCH_GPIO24(R288) pull up to +3V_PCH

2011/09/26 No22 V change P18 (R311,R330,R286,R329) for UMA and Optimus memon
2011/09/26 No23 V change net name PCH_THRMTRIP#_R to VGA_THRMTRIP#
PQ702 change to TPC8065,Del PR705
2011/09/26 No24 V V PQ1001,PQ1002,PQ1005 change to TOC8065,Del PR1001,PR1002,PR1007
p43 change Q2304 dual channel 2n7002 to single channel Q2304,Q2305(Q2305 @)

2011/09/26 No25 V V p43 change Q2306 dual channel 2n7002 to single channel Q2306,Q2311(Q2311 @)
2011/09/27 No27 V modify EC Board ID R2213 to 18K

2011/09/27 No28 V V net name CX_GPIO0 connect to U1101 pin 38
2011/09/27 No29 V V Add C2152,C2153,D2113 for ESD
2011/09/27 No30 V V change NVIDIA N13M ROM_SCLK from 15K PU to 5K PU
2011/09/27 No31 V V change ESD part D2401,D2403,D2405 power from +5VALW to +USB VCCA
2011/09/27 No32 V V Add C2108 for GPU_CLKREQA
2011/09/27 No33 Add Q2406 , modify R2401,Change PCH_GPIO19 to ODD_DET#,for zero power ODD
2011/09/27 No34 change WLBT_OFF# to PCH_GPIO34
2011/09/27 No35 change PCH_GPIO34 to WLBT_OFF#(mini card pin5)
2011/09/27 No36 change BT_ON# connect to WLBT_OFF#(mini card pin51)
C
2011/09/28 No37 C76 , R1123 , c1131 , R2201,C2209 C84,C85 from @ to mount for RF team C
2011/09/29 No38 R1529 change to 15K

2011/09/29 No39 Add CONN JDB3 fo debug
2011/09/29 No40 Add R2460,R2438,R2471,R2472,R2475,R2476 for PS8520B
2011/09/29 No41 change D2403 ,D2401 power to +USB_VCCB,and del D2403 ,D2401,D2405 Pin3 net
2011/09/29 No42 change power schematic
del PC606 (22U_0805_6.3V6M)
PR855.1 net change form +VGA_CORE to +VGA_COREP
PR827 mount change to @(non-mount)
PR839 for 47Kohm change to 147Kohm
2011/09/29 No43 PR103 for 0ohm change to 270ohm
PC1166 non-mount,PC1173 non-mount,PC1158 non-mount
2011/09/29 No44 Add Q2313,C2305,C2306,C2307,C2308,R2318,R2320,R2320,C2322 for +3V_PCH

change CRT CONN to DC061109231(footprint pin modify)
Add PR954,PR955
2011/09/29 No45 Add H16,H27
change Q2304.Q2305 to Q2304
modify PTH H11,H18 ,H21
Del T10 for SUS_STAT(SLP_S3# 走走走走)
reserve R352,R353 for SATA re-drive PS-8131B

change net name fron WLBT_OFF to WLBT_OFF_5#
2011/10/04 No46 modify PCH_GPIO34 connect to BT_ON# for BT module
modify PCH_GPIO36 from BT_ON# connect to WLBT_OFF_51# for mini card BT combo module
changr Q2301 to 2N7002
D D
Del R2469,T49,T45,T41,T37,T36,T28,T26 for ME 限限0
2011/10/05 No47 changer power net +3VS_FP to +3VS
update power schematics P44~P57
2011/10/06 No48 change Q1202 part to SB000007H10.

change JCARD1 PN to SP02000H810 footprint: ACES_87213-1400G_14P
change some CONN part NO. for ME CONN list
Add D2416
Title
PIR (EE)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8133P 1.0
Date: Friday, January 13, 2012 Sheet 58 of 58
1 2 3 4 5
www.s-manuals.com

Compal La-8131p, La-8133p r1.0 Schematics

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Compal La-8131p, La-8133p r1.0 Schematics

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1 2 3 4 5

M/B Schematics Document

Security Classification Compal Secret Data

DDR3*8 PCI-E X16 Ivy Bridge Dual Channel

HDMI Connector Page 4~10

LVDS Connector LVDS

RJ45 CONN EC TPM

PCI Express USB(BT)

PCI Express USB

Mini card SATA

SIM Card Security Classification Compal Secret Data

+5VS Full ON HIGH HIGH HIGH HIGH ON ON ON ON

SMBUS Control Table

Security Classification Compal Secret Data

PCI EXPRESS* - GRAPHICS

Nvidia support PCIE Gen2

Security Classification Compal Secret Data

A28 CLK_CPU_DMI_R R4 1 @ 2 0_0402_5%

R8 1 @ 2 10K_0402_5% AN34 SKTOCC# R9

H_CATERR# AL33 CATERR#

P+ AP29 XDP_PRDY# PU/PD for JTAG signals

JTAG & BPM

+3VS +3VALW +1.5V_CPU_VDDQ +3VS +1.05VS

1 Buffered reset to CPU 1

10K_0402_5% 74AHC1G09GW_TSSOP5 1 43_0402_1%

Security Classification Compal Secret Data

JCPU1C CONN@ JCPU1D CONN@

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

R43 1 @ 2 0_0402_5% DRAMRST_CNTRL

CFG Straps for Processor

AH27 1: Normal Operation; Lane # definition matches

AN26 AJ27 1K_0402_1%

RSVD37 T8 Display Port Presence Strap

1: (Default) PEG Train immediately following xxRESETB

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data

JCPU1F POWER CONN@

PEG AND DDR

Security Classification Compal Secret Data

M3 Support R67 1 @ 2 0_0402_5%

DDR3 -1.5V RAILS

AH24 VAXG49 VCCSA2 M26

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 (49)

‧ Can connect to GND if motherboard only

JCPU1H CONN@ JCPU1I CONN@

AT35 VSS1 VSS81 AJ22

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data

(6) DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA (6)

+1.5V DDR_B_DQS#[0..7] (6)

(6) DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB (6)

DDR_B_D56 181 182 DDR_B_D61

1 1 DDR_B_D57 183 184

DDR_B_D59 DQ58 DQ62 DDR_B_D63

Security Classification Compal Secret Data

ME HDA_SPKR T10 P- AM10 SATA_DTX_C_PRX_N1

8MB+4MB SPI ROM FOR 5M ME(SBA)

Q8 if supply SBA function R110 @,R112 mount

R109 BSS138_NL_SOT23-3 R112 1 SBA@ 2 0_0402_5%

R111 SPI_SO_R R343 1 CS# VCC

SPI_SB_CS0# R340 1 2 0_0402_5% CS# 1 8 Reserve for EMI please close to U3

EON Reserve for RF please close to U5, U6