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Abstract—This research deals with the design and simulation more expensive, large size, low power factor and reducing the
of induction furnace power source (inverter) using MATLAB overall system efficiency. In this work, a single control stage
package. This source designed to lock on the resonant frequency high power inverter is designed to do both locking on the
of the load by using self-oscillating technique, also it has the resonance frequency as well as controlling the output power.
capability to control the power supplied to the load using phase
shift pulse width modulation (PSPWM) technique. These II. SINGLE STAGE HIGH POWER INVERTER CIRCUIT
characteristics used to overcome the load nonlinear behavior DESIGN
during the brazing process and to achieve soft switching of the
inverter elements. Also, the inverter has the capability to operate The control circuit used in this work is an improvement of
with or without load (workpiece). The implemented prototype U.S. Invention Patent [6], which demonstrates a self-
operates at a frequency range (50-100)kHz and 10kW was oscillating technique for locking on the resonance frequency
successfully used for brazing two copper workpieces. of the load to control the inverter frequency feeding the load
in period by period without any lags. This method becomes
Index Terms—Self-oscillating, phase shift pulse width
more popular in most applications such as electronic ballasts
modulation (PSPWM), MATLAB.
(economical fluorescent lamp) [7-9],but in this method, the
I. INTRODUCTION load must be constant that is not the case in IH load.
Therefore, this method requires another stage before the
The resonant inverter [1] is usually used in induction
inverter to control the output power [2].
heating (IH) systems. The load of the resonant inverter consists
The improved circuit in this work has the capability to lock
of a capacitor, an inductor and resistor. Two types of resonant
on the resonance frequency in condition that the starting
inverters, depending on the resonance of the load arrangement
frequency is less than the resonance frequency. But it must be
are generally used: 1) Parallel resonant inverter, and 2) Series
mentioned that when the starting frequency is less than the
resonant inverter. The inverter must be operating close to the
resonance frequency, the power transistors suffer from hard
resonance frequency of the load in order to make the current or
switching for a few microseconds before the control circuit
voltage output waveform is approximately sinusoidal and to
locks on to the resonance frequency. This case can be avoided
achieve maximum power delivered to the load. Current-fed
by using soft starting during this period.
inverter and voltage-fed inverter are two basic types of the
The improved circuit uses the integrated circuit (I.C4-
inverters used in the resonant induction heating system.
UC3875) as an output power controller. Also, the integrated
Because of current-fed parallel resonant inverters needs
circuit UC3875 and its family is a phase shift pulse width
over voltage protection circuit [2] which increase the
modulation (PSPWM) controller which is the heart of the
complexity of the overall design of the IH system, voltage-fed
inverter control circuit. It usually implements voltage control
inverters (VFI) with series resonant load is used.
of the full bridge inverter by phase shifting the switching of
To achieve brazing process, the high-frequency series
one leg of bridge with respect to other by an angle (ĭ)
resonant inverter must be designed to lock on the resonance
allowing constant frequency pulse width modulation at high
frequency and has the capability to control the output power
frequencies. Varying the phase shift angle (ĭ) will vary the
according to the load variation through the heating process.
output voltage of the inverter and hence the output power.
Most of high power induction heating (IH) systems consist
Many published papers [10-13] and researches [14-16]
of two control stages [3-5] or more [2] to control both the
used this integrated circuit or one of its families and
output power and the process of locking on the resonance
concentrated on the benefits and performance of the phase
frequency. The first stage is usually used to control the DC
shift full bridge inverter (PSFBI).
input voltage using controlled rectifier to control the output
The improved circuit in the present work uses the
power while the second stage is the inverter which is used for
integrated circuit (I.C4-UC3875) which is designed to operate
locking on the resonance frequency. This makes the IH system
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
at a variable frequency (resonance frequency of the IH load) the problem due to the delays caused by the triggering and
with phase shift pulse width modulation (PSPWM) process. control circuit of IGBTs.
The PSFBI is designed such that each transistor operates at 0.5 +5V -5V
Y
T P3 T P4 M onostable stage T P6
IC1 IC2
duty cycle. Dead time is entered between the lower and upper R35 R36 SN75107 CD40106:A
C7
CD40106:B CD40106:C
transistors for each leg of the full bridge inverter to permit the 1
2 1A
1B
1Y
2Y
4
9
1 2 3 4 5 6
6
PSPWM stage Vref IC4 IC3
The overall IH system design used for brazing is shown in R8
UC3875
T P9
SN7402:B
1 Vref GND 20
Fig.1 and Fig.2. The power stage with its current feedback DC-FB C9
Vref
SN7402:C
2
E/O RAMP
19
R9 R10 C10
circuit and five isolated DC power supply is shown in Fig.1, T P8 3 SLOPE 18
4
-E
9
R11 R7 4 SY NC 17 10
while the self-oscillating PSPWM control circuit with its R12 5 CS
+E
Freq-Set
16
8
R13
isolated IGBTs modules driver stage is shown in Fig.2 C11
R16
SYNC stage 6 Sof t Start
Delay A/B
15
7 T P11
Unontrolled Full Bridge Delay C/D OUT A 14 A
rectifier Inverter Series Connected T P13 R14 T P12
D 8 OUT D OUT B 13 B C13
I QD1 I QD2 Output Circuit C12
T P14 9 R17
C OUT C GND Power 12 R19
io2 R15 10 R20 C14
Q1 D1 C1 Q2 D2 C2 R18 VC VIN
11
Ro Vcc5=+12V
+ G1 + G2 T1 C15
D5 D6 D7
+ - G1 - G2 IH
Input CC
CDC Load
3 Phase A i o1
Line R29 Lo
frequency B
Q4 D4 C4 Q3 D3 C3 N1 : N2
D8 D9 D10 Matching Co Resonant
+ G4 + G3 Capacitor
Vcc2=+12V Vcc1=+12V
Transformer
IGBT Driver1 IGBT Driver2
I Q4 I Q3
1 8 1 8
- G4 - G3 NC Vcc NC Vcc
2 Anode Vo 7 2 Anode Vo 7
B A
T P10 3 6 3 6
VR34 R33 D11 Cathode Vo Cathode Vo
DC-FB C5 4 NC Vee 5 R22
4 NC Vee 5
T P2 T P1 D15 R24
T P3 C6 D14
Y
CT
Vee2= -5V Vee1= -5V
D13 D12 R32
F.B. + G4 + G1
R31 R30 Current
ZD2 ZD1 N2 : N1
Vcc3=+12V
Vcc4=+12V
Voltage clipping stage Leading stage CT stage
Fig. 1. Diagram for full bridge series resonant inverter with feedback current IGBT Driver3 IGBT Driver4
1 NC Vcc 8 1 NC Vcc 8
circuit. 2 7 2 7
D Anode Vo C Anode Vo
3 Cathode Vo 6 3 Cathode Vo 6
1) Current transformer (CT) stage (Fig.1). Fig. 2. Diagram for self-oscillating PSPWM control circuit.
2) Leading stage (Fig.1).
3) Voltage clipping stage (Fig.1). 3) Voltage clipping stage (R32, D12, D13, ZD1 and ZD2):
4) Comparator stage (Fig.2). This circuit is shown in Fig.1. It is designed to convert the
5) Monostable stage (Fig.2). sinusoidal input signal coming from leading circuit into a
6) SYNC stage (Fig.2). clipped square wave (clipping signal) (TP3) with an
7) PSPWM stage (Fig.2). appropriate voltage limit (± 4V).
8) IGBTs driver stage (Fig.2). 4) Comparator stage (IC1-SN75107): This integrated
These stages are explained as follows: (SN75107) has two comparators which are connected to the
1) Current transformer (CT) stage: It is a current transformer output of the voltage clipping circuit as illustrated in Fig.2.
with 1/22 turns ratio as illustrated in Fig.1. The primary These comparators produce two pulses according to the
winding of the current transformer (CT) is joined at the polarity of the input signal with duty cycle approximately
primary of the main matching transformer (T1). The 50%. The two output pulses (TP4 and TP5) are positive and
secondary of this CT is terminated with a 22UHVLVWRU R30) the phase shift between them is 180°.
which works as (a transducer) current to voltage converter. 5) Monostable stage (I.C2-CD40106): There are two
This voltage is used to generate two signals, the synchronized monostable groups ((I.C2-CD40106: A, B, C, with C7, and
signal (Y) and DC feedback current (DC-FB) signal. R5) and (I.C2-CD40106: D, E, F, with C8, and R6)) as shown
2) The leading stage (C6 and R31): It is an RC circuit as in Fig.2. These monostables produce double narrow pulses
illustrated in Fig.1. It advances the signal supplied to the (TP6 and TP7).
voltage clipping circuit in a few microseconds to overcome 6) SYNC stage (I.C3-SN7402): The NOR gates (I.C3-SN7402:
B and C) shown in Fig.2 summing the double pulses coming
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
from the two monostables to produce a synchronization signal The full bridge inverter is often referred to as a square
(SYNC signal) (TP8) represents the zero crossing detection of wave generator, then the input voltage supplied to the
the clipping signal. matching transformer is represented as rectangular wave shape
7) PSPWM stage (I.C4-UC3875): The integrated circuit (I.C4- I QD1 I QD2
drive one leg of the full bridge inverter through their driving Vin Vin u(t) L o
full bridge inverter by controlling the phase shift between the (a)
two legs of the full bridge. The phase shift is controlled by the i o1 CC R1 L l1 i 'o2 L 'l2 R '2
A
sawtooth signal and the error amplifier output inside the I.C4-
UC387 It has the capability to control the duty cycle of its R 'o
output pair (A/B and C/D) and thus the full bridge inverter VV '
output voltage from zero to 100% by paying back the DC Vin u(t) Rm Lm
o
Lo'
feedback current (DC-FB) signals to the pin 3 of (I.C4- Vin u(t)
-2
DC
-4 filter
capacitor
-6 IGBTs module
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
Q2/Q3
x 10
-4
IGBTs module
Q1/Q4
50
(c) io1 (A)
Fig. 7. A prototype of the full bridge self-oscillating series resonant
Vin u(t)*15 (V)
inverter.
-50
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
-4
x 10
50
(d) io1 (A)
Time (s) Vin u(t)*15 (V)