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2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-

MITCSA) – IRAQ (9-10) May

Design, Simulation and Implementation of a Self-


Oscillating Control Circuit to Drive Series Resonant
Inverter Feeding a Brazing Induction Furnace
Mohammad Hameed Khazaal Isam Mahmood Abdulbaqi Rabee’ Hashim Thejel
Ministry of Industry and Minerals College of Engineering College of Engineering
State Military Industrials Company Al-Mustansiriayah University University of Basrah
Baghdad, Iraq Baghdad, Iraq Basrah, Iraq
mohammadhameed1972@gmail.com embaki56@yahoo.com rabee_alabbasi@ieee.org

Abstract—This research deals with the design and simulation more expensive, large size, low power factor and reducing the
of induction furnace power source (inverter) using MATLAB overall system efficiency. In this work, a single control stage
package. This source designed to lock on the resonant frequency high power inverter is designed to do both locking on the
of the load by using self-oscillating technique, also it has the resonance frequency as well as controlling the output power.
capability to control the power supplied to the load using phase
shift pulse width modulation (PSPWM) technique. These II. SINGLE STAGE HIGH POWER INVERTER CIRCUIT
characteristics used to overcome the load nonlinear behavior DESIGN
during the brazing process and to achieve soft switching of the
inverter elements. Also, the inverter has the capability to operate The control circuit used in this work is an improvement of
with or without load (workpiece). The implemented prototype U.S. Invention Patent [6], which demonstrates a self-
operates at a frequency range (50-100)kHz and 10kW was oscillating technique for locking on the resonance frequency
successfully used for brazing two copper workpieces. of the load to control the inverter frequency feeding the load
in period by period without any lags. This method becomes
Index Terms—Self-oscillating, phase shift pulse width
more popular in most applications such as electronic ballasts
modulation (PSPWM), MATLAB.
(economical fluorescent lamp) [7-9],but in this method, the
I. INTRODUCTION load must be constant that is not the case in IH load.
Therefore, this method requires another stage before the
The resonant inverter [1] is usually used in induction
inverter to control the output power [2].
heating (IH) systems. The load of the resonant inverter consists
The improved circuit in this work has the capability to lock
of a capacitor, an inductor and resistor. Two types of resonant
on the resonance frequency in condition that the starting
inverters, depending on the resonance of the load arrangement
frequency is less than the resonance frequency. But it must be
are generally used: 1) Parallel resonant inverter, and 2) Series
mentioned that when the starting frequency is less than the
resonant inverter. The inverter must be operating close to the
resonance frequency, the power transistors suffer from hard
resonance frequency of the load in order to make the current or
switching for a few microseconds before the control circuit
voltage output waveform is approximately sinusoidal and to
locks on to the resonance frequency. This case can be avoided
achieve maximum power delivered to the load. Current-fed
by using soft starting during this period.
inverter and voltage-fed inverter are two basic types of the
The improved circuit uses the integrated circuit (I.C4-
inverters used in the resonant induction heating system.
UC3875) as an output power controller. Also, the integrated
Because of current-fed parallel resonant inverters needs
circuit UC3875 and its family is a phase shift pulse width
over voltage protection circuit [2] which increase the
modulation (PSPWM) controller which is the heart of the
complexity of the overall design of the IH system, voltage-fed
inverter control circuit. It usually implements voltage control
inverters (VFI) with series resonant load is used.
of the full bridge inverter by phase shifting the switching of
To achieve brazing process, the high-frequency series
one leg of bridge with respect to other by an angle (ĭ)
resonant inverter must be designed to lock on the resonance
allowing constant frequency pulse width modulation at high
frequency and has the capability to control the output power
frequencies. Varying the phase shift angle (ĭ) will vary the
according to the load variation through the heating process.
output voltage of the inverter and hence the output power.
Most of high power induction heating (IH) systems consist
Many published papers [10-13] and researches [14-16]
of two control stages [3-5] or more [2] to control both the
used this integrated circuit or one of its families and
output power and the process of locking on the resonance
concentrated on the benefits and performance of the phase
frequency. The first stage is usually used to control the DC
shift full bridge inverter (PSFBI).
input voltage using controlled rectifier to control the output
The improved circuit in the present work uses the
power while the second stage is the inverter which is used for
integrated circuit (I.C4-UC3875) which is designed to operate
locking on the resonance frequency. This makes the IH system
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
at a variable frequency (resonance frequency of the IH load) the problem due to the delays caused by the triggering and
with phase shift pulse width modulation (PSPWM) process. control circuit of IGBTs.
The PSFBI is designed such that each transistor operates at 0.5 +5V -5V
Y
T P3 T P4 M onostable stage T P6
IC1 IC2
duty cycle. Dead time is entered between the lower and upper R35 R36 SN75107 CD40106:A
C7
CD40106:B CD40106:C

transistors for each leg of the full bridge inverter to permit the 1
2 1A
1B
1Y
2Y
4
9
1 2 3 4 5 6

resonant transformation for achieving ZVS and to prevent R3


R5 12
11 2A
2B

shot-through current. Power transfer to the load is adjusted by R4


+5V T P5
CD40106:F CD40106:E
T P7
CD40106:D
5
8 1G
2G
controlling the phase shift (ĭ) between the two legs of the full C8 6
S 13 12 11 10 9 8

bridge inverter. The pin configuration and necessary Comparator stage


R6

information for (I.C4-UC3875) are shown in [17, 18].

6
PSPWM stage Vref IC4 IC3
The overall IH system design used for brazing is shown in R8
UC3875
T P9
SN7402:B
1 Vref GND 20
Fig.1 and Fig.2. The power stage with its current feedback DC-FB C9
Vref
SN7402:C
2
E/O RAMP
19
R9 R10 C10
circuit and five isolated DC power supply is shown in Fig.1, T P8 3 SLOPE 18

4
-E
9
R11 R7 4 SY NC 17 10
while the self-oscillating PSPWM control circuit with its R12 5 CS
+E

Freq-Set
16
8
R13
isolated IGBTs modules driver stage is shown in Fig.2 C11
R16
SYNC stage 6 Sof t Start
Delay A/B
15

7 T P11
Unontrolled Full Bridge Delay C/D OUT A 14 A
rectifier Inverter Series Connected T P13 R14 T P12
D 8 OUT D OUT B 13 B C13
I QD1 I QD2 Output Circuit C12
T P14 9 R17
C OUT C GND Power 12 R19
io2 R15 10 R20 C14
Q1 D1 C1 Q2 D2 C2 R18 VC VIN
11
Ro Vcc5=+12V
+ G1 + G2 T1 C15
D5 D6 D7
+ - G1 - G2 IH
Input CC
CDC Load
3 Phase A i o1
Line R29 Lo
frequency B

Q4 D4 C4 Q3 D3 C3 N1 : N2
D8 D9 D10 Matching Co Resonant
+ G4 + G3 Capacitor
Vcc2=+12V Vcc1=+12V
Transformer
IGBT Driver1 IGBT Driver2
I Q4 I Q3
1 8 1 8
- G4 - G3 NC Vcc NC Vcc
2 Anode Vo 7 2 Anode Vo 7
B A
T P10 3 6 3 6
VR34 R33 D11 Cathode Vo Cathode Vo
DC-FB C5 4 NC Vee 5 R22
4 NC Vee 5
T P2 T P1 D15 R24
T P3 C6 D14
Y
CT
Vee2= -5V Vee1= -5V
D13 D12 R32
F.B. + G4 + G1
R31 R30 Current

ZD2 ZD1 N2 : N1

Vcc3=+12V
Vcc4=+12V
Voltage clipping stage Leading stage CT stage
Fig. 1. Diagram for full bridge series resonant inverter with feedback current IGBT Driver3 IGBT Driver4
1 NC Vcc 8 1 NC Vcc 8
circuit. 2 7 2 7
D Anode Vo C Anode Vo
3 Cathode Vo 6 3 Cathode Vo 6

III. DESCRIPTION OF THE CONTROL CIRCUIT 4 NC Vee 5 R26


4 NC Vee 5
R28
D17 D16
The self-oscillating PSPWM inverter consists of the Vee4= -5V
Vee3= -5V

following stages: IGBTs modules driver stage + G3 + G2

1) Current transformer (CT) stage (Fig.1). Fig. 2. Diagram for self-oscillating PSPWM control circuit.
2) Leading stage (Fig.1).
3) Voltage clipping stage (Fig.1). 3) Voltage clipping stage (R32, D12, D13, ZD1 and ZD2):
4) Comparator stage (Fig.2). This circuit is shown in Fig.1. It is designed to convert the
5) Monostable stage (Fig.2). sinusoidal input signal coming from leading circuit into a
6) SYNC stage (Fig.2). clipped square wave (clipping signal) (TP3) with an
7) PSPWM stage (Fig.2). appropriate voltage limit (± 4V).
8) IGBTs driver stage (Fig.2). 4) Comparator stage (IC1-SN75107): This integrated
These stages are explained as follows: (SN75107) has two comparators which are connected to the
1) Current transformer (CT) stage: It is a current transformer output of the voltage clipping circuit as illustrated in Fig.2.
with 1/22 turns ratio as illustrated in Fig.1. The primary These comparators produce two pulses according to the
winding of the current transformer (CT) is joined at the polarity of the input signal with duty cycle approximately
primary of the main matching transformer (T1). The 50%. The two output pulses (TP4 and TP5) are positive and
secondary of this CT is terminated with a 22ŸUHVLVWRU R30) the phase shift between them is 180°.
which works as (a transducer) current to voltage converter. 5) Monostable stage (I.C2-CD40106): There are two
This voltage is used to generate two signals, the synchronized monostable groups ((I.C2-CD40106: A, B, C, with C7, and
signal (Y) and DC feedback current (DC-FB) signal. R5) and (I.C2-CD40106: D, E, F, with C8, and R6)) as shown
2) The leading stage (C6 and R31): It is an RC circuit as in Fig.2. These monostables produce double narrow pulses
illustrated in Fig.1. It advances the signal supplied to the (TP6 and TP7).
voltage clipping circuit in a few microseconds to overcome 6) SYNC stage (I.C3-SN7402): The NOR gates (I.C3-SN7402:
B and C) shown in Fig.2 summing the double pulses coming
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
from the two monostables to produce a synchronization signal The full bridge inverter is often referred to as a square
(SYNC signal) (TP8) represents the zero crossing detection of wave generator, then the input voltage supplied to the
the clipping signal. matching transformer is represented as rectangular wave shape
7) PSPWM stage (I.C4-UC3875): The integrated circuit (I.C4- I QD1 I QD2

UC3875) is the heart of the control circuit as illustrated in Q1 D1 C1 Q2 D2 C2


R L L R
i o2
CC 1 l1 N :N l2 2
Fig.2. It generates four pulses (A, B, C and D) (TP11, TP12, + G1
- G1
+ G2
- G2
1 2 R o

TP13 and TP14 respectively). Each two pulses are assigned to A


i o1 R L m m
V
V ' o

drive one leg of the full bridge inverter through their driving Vin Vin u(t) L o

circuits. The two pulses A and B are used to drive IGBTs Q1 B


C o

and Q4 respectively, while the two pulses C and D are used to + G4


Q4 D4 C4
+ G3
Q3 D3 C3 Vin u(t)

drive IGBTs Q2 and Q3 respectively. The integrated circuit I Q4 I Q3

(I.C4-UC3875) is dedicated to control the output power of the - G4 - G3

full bridge inverter by controlling the phase shift between the (a)
two legs of the full bridge. The phase shift is controlled by the i o1 CC R1 L l1 i 'o2 L 'l2 R '2
A
sawtooth signal and the error amplifier output inside the I.C4-
UC387 It has the capability to control the duty cycle of its R 'o

output pair (A/B and C/D) and thus the full bridge inverter VV '
output voltage from zero to 100% by paying back the DC Vin u(t) Rm Lm
o
Lo'
feedback current (DC-FB) signals to the pin 3 of (I.C4- Vin u(t)

UC3875). Also, the I.C4-UC3875 is designed to lock on at the Co'


im
resonance frequency. At starting, the I.C4-UC3875 is designed B
to operate at a free running frequency (50kHz) via R20 and (b)
C14 from the Freq-Set pin. After a few microseconds and Fig. 3. Series resonant inverter with the transformer model circuit. (a) Series
while the inverter is operating in the free-running frequency, resonant inverter with the equivalent transformer model. (b) Circuit model of
the series resonant inverter with the referred impedances.
the SYNC stage starts generating the SYNC signal (TP8) and
the I.C4-UC3875 starts operating at the resonance frequency. ( Vinu (t ) ). By using KCL and KVL to the circuit in Fig.3b
A dead-time of 1μs is inserted in each output stage using (C12
and R17) and (C13 and R17). This delay is independently yields the following set of equations:
controllable for each output pair (A/B and C/D) and providing
time to allow the resonant switching action. The four outputs 1 di di
(A, B, C and D) of the I.C4-UC3875 are interfaced to the full
Vinu (t )
cc ³ io1dt  R1io1  Ll1 o1  Lm m .
dt dt
(1)

bridge inverter through a driver circuit. § L · di


io1 ¨¨ m ¸¸ m  im  io' 2 . (2)
8) IGBTs modules driver stage: Four symmetrical gate drive
© Rm ¹ dt
circuits (IGBT Deiver1- IGBT Deiver4) (HCPL3117) are used
as shown in Fig.2. The IGBT current drivers have the di di ' di ' 1
Lm m R2' io' 2  L'l 2 o 2  Ro' io' 2  L'o o 2  ' ³ io' 2 dt. (3)
capability of 2.5A peak source and sink currents. dt dt dt co
'
IV. SIMULATION OF FULL BRIDGE SELF-OSCILLATING dvCo (4)
io' 2 co' .
RESONANT INVERTER dt
The full bridge self-oscillating PSPWM resonant inverter is dio' 2 1 ' (5)
vo' Ro' io' 2  L'o  ' ³ io 2 dt.
simulated relating to its behavior rather than using real dt co
transistor models. The load of the inverter circuit is the primary
winding of the matching transformer. The full bridge inverter Where Vin 540V ( DC ) and
with the equivalent circuit of the matching transformer is u (t ) ^ 11 0dt T / 2
T / 2dt T
(6)
illustrated in Fig.3a. To facilitate the analysis and simulation of
the circuit, the secondary and the load impedances are referred The state variables of the circuit in Fig.3b are the inverter
to the primary winding as illustrated in Fig.3b. current ( io1 ), the magnetizing current ( im ), the refer
A series resonant capacitor added to the secondary in an '
attempt to achieve resonance and sinusoidal shape for the transformer secondary current ( io 2 ) and the referred output
current. The primary components of the matching transformer '
voltage ( vo ). The solution of equations 1-3 for the derivatives
are R1 , Ll1 , Rm and Lm . The resonant capacitor refers to
of the state variables are as follows:
primary side is Co' . The other secondary side component dio1 1 ª di 1 º (7)
dt cc ³
Vinu (t )  R1io1  Lm m  io1dt » .
referred to the primary side are R2' , L'l 2 , Ro' and L'o . Where dt Ll1 «¬ ¼
Ro' and L'o are the equivalent resistance and inductance of the dim
dt
Rm
Lm
>
io1  im  io' 2 . @ (8)
IH load referred to the primary.
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
dio' 2 1 ª dim 1 º TABLE I. DESIGN SPECIFICATIONS AND CIRCUIT PARAMETERS FOR THE
 ( R2'  Ro' )io' 2  ' ³ io' 2 dt » (9)
« Lm MATLAB MODEL.
dt ( Ll 2  Lo ) ¬
' '
dt co ¼
wn Symbol Value
The above equations are solved using Matlab/Simulink to 540V square wave with
simulate the overall model of full bridge self-oscillating Input voltage V inu(t)
variable frequency
PSPWM resonant inverter as shown in Fig.4. This figure Coupling capacitor CC 10μf
consists of five subsystems; the first subsystem is the inverter Resistance of the primary winding
R1 4.3×10-3 Ÿ
and control circuit. It receives the inverter output current (io1) of the matching transformer
Leakage inductance of the primary
and generates a square wave (Vinu(t)) with self-oscillating winding of the matching Ll1 69.66×10-6 H
PSPWM technique. The second subsystem simulates Eq.7. transformer
The third subsystem simulates Eq.8. The fourth subsystem Resistance of core loss Rm 3.4×103 Ÿ
simulates Eq.9 and the Eq.5. The fifth subsystem represents Magnetizing inductance Lm 89×10-3 H
the subsystem of the impedance referring. Resistance of secondary winding of
the matching transformer R2 1.3×10-3 Ÿ
Leakage inductance of the
secondary winding of the matching Ll2 0.49×10-6 H
݅‫݋‬1 ܸ݅݊ ‫)ݐ(ݑ‬ transformer
Primary winding (number of turns)
of the matching transformer N1 12 turns
Secondary winding (number of
Inverter and control circuit turns) of the matching transformer N2 1 turn
Resistance of the work coil Rc 0.02 Ÿ
‫ ݉݅݀( ݉ܮ‬/݀‫)ݐ‬ Ԣ
݅‫݋‬2
Resistance of the workpiece Rw Variable resistance
ܸ݅݊ ‫)ݐ(ݑ‬ ݅݉
Inductance of work coil and load Lo 4 μH
݅‫݋‬1 ݅݉
Series resonant capacitor Co 0.99 μF
ܴ1 ܴ1 ݅‫݋‬1
ܴ݉ ܴ݉
‫ ݉݅݀( ݉ܮ‬/݀‫)ݐ‬
‫݈ܮ‬1 ‫݈ܮ‬1
‫݉ܮ‬
The inverter output voltage (Vinu(t)) and current (io1) with DC-
‫݉ܮ‬
‫ܥܥ‬ ‫ܥܥ‬ FB=1.14V are shown in Fig.6. The Matlab model is operated
Eq. (8) (݀݅݉ /݀‫)ݐ‬ with both cases, locking on the resonance frequency and power
Eq. (7) (݀݅‫݋‬1 /݀‫)ݐ‬
control (power regulation). This figure shows that after 0.23ms,
ܰ1 ܰ1 ‫ܮ‬Ԣ݈2 + ‫ܮ‬Ԣ‫݋‬
‫ ݉݅݀( ݉ܮ‬/݀‫)ݐ‬
the inverter Matlab model is started in a power regulation case
ܰ2 ܰ2 Ԣ
while Vinu(t) becomes a quasi-square wave. At the end of
݅‫݋‬2
ܴ2Ԣ + ܴ‫݋‬Ԣ ‫ܮ‬Ԣ݈2 + ‫ܮ‬Ԣ‫݋‬ Ԣ
݅‫݋‬2 simulation time, from 0.9ms to 1ms, where io1 is regulated at
ܴ2 ܴ2
ܴ2Ԣ + ܴ‫݋‬Ԣ the constant peak level (25A peak current).
ܴܿ ܴܿ ‫݋ܥ‬Ԣ
‫݋ܥ‬Ԣ VI. EXPERIMENTAL RESULTS
ܴ‫ݓ‬ ܴ‫ݓ‬ ܸ‫݋‬Ԣ
ܴ‫݋‬Ԣ ܴ‫݋‬Ԣ ܸ‫݋‬Ԣ The circuit shown in Figs.1 and 2 is practically
‫݈ܮ‬2 ‫݈ܮ‬2
‫ܮ‬Ԣ‫݋‬
implemented to braze two copper workpieces.
‫݋ܮ‬ ‫݋ܮ‬ ‫ܮ‬Ԣ‫݋‬ Figure 6 shows the practical results of the collector voltage
‫݋ܥ‬ ‫݋ܥ‬
Ԣ
Eq. (9)(݀݅‫݋‬2 /݀‫ )ݐ‬and Eq. (5)(ܸ‫݋‬Ԣ ) (Vce) of one transistor (Q4) and output current (i o 1 ) after
locking on the resonant frequency (76.9kHz). This figure
Impedance shows that the output current is in phase with the transistor
referring
collector voltage.
Fig. 4. Overall Matlab/Simulink model of the self-oscillating PSPWM
Figure 7 shows a prototype of the full bridge self-
full bridge series resonant inverter.
oscillating series resonant inverter. Figure 8 shows the
The Matlab/Simulink model parameters of the full bridge Brazing for different shapes and sizes of copper workpieces
self oscillating PSPWM resonant inverter are indicated in which approximately take 150s to achieve this process.
Table-1.
V. MATLAB SIMULATION RESULTS
The overall Simulink/Matlab model of the self-oscillating VII. CONCLUSIONS
PSPWM full bridge series resonant inverter starts at constant In this paper, a self-oscillating control circuit is designed,
free running frequency (50kHz) for a fraction of milliseconds improved, simulated and implemented to drive full bridge
(0.2ms). After 0.2ms, the inverter gets SYNC signal which series resonant inverter used in the induction heating process.
makes the inverter changes the output frequency and locks on The implemented prototype operates at a frequency range (50-
the resonant frequency of the IH load. 100)kHz and 10kW was successfully used for brazing two
The inverter output voltage (Vinu(t)) and current (io1) with copper workpieces.
DC-FB=1.14V (i.e. with power control) are shown in Fig.5.
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
30 io1 (A)

20 Vin u(t)*20 (V)


From this work the following conclusions have been reported:
10
1- The experimental and simulation results show good
0
agreement.
-10
2- The improved circuit has the capability to lock on the
-20
resonance frequency if the starting frequency is less than the
-30 (a)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
resonant frequency.
-3
x 10
Three phase rectifier
Self-oscillating
6 PSPWM
(b) io1 (A) control
4
Vin u(t)*100 (V) circuit
2
Isolated power supply
0

-2
DC
-4 filter
capacitor
-6 IGBTs module
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
Q2/Q3
x 10
-4
IGBTs module
Q1/Q4
50
(c) io1 (A)
Fig. 7. A prototype of the full bridge self-oscillating series resonant
Vin u(t)*15 (V)
inverter.

-50
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
-4
x 10

50
(d) io1 (A)
Time (s) Vin u(t)*15 (V)

Fig. 8. Brazing for different shapes and sizes of copper workpieces.


0

The implemented prototype operates at a frequency range (50-


100)kHz and 10kW was successfully used for brazing two
-50
9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10 copper workpieces. From this work the following conclusions
x 10
-4
have been reported:
3- The experimental and simulation results show good
Fig. 5. Inverter output voltage (Vinu(t)) and current (io1) with DC- agreement.
FB=1.14V (i.e. with power control). 4- The improved circuit has the capability to lock on the
(d)
Time(s) resonance frequency if the starting frequency is less than the
resonant frequency.
5- It has the capability to control the output power. The
ZCS has proven to occur for all the transistors of IGBTs
modules at the resonant frequency before the power control
process starts. When the power control process started, the
ZCS only occurs in one leg of the full bridge inverter while
the other suffers from hard switching.
6- Through high power control process, a high
circulating current occurs which causes high losses at the
primary winding of the matching transformer. But, if the
primary winding of the matching transformer is built using
Litz‫ތ‬V ZLUHV WKLV ZLOO KHOSV WR UHGXFH WKH losses as much as
possible.
Fig. 6. Practical results, m- Collector voltage (Vce) of Q4 (200 V/div.) 7- Through heating process, when the temperature of
and n- Inverter output current (io1) (Tp1) signal (20 V/div.) with time the workpiece is increased the power control process is
scale (2μs/div.) after locking on the resonant frequenc
2016 Al-Sadeq International Conference on Multidisciplinary in IT and Communication Science and Applications (AIC-
MITCSA) – IRAQ (9-10) May
started. This confirms that the inverter current is increased [12] Tomokazu Mishima and Mutsuo Nakaoka, "A Load-
because of decreasing the equivalent workpiece resistance. Power Adaptive Dual Pulse Modulated Current Phasor-
8- The full bridge inverter needs no voltage protection Controlled ZVS High-Frequency Resonant Inverter for
while the power control process is operated as current Induction Heating Applications",IEEE Trans. on Power
protection. Electronics, Vol. 29, No. 8, August 2014.
[13] Tomokazu Mishima, Chikanori Takami, and Mutsuo
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