PCS-9705

PCS-9705
Bay Control & Protection Unit

Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety

The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to be maintained in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
Instructions and Warnings

The following indicators and standard definitions are used:
PCS-9705 Bay Control & Protection Unit i

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Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
environment free of abnormal vibration.
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Preface
 Ratings
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing

features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2017 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD. Tel: +86-25-87178888

Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrec.com
P/N: ZL_PCS-9705_X_Instruction Manual_EN_Customized_ECKF162122 Version: R1.10
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Preface
Documentation Structure
The manual provides a functional and technical description of this device and a comprehensive
set of instructions for the device’s use and application.
All contents provided by this manual are summarized as below.
1 Introduction
Brief introduction of the application, functions and features.
2 Technical Data
Lists of the technical data such as electrical specifications, mechanical specifications, ambient
temperature and humidity range, communication port parameters, type tests and accuracy
limits.
3 Operation Theory
Comprehensive and detailed functional description.
4 Supervision
Automatic self-supervision function of device.
5 Management
Management function (measurement, recording, metering, etc.) of this device.
6 Hardware
Description of plug-in modules and definition of pins.
7 Settings
Setting lists including system settings, communication settings and etc.
8 Human Machine Interface

Description of the HMI panel, LCD display, menu tree and a detailed operating guide
9 Configurable Function
Brief introduction of configurable functions and configuration software.
10 Communication
Supported conmmunication protocol details.
11 Installation
Recommendation for unpacking, handling, inspection and storage with a guide to the
mechanical and electrical installation. A typical wiring connection is also indicated.
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Preface
12 Commissioning
Commissioning recommendation for comprising checks on the calibration and functionality of
device.
13 Maintenance
General maintenance policy.
14 Decommissioning and Disposal

General decommissioning and disposal policy.
15 Manual Version History

List of instruction manual versions and history records of update.
Typographic and Graphical Conventions

Deviations may be permitted in drawings and tables so that the type of designator can be
obviously derived from the illustration.
The following symbols may be used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
SIG Input of binary signal except those signals via opto-coupler
XXX Output signal
Timer
t
Time (optional definite-time or inverse-time characteristic)
t
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Preface
10ms 0ms
Timer [delay pickup (10ms), delay drop off (0ms), non-settable]
[XXX] 0ms
Timer (delay pickup, settable)
0ms [XXX]
Timer (delay drop off, settable)
[XXX] [XXX]
Timer (delay pickup, delay drop off, settable)
IDMT Timer (inverse-time characteristic)
Symbol Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
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1 Introduction
1 Introduction
Table of Contents
1 Introduction .......................................................................................1-a
1.1 Application ....................................................................................................... 1-1
1.2 Function ........................................................................................................... 1-2
1.2.1 Measurement & Control ....................................................................................................... 1-2
1.2.2 Circuit Breaker Protection .................................................................................................... 1-2
1.2.3 Monitoring ............................................................................................................................ 1-2
1.2.4 Auxiliary Function ................................................................................................................. 1-2
1.2.5 Communication .................................................................................................................... 1-3
1.3 Feature ............................................................................................................. 1-3
List of Figures
Figure 1.1-1 Typical application................................................................................................. 1-1
PCS-9705 Bay Control & Protection Unit 1-a
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1 Introduction
1-b PCS-9705 Bay Control & Protection Unit
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1 Introduction
1.1 Application
The PCS-9705 Bay Control & Protection Unit is used for bay level controlling, monitoring and
protection in power grid. It is suitable for applications in Substation Automation System
(abbreviated as SAS) with distributed control IEDs.
The PCS-9705 can be applied into SAS via electrical and optical communication interfaces. It can
send/receive GOOSE (Generic Object Oriented Substation Event) message in station level
network for interlocking signal and in process level network for tripping or other binary signal. The
GOOSE and SV (Sampled Value) communication scheme supports both P2P mode and
networking mode.
Ethernet cable Remote Control Center
Clock synchronization bus

Station Level
Process bus
Control circuit
PCS-9785
PCS-9700 HMI System PCS-9799 Satellite-
(SCADA) Station Manager Synchronized Clock
Printer
PCS-9882
Ethernet Switch
100M/1000M Ethernet MMS/GOOSE Network
Clock Synchronization Bus
BAY 1 BAY n
Bay Level
PCS-9882 PCS-9882
Ethernet Switch Ethernet Switch
PCS-9705 PCS-900 PCS-9600 PCS-9705 PCS-900 PCS-9600

Protection Protection Protection Protection
Relay Relay Relay Relay
PCS-9882
Ethernet Switch
10M/100M Ethernet IEC 61850-9-2
Process Level
(Optional)
PCS-221 PCS-222 PCS-221 PCS-222

Merging Unit Circuit Breaker Controller Merging Unit Circuit Breaker Controller
PCS-9250 Series ECT/EVT Circuit Breaker PCS-9250 Series ECT/EVT Circuit Breaker
Figure 1.1-1 Typical application
The PCS-9705 is designed for controlling, monitoring and protection of switchgears such as
circuit breaker, disconnector, and earthing switch. Additionally, it supports tap changer control for
transformer or shunt reactor.
The PCS-9705 can be used in single bus, double bus, 3/2 CB and bus couple arrangements.
Furthermore, breaker failure protection (50BF), pole discrepancy protection (62PD), phase
overcurrent protection (50/51P), earth fault protection (50/51G), frequency protection (81), closing
synchronism check (25) and auto-reclosure (79) functions are integrated.
PCS-9705 Bay Control & Protection Unit 1-1
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1 Introduction
1.2 Function
1.2.1 Measurement & Control
 AC analog input
 DC analog input
 Configurable binary input
 Binary output for switch control
 CB closing synchronism check (25)
 Programmable interlocking logic
 GOOSE tripping
 Programmable LED indicators
1.2.2 Circuit Breaker Protection

 Breaker failure protection (50BF)
 Pole discrepancy protection (62PD)
 Phase overcurrent protection (50/51P)
 Earth fault protection (50/51G)
 Frequency protection (81)
1.2.3 Monitoring
 Switch status supervision
 DC power supply supervision
 VT circuit supervision (VTS)
 CT circuit supervision (CTS)
1.2.4 Auxiliary Function

 Breaker automatic reclosure (79)
 Voltage and current drift auto adjustment
 Sequence Of Event (SOE) recorder
 Diturbance & Fault Recorder (DFR)
 Clock synchronization methods
 Conventional
 PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
 IRIG-B (RS-485): IRIG-B via RS-485 differential level
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1 Introduction
 PPM (DIN): Pulse per minute (PPM) via the optical coupler
 PPS (DIN): Pulse per second (PPS) via the optical coupler
 SAS
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103): Clock messages through IEC103 protocol
 Advanced
 IRIG-B (Fiber): IRIG-B via optical-fibre interface
 PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface
 NoTimeSyn
1.2.5 Communication
 Ethernet ports conform to IEC 61850-8-1 and NR privat 103 protocols over TCP/IP
 Ethernet ports conform to IEC 61850-9-2 protocol
 RS-485/TTL port for clock synchronization (IRIG-B signal)
 RS-232 port for printer
 Multiplex RJ-45 port for debugging
1.3 Feature
 PCS-9705 adopts a fully closed chassis with a complete panel. Completely isolation for
electronic and electrical system is provided.
 Back plug-in module structure is adopted. Electrical and electronic circuits are strictly
separated to enhance EMC immunity performance.
 PCS-9705 adopts NR's new UAPC hardware platform, 16 bits parallel A/D converter, graphic
dot matrix LCD, and real time multi-task operating system for industrial purpose so as to
realize the high-capacity, high-precision, fast and real-time information processing. With the
high-precision parallel A/D converter, synchronization sampling can be conducted for all the
AC signals to ensure the accuracy of analog quantity measurement.
 Software and hardware clock synchronization are both adopted with 1ms timing accuracy to
ensure the resolution of Sequence Of Events (abbreviated as SOE).
 Large scale LCD providing graph and text makes a convenient humain-machine interaction.
 Low power consumption and wide ambient temperature range.
 Powerful PC tool software can fulfill function configuration, setting modification and waveform
analysis.
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1 Introduction
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2 Technical Data
2 Technical Data
Table of Contents
2 Technical Data ...................................................................................2-a
2.1 Electrical Specification ................................................................................... 2-1
2.1.1 AC Current Input .................................................................................................................. 2-1
2.1.2 AC Voltage Input .................................................................................................................. 2-1
2.1.3 Device Power Supply ........................................................................................................... 2-1
2.1.4 DC Analog Input ................................................................................................................... 2-1
2.1.5 Binary Input .......................................................................................................................... 2-2
2.1.6 Binary Output ....................................................................................................................... 2-2
2.2 Mechanical Specification ................................................................................ 2-2

2.3 Ambient Temperature and Humidity Range .................................................. 2-3
2.4 Communication Port ....................................................................................... 2-3
2.4.1 EIA-485 Port......................................................................................................................... 2-3
2.4.2 Ethernet Port ........................................................................................................................ 2-3
2.4.3 Clock Synchronization Port .................................................................................................. 2-4
2.5 Type Test .......................................................................................................... 2-4

2.5.1 Environmental Test............................................................................................................... 2-4
2.5.2 Mechanical Test ................................................................................................................... 2-4
2.5.3 Insulation Test ...................................................................................................................... 2-4
2.5.4 Electromagnetic Compatibility ............................................................................................. 2-5
2.6 Certifications ................................................................................................... 2-5

2.7 Management Function .................................................................................... 2-6
2.7.1 Measurement Scope and Accuracy ..................................................................................... 2-6
2.7.2 Control Performance ............................................................................................................ 2-6
2.7.3 Clock Performance .............................................................................................................. 2-6
2.7.4 Binary Input Signal ............................................................................................................... 2-6
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2 Technical Data
2.8 Terminal Connecter ......................................................................................... 2-7

2.9 Protective Functions ....................................................................................... 2-7
2.9.1 Fault Detector....................................................................................................................... 2-7
2.9.2 Distance Protection .............................................................................................................. 2-7
2.9.3 Phase Overcurrent Protection ............................................................................................. 2-7
2.9.4 Earth Fault Protection .......................................................................................................... 2-8
2.9.5 Overfrequency Protection .................................................................................................... 2-8
2.9.6 Underfrequency Protection .................................................................................................. 2-8
2.9.7 Breaker Failure Protection ................................................................................................... 2-8
2.9.8 Pole Discrepancy Protection ................................................................................................ 2-8
2.9.9 Auto-reclosing ...................................................................................................................... 2-9
2.9.10 Transient Overreach .......................................................................................................... 2-9
2.9.11 Fault Locator ...................................................................................................................... 2-9
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2 Technical Data
2.1 Electrical Specification

2.1.1 AC Current Input
Phase rotation ABC
Rated frequency (fn) 50Hz
Rated current (In) 1A 5A
Linear to 0.05In~2In or 0.05~40In
Thermal withstand capability
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Max. burden @In 0.15VA/phase 0.25VA/phase
2.1.2 AC Voltage Input

Phase rotation ABC
Rated frequency (fn) 50Hz
Rated voltage (Un) 100V~130V, phase-phase
Linear to (phase-ground) 1V~170V, phase-ground
Thermal withstand capability Phase-ground Phase-phase
-continuously 200V 346V
-10s 260V 450V
-1s 300V 519V
Max. burden @Un 0.20VA/phase
2.1.3 Device Power Supply

Standard IEC 60255-11:2008
Rated voltage 110Vdc/125Vdc/220Vdc/250Vdc 110Vac/220Vac
Operating range 88~300Vdc 88~264Vac
Permissible AC ripple voltage Max. 15% of the nominal auxiliary voltage
Burden
Quiescent condition <30W
Operating condition <35W
2.1.4 DC Analog Input

Input range 0-20mA 0~10V 0~220V
Input resistance 86Ω 112 kΩ 5.12MΩ
Accuracy 0.2% 0.2% 0.5%
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2 Technical Data
2.1.5 Binary Input

Rated voltage 110Vdc 125Vdc 220Vdc 220Vdc
Rated current drain 1.1mA 1.25mA 2.2mA 2.85mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 176-264Vdc
Off value (max.) 55Vdc 62.5Vdc 110Vdc 140Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously)
Response time for logic input ≤1ms
2.1.6 Binary Output

Maximal system voltage 380Vac, 250Vdc
Test voltage across open
1000V RMS in 1min
contact
Output mode Single contact Parallel contacts
Continuous carry 5A 8A
8A@3s 12A@3s
12A@1s 18A@1s
Short duration current
16A@0.5s 24A@0.5s
30A@0.2s 40A@0.2s
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
Pickup time Max. 8ms (typical 3ms)
Drop off time Max. 5ms
Durability Min. 10,000 operations
2.2 Mechanical Specification

Mounting Way Flush mounted
Chassis color Silver grey
Weight per device Approx. 15kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection class IEC 60225-1:2009
HMI side IP51
Terminal side IP30
Other sides IP50
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2 Technical Data
2.3 Ambient Temperature and Humidity Range

Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage
-40°C to +70°C
temperature
Permissible humidity 5%-95%, without condensation
Altitude Max. 3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Transmission distance Max. 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port

2.4.2.1 Electrical Port
Connector type RJ-45

Transmission rate 100Mbits/s
Transmission standard 10Base-T/100Base-TX
Protocol IEC 60870-5-103:1997 or IEC 61850
2.4.2.2 Optical Port (Station Level)
Characteristic Glass optical fiber

Connector type ST or SC
Fiber type Multi-mode (50/125μm, 62.5/125μm)
Transmission distance Max. 2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Receiving power Min. -30.0dBm
Margin Min. +3.0dB
2.4.2.3 Optical Port (Process Level)

Connector type LC ST
Transmission distance Max. 2km
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2 Technical Data
Wave length 1310nm 850nm

Transmission power Min. -20.0dBm
Receiving power Min. -30.0dBm
Margin Min. +3.0dB
2.4.3 Clock Synchronization Port

2.4.3.1 Electrical Port
Type Differential RS-485

Maximal capacity 32
Timing standard PPS, PPM, IRIG-B
2.4.3.2 Optical Port (if available)

Connector type ST
Wave length 820nm
Minimum receiving power Min. -25.0dBm
Margin Min. +3.0dB
2.5 Type Test

2.5.1 Environmental Test
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Test

Vibration test IEC 60255-21-1: 1988 Class I
Shock test IEC 60255-21-2: 1988 Class I
Bump test IEC 60255-21-2: 1988 Class I
Earthquake test IEC 60255-21-3: 1993 Class I
2.5.3 Insulation Test

Standard IEC 60255-27-2013
2.8kV, DC, 1min
Dielectric withstand
2.0kV, AC, 1min
Impulse voltage 5kV
Overvoltage category Class III
Insulation resistance Min. 100MΩ @500Vdc
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2 Technical Data
2.5.4 Electromagnetic Compatibility

IEC 60255-26-2013, Class III
1MHz burst disturbance test Common mode: 2.5kV
Differential mode: 1.0kV
IEC 60255-26-2013, Class IV
Electrostatic discharge test For contact discharge: ±8kV
For air discharge: ±15kV
IEC 60255-26-2013, Class III
Radio frequency interference Frequency sweep
tests Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
IEC 60255-26-2013, Class IV
Fast transient disturbance
Power supply, I/O, Earth: ±4kV, 5kHz for 15ms, 100kHz for 0.75ms
tests
Communication terminals: ±2kV, 5kHz for 15ms, 100kHz for 0.75ms
IEC 60255-26-2013, Class IV
Power supply, AC input, I/O port: 1.2/50μs
Surge immunity test
Common mode: ±4kV
Differential mode: ±2kV
Power frequency magnetic IEC 61000-4-8:2009, Class V
field immunity 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001, Class V
Pulse magnetic field immunity
6.4/16μs, 1000A/m
IEC 60255-26-2013, Class III
Conducted RF
Power supply, AC, I/O, Comm. Terminal: 10Vrms, 150kHz~80MHz
electromagnetic disturbance
Spot frequency, f=27MHz/68MHz
IEC 60255-26-2013, Class A
Power frequency immunity Common mode: 300V
Differential mode: 150V
IEC 60255-26-2013, Class A
Conducted emission
f=0.15MHz~0.5MHz/0.5kHz~30MHz
IEC 60255-26-2013, Class A
Radiated emission
f=30MHz~230MHz/230MHz~1000MHz
Damped oscillatory magnetic IEC 61000-4-10:2001, Class V
field immunity 100kHz & 1MHz, 100A/m
Power supply performance IEC 60255-26-2013
- Voltage dip Max. 200ms for dip to 40% of rated voltage (Un = 220Vdc) without reset
- Voltage short interruption Max. 60ms for interruption falls from and recoveries to 80% of rated voltage (Un
= 220Vdc) without reboot
2.6 Certifications
 ISO9001:2008
 ISO14001:2004
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2 Technical Data
 OHSAS18001:2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 LVD: 2014/35/EU, EN60255-27:2014
2.7 Management Function

2.7.1 Measurement Scope and Accuracy
Item Range Accuracy

Phase range 0°~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
≤ 2.0% of rating (0.05~1.00In)
Current 0.05~5.00In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50Un
≤ 1.0% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Active power (W)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Reactive power (VAr)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Apparent power (VA)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Energy (Wh)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Energy (VAh)
2.7.2 Control Performance

Control mode Local or remote
Accuracy of local control ≤ 1s
Accuracy of remote control ≤ 3s
2.7.3 Clock Performance

Real time clock accuracy ≤ 3s/day
Accuracy of GPS
≤ 1ms
synchronization
External time synchronization IRIG-B (200-98), PPS, PPM or SNTP protocol
2.7.4 Binary Input Signal

Resolution of binary input
≤ 1ms
signal
Binary input mode Potential-free contact
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2 Technical Data
Resolution of SOE ≤ 2ms
2.8 Terminal Connecter

Connecter Type Wire Size
2 2
Screw terminal, 2.5mm ~4.0mm lead
2
AC current input For 4.0mm lead, ONLY dedicated terminal cable lug provided by NR Electric
can be adopted.
2
AC voltage input Screw terminal, 1.5mm lead
2 2
Power supply Screw terminal, 1.0mm ~2.5mm lead
I/O contact Screw terminal, 1.0mm2~2.5mm2 lead
Earthing connection BVR type, 2.5mm²~6.0mm2 lead
2.9 Protective Functions

2.9.1 Fault Detector
2.9.1.1 DPFC Current Element
Setting range 0.050In~30.000In (A)

Accuracy ≤2.5% of setting or 0.02In, whichever is greater
2.9.1.2 Residual Current Element

2.9.1.3 Overvoltage Element
Setting range Un~2Unn (V)

Accuracy ≤2.5% of setting or 0.01Un, whichever is greater
2.9.2 Distance Protection

Setting range (0.000~4Unn)/In (ohm)
Accuracy ≤2.5% of setting or 0.1Ω/In, whichever is greater
Resetting ratio 105%
Time delay 0.000~10.000 (s)
Accuracy ≤1%×Setting+30ms
2.9.3 Phase Overcurrent Protection

Resetting ratio 95%
Time delay 0.000~20.000 (s)
Accuracy (definite-time characteristic) ≤1%×Setting+30ms (at 2 times current setting)
≤2.5% of operating time or 30ms, whichever is greater
Accuracy (inverse-time characteristic)
(for current between 1.2 and 20 multiples of pickup)
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2 Technical Data
2.9.4 Earth Fault Protection

Resetting ratio 95%
Time delay 0.000~20.000 (s)
Accuracy (definite-time characteristic) ≤1%×Setting+30ms (at 2 times current setting)
≤2.5% of operating time or 30ms, whichever is greater
Accuracy (inverse-time characteristic)
(for current between 1.2 and 20 multiples of pickup)
2.9.5 Overfrequency Protection

Setting range 50.00~65.00 (Hz)
Accuracy ≤ 0.02Hz
Time delay 0.000~100.000 (s)
Accuracy ≤1%×Setting+30ms (at 1.2 times frequency setting)
2.9.6 Underfrequency Protection

Setting range 45.00~60.00 (Hz)
Accuracy ≤ 0.02Hz
Time delay 0.000~100.000 (s)
Accuracy ≤1%×Setting+30ms (at 0.8 times frequency setting)
df/dt blocking setting range 0.200~20.000 (Hz/s)
Accuracy ≤ 0.02Hz/s
2.9.7 Breaker Failure Protection

Pick-up time <20ms
Drop-off time <20ms
Setting range of phase current 0.050In~30.000In (A)
Setting range of zero-sequence current 0.050In~30.000In (A)
Setting range of negative-sequence current 0.050In~30.000In (A)
Time delay (first) 0.000~10.000 (s)
Time delay (second) 0.000~10.000 (s)
2.9.8 Pole Discrepancy Protection

Setting range (zero-sequence current) 0.050In~30.000In (A)
Setting range (negative-sequence current) 0.050In~30.000In (A)
Resetting ratio 95%
Time delay 0.000~600.000 (s)
Accuracy ≤1%×Setting+30ms (at 2 times current setting)
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2 Technical Data
2.9.9 Auto-Reclosing
Phase difference setting range 0~89 (Deg)
Accuracy 2.0Deg
Voltage difference setting range 0.02Un~0.8Un (V)
Accuracy Max(0.01Un, 2.5%)
Frequency difference setting range 0.02~1 (Hz)
Accuracy 0.01Hz
Operating time of synchronism check ≤1%×Setting+20ms
Operating time of energizing check ≤1%×Setting+20ms
Operating time of auto-reclosing ≤1%×Setting+20ms
2.9.10 Transient Overreach

Tolerance for all high-speed protection ≤2%
2.9.11 Fault Locator

Accuracy for multi-phase faults with single end feed < ±2.5%
Tolerance will be higher in case of single-phase fault with high ground resistance.
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3 Operation Theory
3 Operation Theory
Table of Contents
3 Operation Theory ..............................................................................3-a
3.1 AC Analog Input .............................................................................................. 3-1
3.2 DC Analog Input .............................................................................................. 3-1
3.3 Binary Input ..................................................................................................... 3-1
3.4 Binary Output .................................................................................................. 3-2
3.5 Tap Changer Control ....................................................................................... 3-3
3.6 Interlocking Logic Output ............................................................................... 3-3
3.7 Synchronism Check for Manual Closing ....................................................... 3-4
3.8 Clock Management .......................................................................................... 3-6
3.9 Circuit Breaker Wear Statistic ........................................................................ 3-6
3.9.1 Function Description ............................................................................................................ 3-6
3.9.2 Function Block...................................................................................................................... 3-7
3.9.3 I/O Signals ............................................................................................................................ 3-7
3.10 Frequency Calculation .................................................................................. 3-7

3.10.1 General Application ............................................................................................................ 3-7
3.10.2 Function Description .......................................................................................................... 3-7
3.10.3 Function Block ................................................................................................................... 3-8
3.10.4 I/O Signal ........................................................................................................................... 3-8
3.10.5 Logic ................................................................................................................................... 3-8
3.11 Circuit Breaker Position Supervision .......................................................... 3-9

3.11.1 General Application ............................................................................................................ 3-9
3.11.2 Function Description .......................................................................................................... 3-9
3.11.3 Function Block .................................................................................................................... 3-9
3.11.4 I/O Signals ........................................................................................................................ 3-10
3.11.5 Logic ................................................................................................................................. 3-11
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3 Operation Theory
3.12 Fault Detector (FD) ...................................................................................... 3-12

3.12.1 General Application .......................................................................................................... 3-12
3.12.2 Fault Detector in Fault Detector DSP .............................................................................. 3-12
3.12.3 Protection Fault Detector in Protection Calculation DSP ................................................ 3-15
3.12.4 Function Block ................................................................................................................. 3-16
3.12.5 I/O Signals........................................................................................................................ 3-16
3.12.6 Logic ................................................................................................................................. 3-17
3.13 Current Direction ......................................................................................... 3-17

3.13.2 Function Description ........................................................................................................ 3-17
3.13.3 Function Block ................................................................................................................. 3-22
3.13.4 I/O Signals........................................................................................................................ 3-22
3.13.5 Settings ............................................................................................................................ 3-23
3.14 Phase Overcurrent Protection.................................................................... 3-23

3.14.3 Function Block ................................................................................................................. 3-26
3.14.4 I/O Signals........................................................................................................................ 3-26
3.14.5 Logic ................................................................................................................................. 3-27
3.14.6 Settings ............................................................................................................................ 3-27
3.15 Earth Fault Protection ................................................................................. 3-32

3.15.3 Function Block ................................................................................................................. 3-34
3.15.4 I/O Signals........................................................................................................................ 3-34
3.15.5 Logic ................................................................................................................................. 3-35
3.15.6 Settings ............................................................................................................................ 3-37
3.16 Frequency Protection ................................................................................. 3-42

3.16.1 Overfrequency Protection ................................................................................................ 3-42
3.16.2 Underfrequency Protection .............................................................................................. 3-44
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3 Operation Theory
3.17 Breaker Failure Protection.......................................................................... 3-48

3.17.3 Function Block ................................................................................................................. 3-49
3.17.4 I/O Signals........................................................................................................................ 3-49
3.17.5 Logic ................................................................................................................................. 3-50
3.17.6 Settings ............................................................................................................................ 3-51
3.18 Pole Discrepancy Protection ...................................................................... 3-51

3.18.3 Function Block ................................................................................................................. 3-52
3.18.4 I/O Signals........................................................................................................................ 3-52
3.18.5 Logic ................................................................................................................................. 3-52
3.18.6 Settings ............................................................................................................................ 3-53
3.19 Synchro-check for Automatic Reclosure .................................................. 3-54

3.19.3 Function Block ................................................................................................................. 3-62
3.19.4 I/O Signals........................................................................................................................ 3-62
3.19.5 Logic ................................................................................................................................. 3-64
3.19.6 Settings ............................................................................................................................ 3-67
3.20 Automatic Reclosure................................................................................... 3-69

3.20.3 Function Block ................................................................................................................. 3-70
3.20.4 I/O Signals........................................................................................................................ 3-71
3.20.5 Logic ................................................................................................................................. 3-72
3.20.6 Settings ............................................................................................................................ 3-84
3.21 Trip Logic ..................................................................................................... 3-86

3.21.1 Application ........................................................................................................................ 3-86
PCS-9705 Bay Control & Protection Unit 3-c
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3 Operation Theory
3.21.3 I/O Signals........................................................................................................................ 3-86
3.21.4 Logic ................................................................................................................................. 3-87
3.21.5 Settings ............................................................................................................................ 3-89
3.22 VT Circuit Supervision ................................................................................ 3-89

3.22.3 Function Block ................................................................................................................. 3-90
3.22.4 I/O Signals........................................................................................................................ 3-90
3.22.5 Logic ................................................................................................................................. 3-91
3.22.6 Settings ............................................................................................................................ 3-92
3.23 CT Circuit Supervision ................................................................................ 3-92

3.23.1 Application ........................................................................................................................ 3-92
3.23.3 Function Block ................................................................................................................. 3-93
3.23.4 I/O Signals........................................................................................................................ 3-93
3.23.5 Logic ................................................................................................................................. 3-93
List of Figures
Figure 3.3-1 Debouncing technique .......................................................................................... 3-2
Figure 3.7-1 Relationship between reference voltage and synchronous voltage ............... 3-4
Figure 3.7-2 Synchro-check logic diagram (manual closing) ................................................ 3-5
Figure 3.7-3 Dead check logic diagram (manual closing) ...................................................... 3-6
Figure 3.10-1 Frequency calculation logic diagram ................................................................ 3-8
Figure 3.11-1 CB position supervision logic diagram ........................................................... 3-11
Figure 3.11-2 Tripping & closing circuit supervision logic diagram ................................... 3-11
Figure 3.11-3 Logic diagram of pole open states .................................................................. 3-12
Figure 3.12-1 Flow chart of protection program .................................................................... 3-16
3-d PCS-9705 Bay Control & Protection Unit
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3 Operation Theory
Figure 3.12-2 Fault detector logic diagram ............................................................................ 3-17
Figure 3.13-1 Line fault description ........................................................................................ 3-17
Figure 3.13-2 Vector diagram of current and voltage............................................................ 3-18
Figure 3.13-3 Vector diagram of zero-sequence power ........................................................ 3-20
Figure 3.14-1 Logic diagram of phase overcurrent protection ............................................ 3-27
Figure 3.15-1 Logic diagram of earth fault protection (stage 1) .......................................... 3-35
Figure 3.15-2 Logic diagram of earth fault protection (stage x) .......................................... 3-36
Figure 3.16-1 Logic diagram of overfrequency protection (start) ....................................... 3-43
Figure 3.16-2 Logic diagram of stage i of overfrequency protection .................................. 3-44
Figure 3.16-3 Logic diagram of underfrequency protection (start) ..................................... 3-46
Figure 3.16-4 Logic diagram of stage i of underfrequency protection ............................... 3-47
Figure 3.17-1 Breaker failure protection logic diagram ........................................................ 3-50
Figure 3.18-1 Pole discrepancy protection logic diagram .................................................... 3-53
Figure 3.19-1 Relationship between reference voltage and synchronism voltage............ 3-54
Figure 3.19-2 Voltage connection 1 for single busbar arrangement ................................... 3-56
Figure 3.19-3 Voltage connection 2 for single busbar arrangement ................................... 3-56
Figure 3.19-4 Voltage connection for double busbars arrangement ................................... 3-57
Figure 3.19-5 Voltage selection for double busbars arrangement ...................................... 3-57
Figure 3.19-6 Voltage connection for one and a half breakers arrangement ..................... 3-58
Figure 3.19-7 Voltage selection for bus CB of one and a half breakers arrangement....... 3-59
Figure 3.19-8 Voltage selection for tie CB of one and a half breakers arrangement ......... 3-60
Figure 3.19-9 Reference voltage circuit failure supervision logic diagram (auto-reclosure)
............................................................................................................................................. 3-61
Figure 3.19-10 Synchronism voltage circuit failure supervision logic diagram

(auto-reclosure) ................................................................................................................. 3-61
Figure 3.19-11 Synchronism check mode selection (auto-reclosure) ................................ 3-65
Figure 3.19-12 Synchronism check logic diagram (auto-reclosure) ................................... 3-65
Figure 3.19-13 Dead charge check mode selection .............................................................. 3-66
Figure 3.19-14 Dead charge check logic diagram (auto-reclosure) .................................... 3-66
Figure 3.19-15 No check mode selection ............................................................................... 3-67
PCS-9705 Bay Control & Protection Unit 3-e
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3 Operation Theory
Figure 3.19-16 Synchro-check logic diagram (auto-reclosure) ........................................... 3-67
Figure 3.20-1 Automatic reclosure block logic diagram ....................................................... 3-73
Figure 3.20-2 Automatic reclosure ready logic diagram ...................................................... 3-74
Figure 3.20-3 Tripping condition output ................................................................................. 3-75
Figure 3.20-4 Single-phase tripping initiating AR ................................................................. 3-76
Figure 3.20-5 Three-phase tripping initiating AR .................................................................. 3-76
Figure 3.20-6 1-pole AR initiation ............................................................................................ 3-77
Figure 3.20-7 3-pole AR initiation ............................................................................................ 3-77
Figure 3.20-8 One-shot AR ....................................................................................................... 3-78
Figure 3.20-9 Extra time delay and blocking logic of AR ..................................................... 3-78
Figure 3.20-10 Reclosing output logic .................................................................................... 3-79
Figure 3.20-11 Wait to slave signal.......................................................................................... 3-79
Figure 3.20-12 Reclosing failure and success ....................................................................... 3-80
Figure 3.20-13 Single-phase transient fault ........................................................................... 3-83
Figure 3.20-14 Single-phase permanent fault ([79.N_Rcls]=2)............................................. 3-84
Figure 3.21-1 Simplified trip logic ........................................................................................... 3-88
Figure 3.21-2 Blocking AR logic .............................................................................................. 3-89
Figure 3.22-1 VT circuit supervision logic diagram .............................................................. 3-91
Figure 3.22-2 VT neutral point supervision logic diagram ................................................... 3-91
Figure 3.22-3 VT circuit supervision logic diagram for measurement ................................ 3-92
Figure 3.23-1 CT circuit failure supervision logic diagram .................................................. 3-93
Figure 3.23-2 CT circuit supervision logic diagram for measurement ............................... 3-93
List of Tables
Table 3.10-1 I/O signals of frequency calculation function .................................................... 3-8
Table 3.11-1 I/O signals of CB position supervision ............................................................. 3-10
Table 3.12-1 I/O signals of fault detector ................................................................................ 3-16
Table 3.13-1 Direction description .......................................................................................... 3-19
3-f PCS-9705 Bay Control & Protection Unit
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3 Operation Theory
Table 3.13-2 I/O signals of current direction .......................................................................... 3-22
Table 3.13-3 Settings of current direction .............................................................................. 3-23
Table 3.14-1 Inverse-time curve parameters .......................................................................... 3-25
Table 3.14-2 I/O signals of phase overcurrent protection .................................................... 3-26
Table 3.14-3 Settings of phase overcurrent protection ........................................................ 3-27
Table 3.15-1 Inverse-time curve parameters .......................................................................... 3-34
Table 3.15-2 I/O signals of earth fault protection................................................................... 3-34
Table 3.15-3 Settings of earth fault protection....................................................................... 3-37
Table 3.16-1 I/O signals of overfrequency protection ........................................................... 3-43
Table 3.16-2 Settings of overfrequency protection ............................................................... 3-44
Table 3.16-3 I/O signals of underfrequency protection......................................................... 3-46
Table 3.16-4 Settings of underfrequency protection ............................................................. 3-47
Table 3.17-1 I/O signals of breaker failure protection ........................................................... 3-49
Table 3.17-2 Settings of breaker failure protection ............................................................... 3-51
Table 3.18-1 I/O signals of pole discrepancy protection....................................................... 3-52
Table 3.18-2 Settings of pole discrepancy protection........................................................... 3-53
Table 3.19-1 I/O signals of synchro-check (auto-reclosure)................................................. 3-62
Table 3.19-2 Synchro-check settings ...................................................................................... 3-67
Table 3.20-1 I/O signals of auto-reclosing .............................................................................. 3-71
Table 3.20-2 Reclosing number ............................................................................................... 3-82
Table 3.20-3 Settings of auto-reclosing .................................................................................. 3-84
Table 3.21-1 I/O signals of trip logic........................................................................................ 3-86
Table 3.21-2 Settings of trip logic............................................................................................ 3-89
Table 3.22-1 I/O signals of VT circuit supervision ................................................................. 3-90
Table 3.22-2 VTS settings ......................................................................................................... 3-92
Table 3.23-1 I/O signals of CT circuit supervision ................................................................. 3-93
PCS-9705 Bay Control & Protection Unit 3-g
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3 Operation Theory
3-h PCS-9705 Bay Control & Protection Unit
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3 Operation Theory
3.1 AC Analog Input

The sampling rate of measurement is 80 points per cycle (0.02s), and the values displayed on
LCD will be refreshed every 0.1s. Besides observing from the LCD, user can use the auxiliary
software PCS-Explorer or SAS system to supervise the measurement via communication
protocol.
Here is the calculation theory of measurement:
N
U 1  U 2 ( n)
N
n 1
N
I 1  I 2 ( n)
N
n 1
1 N
P  [U ( n) I ( n)  U ( n) I ( n)  U ( n) I ( n)]
N n 1 a a b b c c
1 N
Q  [U ( n) I ( n  3 N )  U ( n) I ( n  3 N )  U ( n) I ( n  3 N )]
N n 1 a a 4 b b 4 c c 4
Cos  P
P  Q2
2
N The sampling rate of measurement
P, Q Active/Reactive power calculated by three-meter method
3.2 DC Analog Input

The DC AI module completes the acquisition of incoming DC analog voltage or current, especially
for temperature, humidity or pressure transducer.
The sampling rate of the measurement is 500 SPS (sample-per-second). After algorithm and
digital RC filtering, the measurement can achieve the high accuracy 0.1%.
Besides observing from the LCD of device, user can also use SAS or the auxiliary software
PCS-Explorer to supervise the measurement via communication protocol.
NOTICE!
Different measurement ranges of DC analog input can be selected according to the

right configuration of jumper links in the DC AI module. Please refer to the chapter 6 for
the jumpers’ configuration.
3.3 Binary Input

Electrical signals are introduced into the device via optical isolation and then converted into digital
signals. These signals are configurable in using the auxiliary software PCS-Explorer.
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3 Operation Theory
After the filter circuit and debouncing algorithm processing, external interference can be filtered
effectively. As shown in the following figure, a well-designed debouncing technique is adopted in
this device. Binary input state change within "Debouncing time" (t0-t1 can be set 0~30s) will be
ignored, in order to ensure the accuracy of the signal status. Once there is a confirmation of
change status of signal (start from t1), a SOE record will be noted in the device.
Binary input state
1
Validate the binary
input state change &
write it into SOE
record
Debouncing
time Time
t0 t1
Figure 3.3-1 Debouncing technique
3.4 Binary Output

The control output function performs execution to primary equipment, such as CB/DS/ES
switching, tap position change, etc.
To ensure more security of this function, each binary output consists of power relay, fault detector
relay and output relay in series. An error of one or two relays will not cause the undesired output,
so as to enhance the dependability of binary output. Furthermore, each execution is controlled by
two CPU chips and the circuit to block control is also available to prevent output by mistake during
breakdown of hardware.
The control output function, which is based on the principle "Select Before Operate (abbreviated
as SBO)", can be performed from device LCD (local mode) or SCADA (remote mode).
One integrated procedure of control contains:
1. Send the selection command from device LCD (local mode), or SCADA (remote mode);
2. After logic judgment function, the device returns "selection success" or "fail reason";
3. Send the execution command from device LCD (local mode), or SCADA (remote mode) if the
result "selection success" is received;
4. After logic judgment function, the device does or cancels the execution and returns
corresponding "execution success" or "fail reason";
Synchronism check function is available along with the control output function during a bay
combination to power grid.
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3 Operation Theory
Interlocking control function is also available and configurable logically to accomplish different
switching scheme.
3.5 Tap Changer Control

A tap changer is a connection point selection mechanism along a power transformer winding that
allows a variable number of turns to be selected in discrete steps. A transformer with a variable
turn's ratio is produced, enabling stepped voltage regulation of the output. The tap selection may
be made via an automatic or manual tap changer mechanism.
If only one tap changer is required, manually operated tap points are usually made on the high
voltage (primary) or lower current winding of the transformer to minimize the current handling
requirements of the contacts. However, a transformer may include a tap changer on each winding
if there are advantages to do so. For example, in power distribution networks, a large step-down
transformer may have an off-load tap changer on the primary winding and an on-load automatic
tap changer on the secondary winding or windings. The high voltage tap is set to match long-term
system profile on the high voltage network (typically supply voltage averages) and is rarely
changed. The low voltage tap may be requested to change positions multiple times each day,
without interrupting the power delivery, to follow loading conditions on the low-voltage (secondary
winding) network.
The on-load design is also called on circuit tap changer or On Load Tap Changer (OLTC). For
many power transformer applications, a supply interruption during a tap change is unacceptable,
and the transformer is often fitted with a more expensive and complex OLTC mechanism
electronic.
The control and supervision of OLTC is treated as a special kind of binary output in this device.
The difference with an ordinary one is that, during a tap changer control process, if "running tap"
occurs, the tap position will be out of control (steps up or down continuously). An output contact
"BO_EmergStopTP" is then provided to issue an emergency stop command for this situation.
3.6 Interlocking Logic Output

Programmable interlocking logic is available to accomplish different switching schemes. The
interlocking logic can block the device's capability of primary equipment's switching control. The
logic can be distributed to each IED. For station-wide interlock, an IED communicates via the
system-wide inter-bay bus (IEC 61850-8-1) and an interlocking criterion depends on the circuit
configuration and primary equipment status. For easy and safe implementation of the interlocking
logic, the criterion are configurable to meet any specific requirement.
The interlocking logic function is enabled by setting the parameter [CSWI**.En_Opn_Blk] and
[CSWI**.En_Cls_Blk]. When executing a switching output, if the interlocking logical criterions are
met, besides the internal software interlock, this device also provides hardware interlock with the
help of PLC module (normally open contact output controlled by the result of interlocking logical
calculation).
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3 Operation Theory
3.7 Synchronism Check for Manual Closing

The synchronism check takes effect while combining the bay to power grid. It acquires the
information across the corresponding circuit breaker and compares the information with the
synchronism check related settings. Closing output command is only given if all synchronism
check criterions are satisfied.
This device supports synchronism check for manual closing (remote and local). Several check
modes are available, including no-check mode, synchro-check mode and dead check mode.
Several logic links for synchronism check are listed in "MainMenu"->"Settings"->"Logic

Links"->"Function Links". For device local control mode, the selection of synchronism check
mode is realized in using of these logic links: [25.Link_DeadChk] and [25.Link_SynChk]. For
device remote control mode, all the logic links are invalid and the synchronism check mode will be
determined by remote control system (i.e. SCADA, dispatching centre, etc.).
NOTICE!
[25.Link_DeadChk] and [25.Link_SynChk] can be enabled independently or together.
Please refer to "25.HMI_Mode" in the chapter 7 for more details about the coordination
between the logic links and the selection of remote/local control mode.
 No-Check Logic
All the logic links are disabled (i.e. "0"), and a closing command will be sent out without any
block from the synchronism check logic.
 Synchro-Check Logic
The comparative relationship between the reference voltage and the incoming voltage for
synchro-check is as follow.
UL
UB
Figure 3.7-1 Relationship between reference voltage and synchronous voltage
UL Line voltage
UB Bus voltage
This figure shows the characteristics of synchro-check element used for CB closing if both
line and busbar are live. The element operates if the voltage difference, frequency difference,
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3 Operation Theory
slip frequency difference and phase angle difference are all within their setting ranges.
1. The voltage difference is checked by the following equation
[25.U_LiveChk] ≤ UB
[25.U_LiveChk] ≤ UL
[25.U_Diff_SynChk] ≤ |UB- UL|
2. The frequency difference is checked by the following equation
|f(UB)-f(UL)| ≤ [25.f_Diff_SynChk]
3. The slip frequency difference is checked by the following equation
df/dt ≤ [25.df/dt_SynChk]
4. The phase difference is checked by the following equation
∆δ ≤ [25.phi_Comp_Diff]
NOTICE!
If the logic setting [25.Opt_Mode_SynChk]=1, the phase difference will be fixed at 1

degree, and the condition 4 is always satisfied.
SIG [BI_Rmt/Loc]=0 (Local mode)

SIG df/dt ≤ [25.df/dt_SynChk]
Δt=1.667ms
SIG ΔU ≤ [25.U_Diff_SynChk] & 25.BI_RSYN_OK
SIG Δf ≤ [25.f_Diff_SynChk]
SIG Δδ ≤ [25.phi_Comp_Diff]
Figure 3.7-2 Synchro-check logic diagram (manual closing)
 Dead Check Logic
This logic checks only the voltages for synchronism. Several options are supported, please
refer to "Syn Settings" in the chapter 7 for more details about these modes.
The device will calculate the measured bus voltage and line voltage at both sides of the
circuit breaker and compare them with the settings [25.U_LiveChk] and [25.U_DeadChk]. If
the voltage is higher than [25.U_LiveChk], the bus/line is regarded as live. If the voltage is
lower than [25.U_DeadChk], the bus/line is regarded as dead.
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3 Operation Theory
SIG UABC < [25.U_DeadChk]

SIG USyn < [25.U_DeadChk] Dead
Check
SIG UABC > [25.U_LiveChk]
SIG USyn > [25.U_LiveChk]
Δt=1.667ms
& 25.BI_RSYN_OK
SET [25.Opt_Mode_DeadChk]
SIG [YYY Y.Alm_VTS_Measmt]

SIG [BI_Rmt/Loc]=0 (Local mode)
Figure 3.7-3 Dead check logic diagram (manual closing)
3.8 Clock Management

 Real-Time Clock
The MON module in this device has an inner real-time high-precision clock. This clock can
last for one month even if the device is switched off.
 Clock Synchronization
The clock synchronization function supports various synchronization signals, including

differential IRIG-B, optical fiber IRIG-B, optical fiber PPS, differential PPS, free contact
PPS/PPM, SNTP broadcast, SNTP peer-to-peer, received from a timing source device (E.g. :
RCS-9785 GPS Synchronized Clock).
3.9 Circuit Breaker Wear Statistic
3.9.1 Function Description
The circuit breaker wear is caused by breaking current when a CB is tripped by a protection
operation or a control command.
During a CB tripping process, when the BCU detects a CB position change from close to open,
the CB wear statistic process starts. After a tripping execution, within 10s, if the CB open position
is detected, the CB wear statistic process will be effective. During a CB wear statistic process, the
maximal breaking current is recorded to be compared with the current in the CB wear table, which
is provided by the CB manufacturer. Then, BCU can calculate the CB wear status.
Generally, the value of "CBWear.Stat" is proportional to the root-mean-square value of the

breaking current. If it is greater than the corresponding threshold [CBWear.Th_Wear], the alarm
"CBWear.Alm " will be issued. This alarm will be displayed in the LCD of BCU and can be sent to
SAS.
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3 Operation Theory
3.9.2 Function Block
CBWear
CBWear.Ia CBWear.N_Trp
CBWear.Ib CBWear.Alm
CBWear.Ic CBWear.Stat
52a
52b
3.9.3 I/O Signals
No. Input Signal Description

1 CBWear.Ia
2 CBWear.Ib The measured three-phase currents through the CB
3 CBWear.Ic
4 52a The CB CLOSE position
5 52b The CB OPEN position
No. Output Signal Description
1 CBWear.N_Trp The tripping counter
2 CBWear.Alm The CB wear alarm
3 CBWear.Stat The CB wear statistic
3.10 Frequency Calculation

3.10.1 General Application
The frequency is an important parameter to characterize power system, and the measurement
and calculation of frequency are the basis of many protection functions. The frequency calculation
module can accurately calculate the frequency of voltage component.

Protection device can be applied to the power system within frequency range of 40Hz~63Hz, the
reference frequency can be set as 50Hz or 60Hz via the system setting [Opt_SysFreq].
Protection device provide frequency tracing function, which can improve the accuracy of
protection algorithm and the performance of protection devices. For the power system using 50Hz
or 60Hz as reference frequency, the frequency tracing function can be disabled if the fluctuation of
the frequency range is not great. For the power system that the fluctuation of the frequency range
is great, the frequency tracing function can be enabled to improve protection performance.
Frequency tracing module adopts the positive-sequence voltage which derived from protection
used voltage as the calculation reference, the positive-sequence voltage can be calculated as
following:
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U1  (U a  Ube j120  U c e j 240 ) / 3
When no VT is connected to the protection device, the frequency tracing function is disabled
automatically, then the protection device calculates protection algorithm using the system
reference frequency. When the protection device detects a fault happening to the power system or
the voltage is smaller than 0.15Un, the frequency tracing function is disabled.
This module, which combines all above cases, outputs system frequency to the various protection
functions.
FreqCal
FreqTrack f
fn Alm_Freq
3.10.4 I/O Signal

Table 3.10-1 I/O signals of frequency calculation function

It is used to enabled or disable frequency track function by the configuration
1 FreqTrack
software PCS-Explorer.
2 fn It is the system frequency, which is decided by the setting [Opt_SysFreq].
1 f Frequency calculation result
2 Alm_Freq Frequency abnormality alarm
3.10.5 Logic
SIG U3P
fn Freqence
SIG f
calulation
SIG FreqTrace
SIG f<[f_Low_FreqAlm] >=1

Alm_Freq
SIG f>[f_High_FreqAlm]
Figure 3.10-1 Frequency calculation logic diagram
FreqTrace: Frequency calculation function is enabled.
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3.11 Circuit Breaker Position Supervision

The status of circuit breaker (CB) position is applied for protection and control functions in this
device, such as, PD protection, auto-reclose and VT circuit supervision, etc. The status of CB
position can be applied as input signals for other features configured by user.

The signal reflecting CB position is acquired via opto-coupler with settable delay pickup and
drop-off, and forms digital signal used by protection functions. CB position can reflect the status of
each phase by means of phase-segregated inputs.
In order to prevent that wrong status of CB position is input into the device via binary input,
appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected but there is current detected in the line, the status of CB
position will be thought as incorrect and an alarm [Alm_52b] will be issued.
Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.

1. For phase-segregated circuit breaker
CB Position Supervision
52b_PhA Alm_52b
52b_PhB
52b_PhC
2. For non-phase segregated circuit breaker
CB Position Supervision
52b Alm_52b
3. Tripping & closing circuit supervision (TCCS)
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TCCS
52a TCCS.Alm
52b
TCCS.Input
TCCS will be disabled automatically when it is used for phase-segregated circuit breaker.
3.11.4 I/O Signals

Table 3.11-1 I/O signals of CB position supervision

1 52b_PhA Normally closed contact of A-phase of circuit breaker
2 52b_PhB Normally closed contact of B-phase of circuit breaker
3 52b_PhC Normally closed contact of C-phase of circuit breaker
5 52b Normally closed contact of three-phase of circuit breaker
6 52a Normally open contact of three-phase of circuit breaker
Control circuit failure (normally closed contact and normally open contact of
7 TCCS.Input three-phase circuit breaker are all de-energized due to DC power loss of control
circuit)
1 Alm_52b CB position is abnormal
2 TCCS.Alm Control circuit of circuit breaker is abnormal
NOTICE!
The signal [52a] only take effect in the tripping/closing circuit supervision and not affect
any protection function. Only if tripping/closing circuit supervision is configured, this
signal needs to be connected to the device.
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3.11.5 Logic
BI [52b_PhA] >=1
&
&
BI [52b_PhB] >=1
& &
BI [52b_PhC] >=1 >=1

&
BI [52b]
&
SIG Ia>I_Line
>=1
& >=1 10s 10s Alm_52b
SIG Ib>I_Line
&
SIG Ic>I_Line
Figure 3.11-1 CB position supervision logic diagram
BI [52a] >=1
>=1
BI [52b] [TCCS.t_DPU] [TCCS.t_DDO] TCCS.Alm
BI [TCCS.Input]
Figure 3.11-2 Tripping & closing circuit supervision logic diagram
I_Line is the threshold value used to determine whether line is on-load or no-load. Its default value
is 0.06In.
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SIG 52b_PhA &

50ms 0ms
SIG Ia<I_Line
SIG 52b_PhB &

50ms 0ms
SIG Ib<I_Line
SIG 52b_PhC &

50ms 0ms
SIG Ic<I_Line
>=1
SET
SIG Trp A S Q & Pole A open
50ms 0ms
SIG FD.Pkp R CLR Q
SIG Ia<I_Line
>=1
SET
SIG Trp B S Q & Pole B open
50ms 0ms
R CLR Q
SIG Ib<I_Line
>=1
SET
SIG Trp C S Q & Pole C open
50ms 0ms
R CLR Q
SIG Ic<I_Line
Figure 3.11-3 Logic diagram of pole open states
3.12 Fault Detector (FD)

The device has one DSP module with fault detector DSP and protection DSP for fault detector and
protection calculation respectively. Protection DSP with protection fault detector element is
responsible for calculation of protection elements, and fault detector DSP is responsible to
determine fault appearance on the protected power system. Fault detector in fault detector DSP
picks up to provide positive supply to output relays. The output relays can only operate when both
the fault detector in fault detector DSP and a protection element operate simultaneously.
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
outputs if a protection element operates while the fault detector does not operate.
3.12.2 Fault Detector in Fault Detector DSP

Main part of FD is DPFC (Deviation of Power Frequency Component) current detector element
that detects the change of phase-to-phase power frequency current, and residual current fault
detector element that calculates the vector sum of 3 phase currents as supplementary. They are
continuously calculating the analog input signals.
All fault detectors in this device include:
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1. Fault detector based on DPFC current: DPFC current is greater than the setting value
2. Fault detector based on residual current: Residual current is greater than the setting value
3. Fault detector based on negative-sequence current: Negative-sequence current is greater

than the setting value
4. Fault detector based on phase current: Phase current is greater than the setting value
5. Fault detector based on voltage: Phase voltage or phase-to-phase voltage is greater than the
setting value
6. Fault detector based on circuit breaker position: Circuit breaker position discrepancy
If any of the above conditions is complied, FD will operate to activate the output circuit providing
DC power supply to the output relays, then all protection functions are permitted to operate when
FD operate. The fault detector based on DPFC current and the fault detector based on residual
current are always enabled.
3.12.2.1 Fault Detector Based on DPFC Current (pickup condition 1)
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of
a cycle before.
ΔI = I(k)-I(k-24)
Where:
I(k) is the sampling value at a point.
I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.12-1.
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For multi-phase short-circuit fault, the DPFC phase-to-phase current has high sensitivity to ensure
the pickup of protection device. For usual single phase to earth fault, it also has sufficient
sensitivity to pick up except the earth fault with very large fault resistance. Under this condition the
DPFC current is relative small, however, residual current is also used to judge pickup condition
(pickup condition 2).
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steadily under normal or power swing
condition, the adaptive floating threshold with the ΔISet is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
ΔIΦΦMAX>1.25ΔITh+ΔISet Equation 3.12-1
Where:
ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC, CA)
ΔISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ΔITh: The floating threshold value
The coefficient "1.25" is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operating condition is met, the fault detector based on DPFC current will operate to provide DC
power supply for output relays, the pickup signal will maintain 7s after the fault detector based on
DPFC current drops off.
3.12.2.2 Fault Detector Based on Residual Current (pickup condition 2)
The operation condition will be met when 3I0 is greater than the setting [FD.ROC.3I0_Set]. The
fault detector based on residual current is always in service.
Where:
3I0: residual current calculates from the vector sum of Ia, Ib and Ic
When the fault detector based on residual current operates and lasts for longer than 10 seconds,
an alarm [Alm_Pkp_I0] will be issued.
If operation condition is met, the fault detector based on residual current will operate to provide
DC power supply for output relay, and the pickup signal will maintain 7s after the fault detector
based on residual current drops off.
3.12.2.3 Fault detector Based on Negative-sequence Current
The operation condition will be met when negative-sequence current (I2) is greater than the
setting [FD.NOC.I2_Set]. It can be enabled or disabled by the logic setting [FD.NOC.En].
If operation condition is met, the fault detector based on negative-sequence current will operate to
provide DC power supply for output relay, and the pickup signal will maintain 7s after the fault
detector based on negative-sequence current drops off.
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3.12.2.4 Fault Detector Based on Phase Current
The fault detector based on phase current will operate to provide DC power supply for output relay
when phase overcurrent protection is enabled and meets the operation condition, and the pickup
signal will maintain 500ms after the fault detector based on phase current drops off.
3.12.2.5 Fault Detector Based on Voltage
This fault detector based on voltage includes the fault detectors of overvoltage protection, under
voltage protection and frequency protection. The fault detector based on voltage will operate to
provide DC power supply for output relay when corresponding voltage element is enabled and
meets the operation condition, and the pickup signal will maintain 500ms after the fault detector
based on voltage drops off.
3.12.2.6 Fault Detector Based on Circuit Breaker Position
When pole discrepancy protection is enabled, i.e. the logic setting [62PD.En] is set as "1", and if
three phases of circuit breaker are not in the same status, the fault detector based on circuit
breaker position will operate to provide DC power supply for output relays, and the pickup signal
will maintain 500ms after the the fault detector based on circuit breaker position drops off.
3.12.3 Protection Fault Detector in Protection Calculation DSP

The protection device is running either of the two programs: one is "Regular program" for normal
state, and the other is "Fault calculation program" after protection fault detector picks up.
Under the normal state, the protection device will perform the following tasks:
1. Calculate analog quantity
2. Read binary input
3. Hardware self-check
4. Circuit breaker position supervision
5. Analog quantity input supervision
Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of phase overcurrent
protection, and to determine logic. If the fault is within the protected zone, the protection device
will send tripping command.
The protection program flow chart is shown as Figure 3.12-1.
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Main program
Sampling program
No Yes
Pickup?
Regular program Fault calculation program
Figure 3.12-1 Flow chart of protection program
The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
refer to section 3.12.2 for details.
FD
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
FD.NOC.Pkp
3.12.5 I/O Signals

Table 3.12-1 I/O signals of fault detector

1 FD.Pkp The device picks up
2 FD.DPFC.Pkp DPFC current fault detector element operates.
3 FD.ROC.Pkp Residual current fault detector element operates.
4 FD.NOC.Pkp Negative-sequence fault detector element operates.
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3.12.6 Logic
SIG Ia Calculate DPFC phase-to- ΔIab>[FD.DPFC.I_Set]

phase current: >=1
ΔIab=Δ(Ia-Ib)
SIG Ib ΔIbc>[FD.DPFC.I_Set] FD.DPFC.Pkp
ΔIbc=Δ(Ib-Ic)
ΔIca=Δ(Ic-Ia)
SIG Ic ΔIca>[FD.DPFC.I_Set] >=1
0s 7s FD.Pkp
Calculate residual current:

3I0>[FD.ROC.3I0_Set] FD.ROC.Pkp
3I0=Ia+Ib+Ic
Calculate negative-
I2>[FD.NOC.I2_Set] &
sequence current: I2
FD.NOC.Pkp
EN FD.NOC.En
Figure 3.12-2 Fault detector logic diagram
3.13 Current Direction

Overcurrent protection is widely used in the power system as backup protection, but in some
cases, the direction of current is necessary to aid to complete the selective tripping. As shown
below:
L M N
EM C D A B EN
Fault
Figure 3.13-1 Line fault description
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional
earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to
detect high resistance fault.

The module computes direction of phase current and phase-to-phase current, zero-sequence
current and negative-sequence current.
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The direction of phase current and phase-to-phase current equips with an under-voltage direction
function to ensure that phase or phase-to-phase overcurrent protection has explicit directionality
when the polarized voltage is too low for close up fault.
The direction of zero-sequence current and negative-sequence current direction equips with an
impedance compensation function to ensure that zero-sequence or negative-sequence
overcurrent protection has explicit directionality when the zero-sequence voltage or the
negative-sequence voltage is too low.
3.13.2.1 Phase/Phase-to-phase Current Direction
By setting the characteristic angle [RCA_OC] to determine the most sensitive forward angle of
phase current and phase-to-phase current, power value is calculated using phase current with
phase polarized voltage or phase-to-phase current with phase-to-phase polarized voltage to
determine the direction of phase current or phase-to-phase current respectively in forward
direction or reverse direction. When the power value is zero, neither forward direction nor reverse
direction is considered. As shown below:
jX
U
φ
θ I
R
O
Forward direction
Reverse direction
Figure 3.13-2 Vector diagram of current and voltage
Where:
φ is the setting [RCA_OC]
θ is the phase angle between polarized voltage and current
The power value is calculated as below:
P=U×[I×COS(θ-φ)]
1. If P>0, the current direction polarized by U is forward direction
2. If P<0, the current direction polarized by U is reverse direction
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From above diagram can be seen, when θ=φ, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, φ is called as sensitivity angle of phase
overcurrent protection.
1. Polarized voltage of phase or phase-to-phase current direction
In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
cycles pre-fault positive-sequence voltage.
2. Phase or phase-to-phase current direction under normal polarized voltage condition
When using normal polarized voltage to calculate phase and phase-to-phase current direction,
there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.13-1 Direction description
Direction Polarized Voltage Current

Forward direction U1a Ia
Phase A
Reverse direction U1a Ia
Forward direction U1b Ib
Phase B
Reverse direction U1b Ib
Forward direction U1c Ic
Phase C
Reverse direction U1c Ic
Forward direction U1ab Iab
Phase AB
Reverse direction U1ab Iab
Forward direction U1bc Ibc
Phase BC
Reverse direction U1bc Ibc
Forward direction U1ca Ica
Phase CA
Reverse direction U1ca Ica
3. Phase or phase-to-phase current direction for under-voltage conditions
When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
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3.13.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.
jX 3U0
θ-180°
-3I0
φ
R
O
3I0
θ Reverse direction
Forward direction
Figure 3.13-3 Vector diagram of zero-sequence power
Vector diagram of negative-sequence power is similar to that of zero-sequence power.
Where:
φ is the setting [RCA_ROC] or the setting [RCA_NegOC]
θ is the phase angle between zero/negative-sequence voltage and zero/negative-sequence

current
3I0: calculated zero-sequence current by vector sum of Ia, Ib and Ic
The power value is calculated as below:
P=U×[I×COS(θ-φ)]
 If P>0, the direction of zero /negative-sequence current is reverse direction
 If P<-0.1InVA, the direction of zero /negative-sequence current is forward direction
1. The direction of zero-sequence current
Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
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3 Operation Theory
to determine the direction of zero-sequence current
According to the equation:
The zero-sequence current and the zero-sequence voltage can be gained by calculation
Zero-sequence power is: P=3U0×[3I0×COS(θ-φ)]
2. The direction of negative-sequence current
Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:
The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2×[3I2×COS(θ-φ)]
3. The direction of zero-sequence/negative-sequence current with impedance compensation
When zero-sequence impedance or negative-sequence impedance behind the device is very

small, if the fault in forward direction happens, the measured zero-sequence voltage or
negative-sequence voltage by the device may be relatively small to determine correct direction. In
order to solve this problem, compensated zero-sequence voltage and negative-sequence voltage
are used for power calculation.
The compensation formula is as follows:
is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line
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DIR
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
FwdDir_C
RevDir_A
RevDir_B
RevDir_C
FwdDir_AB
FwdDir_BC
FwdDir_CA
RevDir_AB
RevDir_BC
RevDir_CA
3.13.4 I/O Signals

Table 3.13-2 I/O signals of current direction

1 FwdDir_ROC The forward direction of zero-sequence power
2 RevDir_ROC The reverse direction of zero-sequence power
3 FwdDir_NegOC The forward direction of negative-sequence power
4 RevDir_NegOC The reverse direction of negative-sequence power
5 FwdDir_A The forward direction of phase-A current
6 FwdDir_B The forward direction of phase-B current
7 FwdDir_C The forward direction of phase-C current
8 RevDir_A The reverse direction of phase-A current
9 RevDir_B The reverse direction of phase-B current
10 RevDir_C The reverse direction of phase-C current
11 FwdDir_AB The forward direction of phase-AB current
12 FwdDir_BC The forward direction of phase-BC current
13 FwdDir_CA The forward direction of phase-CA current
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14 RevDir_AB The reverse direction of phase-AB current

15 RevDir_BC The reverse direction of phase-BC current
16 RevDir_CA The reverse direction of phase-CA current
3.13.5 Settings
Table 3.13-3 Settings of current direction
No. Name Range Step Unit Remark

The characteristic angle of directional phase overcurrent
1 RCA_OC 30~89 0.01 deg
element
The characteristic angle of directional earth fault
2 RCA_ROC 30~89 0.01 deg
element
The characteristic angle of directional
3 RCA_NegOC 30~89 0.01 deg
negative-sequence overcurrent element
4 Z0_Comp (0.000~4Unn)/In 0.001 ohm The compensated zero-sequence impedance
5 Z2_Comp (0.000~4Unn)/In 0.001 ohm The compensated negative-sequence impedance
3.14 Phase Overcurrent Protection

When a fault occurs in power system, usually the fault current would be very large and phase
overcurrent protection operates monitoring fault current is then adopted to avoid further damage
to protected equipment. Directional element can be selected to improve the sensitivity and
selectivity of the protection. For application on feeder-transformer circuits, second harmonic can
also be selected to block phase overcurrent protection to avoid the effect of inrush current on the
protection.

Phase overcurrent protection has following functions:
1. Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
2. All stages can be selected as definite-time or inverse-time characteristic. The inverse-time

characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of phase overcurrent
protection.
3. Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.
4. Second harmonic can be selected to block each stage of phase overcurrent protection.
3.14.2.1 Overview
Phase overcurrent protection consists of following three elements:
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1. Overcurrent element: each stage is independent overcurrent element.
2. Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction. When phase
overcurrent protection is controlled by direction control element, negative-sequence current
direction element is also effective to ensure correct operation, especially for phase-to-phase
fault.
3. Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.
3.14.2.2 Phase Overcurrent Element
The operation criterion for each stage of overcurrent element is:
Ip> [50/51Px.I_Set] Equation 3.14-1
Where:
Ip is measured phase current.
[50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element.
3.14.2.3 Direction Control Element
In order to prevent phase current direction element from overreaching operation characteristic for
phase-to-phase fault, negative-sequence current direction element is also used as auxiliary
direction criterion of phase overcurrent protection for asymmetric fault. Please refer to Section
3.13 for details.
3.14.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder-transformer circuits harmonic

blocking function can be selected for each stage of phase overcurrent element by configuring
logic setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled.
Operation criterion:
IP_2nd>[50/51P. K_Hm2]×IP Equation 3.14-2
Where:
is second harmonic of phase current
is fundamental component of phase current.
[50/51P.K_Hm2] is harmonic blocking coefficient.
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If fundamental component of any phase current is lower than the minimum operating current
(0.1In), then harmonic calculation is not carried out and harmonic blocking element does not
operate.
3.14.2.5 Characteristic Curve
All stages can be selected as definite-time or inverse-time characteristic, inverse-time operating

characteristic is as follows.
Equation 3.14-3
Where:
Iset is current setting [50/51Px.I_Set].
Tp is time multiplier setting [50/51Px.TMS].
α is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.14-1 Inverse-time curve parameters
50/51Px.Opt_Curve Time Characteristic K α C

DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined
If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as
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“UserDefine” to customize the inverse-time curve characteristic with constants α, K and C. (only
stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Px.tmin], then the operating time of the protection changes to the value of setting
[50/51Px.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.
50/51Px
50/51Px.En1 50/51Px.On
50/51Px.En2 50/51Px.StA
50/51Px.Blk 50/51Px.StB
50/51Px.StC
50/51Px.St
50/51Px.Op
3.14.4 I/O Signals

Table 3.14-2 I/O signals of phase overcurrent protection

Stage x of phase overcurrent protection enabling input 1, it is triggered from binary
1 50/51Px.En1
input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from binary
2 50/51Px.En2
Stage x of phase overcurrent protection blocking input, it is triggered from binary
3 50/51Px.Blk
1 50/51Px.On Stage x of phase overcurrent protection is enabled.
2 50/51Px.Op Stage x of phase overcurrent protection operates.
3 50/51Px.St Stage x of phase overcurrent protection starts.
4 50/51Px.StA Stage x of phase overcurrent protection starts (A-Phase).
5 50/51Px.StB Stage x of phase overcurrent protection starts (B-Phase).
6 50/51Px.StC Stage x of phase overcurrent protection starts (C-Phase).
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3.14.5 Logic
SET Ia>[50/51Px.I_Set] &

50/51Px.StA
SET Ib>[50/51Px.I_Set]
SET Ic>[50/51Px.I_Set]
&
SET [50/51Px.Opt_Dir]=Foward & 50/51Px.StB
SIG Forward DIR
SET [50/51Px.Opt_Dir]=Reverse & &

50/51Px.StC
SIG Reverse DIR
>=1
SET [50/51Px.Opt_Dir]=Non_Directional
>=1
SIG VTS.Alm & 50/51Px.St
Timer
EN [50/51P1.En_VTS_Blk] t
50/51Px.Op
t
SIG I3P 2nd Hm Detect & &
SET [50/51Px.En_Hm2_Blk]
EN [50/51Px.En]
&
SIG 50/51Px.En1 &
50/51Px.On
SIG 50/51Px.En2
&
SIG 50/51Px.Blk
SIG FD.Pkp
Figure 3.14-1 Logic diagram of phase overcurrent protection
x=1, 2, 3, 4
3.14.6 Settings
Table 3.14-3 Settings of phase overcurrent protection

Setting of second harmonic component for
1 50/51P.K_Hm2 0.000~1.000 0.001
blocking phase overcurrent elements
Current setting for stage 1 of phase
2 50/51P1.I_Set (0.050~30.000)×In 0.001 A
overcurrent protection
Time delay for stage 1 of phase overcurrent
3 50/51P1.t_Op 0.000~20.000 0.001 s
protection
Enabling/disabling stage 1 of phase
4 50/51P1.En 0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing blocked
5 50/51P1.En_BlkAR 0 or 1
when stage 1 of phase overcurrent protection
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operates
0: disable
1: enable
Enabling/Disabling stage 1 of phase
overcurrent protection is blocked by VT
6 50/51P1.En_VTS_Blk 0 or 1 circuit failure
0: disable
1: enable
Non-Directional
Direction option for stage 1 of phase
7 50/51P1.Opt_Dir Forward
Reverse
Enabling/disabling second harmonic blocking
for stage 1 of phase overcurrent protection
8 50/51P1.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIE Option of characteristic curve for stage 1 of
9 50/51P1.Opt_Curve
ANSIV phase overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 1 of
10 50/51P1.TMS 0.010~200.000 0.001
inverse-time phase overcurrent protection
Minimum operating time for stage 1 of
11 50/51P1.tmin 0.000~20.000 0.001 s
Constant “α” for stage 1 of customized
12 50/51P1.Alpha 0.010~5.000 0.001 inverse-time characteristic phase overcurrent
protection
Constant “C” for stage 1 of customized
13 50/51P1.C 0.000~20.000 0.001 inverse-time characteristic phase overcurrent
protection
Constant “K” for stage 1 of customized
14 50/51P1.K 0.050~20.000 0.001 inverse-time characteristic phase overcurrent
protection
15 50/51P2.I_Set (0.050~30.000)×In 0.001 A Current setting for stage 2 of phase
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16 50/51P2.t_Op 0.000~20.000 0.001 s
protection
17 50/51P2.En 0 or 1
0: disable
1: enable
18 50/51P2.En_BlkAR 0 or 1 operates
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
21 50/51P2.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for stage 2 of
22 50/51P2.Opt_Curve ANSIE
phase overcurrent protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
23 50/51P2.TMS 0.010~200.000 0.001
inverse-time phase overcurrent protection.
24 50/51P2.tmin 0.000~20.000 0.001 s
25 50/51P3.I_Set (0.050~30.000)×In 0.001 A
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26 50/51P3.t_Op 0.000~20.000 0.001 s
protection
27 50/51P3.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
31 50/51P3.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
33 50/51P3.TMS 0.010~200.000 0.001
34 50/51P3.tmin 0.000~20.000 0.001 s
35 50/51P4.I_Set (0.050~30.000)×In 0.001 A
36 50/51P4.t_Op 0.000~20.000 0.001 s Time delay for stage 4 of phase overcurrent
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protection
37 50/51P4.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
41 50/51P4.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
43 50/51P4.TMS 0.010~200.000 0.001
44 50/51P4.tmin 0.010~20.000 0.001 s
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3 Operation Theory
3.15 Earth Fault Protection

During normal operation of power system, there is trace residual current, whereas a fault current
flows to earth will result in greater residual current. Therefore, residual current is adopted for the
calculation of earth fault protection.
In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
line-transformer unit, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.

Earth fault protection has following functions:
1. Four-stage earth fault protection with independent logic, current and time delay settings.
2. All stages can be selected as definite-time or inverse-time characteristic. The inverse-time

characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of earth fault protection.
3. Directional element can be selected to control each stage of earth fault protection with three
options: no direction, forward direction and reverse direction.
4. Second harmonic can be selected to block each stage of earth fault protection.
5. Stage 2, 3, 4 of earth fault protection can enable short time delay to improve operation speed.
3.15.2.1 Overview
Earth fault protection consists of following three elements:
1. Overcurrent element: each stage equipped with one independent overcurrent element.
2. Directional control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3. Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.
3.15.2.2 Zero-sequence Overcurrent Element
The operation criterion for each stage of earth fault protection is:
3I0>[50/51Gx.3I0_Set] Equation 3.15-1
Where:
3I0 is the calculated residual current.
[50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection.
Date: 2017-08-17
3 Operation Theory
3.15.2.3 Direction Control Element
Please refer to section 3.13 for details.
3.15.2.4 Harmonic Blocking Element
In order to prevent effects of inrush current on earth fault protection, harmonic blocking function
can be selected for each stage of earth fault element by configuring logic setting
[50/51Gx.En_Hm2_Blk] (x=1, 2, 3 or 4).
When the percentage of second harmonic component to fundamental component of residual

current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled
Operation criterion:
I0_2nd>[50/51G. K_Hm2]×I0 Equation 3.15-2
Where:
is second harmonic of residual current
is fundamental component of residual current.
[50/51G.K_Hm2] is harmonic blocking coefficient.
If fundamental component of residual current is lower than the minimum operating current (0.1In)
then harmonic calculation is not carried out and harmonic blocking element does not operate.
3.15.2.5 Characteristic Curve
All 4 stages earth fault protection can be selected as definite-time or inverse-time characteristic,
and inverse-time operating time curve is as follows.
Equation 3.15-3
Where:
Iset is residual current setting [50/51G.3I0_Set]
Tp is time multiplier setting [50/51Gx.TMS].
K is a constant
C is a constant.
α is a constant.
3I0 is the calculated residual current.
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3 Operation Theory
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Gx.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.15-1 Inverse-time curve parameters
50/51Gx.Opt_Curve Time Characteristic K α C

DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Gx.tmin], then the operating time of the protection changes to the value of setting
[50/51Gx.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.
50/51Gx
50/51Gx.En1 50/51Gx.On
50/51Gx.En2 50/51Gx.On_ShortDly
50/51Gx.Blk 50/51Gx.St
50/51Gx.En_ShortDly 50/51Gx.Op
50/51Gx.Blk_ShortDly
3.15.4 I/O Signals

Table 3.15-2 I/O signals of earth fault protection
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Stage x of earth fault protection enabling input 1, it is triggered from binary
1 50/51Gx.En1
input or programmable logic etc. (x=1, 2, 3, 4)
Stage x of earth fault protection enabling input 2, it is triggered from binary
2 50/51Gx.En2
input or programmable logic etc. (x=1, 2, 3, 4)
Stage x of earth fault protection blocking input, it is triggered from binary input
3 50/51Gx.Blk
or programmable logic etc. (x=1, 2, 3, 4)
Short time delay for stage x of earth fault protection enabling input, it is
4 50/51Gx.En_ShortDly
triggered from binary input or programmable logic etc. (x=2, 3, 4)
Short time delay for stage x of earth fault protection blocking input, it is
5 50/51Gx.Blk_ShortDly
triggered from binary input or programmable logic etc. (x=2, 3, 4)
1 50/51Gx.On Stage x of earth fault protection is enabled. (x=1, 2, 3, 4)
2 50/51Gx.On_ShortDly Short time delay for stage x of earth fault protection is enabled. (x=2, 3, 4)
3 50/51Gx.St Stage x of earth fault protection starts. (x=1, 2, 3, 4)
4 50/51Gx.Op Stage x of earth fault protection operates. (x=1, 2, 3, 4)
3.15.5 Logic
EN [50/51G1.En]
&
SIG 50/51G1.En1 &
50/51G1.On
SIG 50/51G1.En2
SIG 50/51G1.Blk
SET 3I0>[50/51G1.3I0_Set]
EN [50/51G1.En_Abnor_Blk] >=1
SIG No abnormal conditions
&
SET [50/51G1.Opt_Dir]=Forward &

& &
& 50/51G1.St
SIG Forward DIR
>=1
SET [50/51G1.Opt_Dir]=Reverse & >=1
& Timer
t
SIG Reverse DIR
SET [50/51G1.Opt_Dir]=Non_Directional
SIG CTS.Alm &
EN [50/51G1.En_CTS_Blk]
>=1 >=1
SIG I3P 2nd Hm Detect & & 50/51G1.Op
[50/51G1.t_Op] 0
SET [50/51G1.En_Hm2_Blk]
SET [50/51G1.Opt_Curve]=DefTime
Figure 3.15-1 Logic diagram of earth fault protection (stage 1)
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3 Operation Theory
EN [50/51Gx.En]
&
SIG 50/51Gx.En1 &
50/51Gx.On
SIG 50/51Gx.En2
SIG 50/51Gx.Blk
SET 3I0>[50/51Gx.3I0_Set]
EN [50/51Gx.En_Abnor_Blk] >=1
SIG No abnormal conditions
&
SET [50/51Gx.Opt_Dir]=Forward &

& &
& 50/51Gx.St
SIG Forward DIR
>=1
SET [50/51Gx.Opt_Dir]=Reverse & >=1
& Timer
t
SIG Reverse DIR
SET [50/51Gx.Opt_Dir]=Non_Directional
SIG CTS.Alm &
EN [50/51Gx.En_CTS_Blk]
>=1
SIG I3P 2nd Hm Detect & &
[50/51Gx.t_Op] 0
SET [50/51Gx.En_Hm2_Blk]
>=1
SET [50/51Gx.Opt_Curve]=DefTime & 50/51Gx.Op
[50/51Gx.t_ShortDly] 0
EN [50/51Gx.En_ShortDly]
&
SIG [50/51Gx.En_ShortDly] 50/51Gx.On_ShortDly
SIG [50/51Gx.Blk_ShortDly]
Figure 3.15-2 Logic diagram of earth fault protection (stage x)
x=2, 3, 4
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x
of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by
direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”,
the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is
set as “0”, earth fault protection is not controlled by direction element.
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3 Operation Theory
3.15.6 Settings
Table 3.15-3 Settings of earth fault protection

1 50/51G.K_Hm2 0.000~1.000 0.001
blocking earth fault elements
Current setting for stage 1 of earth fault
2 50/51G1.3I0_Set (0.050~30.000)×In 0.001 A
protection
Time delay for stage 1 of earth fault
3 50/51G1.t_Op 0.000~20.000 0.001 s
protection
Enabling/disabling stage 1 of earth fault
protection
4 50/51G1.En 0 or 1
0: disable
1: enable
when stage 1 of earth fault protection
5 50/51G1.En_BlkAR 0 or 1 operates
0: disable
1: enable
Non_Directional
Direction option for stage 1 of earth fault
6 50/51G1.Opt_Dir Forward
protection
Reverse
Enabling/disabling second harmonic
blocking for stage 1 of earth fault protection
7 50/51G1.En_Hm2_Blk 0 or 1
0: disable
1: enable
Enabling/disabling blocking for stage 1 of
earth fault protection under abnormal
8 50/51G1.En_Abnor_Blk 0 or 1 conditions
0: disable
1: enable
earth fault protection under CT failure
9 50/51G1.En_CTS_Blk 0 or 1 conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE Option of characteristic curve for stage 1 of
10 50/51G1.Opt_Curve
IECST earth fault protection
IECLT
ANSIE
ANSIV
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3 Operation Theory

ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
11 50/51G1.TMS 0.010~200.000 0.001
inverse-time earth fault protection
12 50/51G1.tmin 0.050~20.000 0.001 s
13 50/51G1.Alpha 0.010~5.000 0.001 inverse-time characteristic earth fault
protection
14 50/51G1.C 0.000~20.000 0.001 inverse-time characteristic earth fault
protection
15 50/51G1.K 0.050~20.000 0.001 inverse-time characteristic earth fault
protection
16 50/51G2.3I0_Set (0.050~30.000)×In 0.001 A
protection
17 50/51G2.t_Op 0.000~20.000 0.001 s
protection
Short time delay for stage 2 of earth fault
18 50/51G2.t_ShortDly 0.000~20.000 0.001 s
protection
protection
19 50/51G2.En 0 or 1
0: disable
1: enable
Enabling/disabling short time delay for
stage 2 of earth fault protection
20 50/51G2.En_ShortDly 0 or 1
0: disable
1: enable
0: disable
1: enable
Non_Directional
protection
Reverse
23 50/51G2.En_Hm2_Blk 0 or 1
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0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
26 50/51G2.Opt_Curve ANSIE
earth fault protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
27 50/51G2.TMS 0.010~200.000 0.001
28 50/51G2.tmin 0.050~20.000 0.001 s
29 50/51G3.3I0_Set (0.050~30.000)×In 0.001 A
protection
30 50/51G3.t_Op 0.000~20.000 0.001 s
protection
31 50/51G3.t_ShortDly 0.000~20.000 0.001 s
protection
protection
32 50/51G3.En 0 or 1
0: disable
1: enable
0: disable
1: enable
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0: disable
1: enable
Non_Directional
protection
Reverse
36 50/51G3.En_Hm2_Blk 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
40 50/51G3.TMS 0.010~200.000 0.001
41 50/51G3.tmin 0.050~20.000 0.001 s
42 50/51G4.3I0_Set (0.050~30.000)×In 0.001 A
protection
43 50/51G4.t_Op 0.000~20.000 0.001 s
protection
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44 50/51G4.t_ShortDly 0.000~20.000 0.001 s
protection
protection
45 50/51G4.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non_Directional
protection
Reverse
49 50/51G4.En_Hm2_Blk 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
52 50/51G4.Opt_Curve IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
Date: 2017-08-17
3 Operation Theory

ANSILTV
ANSILT
53 50/51G4.TMS 0.010~200.000 0.001
54 50/51G4.tmin 0.050~20.000 0.001 s
3.16 Frequency Protection

3.16.1 Overfrequency Protection
3.16.1.1 General Application
If the power frequency of regional rises due to the active power excess demand, overfrequency
protection operates to perform generator rejection to shed part of the generators automatically
according to the rising frequency so that power supply and the load are re-balanced.
3.16.1.2 Function Description
The device provides four stages overfrequency protection. When system frequency is greater
than the setting [81O.f_Pkp], overfrequency protection will put into service.
In order to prevent possible maloperation of overfreqency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1. Blocking in undervoltage condition
If the positive voltage U1<[81O.U1_Set], the calculation of protection is not carried out and the
output relay will be blocked.
2. Frequency abnormality condition
When f<40Hz or f>65Hz, overfrequency protection will be blocked
Operation criteria of overfrequency protection is shown in the following equation.
f>[81O.OFi.f_Set] Equation 3.16-1
Where:
f is system frequency.
[81O.OFi.f_Set] is the frequency setting of stage i of overfrequency protection. (i=1, 2, 3, 4)
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3 Operation Theory
3.16.1.3 Function Block Diagram
81O.OFi
81O.En1 81O.OFi.On
81O.En2 81O.St
81O.Blk 81O.OFi.Op
3.16.1.4 I/O Signals
Table 3.16-1 I/O signals of overfrequency protection

Overfrequency protection enabling input 1, it is triggered from binary input or
1 81O.En1
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
2 81O.En2
Overfrequency protection blocking input, it is triggered from binary input or
3 81O.Blk
1 81O.OFi.On Stage i of overfrequency protection is enabled (i=1, 2, 3, 4).
2 81O.OFi.Op Stage i of overfrequency protection operates (i=1, 2, 3, 4).
3 81O.St Overfrequency protection starts.
3.16.1.5 Logic
SIG 81O.St1 >=1
SIG 81O.St2
>=1
SIG 81O.St3 >=1 81O.St
SIG 81O.St4
Figure 3.16-1 Logic diagram of overfrequency protection (start)
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3 Operation Theory
SIG 81O.En1
&
SIG 81O.En2 &
81O.OFi.On
EN [81O.OFi.En]
SIG 81O.Blk
&
SIG FD.Pkp
SIG U1<0.15Un >=1
SIG f<40 or f>65

&
SET f>[81O.f_Pkp] 50ms 0ms

81O.Sti
&
SET f>[81O.OFi.f_Set] & [81O.OFi.t_Op] 0ms 81O.OFi.Op
EN [81O.OFi.En]
Figure 3.16-2 Logic diagram of stage i of overfrequency protection
i=1, 2, 3, 4
3.16.1.6 Settings
Table 3.16-2 Settings of overfrequency protection

Frequency pickup setting for overfrequency
1 81O.f_Pkp 50.000~65.000 0.001 Hz
protection
Blocking voltage setting for overfrequency
2 81O.U1_Set 0.150Un~1.000Un 0.001 V
protection
Frequency setting for stage i of overfrequency
3 81O.OFi.f_Set 50.000~65.000 0.001 Hz
protection (i=1, 2, 3, 4)
Time delay for stage i of overfrequency protection
4 81O.OFi.t_Op 0.000~20.000 0.001 s
(i=1, 2, 3, 4)
Enabling/disabling stage i of overfrequency
5 81O.OFi.En 0 or 1
0: disable
1: enable
3.16.2 Underfrequency Protection

3.16.2.1 General Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to
re-balance the power supply and the load.
3.16.2.2 Function Description
The device provides four stages underfrequency protection. When system frequency is smaller
than the setting [81U.f_Pkp], underfrequency protection will put into service.
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3 Operation Theory
In order to prevent possible maloperation of underfrequency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1. Blocking in undervoltage condition
If the positive voltage U1<[81U.U1_Set], the calculation of protection is not carried out and the
output relay will be blocked.
2. df/dt blocking element
If －df/dt≥[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
3. Frequency abnormality condition
When f<40Hz or f>65Hz, underfrequency protection will be blocked
Operation criteria of underfrequency protection is shown in the following equation.
f<[81U.UFi.f_Set] Equation 3.16-2
Where:
f is system frequency.
[81U.UFi.f_Set] is the frequency settings of stage i of underfrequency protection. (i=1, 2, 3, 4)
The equation of df/dt blocking function is as follows.
df/dt≥[81U.df/dt_Blk] Equation 3.16-3
Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calucation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[81U.UFi.En_df/dt_Blk] is set as “1”, when Equation 3.16-2 and Equation 3.16-3 are met, it is
decided that a fault occurred and the corresponding stage underfrequency protection is blocked at
the same time for the purpose of waiting for operation of other related protection. The blocking
signal will not reset until the system frequency recovers, i.e. the system frequency is greater than
the setting [81U.f_Pkp]. If the logic setting is set as “0”, when Equation 3.16-2 and Equation
3.16-3 are met, the stage underfrequency protection will be released to operate.
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3.16.2.3 Function Block Diagram
81U.UFi
81U.En1 81U.UFi.On
81U.En2 81U.St
81U.Blk 81U.UFi.Op
3.16.2.4 I/O Signals
Table 3.16-3 I/O signals of underfrequency protection

Underfrequency protection enabling input 1, it is triggered from binary input or
1 81U.En1
Underfrequency protection enabling input 2, it is triggered from binary input or
2 81U.En2
Underfrequency protection blocking input, it is triggered from binary input or
3 81U.Blk
1 81U.UFi.On Stage i of underfrequency protection is enabled (i=1, 2, 3, 4).
2 81U.UFi.Op Stage i of underfrequency protection operates (i=1, 2, 3, 4).
3 81U.St Underfrequency protection starts.
3.16.2.5 Logic
SIG 81U.St1 >=1
SIG 81U.St2
>=1
SIG 81U.St3 >=1 81U.St
SIG 81U.St4
Figure 3.16-3 Logic diagram of underfrequency protection (start)
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SIG 81U.En1
&
SIG 81U.En2
EN [81U.UFi.En]
&
81U.UFi.On
SIG 81U.Blk
&
SIG FD.Pkp &
SIG U1<0.15Un >=1
SIG f<40 or f>65
SET f<[81U.f_Pkp] 50ms 0ms

81U.Sti
SET -df/dt<[81U.df/dt_Blk] >=1 &
[81U.UFi.t_Op] 0ms 81U.UFi.Op
EN [81U.UFi.En_df/dt_Blk]
SET f<[81U.UFi.f_Set] &
EN [81U.UFi.En]
Figure 3.16-4 Logic diagram of stage i of underfrequency protection
i=1, 2, 3, 4
3.16.2.6 Settings
Table 3.16-4 Settings of underfrequency protection

Frequency pickup setting for underfrequency
1 81U.f_Pkp 45.000~60.000 0.01 Hz
protection
Blocking voltage setting for underfrequency
2 81U.U1_Set 0.150Un~1.000Un 0.001 V
protection
Rate of frequency change for blocking
3 81U.df/dt_Blk 0.200~20.000 0.01 Hz/s
underfrequency protection
Frequency setting for stage i of
4 81U.UFi.f_Set 45.000~60.000 0.001 Hz
underfrequency protection (i=1, 2, 3, 4)
Time delay for stage i of underfrequency
5 81U.UFi.t_Op 0.000~30.000 0.01 s
Enabling/disabling stage i of underfrequency
6 81U.UFi.En 0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency change
to block stage i of underfrequency protection
7 81U.UFi.En_df/dt_Blk 0 or 1 (i=1, 2, 3, 4)
0: disable
1: enable
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3.17 Breaker Failure Protection

Duplicated protection configurations are usually adopted for EHV power system, but the primary
equipment, circuit breaker, is not duplicated. Breaker failure protection is adopted to cater circuit
breaker tripping failure.
Breaker failure protection issues a back-up trip command to trip adjacent circuit breakers in case
of a tripping failure of the circuit breaker, and clears the fault as requested by the device. To utilize
the protection information of faulty equipment and the electrical information of failure circuit
breaker to constitute the criterion of breaker failure protection, it can ensure that the adjacent
circuit breakers of failure circuit breaker are tripped with a shorter time delay, so that the affected
area is minimized, and ensure stable operation of the entire power grid to prevent generators,
transformers and other components from seriously damaged.

The instantaneous re-tripping function, after receiving tripping signal from other device and the
corresponding phase overcurrent element operating, is available and provides phase-segregated
binary output contact, which can ensure the circuit breaker is still tripped in case the secondary
circuit between the device and the circuit breaker is abnormal, to avoid undesired tripping of
breaker failure protection and the expansion of the affected area. Instantaneous re-tripping
function does not block AR.
When both the phase-segregated tripping contact from line protection and the corresponding
phase overcurrent element operate, or both the three-phase tripping contact and any phase
overcurrent element operate, breaker failure protection will send three-phase tripping command to
trip local circuit breaker after time delay of [50BF.t1_Op] and trip all adjacent circuit breakers after
time delay of [50BF.t2_Op].
When the protection element except under voltage element within this device operates and issues
tripping signal, breaker failure protection will also be initiated.
Taking into account that the faulty current is too small for generator or transformer fault, the
sensitivity of phase current element may not meet the requirements, residual current criterion and
negative-sequence current criterion are provided in addition to the phase overcurrent element for
breaker failure protection initiated by input signal [50BF.ExTrp3P_GT] from generator and
transformer protection. They can be enabled or disabled by logic settings [50BF.En_3I0_3P] and
[50BF.En_I2_3P] respectively.
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal [50BF.ExTrp_WOI] is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact (52b) as an option criterion for breaker failure check.
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50BF
50BF.ExTrp3P_L 50BF.On
50BF.ExTrp3P_GT 50BF.Op_ReTrpA
50BF.ExTrp_WOI 50BF.Op_ReTrpB
50BF.ExTrpA 50BF.Op_ReTrpC
50BF.ExTrpB 50BF.Op_ReTrp3P
50BF.ExTrpC 50BF.Op_t1
50BF.En 50BF.Op_t2
50BF.Blk
3.17.4 I/O Signals

Table 3.17-1 I/O signals of breaker failure protection

1 50BF.ExTrp3P_L Input signal of three-phase tripping contact from line protection
Input signal of three-phase tripping contact from generator or transformer
2 50BF.ExTrp3P_GT
protection
3 50BF.ExTrpA Input signal of phase-A tripping contact from external device
4 50BF.ExTrpB Input signal of phase-B tripping contact from external device
5 50BF.ExTrpC Input signal of phase-C tripping contact from external device
Input signal of three-phase tripping contact from external device. Once it is
6 50BF.ExTrp_WOI energized, normally closed auxiliary contact of circuit breaker is chosen in
addition to breaker failure current check to trigger breaker failure timers.
Breaker failure protection enabling input, it is triggered from binary input or
7 50BF.En
Breaker failure protection blocking input, it is triggered from binary input or
8 50BF.Blk
1 50BF.On Breaker failure protection is enabled
2 50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker
3 50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker
4 50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker
5 50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phase circuit breaker
6 50BF.Op_t1 Stage 1 breaker failure protection operates
7 50BF.Op_t2 Stage 2 breaker failure protection operates
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3.17.5 Logic
SIG 50BF.En
&
EN [ 50BF.En] 50BF.On
SIG 50BF.Blk
SIG 50BF.On
&
SIG FD.Pkp
EN [ 50BF.En_ReTrp]
EN [ 50BF.En_3I0_1P] >=1
SET 3I0>[ 50BF.3I0_Set]

&
SIG BFI_A >=1 & [ 50BF.t_ReTrp] 0ms 50BF.Op_ReTrpA
BI [ 50BF.ExTrpA]
SET IA>[ 50BF.I_Set]

&
SIG BFI_B >=1 & [ 50BF.t_ReTrp] 0ms 50BF.Op_ReTrpB
BI [ 50BF.ExTrpB]
SET IB>[ 50BF.I_Set]

&
SIG BFI_C >=1 & [ 50BF.t_ReTrp] 0ms 50BF.Op_ReTrpC
BI [ 50BF.ExTrpC] >=1
SET IC>[ 50BF.I_Set] >=1
SIG BFI_3P >=1

&
& >=1
BI [ 50BF.ExTrp3P_L]
>=1 [ 50BF.t_ReTrp] 0ms [ 50BF.Op_ReTrp3P]
BI [ 50BF.ExTrp3P_GT] >=1
&
BI [ 50BF.ExTrp_WOI]
&
EN [ 50BF.En_3I0_3P] &
SET 3I0>[ 50BF.3I0_Set]

& >=1 >=1 [ 50BF.t1_Op] 0ms 50BF.Op_t1
EN [ 50BF.En_I2_3P] & &
[ 50BF.t2_Op] 0ms 50BF.Op_t2
SET I2>[ 50BF.I2_Set]
&
EN [ 50BF.En_CB_Ctrl]
BI [ 52b_PhA]
&
BI [ 52b_PhB]
BI [ 52b_PhC]
SIG 50BF.On &
SIG FD.Pkp
Figure 3.17-1 Breaker failure protection logic diagram
Where:
BFI_A, BFI_B, BFI_C: A-phase, B-phase and C-phase breaker failure protection initiating signal,
please refer to.
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3.17.6 Settings
Table 3.17-2 Settings of breaker failure protection

1 50BF.I_Set (0.050~30.000)×In 0.001 A Current setting of phase current criterion for BFP
Current setting of zero-sequence current
2 50BF.3I0_Set (0.050~30.000)×In 0.001 A
criterion for BFP
Current setting of negative-sequence current
3 50BF.I2_Set (0.050~30.000)×In 0.001 A
criterion for BFP
4 50BF.t_ReTrp 0.000~10.000 0.001 s Time delay of re-tripping for BFP
5 50BF.t1_Op 0.000~10.000 0.001 s Time delay of stage 1 for BFP

Enabling/disabling breaker failure protection
7 50BF.En 0 or 1 0: disable
1: enable
Enabling/disabling re-trip function for BFP
8 50BF.En_ReTrp 0 or 1 0: disable
1: enable
Enabling/disabling zero-sequence current
criterion for BFP initiated by single-phase tripping
9 50BF.En_3I0_1P 0 or 1 contact
0: disable
1: enable
criterion for BFP initiated by three-phase tripping
0: disable
1: enable
Enabling/disabling negative-sequence current
11 50BF.En_I2_3P 0 or 1 contact
0: disable
1: enable
Enabling/disabling breaker failure protection can
be initiated by normally closed contact of circuit
12 50BF.En_CB_Ctrl 0 or 1 breaker
0: disable
1: enable
3.18 Pole Discrepancy Protection

The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated
operating gears for the three phases. The reason could be an interruption in the tripping/closing
circuits, or mechanical failure. A pole discrepancy can only be tolerated for a limited period. When
there is loading, zero-sequence or negative-sequence current will be generated in the power
system, which will result in overheat of the generator or the motor. With the load current
increasing, overcurrent elements based on residual current or negative-sequence current may
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3 Operation Theory
operate. Pole discrepancy protection is required to operate before the operation of these
overcurrent elements.

Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its
phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy
protection, the asymmetrical current component can be selected as addition criteria when
needed.
62PD
62PD.En1 62PD.On
62PD.En2 62PD.Op
62PD.Blk 62PD.St
3.18.4 I/O Signals

Table 3.18-1 I/O signals of pole discrepancy protection

Pole discrepancy protection enabling input 1, it is triggered from binary input or
1 62PD.En1
Pole discrepancy protection enabling input 2, it is triggered from binary input or
2 62PD.En2
Pole discrepancy protection blocking input, it is triggered from binary input or
3 62PD.Blk
1 62PD.On Pole discrepancy protection is enabled
2 62PD.St Pole discrepancy protection starts
3 62PD.Op Pole discrepancy protection operates to trip
3.18.5 Logic
Pole discrepancy protection can be initiated following method.
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy
protection will be started and initiate output after a time delay [62PD.t_Op].
Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.
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SIG 62PD.En1
&
SIG 62PD.En2 &
62PD.On
EN [62PD.En]
SIG 62PD.Blk
&
SIG FD.Pkp
EN [62PD.En_3I0/I2_Ctrl] >=1
SET 3I0>[62PD.3I0_Set] >=1
SET I2>[62PD.I2_Set]
BI [52b_PhA] & 62PD.St

& &
SIG Ia<0.06In & [62PD.t_Op] 0ms 62PD.Op
BI [52b_PhB] &
SIG Ib<0.06In
>=1
BI [52b_PhC] &
SIG Ic<0.06In
Figure 3.18-1 Pole discrepancy protection logic diagram
Where:
3I0: Calculated residual current by vector sum of Ia, Ib and Ic.
3.18.6 Settings
Table 3.18-2 Settings of pole discrepancy protection

Current setting of residual current criterion
1 62PD.3I0_Set (0.050~30.000)×In 0.001 A
for pole discrepancy protection
2 62PD.I2_Set (0.050~30.000)×In 0.001 A
criterion for pole discrepancy protection
3 62PD.t_Op 0.000~600.000 0.001 s Time delay of pole discrepancy protection
Enabling/disabling pole discrepancy
protection
4 62PD.En 0 or 1
0: disable
1: enable
Enabling/disabling residual current criterion
and negative-sequence current criterion for
5 62PD.En_3I0/I2_Ctrl 0 or 1 pole discrepancy protection
0: disable
1: enable
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3.19 Synchro-check for Automatic Reclosure

The purpose of synchro-check is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchro-check to avoid this situation and maintain the system
stability. The synchro-check includes synchronism check and dead charge check.

The synchronism check function measures the conditions across the circuit breaker and
compares them with the corresponding settings. The output is only given if all measured
quantities are simultaneously within their set limits.
The dead charge check function measures the amplitude of reference voltage and synchronism
voltage, and then compare them with the live check setting [25.U_Lv] and the dead check setting
[25.U_Dd]. The output is only given when the measured quantities comply with the criteria.
Synchro-check in this device can be used for auto-reclosing and manual closing for both
single-breaker and dual-breakers. Details are described in the following sections.
When used for the synchro-check of single-breaker, comparative relationship between reference
voltage (Uref) and synchronism voltage (Usyn) for synchro-check is as follows.
Uref Usyn
Figure 3.19-1 Relationship between reference voltage and synchronism voltage
Figure 3.19-1 shows the characteristics of synchronism check element used for the auto-reclosing
if both reference voltage and synchronism voltage are live. The synchronism check element
operates if voltage difference, phase angle difference and frequency difference are all within their
setting values.
1. The voltage difference is checked by the following equations.
Usyn≥[25.U_Lv]
Uref≥[25.U_Lv]
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3 Operation Theory
|Usyn- Uref|≤[25.U_Diff]
2. The phase difference is checked by the following equations.
Usyn×Uref×cosØ≥0
Usyn×Uref×sin([25.phi_Diff]) ≥Usyn×Uref×|sinØ|
Where,
Ø is phase difference between Usyn and Uref
3. The frequency difference is checked by the following equations.
|f(Usyn)-f(Uref)|≤[25.f_Diff]
If frequency check is disabled (i.e. [25.En_fDiffChk] is set as "0"), a detected maximum slip cycle
can also be determined by the following equation based on phase difference setting and the
synchronism check time setting:
f =[25.phi_Diff]/(180×[25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [25.En_fDiffChk] is set as "1"), then [25.t_SynChk] can be set to
be a very small value (default value is 50ms).
This function module supports voltage switching. In general, voltage switching is fulfilled by
external circuit, and the busbar arrangement should be determined, including three options, single
busbar arrangement, double busbars arrangement and 1½ breakers arrangement, if using this
module to fulfill voltage switching.
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on.
UB1: it connects with single synchronism voltage (from line or busbar).
UL2: it connects with single synchronism voltage (from the other line of the same diameter in 1½
breakers arrangement). When voltage switching is available, it is only used by 1½ breakers
arrangement.
UB2: it connects with single synchronism voltage (from busbar). When voltage switching is
available, it is only used by double busbars arrangement and 1½ breakers arrangement.
The reference voltage (Uref) is determined to use phase voltage or phase-to-phase voltage (UL1)
from three-phase protection voltages and by the setting [25.Opt_Source_UL1].
The synchronism voltage (Usyn) always connects with UB1 if not adopting voltage switching. It
connects with one of UB1, UL2 and UB2 according to the result of voltage switching if adopting
voltage switching.
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3.19.2.1 Single Busbar Arrangement
Voltage selection function is not required for this busbar arrangement, the connection of the
voltage signals and respective VT MCB auxiliary contacts to the device is shown in the Figure
3.19-2 and Figure 3.19-3.
1. Three-phase bus voltage used for protection ([VTS.En_LineVT]=0)
Bus
 Ua
UL1 Ub CB
Uc
25.MCB_VT_UL1
UB1
25.MCB_VT_UB1
Line
Figure 3.19-2 Voltage connection 1 for single busbar arrangement
Three-phase protection voltages are from busbar VT. As shown in above figure, the reference
voltage (Uref) is selected among three-phase protection voltages, and synchronism voltage (Usyn)
is from line VT.
2. Three-phase line voltage used for protection ([VTS.En_LineVT]=1)
Bus
UB1 CB
25.MCB_VT_UB1
 Ua
UL1 Ub
Uc
25.MCB_VT_UL1 Line
Figure 3.19-3 Voltage connection 2 for single busbar arrangement
In the figures, the setting [VTS.En_LineVT] is used to determine protection voltage signals (Ua,
Ub, Uc) from line VT or bus VT according to the condition. This setting is only used for VT circuit
failure logic, and it does not affect the synchro-check mode. Three-phase protection voltages are
from line VT, as shown in above figure, the reference voltage (Uref) is selected among UL1
three-phase protection voltages, and synchronism voltage (Usyn) is from busbar VT.
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3 Operation Theory
3.19.2.2 Double Busbars Arrangement
Bus2
Bus1
B1D B2D
UB1
25.MCB_VT_UB1
UB2
25.MCB_VT_UB2
25.NC_UB1DS
25.NO_UB1DS CB
25.NC_UB2DS
25.NO_UB2DS
 Ua
UL1 Ub
Line
Uc
25.MCB_VT_UL1
Figure 3.19-4 Voltage connection for double busbars arrangement
For double busbars arrangement, selection of appropriate voltage signals from Bus 1 and Bus 2
for synchronizing are required. Line VT signal is taken as reference to check synchronizing with
the voltage after voltage selection function. Selection approach is as follows.
For the disconnector positions, the normally open (NO) and normally closed (NC) contacts of the
disconnector for bus 1 and bus 2 are required to determine the disconnector open and closed
positions. The voltage selection logic is as follows.
BI 25.NC_UB1DS &
Voltage Selection Logic
UB1_Sel
BI 25.NO_UB1DS
BI 25.NC_UB2DS &
UB2_Sel
BI 25.NO_UB2DS
&
Alm_Invalid_Sel
UB1 Usyn
UB2
Figure 3.19-5 Voltage selection for double busbars arrangement
After acquiring the disconnector open and closed positions of double busbars, use the following
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logic to acquire the feeder voltage of double busbars.
DS2 CLOSED DS2 OPEN

DS1 CLOSED Keep original value Voltage from Bus 1 VT (UB1_Sel=1)
DS1 OPEN Voltage from Bus 2 VT (UB2_Sel=1) Keep original value
DS1 is disconnector of Bus 1
DS2 is disconnector of Bus 2
If voltage selection is invalid (Alm_Invalid_Sel=1), keep original selection and without switchover.
3.19.2.3 One and A Half Breakers Arrangement
For one and a half breakers arrangement, selection of appropriate voltage signals among Line1
VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1 voltage signal
for closing breaker at Bus 1 side.
Bus1
UB1
25.MCB_VT_UB1
25.NC_UB1DS
B1D
25.NO_UB1DS
 Ua Line 1
UL1 Ub
Uc
25.MCB_VT_UL1
L1D
25.NC_UL1DS
25.NO_UL1DS
Line 2
UL2
25.MCB_VT_UL2
25.NC_UL2DS
25.NO_UL2DS
L2D
25.NC_UB2DS
25.NO_UB2DS
UB2
25.MCB_VT_UB2
B2D
Bus2
Figure 3.19-6 Voltage connection for one and a half breakers arrangement
For the circuit breaker at bus side (take bus breaker of bus 1 as an example), the device acquires
the disconnector open and closed positions of two feeders and bus 2. The voltage selection logic
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is as follows.
BI 25.NC_UL1DS &
UL1_Sel
BI 25.NO_UL1DS
&
BI 25.NC_UL2DS & UL2_Sel
BI 25.NO_UL2DS
&
BI 25.NC_UB2DS & UB2_Sel
BI 25.NO_UB2DS
&
Alm_Invalid_Sel
UL1 Uref
UL2
UB2
UB1 Usyn
Figure 3.19-7 Voltage selection for bus CB of one and a half breakers arrangement
For the tie breaker, the device acquires the disconnector open and closed positions of two feeders
and two busbars. Either Line 1 VT or Bus 1 VT signal is selected as reference voltage to check
synchronizing with the selected voltage between Line 2 VT and Bus 2 VT. The voltage selection
logic is as follows.
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BI 25.NC_UL1DS &
UL1_Sel
BI 25.NO_UL1DS
&
BI 25.NO_UB1DS
&
UL1 Uref
UB1
BI 25.NC_UL2DS &
UL2_Sel
BI 25.NO_UL2DS
&
BI 25.NO_UB2DS
>=1
& Alm_Invalid_Sel
UL2 Usyn
UB2
Figure 3.19-8 Voltage selection for tie CB of one and a half breakers arrangement
When the voltage selection fails (including VT circuit failure and MCB failure), the device will issue
the corresponding failure signal. If the voltage selection is invalid (Alm_Invalid_Sel=1), keep
original selection and without switchover.
In order to simplify description, one of the two voltages used in the synchro-check (synchronism check
and dead charge check) which obtained after voltage selection function is regarded as line voltage,
and another is bus voltage.
3.19.2.4 Synchronism Voltage Circuit Failure Supervision
If voltage from synchronism voltage VT or reference voltage VT is used for auto-reclosing with
synchronism or dead reference voltage or synchronism voltage check, the synchronism voltage
circuit and reference voltage circuit are monitored.
During normal operation, the circuit breaker is in closed state (52b of three phases are
de-energized), if automatic reclosing cycle is in progress and no fault detector operates, then the
synchronism voltage is lower than the setting [25.U_Lv], it means that synchronism voltage circuit
fails and the synchronism voltage alarm [25.Alm_VTS_Usyn] or reference voltage alarm
[25.Alm_VTS_Uref] will be issued with a time delay of 10s. If the MCB of synchronism voltage or
reference voltage is open, the corresponding alarm signal [25.Alm_VTS_Usyn] or
[25.Alm_VTS_Uref] will be issued instantaneously.
If no check mode is enabled (the signal [25.On_NoChk] is "1"), synchro-check used voltage circuit
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3 Operation Theory
failure supervision will be disabled.
When synchronism voltage circuit failure is detected, function of dead check in auto-reclosing
logic will be disabled.
After synchronism voltage reverted to normal condition, the alarm will be reset automatically with
a time delay of 10s.
SIG FD.Pkp >=1
SIG 79.Inprog
&
10s 10s
SIG Uref<[25.U_Lv]
>=1
&
BI 25.MCB of Uref 25.Alm_VTS_Uref
EN 25.En_SynChk >=1
SIG 25.En_DdL_DdB &
SIG 25.En_DdL_LvB
SIG 25.En_LvL_DdB
SIG 25.Blk_VTS_UL
Figure 3.19-9 Reference voltage circuit failure supervision logic diagram (auto-reclosure)
SIG FD.Pkp >=1
SIG 79.Inprog
&
10s 10s >=1
SIG Usyn<[25.U_Lv] &
25.Alm_VTS_Usyn
BI 25.MCB of Usyn
EN 25.En_SynChk >=1
SIG 25.En_DdL_DdB &
SIG 25.En_DdL_LvB
SIG 25.En_LvL_DdB
SIG 25.Blk_VTS_UB
Figure 3.19-10 Synchronism voltage circuit failure supervision logic diagram (auto-reclosure)
Where:
"25.MCB of Uref" means binary input for VT MCB auxiliary contact of the reference voltage after
voltage switching.
"25.MCB of Usyn" means binary input for VT MCB auxiliary contact of the synchronism voltage
after voltage switching.
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25
25.Blk_Chk UL1_Sel
UL2_Sel
25.Blk_SynChk
UB1_Sel
25.Blk_DdChk UB2_Sel
Alm_Invalid_Sel
25.Start_Chk
25.On_SynChk
25.Start_3PLvChk 25.On_DdL_DdB
25.Sel_SynChk 25.On_DdL_LvB
25.On_LvL_DdB
25.Sel_DdL_DdB
25.On_NoChk
25.Sel_DdL_LvB 25.Ok_fDiffChk
25.Ok_UDiffChk
25.Sel_LvL_DdB
25.Ok_phiDiffChk
25.Sel_NoChk
25.Ok_DdL_DdB
25.Blk_VTS_Uref 25.Ok_DdL_LvB
25.Ok_LvL_DdB
25.Blk_VTS_Usyn
25.Chk_LvL
25.MCB_VT_UL1 25.Chk_DdL
25.MCB_VT_UL2 25.Chk_LvB
25.Chk_DdB
25.MCB_VT_UB1
25.Ok_DdChk
25.MCB_VT_UB2 25.Ok_SynChk
25.NC_UL1DS 25.Ok_Chk
25.Ok_3PLvChk
25.NO_UL1DS
25.Alm_VTS_Uref
25.NC_UB1DS
25.Alm_VTS_Usyn
25.NO_UB1DS
25.f_Ref
25.NC_UL2DS 25.f_Syn
25.NO_UL2DS 25.U_Diff
25.f_Diff
25.NC_UB2DS
25.Phi_Diff
25.NO_UB2DS
3.19.4 I/O Signals

Table 3.19-1 I/O signals of synchro-check (auto-reclosure)

1 25.Blk_Chk Input signal of blocking synchro-check function for AR.
Input signal of blocking synchronism check for AR. If the value is “1”, the
2 25.Blk_SynChk
output of synchronism check is “0”.
3 25.Blk_DdChk Input signal of blocking dead charge check for AR.
4 25.Start_Chk Input signal of starting synchronism check, usually it was starting signal of
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AR from auto-reclosing module.

Input signal of starting live three-phase check, usually it was starting signal
5 25.Start_3PLvChk
of 1-pole AR
6 25.Sel_ SynChk Synchronism check is selected.
7 25.Sel_DdL_DdB Dead line and dead bus check is selected.
8 25.Sel_DdL_LvB Dead line and live bus check is selected.
9 25.Sel_ LvL_DdB Live line and live bus check is selected.
10 25.Sel_ NoChk No check is selected.
11 25.Blk_VTS_Usyn VT circuit supervision (Usyn) is blocked
12 25.Blk_VTS_Uref VT circuit supervision (Uref) is blocked
13 25.MCB_VT_UL1 Binary input for VT MCB auxiliary contact (UL1)
14 25.MCB_VT_UL2 Binary input for VT MCB auxiliary contact (UL2)
15 25.MCB_VT_UB1 Binary input for VT MCB auxiliary contact (UB1)
16 25.MCB_VT_UB2 Binary input for VT MCB auxiliary contact (UB2)
17 25.NC_UL1DS Normally closed contact of disconnector (UL1)
18 25.NO_UL1DS Normally open contact of disconnector (UL1)
19 25.NC_UB1DS Normally closed contact of disconnector (UB1)
20 25.NO_UB1DS Normally open contact of disconnector (UB1)
21 25.NC_UL2DS Normally closed contact of disconnector (UL2)
22 25.NO_UL2DS Normally open contact of disconnector (UL2)
23 25.NC_UB2DS Normally closed contact of disconnector (UB2)
24 25.NO_UB2DS Normally open contact of disconnector (UB2)
1 UL1_Sel To select voltage of Line 1
2 UL2_Sel To select voltage of Line 2
3 UB1_Sel To select voltage of Bus 1
4 UB2_Sel To select voltage of Bus 2
5 Alm_Invalid_Sel Synchronism voltage selection is invalid.
6 25.On_SynChk Synchronism check is enabled.
7 25.On_DdL_DdB Dead line and dead bus check is enabled.
8 25.On_DdL_LvB Dead line and live bus check is enabled.
9 25.On_LvL_DdB Live line and dead bus check is enabled.
10 25.On_NoChk No check is enabled.
To indicate that frequency difference condition for synchronism check of AR
11 25.Ok_fDiffChk is met, frequency difference between Usyn and Uref is smaller than
[25.f_Diff].
To indicate that voltage difference condition for synchronism check of AR is
12 25.Ok_UDiffChk
met, voltage difference between Usyn and Uref is smaller than [25.U_Diff]
To indicate phase difference condition for synchronism check of AR is met,
13 25.Ok_phiDiffChk
phase difference between Usyn and Uref is smaller than [25.phi_Diff].
Dead reference voltage and dead synchronism voltage condition is met
14 25.Ok_DdL_DdB (both reference voltage and synchronism voltage are low than voltage
threshold of dead check)
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Dead reference voltage and live synchronism voltage condition is met

15 25.Ok_DdL_LvB (reference voltage is low than voltage threshold of dead check and
synchronism voltage is higher than voltage threshold of live check)
Live reference voltage and dead synchronism voltage condition is met
16 25.Ok_LvL_DdB (reference voltage is higher than voltage threshold of live check and
synchronism voltage is low than voltage threshold of dead check)
Reference voltage is greater than the voltage threshold of live check
17 25.Chk_LvL
[25.U_Lv]
Reference voltage is smaller than the voltage threshold of dead check
18 25.Chk_DdL
[25.U_Dd]
Synchronism voltage is greater than the voltage threshold of live check
19 25.Chk_LvB
[25.U_Lv]
Synchronism voltage is smaller than the voltage threshold of dead check
20 25.Chk_DdB
[25.U_Dd]
21 25.Ok_DdChk To indicate that dead charge check condition of AR is met
22 25.Ok_SynChk To indicate that synchronism check condition of AR is met
23 25.Ok_Chk To indicate that synchrocheck condition of AR is met
24 25.Ok_3PLvChk To indicate that live three-phase check condition is met
25 25.Alm_VTS_Uref Reference voltage circuit is abnormal
26 25.Alm_VTS_Usyn Synchronism voltage circuit is abnormal
27 25.f_Ref Frequency of the voltage used by protection calculation
28 25.f_Syn Frequency of the voltage used by synchrocheck
29 25.U_Diff Voltage difference for synchronism check
30 25.f_Diff Frequency difference for synchronism check
31 25.phi_Diff Phase difference for synchronism check
3.19.5 Logic
3.19.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check. When the synchronism check function is enabled and the voltages of both
ends meets the requirements of the voltage difference, phase difference, and frequency
difference, and there is no synchronism check blocking signal, it is regarded that the synchronism
check conditions are met.
Synchronism check logic is usually used for 3-pole AR, and 1-pole AR is usually adopts no check
logic. However, the circuit breaker at local end cannot reclosed unless the circuit breaker at
remote end is reclosed successfully. In order to meet this requirement, live three-phase check can
be used for 1-pole AR, determined by the setting [25.En_3PLvChk], ensure that three-phase
voltages is restored to normal at local end after the circuit breaker at remote end is reclosed.
Synchronism check mode can be determined by corresponding logic setting [25.En_SynChk] or

external signal. As shown in following figure, when the setting [25.SetOpt] is set as "1",
synchronism check mode is determined by the setting [25.En_SynChk]. Otherwise, synchronism
check mode is determined by external signal.
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3 Operation Theory
1
EN [25.En_SynChk]
25.On_SynChk
SIG 25.Sel_SynChk
0
EN [25.SetOpt]
Figure 3.19-11 Synchronism check mode selection (auto-reclosure)
EN [25.En_3PLvChk]
SIG Uref.a>[25.U_Lv]
>=1
&
SIG Uref.b>[25.U_Lv]
SIG Uref.c>[25.U_Lv]
&
SIG 25.Start_3PLvChk 200ms 0ms 25.Ok_3PLvChk
SIG 25.Blk_Chk >=1
SIG 25.Blk_SynChk
&
SIG [25.On_SynChk]
&
SIG 25.Start_Chk
SIG Usyn>[25.U_Lv]
& &
SIG Uref>[25.U_Lv] 50ms 0ms & [25.t_SynChk] 0ms 25.Ok_SynChk
SIG 25.Ok_UdiffChk
SIG 25.Ok_phiDiffChk
SIG 25.Ok_fDiffChk
Figure 3.19-12 Synchronism check logic diagram (auto-reclosure)
3.19.5.2 Dead Charge Check Logic
The dead charge check conditions have three types, namely, live-synchronism voltage and
dead-reference voltage check, dead-synchronism voltage and live-reference voltage check and
dead-synchronism voltage and dead-reference voltage check. The above three modes can be
enabled and disabled by the corresponding logic settings ([25.En_DdL_DdB], [25.En_LvL_DdB]
and [25.En_DdL_LvB]) or external signal, when the setting [25.SetOpt] is set as "1", dead charge
check mode is determined by corresponding logic settings. Otherwise, dead charge check mode
is determined by external signal.
The device can calculate the measured synchronism voltage and reference voltage and compare
them with the settings [25.U_Lv] and [25.U_Dd]. When the voltage is higher than [25.U_Lv], the
synchronism voltage/reference voltage is regarded as live. When the voltage is lower than
[25.U_Dd], the synchronism voltage/reference voltage is regarded as dead.
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3 Operation Theory
1
EN [25.En_DdL_DdB]
25.On_DdL_DdB
SIG 25.Sel_SynChk
0
EN [25.SetOpt]
1
EN [25.En_LvL_DdB]
25.On_LvL_DdB
SIG 25.Sel_LvL_DdB
0
EN [25.SetOpt]
1
EN [25.En_DdL_LvB]
25.On_DdL_LvB
SIG 25.Sel_DdL_LvB
0
EN [25.SetOpt]
Figure 3.19-13 Dead charge check mode selection
SIG 25.Blk_Chk >=1

&
SIG 25.Blk_DdChk &
>=1 [25.t_DdChk] 0ms 25.Ok_DdChk
SIG 25.Start_Chk
SIG [25.On_DdL_DdB] &

25.Ok_DdL_DdB
SIG Uref<[25.U_Dd] &
SIG Usyn>[25.U_Lv]
SIG [25.On_DdL_LvB] &

25.Ok_DdL_LvB
SIG Uref<[25.U_Dd] &
SIG Usyn>[25.U_Lv]
SIG [25.On_LvL_DdB] &

25.Ok_LvL_DdB
SIG Uref>[25.U_Lv] &
SIG Usyn<[25.U_Dd]
SIG 25.Alm_VTS_Usyn >=1
SIG 25.Alm_VTS_Uref
Figure 3.19-14 Dead charge check logic diagram (auto-reclosure)
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3 Operation Theory
3.19.5.3 Synchro-check Logic
1
EN [25.En_NoChk]
25.On_NoChk
SIG 25.Sel_NoChk
0
EN [25.SetOpt]
Figure 3.19-15 No check mode selection
SIG 25.Ok_SynChk
>=1
EN 25.On_NoChk 25.Ok_Chk
SIG 25.Ok_DdChk
Figure 3.19-16 Synchro-check logic diagram (auto-reclosure)
3.19.6 Settings
Table 3.19-2 Synchro-check settings

Voltage selecting mode of line 1.
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
1 25.Opt_Source_UL1 Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage
Voltage selecting mode of bus 1.
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
2 25.Opt_Source_UB1 Uc: C-phase voltage
Uab
Ubc
Uca
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
Uab
Ubc
Uca
Ua Voltage selecting mode of bus 2.
4 25.Opt_Source_UB2 Ub Ua: A-phase voltage
Uc Ub: B-phase voltage
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3 Operation Theory

Uab Uc: C-phase voltage
Ubc Uab: AB-phase voltage
Uca Ubc: BC-phase voltage
6 25.U_Dd 0.05Un~0.8Un 0.001 V Voltage threshold of dead check
7 25.U_Lv 0.5Un~Un 0.001 V Voltage threshold of live check
8 25.K_Usyn 0.20-5.00 Compensation coefficient for synchronism voltage
Phase difference limit of synchronism check for

9 25.phi_Diff 0~ 89 1 deg
AR
Compensation for phase difference between two
10 25.phi_Comp 0~359 1 deg
synchronism voltages
Frequency difference limit of synchronism check
11 25.f_Diff 0.02~1.00 0.01 Hz
for AR
Voltage difference limit of synchronism check for
12 25.U_Diff 0.02Un~0.8Un V
AR
13 25.t_DdChk 0.010~25.000 s Time delay to confirm dead check condition
Time delay to confirm synchronism check

14 25.t_SynChk 0.010~25.000 s
condition
Enabling/disabling frequency difference check
15 25.En_fDiffChk 0 or 1 0: disable
1: enable
Synchro-check mode selection
16 25.SetOpt 0, 1 1 0: determined by external signal
1: determined by the setting
Enabling/disabling synchronism check
17 25.En_SynChk 0 or 1 0: disable
1: enable
Enabling/disabling dead line and dead bus (DLDB)
check
18 25.En_DdL_DdB 0 or 1
0: disable
1: enable
Enabling/disabling dead line and live bus (DLLB)
check
19 25.En_DdL_LvB 0 or 1
0: disable
1: enable
Enabling/disabling live line and dead bus (LLDB)
check
20 25.En_LvL_DdB 0 or 1
0: disable
1: enable
Enabling/disabling AR without any check
21 25.En_NoChk 0 or 1 0: disable
1: enable
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Enabling/disabling live three-phase check of line
22 25.En_3PLvChk 0 or 1 0: disable
1: enable
3.20 Automatic Reclosure

To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. Auto-reclosing systems are installed to restore the faulted
section of the transmission system once the fault is extinguished (providing it is a transient fault).
For certain transmission systems, auto-reclosure is used to improve system stability by restoring
critical transmission paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and auto-reclosing is not initiated after faulty feeder is tripped.
For some mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines,
etc., it is required to ensure that auto-reclosing is only initiated for faults overhead line section, or
make a choice according to the situation.

This auto-reclosing logic can be used with either integrated device or external device. When the
auto-reclosure is used with integrated device, the internal protection logic can initiate AR,
moreover, a tripping contact from external device can be connected to the device via opto-coupler
input to initiate integrated AR function.
When external auto-reclosure is used, the device can output some configurable output to initiate
external AR, such as, contact of initiating AR, phase-segregated tripping contact, single-phase
tripping contact, three-phase tripping contact and contact of blocking AR. According to
requirement, these contacts can be selectively connected to external auto-reclosure device to
initiate AR.
For phase-segregated circuit breaker, AR mode can be 1-pole AR for single-phase fault and
3-pole AR for multi-phase fault, or always 3-pole AR for any kinds of fault according to system
requirement. For persistent fault or multi-shot AR number preset value is reached, the device will
send final tripping command. The device will provide appropriate tripping command based on
faulty phase selection if adopting 1-pole AR.
AR can be enabled or disabled by logic setting or external signal via binary input. When AR is
enabled, the device will output contact [79.On], otherwise, output contact [79.Off]. After some
reclosing conditions, such as, CB position, CB pressure and so on, is satisfied, the device will
output contact [79.Ready].
According to requirement, the device can be set as one-shot or multi-shot AR. When adopting
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3 Operation Theory
multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole
AR. The rest AR mode is only 3-pole AR and its number is determined by the maximum 3-pole
reclosing number.
For one-shot AR or first reclosing of multi-shot AR, AR mode can be selected by logic setting
[79.En_1PAR], [79.En_3PAR] and [79.En_1P/3PAR] or external signal via binary inputs. When
3-pole or 1/3-pole AR mode is selected, the following three types of check modes can be selected:
dead charge check, synchronism check and no check.
79
79.En 79.On
79.Blk 79.Off
79.Sel_1PAR 79.Close
79.Sel_3PAR 79.Ready
79.Sel_1P/3PAR 79.AR_Blkd
79.Trp 79.Active
79.Trp3P 79.Inprog
79.TrpA 79.Inprog_1P
79.TrpB 79.Inprog_3P
79.TrpC 79.Inprog_3PS1
79.LockOut 79.Inprog_3PS2
79.PLC_Lost 79.Inprog_3PS3
79.WaitMaster 79.Inprog_3PS4
79.CB_Healthy 79.WaitToSlave
79.Clr_Counter 79.Perm_Trp1P
79.Ok_Chk 79.Perm_Trp3P
79.Ok_3PLvChk 79.Rcls_Status
79.Fail_Rcls
79.Succ_Rcls
79.Fail_Chk
79.Mode_1PAR
79.Mode_3PAR
79.Mode_1/3PAR
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3 Operation Theory
3.20.4 I/O Signals

Table 3.20-1 I/O signals of auto-reclosing

Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
1 79.En
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
2 79.Blk
disabling AR will be controlled by the external input
Input signal for selecting 1-pole AR mode of corresponding circuit
3 79.Sel_1PAR
breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
4 79.Sel_3PAR
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
5 79.Sel_1P/3PAR
breaker
6 79.Trp Input signal of single-phase tripping from line protection to initiate AR
7 79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
8 79.TrpA Input signal of A-phase tripping from line protection to initiate AR
9 79.TrpB Input signal of B-phase tripping from line protection to initiate AR
10 79.TrpC Input signal of C-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the
11 79.LockOut operating signals of definite-time protection, transformer protection
and busbar differential protection, etc.
12 79.PLC_Lost Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master AR
13 79.WaitMaster
(when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
14 79.CB_Healthy
perform the close function
15 79.Clr_Counter Clear the reclosing counter
16 79.Ok_Chk Synchro-check condition of AR is met
Live three-phase check condition of AR is met (internal signal, i.e. the
17 79.Ok_3PLvChk
output signal [25.Ok_3PLvChk] in Table 3.19-1)
1 79.On Automatic reclosure is enabled
2 79.Off Automatic reclosure is disabled
3 79.Close Output of auto-reclosing signal
4 79.Ready Automatic reclosure have been ready for reclosing cycle
5 79.AR_Blkd Automatic reclosure is blocked
6 79.Active Automatic reclosing logic is actived
7 79.Inprog Automatic reclosing cycle is in progress
8 79.Inprog_1P The first 1-pole AR cycle is in progress
9 79.Inprog_3P 3-pole AR cycle is in progress
10 79.Inprog_3PS1 First 3-pole AR cycle is in progress
11 79.Inprog_3PS2 Second 3-pole AR cycle is in progress
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3 Operation Theory
12 79.Inprog_3PS3 Third 3-pole AR cycle is in progress

13 79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
Waiting signal of automatic reclosing which will be sent to slave (when
14 79.WaitToSlave
reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
15 79.Perm_Trp1P
operates
Three-phase circuit breaker will be tripped once protection device
16 79.Perm_Trp3P
operates
Automatic reclosure status
0: AR is ready.
17 79.Rcls_Status
1: AR is in progress.
2: AR is successful.
18 79.Fail_Rcls Auto-reclosing fails
19 79.Succ_Rcls Auto-reclosing is successful
20 79.Fail_Chk Synchro-check for AR fails
21 79.Mode_1PAR Output of 1-pole AR mode
22 79.Mode_3PAR Output of 3-pole AR mode
23 79.Mode_1/3PAR Output of 1/3-pole AR mode
Automatic reclosure counter
24 79.N_Total_Rcls Recorded number of all reclosing attempts
25 79.N_Total_Rcls 1-pole Shot 1 Recorded number of first 1-pole reclosing attempts
26 79.N_Total_Rcls 3-pole Shot 1 Recorded number of first 3-pole reclosing attempts
27 79.N_Total_Rcls 3-pole Shot 2 Recorded number of second 3-pole reclosing attempts
28 79.N_Total_Rcls 3-pole Shot 3 Recorded number of third 3-pole reclosing attempts
29 79.N_Total_Rcls 3-pole Shot 4 Recorded number of fourth 3-pole reclosing attempts
3.20.5 Logic
3.20.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR.
When logic setting [79.SetOpt] is set as "1", AR mode is determined by logic settings. When logic
setting [79.SetOpt] is set as "0", AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[79.Ready] means that the auto-reclosure can perform at least one time of reclosing function, i.e.,
breaker open-close-open.
When the device is energized or after the settings are modified, the following conditions must be
met before the reclaim time begins:
1. AR function is enabled.
2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3. The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [79.t_CBClsd].
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3 Operation Theory
4. There is no block signal of auto-reclosing.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [79.Active]=0, in addition to
the above conditions for reclosing again.
The logic of AR ready is shown in Figure 3.20-2.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [79.t_PersistTrp], AR will be blocked, as shown in the following figure.
SIG Any tripping signal [79.t_PersistTrp] 0ms

>=1
SIG 79.LockOut 0ms [79.t_DDO_BlkAR]
SIG 1-pole AR Initiation [79.t_SecFault] 0ms

&
SIG Any tripping signal
En [79.En_PDF_Blk]
SIG 79.Sel_1PAR &
En [79.N_Rcls]=1
>=1
& 79.AR_Blkd
SIG Three phase trip
SIG Phase A open &
SIG Phase B open
& >=1
&
SIG Phase C open
Figure 3.20-1 Automatic reclosure block logic diagram
The input signal [79.CB_Healthy] must be energized before auto-reclosure gets ready. Because
most circuit breakers can finish one complete process: open-closed-open, it is necessary that
circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR
will be blocked if the input signal [79.CB_Healthy] is still not energized within time delay
[79.t_CBReady]. If this function is not required, the input signal [79.CB_Healthy] can be not to
configure, and its state will be thought as "1" by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input of blocking AR, when the circuit breaker is open by manually and there is CB position
input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not
initiated and no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchro-check failure or last shot is

reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
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3 Operation Theory
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [79.LockOut] is energized, auto-reclosure will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, auto-reclosure will be blocked immediately.
SIG CB closed position [79.t_CBClsd] 100ms &

>=1
SIG 79.Active >=1
SIG Any tripping signal

& &
100ms 0 79.Ready
SIG 79.Inprog
BI [79.CB_Healthy] 0ms [79.t_CBReady] &

SIG 79.AR_Blkd >=1
>=1
SIG BlockAR &
SIG 79.Fail_Rcls
>=1
SIG 79.Fail_Chk
SIG Last shot is made
EN [79.En] &
EN [79.En_ExtCtrl]
>=1
79.On
&
SIG 79.En &
SIG 79.Blk
Figure 3.20-2 Automatic reclosure ready logic diagram
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [79.t_SecFault] is used to discriminate another fault which begins after 1-pole AR
initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[79.En_PDF_Blk] is set as "1", and 3-pole AR will be initiated if [79.En_PDF_Blk] is set as "1".
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [79.t_DDO_BlkAR] after blocking signal disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop off (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
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3 Operation Theory
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [79.En]. When logic setting [79.En_ExtCtrl] is set as "1",
AR enable are determined by external signal via binary inputs and logic settings. When logic
setting [79.En_ExtCtrl] set as "0", AR enable are determined only by logic settings.
For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
SIG 79.On
SIG 79.Mode_3PAR
SIG 79.Ready
SIG 79.Trp
SIG 79.Trp3P
SIG 79.TrpA Logic 79.Perm_Trp3P
SIG 79.TrpB 79.Perm_Trp1P
SIG 79.TrpC
SIG Phase A open
SIG Phase B open
SIG Phase C open
Figure 3.20-3 Tripping condition output
When AR is enabled, the device will output the signal [79.Perm_Trp3P] if AR is not ready, or AR
mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.20.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [79.SetOpt] set as "1", AR mode is determined by the internal logic settings. If the logic
settings [79.SetOpt] set as "0", AR mode is determined by the external inputs.
1. AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from
internal trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing ("79.Ready"=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.20-4.
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3 Operation Theory
SIG Reset Command &

>=1
SIG Single-phase Trip
&
SIG 79.Ready
&
1-pole AR Initiation
SIG 79.Sel_1PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.20-4 Single-phase tripping initiating AR
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing ("79.Ready"=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence. (Reset Command) Its logic is
shown in Figure 3.20-5.
SIG Reset Command &

>=1
SIG Three-phase Trip
&
SIG 79.Ready
&
SIG 79.Sel_3PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.20-5 Three-phase tripping initiating AR
2. AR initiated by CB state
A logic setting [79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing ("79.Ready"=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.20-6 and Figure 3.20-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.
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3 Operation Theory
SIG Phase A open >=1
SIG Phase B open &

& &
&
SIG Phase C open 1-pole AR Initiation
EN [79.En_CBInit]
SIG 79.Ready
SIG 79.Sel_1PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.20-6 1-pole AR initiation
SIG Phase A open

&
SIG Phase B open
SIG Phase C open
EN [79.En_CBInit] & &

SIG 79.Ready
EN [79.Sel_1PAR] >=1
EN [79.Sel_1P/3PAR]
Figure 3.20-7 3-pole AR initiation
3.20.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of "1-pole AR initiation" can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, when the setting
[25.En_3PLvChk] is set as "0", the result of synchronism check will not be judged, and reclosing
command will be output directly. When the setting [25.En_3PLvChk] is set as "1", the reclosing is
not permissible unless live three-phase check is met. As far as the 3-pole AR, if the synchronism
check is enabled, the release of reclosing command shall be subject to the result of synchronism
check. After the dead time delay of AR expires, if the synchronism check is still unsuccessful
within the time delay [79.t_wait_Chk], the signal of synchronism check failure (79.Fail_Syn) will be
output and the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of
synchronism check success (25.Ok_Chk) will always be established. And the signal of
synchronism check success (25.Ok_Chk) from the synchronism check logic can be applied by
auto-reclosing function inside the device or external auto-reclosure device.
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79.Inprog_1P
SIG 1-pole AR Initiation >=1
79.Inprog
SIG 3-pole AR Initiation
79.Inprog_3P
SIG 1-pole AR Initiation [79.t_Dd_1PS1] 0ms &

>=1
AR Pulse
&
SIG 79.Ok_3PLvChk
SIG 3-pole AR Initiation [79.t_Dd_3PS1] 0ms &
>=1
& [79.t_Wait_Chk] 0ms 79.Fail_Chk
SIG 79.Ok_Chk
Figure 3.20-8 One-shot AR
In case pilot protection adopting permissive scheme, when the communication channel is
abnormal, pilot protection will be disabled. In the process of channel abnormality, an internal fault
occurs on the transmission line, backup protection at both ends of line will operate to trip the
circuit breaker of each end. The operation time of backup protection at both ends of the line is
possibly non-accordant, whilst the time delay of AR needs to consider the arc-extinguishing and
insulation recovery ability for transient fault, so the time delay of AR shall be considered
comprehensively according to the operation time of the device at both ends. When the
communication channel of main protection is abnormal (input signal [79.PLC_Lost] is energized),
and the logic setting [79.En_AddDly] is set as "1", then the dead time delay of AR shall be equal to
the original dead time delay of AR plus the extra time delay [79.t_AddDly], so as to ensure the
recovery of insulation intensity of fault point when reclosing after transient fault. This extra time
delay [79.t_AddDly] is only valid for the first shot AR.
>=1
SIG Any tripping signal &
BI [79.PLC_Lost]
&
SIG 79.Active
&
Extend AR time
EN [79.En_AddDly]
Figure 3.20-9 Extra time delay and blocking logic of AR
Reclosing pulse length may be set through the setting [79.t_PW_AR]. For the circuit breaker
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3 Operation Theory
without anti-pump interlock, a logic setting [79.En_CutPulse] is available to control the reclosing
pulse. When this function is enabled, if the device operates to trip during reclosing, the reclosing
pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing
command is issued, AR will drop off with time delay [79.t_Reclaim], and can carry out next
reclosing.
SIG WaitMasterValid &

0ms 50ms >=1
SIG AR Pulse 79.AR_Out
0ms [79.t_PW_AR]
SIG Single-phase Trip >=1

&
SIG Three-phase Trip &
EN [79.En_CutPulse]
>=1
&
SIG 79.AR_Out [79.t_Reclaim] 0ms Reset Command
Figure 3.20-10 Reclosing output logic
The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG 1-pole AR Initiation >=1

0ms [79.t_Fail] >=1
SIG 3-pole AR Initiation &
79.WaitToSlave
SIG 79.Fail_Rcls
SET [79.Opt_Priority] =1
Figure 3.20-11 Wait to slave signal
The output signal "79.WaitToSlave" is usually configured to the signal "79.WaitMaster" of slave AR.
Slave AR is permissible to reclosing only if master AR is reclosed successfully.
3.20.5.4 Reclosing Failure and Success
For transient fault, the fault will be cleared after the device operates to trip. After the reclosing
command is issued, AR will drop off after time delay [79.t_Reclaim], and can carry out next
reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR
initiated, the reclosing will be considered as unsuccessful, including the following cases.
1. If any protection element operates to trip when AR is enabled ([79.On]=1) and AR is not
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3 Operation Theory
ready ([79.Ready]=0), the device will output the signal (79.Fail_Rcls).
2. For one-shot AR, if the tripping command is received again within reclaim time after the
reclosing pulse is issued, the reclosing shall be considered as unsuccessful.
3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4. The logic setting [79.En_FailCheck] is available to judge whether the reclosing is successful
by CB state, when it is set as "1". If CB is still in open position with a time delay [79.t_Fail]
after the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this
case, the device will issue a signal (79.Fail_Rcls) to indicate that the reclosing is
unsuccessful, and this signal will drop off after (Reset Command). AR will be blocked if the
reclosing shall be considered as unsuccessful.
SET [79.Opt_Priority]=2 &

WaitMaster Valid
SIG 79.WaitMaster
SIG 79.On
&
SIG 79.Ready
SIG Any tripping command & >=1

0ms 200ms >=1
SIG Last shot is made 79.Fail_Rcls
SIG 79.Inprog &
SIG 79.AR_Blkd
SIG WaitMasterValid &

[79.t_WaitMaster] 0ms
>=1
SIG AR Pulse
&
[79.t_Fail] 0ms &
SIG CB closed
EN [79.En_FailCheck] &
& 79.Succ_Rcls
0 [79.t_Fail]
Figure 3.20-12 Reclosing failure and success
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.
3.20.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.N_Rcls], the
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3 Operation Theory
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
1. 1-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be
initiated only for single-phase fault and respective faulty phase selected, otherwise, AR will be
blocked. For single-phase transient fault on the line, line protection device will operate to trip and
1-pole AR is initiated. After the dead time delay for 1-pole AR is expired, the device will send
reclosing pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to
ready for the next reclosing. For permanent fault, the device will operate to trip again after the
reclosing is performed, and the device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the first
reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing
pulse. The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting [79.t_Dd_3PS1].
For the possible reclosing times of 3-pole AR in 1-pole AR mode, please refer to Table 3.20-2.
2. 3-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the
dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then the
auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next reclosing. For
permanent fault, the device will operate to trip again after the reclosing is performed, and the
device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached.
3. 1/3-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated for
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3 Operation Theory
single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead time
delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop
off after the time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the
device will operate to trip again after the reclosing is performed, and the device will output the
signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached. For the
possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.20-2 .
The table below shows the number of reclose attempts with respect to the settings and AR
modes.
Table 3.20-2 Reclosing number
1-pole AR 3-pole AR 1/3-pole AR

Setting Value
N-1AR N-3AR N-1AR N-3AR N-1AR N-3AR
1 1 0 0 1 1 1
2 1 1 0 2 1 2
3 1 2 0 3 1 3
4 1 3 0 4 1 4
N-1AR: the reclosing number of 1-pole AR
N-3AR: the reclosing number of 3-pole AR
4. Coordination between dual auto-reclosures
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number [79.N_Rcls]
is reached, the auto-reclosure will drop off after the time delay [79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu "Clear Counter". If the circuit breaker is reclosed by other
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3 Operation Theory
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
3.20.5.6 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.
Signal
Fault
Trip
CB 52b
Open
79.t_Reclaim [79.t_Reclaim]
79.Active
79.Inprog [79.t_Dd_1PS1]
79.Inprog_1P [79.t_Dd_1PS1]
79.Ok_Chk
AR Out [79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls
Time
Figure 3.20-13 Single-phase transient fault
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3 Operation Theory
Signal
Fault
Trip
Open Open
52b
79.t_Reclaim [79.t_Reclaim]
79.Active
79.Inprog
79.Inprog_1P [79.t_Dd_1PS1]
79.Inprog_3PS2 [79.t_Dd_3PS2]
79.Ok_Chk
AR Out [79.t_PW_AR] [79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls 200ms
Time
Figure 3.20-14 Single-phase permanent fault ([79.N_Rcls]=2)
3.20.6 Settings
Table 3.20-3 Settings of auto-reclosing
1 79.N_Rcls 1~4 1 Maximum number of reclosing attempts
2 79.t_Dd_1PS1 0.000~600.000 0.001 s Dead time of first shot 1-pole reclosing
4 79.t_Dd_3PS2 0.000~600.000 0.001 s Dead time of second shot 3-pole reclosing
5 79.t_Dd_3PS3 0.000~600.000 0.001 s Dead time of third shot 3-pole reclosing
6 79.t_Dd_3PS4 0.000~600.000 0.001 s Dead time of fourth shot 3-pole reclosing
Time delay of circuit breaker in closed position

7 79.t_CBClsd 0.000~600.000 0.001 s
before reclosing
Time delay to wait for CB healthy, and begin to timing
when the input signal [79.CB_Healthy] is
8 79.t_CBReady 0.000~600.000 0.001 s
de-energized and if it is not energized within this time
delay, AR will be blocked.
9 79.t_Wait_Chk 0.000~600.000 0.001 s Maximum wait time for synchronism check
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3 Operation Theory

Time delay allow for CB status change to conform
10 79.t_Fail 0.000~600.000 0.001 s
reclosing successful
11 79.t_PW_AR 0.000~600.000 0.001 s Pulse width of AR closing signal
12 79.t_Reclaim 0.000~600.000 0.001 s Reclaim time of AR
Time delay of excessive trip signal to block

13 79.t_PersistTrp 0.000~600.000 0.001 s
auto-reclosing
Drop-off time delay of blocking AR, when blocking
14 79.t_DDO_BlkAR 0.000~600.000 0.001 s signal for AR disappears, AR blocking condition
drops off after this time delay
15 79.t_AddDly 0.000~600.000 0.001 s Additional time delay for auto-reclosing
Maximum wait time for reclosing permissive signal

16 79.t_WaitMaster 0.000~600.000 0.001 s
from master AR
Time delay of discriminating another fault, and begin
to times after 1-pole AR initiated, 3-pole AR will be
17 79.t_SecFault 0.000~600.000 0.001 s initiated if another fault happens during this time
delay. AR will be blocked if another fault happens
after that.
Enabling/disabling auto-reclosing blocked when a
fault occurs under pole disagreement condition
18 79.En_PDF_Blk 0 or 1
0: disable
1: enable
Enabling/disabling auto-reclosing with an additional
dead time delay
19 79.En_AddDly 0 or 1
0: disable
1: enable
Enabling/disabling adjust the length of reclosing
pulse
20 79.En_CutPulse 0 or 1
0: disable
1: enable
Enabling/disabling confirm whether AR is successful
by checking CB state
21 79.En_FailCheck 0 or 1
0: disable
1: enable
Enabling/disabling auto-reclosing
22 79.En 0 or 1 0: disable
1: enable
Enabling/disabling AR by external input signal
besides logic setting [79.En]
23 79.En_ExtCtrl 0 or 1
0: only logic setting
1: logic setting and external input signal
Enabling/disabling AR be initiated by open state of
24 79.En_CBInit 0 or 1
circuit breaker
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3 Operation Theory

0: disable
1: enable
Option of AR priority
None, High or None: single-breaker arrangement
25 79.Opt_Priority
Low High: master AR of multi-breaker arrangement
Low: slave AR of multi-breaker arrangement
Control option of AR mode
26 79.SetOpt 0 or 1 1: select AR mode by internal logic settings
0: select AR mode by external input signals
Enabling/disabling 1-pole AR mode
27 79.En_1PAR 0 or 1 0: disable
1: enable
1: enable
Enabling/disabling 1/3-pole AR mode
29 79.En_1P/3PAR 0 or 1 0: disable
1: enable
3.21 Trip Logic

3.21.1 Application
For any enabled protection tripping elements, their operation signal will convert to appropriate
tripping signals through trip logics and then trigger output contacts by configuration.

This module gathers signals from phase selection and protection tripping elements and then
converts the operation signal from protection tripping elements to appropriate tripping signals. The
device can implement phase-segregated tripping or three-phase tripping, and may output the
contact of blocking AR and the contact of initiating breaker failure protection.
3.21.3 I/O Signals

Table 3.21-1 I/O signals of trip logic

Trip enabling input, it is triggered from binary input or programmable
1 TRP.En
logic etc.
Trip blocking input, it is triggered from binary input or programmable

2 TRP.Blk
logic etc.
1 TRP.On Trip output is enabled
2 TRP.BlkAR Blocking auto-reclosing
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3 Operation Theory
3 TrpA Tripping phase-A circuit breaker

4 TrpB Tripping phase-B circuit breaker
5 TrpC Tripping phase-C circuit breaker
6 Trp Tripping any phase of circuit breaker
7 Trp3P Tripping three-phase circuit breaker
A-phase breaker failure protection initiating (BFI) signal, BFI signal
8 BFI_A shall be reset immediately after tripping signal drops off (internal
signal).
B-phase breaker failure protection initiating (BFI) signal, BFI signal
9 BFI_B shall be reset immediately after tripping signal drops off (internal
signal).
C-phase breaker failure protection initiating (BFI) signal, BFI signal
10 BFI_C shall be reset immediately after tripping signal drops off (internal
signal).
Breaker failure protection initiating (BFI) signal, BFI signal shall be
11 BFI
reset immediately after tripping signal drops off (internal signal).
3.21.4 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp]
at least. When the time delay is expired, for phase-segregated tripping, the tripping signal will
drop off immediately if the faulty current of corresponding phase is less than 0.06In (In is
secondary rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.
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3 Operation Theory
SIG TRP.En &

TRP.On
SIG TRP.Blk
0 t_Dwell_Trp
&
&
>=1 TrpA
50BF.Op_ReTrpA t_Dwell_Trp 0
SIG &
SIG Ia>0.06In
0 t_Dwell_Trp
&
&
>=1 TrpB
50BF.Op_ReTrpB t_Dwell_Trp 0
SIG &
SIG Ib>0.06In
0 t_Dwell_Trp
&
&
>=1 TrpC
50BF.Op_ReTrpC t_Dwell_Trp 0
SIG &
SIG Ic>0.06In
>=1
>=1 Trp
0 t_Dwell_Trp
&
&
SIG Prep3PTrp >=1 >=1

t_Dwell_Trp 0
& Trp3P
SIG Op_CBProt
SIG Max(Ia,Ib,Ic)>0.06In
SIG TrpA &

BFI_A
SIG TrpB &

BFI_B
Internal breaker failure protection

TrpC
initiating (BFI) signal
SIG
&
BFI_C
SIG Trp &

BFI
SIG 50/51Gx.Op
>=1
SIG 50/51Px.Op
SIG 81U.UFx.Op >=1

SIG 81O.OFx.Op
SIG 50/51Qx.Op >=1
SIG 62PD.Op
Figure 3.21-1 Simplified trip logic
All operation elements (except for re-tripping element) are 3 phase tripping elements.
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3 Operation Theory
SIG 50/51Px.Op &
EN [50/51Px.En_BlkAR]
>=1
SIG 50/51Gx.Op &
EN 50/51Gx.En_BlkAR
SIG 62PD.Op
>=1 >=1
SIG 81U.UFx.Op TRP.BlkAR
SIG 81O.OFx.Op
SIG 50BF.Op_t1 >=1
SIG 50BF.Op_t2
Figure 3.21-2 Blocking AR logic
3.21.5 Settings
Table 3.21-2 Settings of trip logic

The dwell time of tripping command, empirical value is 0.04
1 t_Dwell_Trp 0.000~10.000 0.001 s The tripping contact shall drop off under conditions of no
current or protection tripping element drop-off.
3.22 VT Circuit Supervision

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
1. Line VT is used as protection VT and the protected line is out of service.
2. Only current protection functions are enabled and VT is not connected to the device.
3. The input positive-sequence voltage is lower than 30V or negative-sequence voltage

exceeds 8V. This alarm signal will pick up with a time delay of 1.25s and will drop off with a
time delay of 10s.
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3 Operation Theory

VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detect residual voltage greater than 8% of Unn to determine
single-phase or two-phase VT circuit failure, and detect three times positive-sequence voltage
less than Unn to determine three-phase VT circuit failure. Upon detecting abnormality on VT
circuit, an alarm will comes up after a time delay of [VTS.t_DPU] and drop off with a time delay of
[VTS.t_DDO] after VT circuit restored to normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay. If the
auxiliary contact is not connected to the device, VT circuit supervision will be issued with time
delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm will be not issued if the logic setting
[VTS.En_Out_VT] is set as "1". However, the alarm is still issued if the binary input [VTS.MCB_VT]
is energized, no matter that the logic setting [VTS.En_Out_VT] is set as "1" or "0".
When VT neutral point fails, third harmonic of residual voltage is comparatively large. If third
harmonic amplitude of residual voltage is larger than 0.2Unn and without operation of fault
detector element, VT neutral point failure alarm signal [VTNS.Alm] will be issued after a time delay
of [VTS.t_DPU] and drop off with a time delay of [VTS.t_DDO] after three phases voltage restored
to normal.
VTS VTNS
VTS.En VTS.Alm VTNS.En VTNS.Alm
VTS.Blk VTNS.Blk
VTS.MCB_VT
3.22.4 I/O Signals

Table 3.22-1 I/O signals of VT circuit supervision

VT supervision enabling input, it is triggered from binary input or programmable
1 VTS.En
logic etc.
2 VTS.Blk VT supervision blocking input, it is triggered from binary input or programmable
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3 Operation Theory
logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
3 VTNS.En
VT neutral point supervision blocking input, it is triggered from binary input or
4 VTNS.Blk
5 VTS.MCB_VT Binary input for VT MCB auxiliary contact
1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTNS.Alm Alarm signal to indicate VT neutral point fails
3.22.5 Logic
SIG FD.Pkp >=1

&
SIG 79.Inprog
SIG 3U0>0.08Unn
>=1
SIG 3U1<Unn &
>=1 If FD.Pkp OR 79.Inprog operate, then
EN [VTS.En_LineVT] & circuit of time delay will be interrupted.
[VTS.t_DPU] [VTS.t_DDO] &

SIG 52b_3P
>=1
EN [VTS.En_Out_VT]
BI [VTS.MCB_VT]
>=1
& VTS.Alm
EN [VTS.En]
&
SIG [VTS.En]
SIG [VTS.Blk]
Figure 3.22-1 VT circuit supervision logic diagram
&
SIG FD.Pkp >=1
SIG 79.Inprog
If FD.Pkp OR 79.Inprog operate, then
circuit of time delay will be interrupted.
OTH U03>0.2Unn & >=1
[VTS.t_DPU] [VTS.t_DDO] & VTNS.Alm
EN [VTS.En_Out_VT]
EN [VTS.En]
&
SIG [VTNS.En]
SIG [VTNS.Blk]
Figure 3.22-2 VT neutral point supervision logic diagram
Unn: rated phase-to-phase voltage
U03: third harmonic amplitude of neutral point residual voltage
If fault detector element operates or automatic reclosing cycle is in progress, and VT circuit failure
signal have been detected, then the VT circuit failure signal will be maintained, only when the fault
detector element and automatic reclosing element are all drop-off, VT circuit supervision will
return to normal operation.
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3 Operation Theory
SIG U2 > 8V
≥1
SIG U1 < 30V
&
SIG Ia > 0.04In
SIG Ib > 0.04In ≥1
SIG Ic > 0.04In
& 1.25s 0
[YYYY.Alm_VTS_Measmt]
EN [YYYY.En_Alm_VTS]
Figure 3.22-3 VT circuit supervision logic diagram for measurement
3.22.6 Settings
Table 3.22-2 VTS settings

1 VTS.t_DPU 0.200~100.000 0.001 s Pickup time delay of VT circuit supervision
2 VTS.t_DDO 0.200~100.000 0.001 s Dropoff time delay of VT circuit supervision
No voltage used for protection calculation
1: enable
0: disable
3 VTS.En_Out_VT 0 or 1
In general, when VT is not connected to the
device, this logic setting should be set as
“1”
Voltage selection for protection calculation
from busbar VT or line VT
4 VTS.En_LineVT 0 or 1
1: line VT
0: busbar VT
Alarm function of VT circuit supervision
5 VTS.En 0 or 1 1: enable
0: disable
3.23 CT Circuit Supervision

3.23.1 Application
The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.

Under normal conditions, CT secondary signal is continuously supervised by detecting the
residual current and voltage. If residual current is larger than 10%In whereas residual voltage is
less than 3V, an error in CT circuit is considered, the concerned protection functions are blocked
and an alarm is issued with a time delay of 10s and drop off with a time delay of 10s after CT
circuit is restored to normal condition.
Under a normal condition, secondary current input for measurement is continuously supervised by
detecting the residual and negative-sequence current. If the residual current is larger than 0.06A
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3 Operation Theory
or the negative-sequence current is greater than 0.10A, a CT circuit error is considered. The
related functions are going to be blocked and an alarm will be issued with a time delay of 1.25s
and drop off with a time delay of 10s after the error disappears.
CTS
CTS.En CTS.Alm
CTS.Blk
3.23.4 I/O Signals

Table 3.23-1 I/O signals of CT circuit supervision

1 U3P Three-phase voltage input
2 I3P Three-phase current input
CT circuit supervision enabling input, it is triggered from binary input or
3 CTS.En
CT circuit supervision blocking input, it is triggered from binary input or
4 CTS.Blk
1 CTS.Alm Alarm signal to indicate CT circuit fails
3.23.5 Logic
SIG CTS.En &

&
SIG CTS.Blk 10s 10s CTS.Alm
SIG 3I0>0.1In
&
SIG 3U0<3V
SIG IA<0.06In
>=1
SIG IB<0.06In
SIG IC<0.06In
Figure 3.23-1 CT circuit failure supervision logic diagram
SIG I0 > 0.06In

≥1
10s 0
SIG I2 > 0.10In & [YYYY.Alm_CTS]
EN [YYYY.En_Alm_CTS]
Figure 3.23-2 CT circuit supervision logic diagram for measurement
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4 Supervision
4 Supervision
Table of Contents
4 Supervision ........................................................................................ 4-a
4.1 BCU Supervision Alarm ................................................................................... 4-1
4.2 GOOSE Alarm ................................................................................................... 4-6
List of Tables
Table 4.1-1 BCU supervision alarm ........................................................................................... 4-1
Table 4.1-2 Troubleshooting for BCU supervision alarm ....................................................... 4-4
Table 4.2-1 GOOSE alarm ............................................................................................................ 4-7
Table 4.2-2 Troubleshooting for GOOSE alarm .......................................................................... 4-7
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4 Supervision
4.1 BCU Supervision Alarm

Hardware circuits and operating status of the device are self-supervised continuously. If any
abnormality is detected, alarm information or report will be displayed on the device LCD and sent
to local/remote control centre.
A minor abnormality may block a certain number of functions while the other functions can still
work. However, if a severe hardware failure is detected, all functions will be blocked, the LED
“HEALTHY” will be extinguished, and the output contact “BO_FAIL”, which locates in the PWR
module, will be electrified. Therefore, this device can no longer be in service and maintenance is
required to eliminate the failure. The alarm signals and their corresponding troubleshooting
suggestions are listed below.
NOTICE!
If the device is blocked or an alarm signal is issued, please find out its reason with the
help of self-diagnostic record. If the reason cannot be found at site, please inform the
local service or the manufacturer.
NOTICE!
"YYYY" is the function name substitution for bay identification such as "BayMMXU",
"Bus1_MMXU", "Bay1_MMXU", "Sum_MMXU", etc.
Access Path: “MainMenu” -> “Status” -> “Superv State” -> “BCU Superv".
Table 4.1-1 BCU supervision alarm
No. Item Description

Failure Signals (Device is blocked, “HEALTHY” LED is lit off, “ALARM” LED is lit on)
The device fails.
1 Fail_Device This signal will pick up if any failure signal picks up and it will drop off when
all failure signals drop off.
Software configuration is incorrect.
2 Fail_Config This signal will pick up instantaneously and will be latched unless the
recommended handling suggestion is adopted.
3 Fail_Sample_AD Error is found during AD sampling.
4 Fail_Settings Error is found during setting check.
Set value of any setting is out of scope.
5 Fail_Setting_OvRange This signal will pick up instantaneously and will be latched unless the
After the configuration file is updated, settings of the file and settings saved
on the device are not matched.
6 Fail_SettingItem_Chgd
This signal will pick up instantaneously and will be latched unless the
DSP chip is damaged.
7 Fail_DSP This signal will pick up instantaneously and will be latched unless the
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4 Supervision

Error is found during checking memory data.
8 Fail_Memory This signal will pick up instantaneously and will be latched unless the
AC current and voltage samplings are abnormal.
9 Fail_Sample This signal will pick up with a time delay of 200ms and will be latched
unless the recommended handling suggestion is adopted.
Communication between two DSP chips is abnormal
10 Fail_DSP_Comm
This signal will pick up instantaneously and will drop off instantaneously.
11 Fail_Initialization Error is found during device initialization process.
12 Fail_FPGA FPGA chip in the MON module is damaged.
13 Fail_Overflow_AD Receiving buffer overflow is found during AD sampling.
14 Fail_SampleSyn_AD Receiving buffer error is found during AD sampling.
15 Alm_Self-Check Error is found in device setting or the device is abnormal.
Mismatch between the configuration of plug-in modules and the designing
16 Fail_BoardConfig
drawing of an applied-specific project.
Alarm Signals (Device is not blocked, “HEALTHY” LED is lit on and “ALARM” LED is lit on)
1 Alm_Device The device is abnormal.
Time synchronization abnormality alarm.
2 Alm_TimeSyn This signal will pick up with a time delay of 60s and will drop off
instantaneously.
Frequency of the system is higher than 65Hz or lower than 45Hz.
3 Alm_Freq This signal will pick up with a time delay of 100ms and will drop off with a
time delay of 10s.
4 Alm_SamplSyn_FO Synchronization error exists in the receiving buffer of NET-DSP module.
5 Alm_Overflow_FO Received frames are beyond the capability of NET-DSP module.
6 Alm_SmplCRC_FO Error is founded in the CRC code received by NET-DSP module.
7 Alm_SmplCounter_FO The frame counter of NET-DSP module is not consecutive.
8 Alm_RecvTimeout_FO The data reception of NET-DSP module is time-out.
9 Alm_Quality_FO The data quality bit received by NET-DSP is "Invalid".
10 Alm_Version Error or inconsistence of program version is detected.
11 Alm_Settings_MON Error is found during setting check in the MON module.
The active group set by settings in device and that set by binary input are
12 Alm_BI_SettingGrp not matched.
This signal will pick up instantaneously and will drop off instantaneously.
13 Alm_SigErr_IRIG-B Error is found during time synchronization
14 Alm_ServiceErr_IRIG-B Error is found in device time synchronization service
15 Alm_TimeJump_IRIG-B Sudden change of time is detected (except the time initialization process)
16 Alm_Insuf_Memory The memory in the MON module is insufficient.
The device is in the communication test mode (virtual measurement and
17 Alm_CommTest
status).
18 Alm_BOTest The device is in the output contact test mode (real relay operation).
19 BXX.Alm_OptoDC The power supply of the BI module in the slot No.XX is abnormal.
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This signal will pick up with a time delay of 10s and will drop off with a time
delay of 10s.
CT circuit of corresponding circuit breaker fails.
20 CTS.Alm This signal will pick up with a time delay of 10s and will drop off with a time
delay of 10s.
Protection VT circuit fails.
21 VTS.Alm This signal will pick up with a time delay [VTS.t_DPU] and will drop off with
a time delay [VTS.t_DDO].
Protection VT circuit of neutral point fails.
22 VTNS.Alm This signal will pick up with a time delay [VTS.t_DPU] and will drop off with
a time delay [VTS.t_DDO].
The auxiliary normally closed contact (52b) of corresponding circuit breaker
is abnormal.
23 Alm_52b
delay of 10s.
Fault detector element operates for longer than 50s.
24 Alm_Pkp_FD This signal will pick up with a time delay of 50s and will drop off with a time
delay of 10s.
Neutral current fault detector element operates for longer than 10s.
25 Alm_Pkp_I0 This signal will pick up with a time delay of 10s and will drop off with a time
delay of 10s.
The [YYYY.UN_Pri] value (indicating residual voltage) is greater than
[YYYY.UN_Alm_ROV]*[YYYY.U1n_VT_Measmt].
26 YYYY.Alm_ROV
delay of 1s
VT circuit fails.
27 YYYY.Alm_VTS_Measmt This signal will pick up with a time delay of 1.25s and will drop off with a
time delay of 10s.
A primary phase voltage value is less than
[YYYY.U_Alm_UV]*[YYYY.U1n_VT_Measmt].
28 YYYY.Alm_UV
delay of 1s.
CT circuit fails.
29 YYYY.Alm_CTS This signal will pick up with a time delay of 10s and will drop off with a time
delay of 10s.
30 BXX.Alm_Output Hardware error is found in the BO module at slot XX.
For a double position synthesis signal, which indicates CB/DS/ES status,
both the normally open (abbreviated as NO) contact and the normally
closed (abbreviated as NC) contact are opened or closed.
31 DPOS.Alm
This signal will pick up with a time delay of
“[DPOS.t_DPU_**]+[DPOS.t_Alm]” and will drop off with a time delay of
[DPOS.t_Alm].
32 25.Alm_VTS_Usyn Synchronism voltage circuit corresponding to circuit breaker is abnormal.
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4 Supervision

This signal will pick up with a time delay of 1.25s and will drop off with a
time delay of 10s.
Reference voltage circuit corresponding to circuit breaker is abnormal.
33 25.Alm_VTS_Uref This signal will pick up with a time delay of 1.25s and will drop off with a
time delay of 10s.
34 79.Fail_Rcls Auto-reclosing corresponding to circuit breaker fails.
35 79.Fail_Chk Synchrocheck for AR corresponding to circuit breaker fails.
Spare alarm signals
36 Alm_Spare** The time delay of pickup and dropoff for these alarm signals can be set by
PCS-Explorer.
Table 4.1-2 Troubleshooting for BCU supervision alarm
No. Item Troubleshooting suggestion

Failure Signals (Device is blocked, “HEALTHY” LED is lit off, “ALARM” LED is lit on)
1 Fail_Device Eliminate all the other alarms firstly.
Please inform configuration engineers to check and confirm visualization
2 Fail_Config
functions of the device
1. Put the device out of service.
2. Check the analog input module and the corresponding wiring
3 Fail_Sample_AD
connector.
3. Reboot the device.
4 Fail_Settings Inform the local technical support or the manufacturer.
Please reset setting values according to the range described in the
5 Fail_Setting_OvRange instruction manual, then re-power or reboot the device and the device will
restore to normal operation state.
Please check the settings mentioned in the prompt message on the LCD,
6 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm_Settings” item to
confirm settings. Then, the device will restore to normal operation stage.
Chips are damaged and please inform the manufacture or the agent
7 Fail_DSP
replacing the module.
8 Fail_Memory Please inform the manufacture or the agent for repair.
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors
9 Fail_Sample connected to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation
state.
10 Fail_DSP_Comm Please inform the manufacture or the agent for repair.
Check whether the software version in LCD display is consistent with the
11 Fail_Initialization
one in the configuration file.
FPGA chip is damaged. Inform the Inform the local technical support or the
12 Fail_FPGA
manufacturer for replacement.
13 Fail_Overflow_AD
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4 Supervision

connector.
14 Fail_SampleSyn_AD
connector.
1. Check whether the software version in LCD display is consistent with
15 Alm_Self-Check the one in the configuration file.
2. Check whether there is a fatal error in this device.
1. Go to the menu “Information”->”Board Info” to check the module
configuration mismatch.
2. If a module is not used, remove it.
16 Fail_BoardConfig
3. If a module is used, check whether it is installed properly and working
normally.
Alarm Signals (Device is not blocked, “HEALTHY” LED is lit on and “ALARM” LED is lit on)
1 Alm_Device Eliminate the other alarms firstly.
1. Check clock synchronization mode and the clock synchronization
source.
2 Alm_TimeSyn 2. Check wiring connection between the device and the source.
3. Check the setting [Opt_TimeSyn]. If there is no clock synchronization,
please set the setting to ”No TimeSyn”.
3 Alm_Freq Adjust the system operating mode
Check the communication channel and the compatibility between the
4 Alm_SamplSyn_FO
device program version and the configuration file.
5 Alm_Overflow_FO
6 Alm_SmplCRC_FO
Check the communication channel and the transmission speed.
7 Alm_SmplCounter_FO
8 Alm_RecvTimeout_FO
Check the MU sending configuration and the compatibility between the
9 Alm_Quality_FO
device program version and the configuration file.
Users may pay no attention to this alarm in commissioning stage, but the
latest program package file (including the correct version checksum file)
ought to be implemented to eliminate this alarm before putting device into
10 Alm_Version
service.
Make sure that [En_MDisk]=0 (Access path: "MainMenu" -> "Settings" ->
"Device Setup") if there is none moveable disk.
11 Alm_Settings_MON Inform the local technical support or the manufacturer.
Please check the value of setting [Active_Grp] and binary input of indiating
active group, and make them matched. Then the “ALARM” LED will be
12 Alm_BI_SettingGrp
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
13 Alm_SigErr_IRIG-B Please check the time synchronization source, connection link and
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4 Supervision

14 Alm_ServiceErr_IRIG-B reception module.
15 Alm_TimeJump_IRIG-B
16 Alm_Insuf_Memory Replace the MON module with another subtype (larger memory).
17 Alm_CommTest
Wait for the completion of test.
18 Alm_BOTest
Please check the corresponding CT secondary circuit. After the
19 CTS.Alm
abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit. After the abnormality
20 VTS.Alm
is eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit of neutral point. After
21 VTNS.Alm
the abnormality is eliminated, the device returns to normal operation state.
Please check the auxiliary contact of CB. After the abnormality is
22 Alm_52b
eliminated, the device returns to normal operation state.
Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
23 Alm_Pkp_FD
then the alarm message will disappear and the device will restore to normal
operation state.
Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
24 Alm_Pkp_I0
then the alarm message will disappear and the device will restore to normal
operation state.
1. Check the connection of binary input modules.
25 BXX.Alm_OptoDC
2. Check whether the device power supply is in required range.
26 YYYY.Alm_ROV Check the residual voltage input or the calculated residual voltage.
27 YYYY.Alm_VTS_Measmt Check the measurement VT secondary circuit.
28 YYYY.Alm_UV Check three-phase voltages.
29 YYYY.Alm_CTS Please check the corresponding CT secondary circuit.
30 BXX.Alm_Output Check the corresponding BO module or PLC module at the slot XX.
Check the double position state (Access the submenu “MainMenu” ->
“Status” -> “Inputs” -> “DPS Inputs”).
[DPOS**]=“DPS_INT”: Intermediate-state;
[DPOS**]=“DPS_OFF”: Open;
31 DPOS.Alm
[DPOS**]=“DPS_ON”: Close;
[DPOS**]=“DPS_BAD”: Bad state.
If [DPOS**]=“DPS_INT” or “DPS_BAD”, check the state of corresponding
CB/DS/ES.
Find the reason according to specific problem. (These signals are
32 Alm_Spare**
user-defined.)
4.2 GOOSE Alarm

If any GOOSE alarm signal is issued, the “ALARM” LED and the "HEALTHY” LED are both lit on. The
device is not blocked. When the GOOSE alarm signal disappears, the device will return to normal
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4 Supervision
state, and the “ALARM” LED will be lit off automatically.
Access Path: “MainMenu” -> “Status” -> “Superv State” -> “GOOSE Superv”.
NOTICE!
"ZZZZ" refers to the a link identification name which can be configured through the
corresponding label setting (Access path: “MainMenu” -> “Settings” -> “Device Setup” ->
“Label Settings”).
"**" is a communication link number.
Table 4.2-1 GOOSE alarm

1 GAlm_Overall_SL The general GOOSE alarm in station level.
2 GAlm_AStorm_SL Network storm exists in station level GOOSE network A.
3 GAlm_BStorm_SL Network storm exists in station level GOOSE network B.
4 GAlm_CfgFile_SL Error exists in station level GOOSE configuration file.
5 ZZZZ.GAlm_ADisc_SL_** Station level GOOSE network A link** is disconnected.
6 ZZZZ.GAlm_BDisc_SL_** Station level GOOSE network B link** is disconnected.
Mismatch is found between the GOOSE control blocks received via network
7 ZZZZ.GAlm_Cfg_SL_**
and that defined in GOOSE configuration file in station level GOOSE network.
Table 4.2-2 Troubleshooting for GOOSE alarm
No. Item Handling suggestion

1 GAlm_Overall_SL
2 GAlm_AStorm_SL
3 GAlm_BStorm_SL
Check Ethernet switches, ports, connections and GOOSE configuration file
4 GAlm_CfgFile_SL
of station level GOOSE network.
5 ZZZZ.GAlm_ADisc_SL_**
6 ZZZZ.GAlm_BDisc_SL_**
7 ZZZZ.GAlm_Cfg_SL_**
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5 Management
5 Management
Table of Contents
5 Management ......................................................................................5-a
5.1 Protection Measurement ................................................................................ 5-1
5.2 BCU Measurement .......................................................................................... 5-1
5.3 Event Recording .............................................................................................. 5-1
5.3.1 Overview .............................................................................................................................. 5-1
5.3.2 Device Supervision Event .................................................................................................... 5-1
5.3.3 Binary Status Change Event ................................................................................................ 5-1
5.3.4 Device Log ........................................................................................................................... 5-1
5.3.5 Switch Control Log ............................................................................................................... 5-1
5.3.6 DC Regulation Log ............................................................................................................... 5-2
5.4 Disturbance Recording ................................................................................... 5-2

5.4.1 Application ............................................................................................................................ 5-2
5.4.2 Design .................................................................................................................................. 5-2
5.4.3 Disturbance Record ............................................................................................................. 5-2
5.4.4 Fault Waveform .................................................................................................................... 5-2
5.5 Present Recording .......................................................................................... 5-3
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5 Management
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5 Management
5.1 Protection Measurement

The menu "Measurements1" is used to display measured values from protection calculation DSP
in secondary value.
The menu "Measurement2" is used to display measured values from fault detector DSP in
secondary value.
This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
5.2 BCU Measurement

The menu "Measurements3" is used to display BCU sampled and calculated values.
This device performs continuous measurement of analog inputs. The device samples multiple
points per cycle, calculates RMS values in each interval, and updates the LCD display in every
0.5s. The measurement can be displayed on the LCD of the device HMI panel and transmitted to
local/remote control centre.
5.3 Event Recording

5.3.1 Overview
The device can store the latest 1024 supervision events, 1024 IO events, 1024 device logs, 256
control logs and 256 regulation logs. All the records are stored in non-volatile memory, and when
the available space is exhausted, the oldest record will be automatically overwritten by the latest
one.
5.3.2 Device Supervision Event

The device is under automatic supervision all the time. If there is any failure or abnormal condition
detected (e.g. VT circuit failure), it will be stored and displayed.
5.3.3 Binary Status Change Event

When a binary input is energized or de-energized, i.e., its state has changed from "0" to "1" or
from "1" to "0", it will be stored and displayed.
5.3.4 Device Log

If an operator implements some operations on the device, such as reboot device, modify setting,
etc., they will be stored and displayed.
5.3.5 Switch Control Log

The total sequence of each attempt of control command will be stored and displayed, including
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5 Management
object, source, remote/local mode, interlock condition, command (selection/execution, open/close,

up/down) and result.
5.3.6 DC Regulation Log

The total sequence of each attempt of regulation command will be stored and displayed, including
object, source, remote/local mode, command (selection/execution), value and result.
5.4 Disturbance Recording

5.4.1 Application
Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
5.4.2 Design
A disturbance record consists of fault record and fault waveform. A disturbance record can be
initiated by fault detector element, tripping element, reclosing element or configurable signal
[BI_TrigDFR].
5.4.3 Disturbance Record

The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.
For each disturbance record, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record.
4. Faulty phase
5. Protection elements
5.4.4 Fault Waveform

MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.
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5 Management
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
Each time recording includes 12-cycle pre-fault waveform, and 250 cycles at least and 500 cycles
at most can be recorded. Each cycle waveform is high-frequency recording at a rate of 1200Hz
(24 poingts per cycle).
5.5 Present Recording

Present recording is a waveform triggered manually on on the device’s LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.
Each time recording includes several-cycle waveform before triggering (the waveform cycle
number is configured via the communication setting [Num_Cyc_PreTrigDFR], the default value is
12-cycle), and 250 cycles at most can be recorded. Each cycle waveform is high-frequency
recording at a rate of 1200Hz or 1440Hz (24 poingts per cycle).
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6 Hardware
6 Hardware
Table of Contents
6 Hardware ............................................................................................6-a
6.1 Overview .......................................................................................................... 6-1
6.2 Module Configuration (for EXAMPLE only)................................................... 6-2
6.3 Plug-In Module Description ............................................................................ 6-3
6.3.1 MON Module (Management & Monitoring) .......................................................................... 6-3
6.3.2 DSP Module (Calculation).................................................................................................... 6-4
6.3.3 AC AI Module (AC Analog Input).......................................................................................... 6-5
6.3.4 DC AI Module (DC Analog Input) ......................................................................................... 6-8
6.3.5 BI Module (Binary Input) ...................................................................................................... 6-9
6.3.6 BO Module (Binary Output) ............................................................................................... 6-12
6.3.7 PWR Module (Device Power Supply) ................................................................................ 6-13
List of Figures
Figure 6.1-1 Hardware diagram ................................................................................................. 6-1
Figure 6.2-1 Module configuration example (conventional CT/VT) ....................................... 6-3
Figure 6.3-1 MON module........................................................................................................... 6-4
Figure 6.3-2 DSP module............................................................................................................ 6-5
Figure 6.3-3 Schematic diagram of CT circuit automatically closed ......................................... 6-6
Figure 6.3-4 AI module................................................................................................................ 6-6
Figure 6.3-5 DC AI module ......................................................................................................... 6-9
Figure 6.3-6 BI module (NR1503) ............................................................................................... 6-10
Figure 6.3-7 BI module (NR1504) ............................................................................................... 6-11
Figure 6.3-8 BO module (NR1521) ........................................................................................... 6-12
Figure 6.3-9 PWR module......................................................................................................... 6-14
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6 Hardware
6.1 Overview
PCS-9705 adopts 32-bit microchip processor as the control core for management and monitoring
function, meanwhile, adopts high-speed digital signal processor DSP for calculation. 80 points are
sampled in every cycle and parallel processing of sampled data can be realized in each sampling
interval to ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of NR's latest software and hardware platform, and this new
platform provides high reliability, networking and great capability for anti-interference.
Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP
ECVT
Fault
A/D Detector Pickup
DSP Relay
ECVT
ETHERNET
LCD +E
Clock SYN
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT
Figure 6.1-1 Hardware diagram
The working process of the device is shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for calculation (ECVT signal is sent to the device without any conversion).
When DSP module completes all the calculation, the result will be recorded in the CPU on MON
module. DSP module carries out fault detector, logic calculation, tripping output, and MON module
perfomes SOE (Sequence Of Event) recording, waveform recording, printing, device internal and
external communication. When fault detector detects a fault and picks up, the positive power
supply for output relay will be available.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-9705 based on microcomputer are
classified into standard and optional modules.
PCS-9705 is comprised of several modules as shown below.
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6 Hardware
Module Type Symbol Brief Slot Remark

NR1110 MON Management and monitoring 01 Mandatory
NR1115 DSP (BCU) Logic calculation 03 Mandatory
NR1161 DSP (PROT) Protection calculation 04 Optional
NR1401 AC AI AC analog input 05&06 Optional
NR1425 DC AI DC analog input (from transducer) 07~10 Optional
NR1503
BI Binary input 02, 07~15 Optional
NR1504
NR1521 BO Binary output for tripping and signalisation 11~15 Optional
NR1301 PWR Device power supply P1 Mandatory
 MON module provides management and monitoring functions, such as SAS communication,
event recording, setting modification, etc. Station level GOOSE message can also be
received by MON module.
 DSP module performs filtering, sampling, protection and fault detector calculation.
 AC AI module converts AC current and voltage from CT/VT to small voltage signal.
 DC AI module can receive DC analog inputs from transducer representing temperature,

humidity, etc.
 BI module provides binary inputs via opto-couplers with rated voltage.
 BO module provides output contacts assigned for protection tripping, remote control and
signalisation.
 PWR module converts 110~250Vdc into various low level DC voltage for modules and
electronic components.
NOTICE!
In different engineering applications, the number of the modules equipped may be

different according to the actual requirement.
6.2 Module Configuration (for EXAMPLE only)

NOTICE!
This section shows several examples of device terminal view and module
arrangement.
The following figures should NOT be used as reference for device configuration or
wiring design. For such purpose, please use the latest corresponding Manufacture
Ordering Table and consult our design department.
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6 Hardware
DSP module 2
DSP module 1
DC AI module
AC AI module
MON module
PWR module
BO module
BI module
Slot No.
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 P1
Figure 6.2-1 Module configuration example (conventional CT/VT)
6.3 Plug-In Module Description

6.3.1 MON Module (Management & Monitoring)
The MON module is obligatory and fixed at the slot 01 in this device. It consists of
high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet controller and other
peripherals. Its functions include management of the complete device, human machine interface,
Commonication, waveform recording, etc.
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temperary or permanent blindness.
Module ID Interface Terminal No. Usage Physical Layer

2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To PRP or HSR Optical fibre LC-type
01 A
RS-485 02 B Reserved
03 SGND
04 A
RS-485 05 B Reserved Twisted pair wire
NR1110B
06 SGND
07 SYN+
RS-485/TTL 08 SYN- To clock synchronization
09 SGND
10 RTS
RS-232 11 TXD Reserved Cable
12 SGND
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6 Hardware
NR1110B
Figure 6.3-1 MON module
6.3.2 DSP Module (Calculation)

This device should be equipped with 2 DSP modules, which is mainly responsible for logic
(NR1115) and protection (NR1161) calculation.
The BCU-DSP module (NR1115) is resposible for remote and manual closing with synchronism
check. It is fixed at the slot 03.
The PROT-DSP module (NR1161) is fixed at the slot 04. It consists of double high-performance
digital signal processors, 16-digit high-accuracy A/D converter that can perform synchronous
sampling and manage other peripherals. One of double DSP is responsible for protection
calculation, and can fulfill analog data acquisition, protection logic calculation and tripping output.
The other is responsible for fault detector, and can fulfill analog data acquisition, fault detector and
providing power supply to output relay.
If the DSP module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AC AI module. if the module is connected with ECT/EVT, it can receive
real-time synchronous sampled value from merging unit through NET-DSP module.
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6 Hardware
NR1115 NR1161
Figure 6.3-2 DSP module
6.3.3 AC AI Module (AC Analog Input)

AC AI module is applicable for conventional CT/VT. It is assigned to the slots 05-06. However, this
module is not neccesary if the device is used with electronic CT/VT.
For AC AI module, if the plug is not put in the socket, external CT circuit is closed itself as shown
below.
Plug
Socket
In
Out
plug is not put in the socket
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In
Out
Put the plug in the socket
Figure 6.3-3 Schematic diagram of CT circuit automatically closed
Ia1 01 Ia1' 02 U1 01 Un1 02

NR1401
Ib1 03 Ib1' 04 U2 03 Un2 04
Ic1 05 Ic1' 06 U3 05 Un3 06
Ia2 07 Ia2' 08 U4 07 Un4 08
Ib2 09 Ib2' 10 U5 09 Un5 10
Ic2 11 Ic2' 12 U6 11 Un6 12
Ua1 13 Ua1' 14 U7 13 Un7 14
Ub1 15 Ub1' 16 U8 15 Un8 16
Uc1 17 Uc1' 18 U9 17 Un9 18
Ua2 19 Ua2' 20 U10 19 Un10 20
Ub2 21 Ub2' 22 U11 21 Un11 22
Uc2 23 Uc2' 24 U12 23 Un12 24

or
Figure 6.3-4 AI module
NOTICE!
The rated value and the linear range of the input current transformer are optional: 1A or
5A. Please declare the CT rated value and linear range when placing the order. It is
necessary to check whether the current transformer inputs are in accordance with the
demand of practical engineering before putting the device into operation.
NOTICE!
The width of AC AI module is doubled. One AC AI module occupies 2 slots.
 CT Requirement
 Rated primary current Ipn
According to the rated current or maximum load current of primary apparatus.
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 Rated continuous thermal current Icth
According to the maximum load current.
 Rated short-time thermal current Ith and rated dynamic current Idyn
According to the maximum fault current.
 Rated secondary current Isn
 Accuracy limit factor Kalf
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor ()Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)
 Performance verification
Esl > Esl′
Rated secondary limiting e.m.f (volts)

Esl
Esl = kalf×Isn×(Rct+Rbn)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)
IPal Rated accuracy limit primary current (amps)
Rct Current transformer secondary winding resistance. (ohms)
Rated resistance burden (ohms)
Rbn
Rbn=Sbn/Isn2
Sbn Rated burden (VAs)
Required secondary limiting e.m.f (volts)
Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance. (ohms)
Real resistance burden (ohms)
Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)
RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
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6 Hardware
 For example:
 Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)
= 30×5×(1+60/25)=510V
 Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.3.4 DC AI Module (DC Analog Input)

The DC AI module, which can be located at slot No.7~10, is used to receive DC analog input from
transducer which normally indicates temperature, humidity, etc.
The NR1425B provides 6 channels of 20mA/10V inputs. The NR1425C provides 4 channels of
20mA/10V and 2 channels of 220V inputs.
The different input ranges of DC analog input can be selected in using the corresponding jumpers
(short-circuit link) on the module.
Input Range JX1 JX2 JX3
0~20mA OFF OFF ON
0~10V OFF ON OFF
0~220V ON OFF OFF
X = A, B, C, D, E, F
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6 Hardware
01
NR1425 02
+ 03
DC input 1
- 04
05
06
+ 07
DC input 2
- 08
09
10
+ 11
DC input 3
- 12
13
+ 14
DC input 4
- 15
16
+ 17
DC input 5
- 18
19
DC input 6 + 20
- 21
22
Figure 6.3-5 DC AI module
6.3.5 BI Module (Binary Input)

Each binary input is processed by a well-designed debouncing technique to avoid any hazardous
behavior (multiple state changes during a given duration). A separate debouncing and jitter time
may be set for each binary input.
NOTICE!
At least one BI module is obligatory in this device.
 NR1503
Each BI module is with a 22-pin connector for 11 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. Each binary input of NR1503 has independent
negative power input of opto-coupler and can be configurable. NR1503A′s pickup voltage and
dropoff voltage are fixed value, and the range is from 55%Un to 70%Un.
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6 Hardware
BI_01 01
NR1503 Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.3-6 BI module (NR1503)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01,

02, ......). Terminal description for NR1503 is shown as follows.
Terminal No. Symbol Description

01 BI_01 Configurable binary input 1
02 Opto01- Negative supply of configurable binary input 1
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6 Hardware

 NR1504
Each BI module is with a 22-pin connector for 18 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. All binary inputs of NR1504A share one common
negative power input and can be configurable. NR1504A′s pickup voltage and dropoff voltage
are fixed value, and the range is from 55%Un to 70%Un.
Opto+ 01
NR1504 BI_01 02
BI_02 03
BI_03 04
BI_04 05
BI_05 06
BI_06 07
08
BI_07 09
BI_08 10
BI_09 11
BI_10 12
BI_11 13
BI_12 14
15
BI_13 16
BI_14 17
BI_15 18
BI_16 19
BI_17 20
BI_18 21
COM- 22
Figure 6.3-7 BI module (NR1504)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1504 is shown as follows.

01 Opto+ Positive supply of power supply of the module
08 Blank Not used
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6 Hardware

15 Blank Not used
22 COM- Common terminal of negative supply of binary inputs
6.3.6 BO Module (Binary Output)

The BO module, which can be located at slot No.11~15, outputs command for switching control
and signalization. The contacts provided are normally open (abbreviated as NO) contacts and can
be configured for tripping or signal respectively by PCS-Explorer software.
The BO module NR1521 provides 11 output contacts.
01
BO_01
NR1521 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-8 BO module (NR1521)
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6 Hardware
NOTICE!
The following signals should be configured to output contacts controlled by fault

detector:
 Pickup signals of fault detector elements (FD)
 Operation signals of protection elements (Op)
 Start signals of protection elements (St)
 Tripping signals, reclosing signal, AR failure signal, breaker failure signal
NOTICE!
However, the signals which will control the circuit breaker directly or initate breaker
failure protection can be configured to output contacts that are NOT controlled by fault
detector:
 Enable signals of protection elements (On)
 Alarm signals of protection elements (Alm)
 Blocking signals of protection elements (Fail)
 Related signals with voltage switchover and synchrocheck and related signals with
AR except reclosing signal and AR failure signal.
Subtype Controlled by FD NOT controlled by FD

NR1521A All 11 0
NR1521C 0 All 11
NR1521D First 5 Last 6
6.3.7 PWR Module (Device Power Supply)

The PWR module is a DC/DC converter with electrical insulation between its input and output. It
provides DC power supply for the other modules of this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.
NOTICE!
The standard rated voltage of PWR module is self-adaptive to 88~300Vdc. If the input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For a non-standard
rated voltage PWR module, please specify when placing order and check if the rated
voltage is the same before putting the device into service.
NOTICE!
The PWR module provides the pin No.12 and a grounding screw for device grounding.
The pin shall be connected to grounding screw and then connected to the earth copper
bar of panel via dedicated grounding wire. Effective grounding is the most important
Date: 2017-08-17
6 Hardware
measure for a device to prevent EMI, so effective grounding must be ensured before
the device is put into service.
NOTICE!
This device, like almost all electronic equipments, contains electrolytic capacitors.
These capacitors are well known to be subject to deterioration over time if voltage is
not applied periodically. Deterioration can be avoided by powering the device up at
least once a year.
NR1301
5V OK ALM
BO_ALM BO_FAI L
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.3-9 PWR module
The pin definition of the connector fixed on the PWR module is described as below.
Pin No. Sign Description
1 BO_COM1 Common pole 1
2 BO_FAIL Device failure output (01-02, NC)
3 BO_ALM Device alarm output (01-03, NO)
4 BO_COM2 Common pole 2
5 BO_FAIL Device failure output (04-05, NC)
6 BO_ALM Device alarm output (04-06, NO)
7 OPTO+ Positive power supply for BI module (24V)
8 OPTO- Negative power supply for BI module (24V)
9 Empty
10 PWR+ Positive input of device power supply
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6 Hardware
Pin No. Sign Description
11 PWR- Negative input of device power supply
12 GND Device grounded connection
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6 Hardware
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7 Settings
7 Settings
Table of Contents
7 Settings ..............................................................................................7-a
7.1 System Settings .............................................................................................. 7-1
7.1 Protection Settings ......................................................................................... 7-1
7.1.1 FD Settings .......................................................................................................................... 7-2
7.1.2 Direction Settings ................................................................................................................. 7-2
7.1.3 ROC Settings ....................................................................................................................... 7-2
7.1.4 OC Settings .......................................................................................................................... 7-7
7.1.5 BFP Settings ...................................................................................................................... 7-12
7.1.6 PD Settings ........................................................................................................................ 7-12
7.1.7 FreqProt Settings ............................................................................................................... 7-13
7.1.8 VTS/CTS Settings .............................................................................................................. 7-14
7.1.9 Trip Logic Settings ............................................................................................................. 7-15
7.1.10 AR/Syn Settings ............................................................................................................... 7-15
7.2 Measurement and Control Settings ............................................................. 7-18

7.2.1 FUN Settings ...................................................................................................................... 7-19
7.2.2 Syn Settings ....................................................................................................................... 7-22
7.2.3 BI Settings .......................................................................................................................... 7-26
7.2.4 Control Settings ................................................................................................................. 7-26
7.2.5 TP Settings ......................................................................................................................... 7-26
7.2.6 Interlock Settings ............................................................................................................... 7-28
7.2.7 AC Calbr Settings ............................................................................................................... 7-28
7.2.8 Misc Settings ...................................................................................................................... 7-28
7.3 Logic Link Settings ....................................................................................... 7-30

7.3.1 Function Links .................................................................................................................... 7-30
7.3.2 GOOSE Recv Links ........................................................................................................... 7-30
7.3.3 Misc Links ......................................................................................................................... 7-31
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7 Settings
7.4 Device Setup .................................................................................................. 7-31

7.4.1 Device Settings .................................................................................................................. 7-31
7.4.2 Communication Settings .................................................................................................... 7-32
7.4.3 Label Settings .................................................................................................................... 7-41
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7 Settings
NOTICE!
According to different applications for different engineering requirements, settings may

be different.
NOTICE!
"YYYY" in the following tables is the wildcard of bay identification that can be set by the
software PCS-Explorer.
NOTICE!
"BXX" in the following tables signifies the module at the No.XX slot.
7.1 System Settings

Access path: "MainMenu" -> "Settings" -> "System Settings"
No. Item Range Step Remark

1 Active_Grp 1~10 1 Active protection settings group
2 Opt_SysFreq 50Hz or 60Hz Option of system frequency.
The description name of the protected primary
3 PrimaryEquip_Name / /
equipment
4 YYYY.U1n_Prot 0.10~1000.00kV 0.01 Primary rated value of VT for protection
5 YYYY.U2n_Prot 1.000~120.000V 0.001 Secondary rated value of VT for protection
6 YYYY.U1n_Measmt 0.10~1000.00kV 0.01 Primary rated value of VT for measurement
7 YYYY.U2n_Measmt 1.000~120.000V 0.001 Secondary rated value of VT for measurement
8 YYYY.I1n_Prot 100~65500A 1 Primary rated value of CT for protection
9 YYYY.I2n_Prot 1 or 5A Secondary rated value of CT for protection
10 YYYY.I1n_Measmt 10~20000A 1 Primary rated value of CT for measurement
11 YYYY.I2n_Measmt 1~5A 1 Secondary rated value of CT for measurement
12 YYYY.I1n_RCT 10~20000A 1 Primary rated value of neutral CT
13 YYYY.I2n_RCT 1~5A 1 Secondary rated value of neutral CT
14 YYYY.U1n_VT_Syn 0.10~1000.00kV 0.01 Primary rated value of CT for synchronization
15 YYYY.U2n_VT_Syn 0.000~120.000V 0.001 Secondary rated value of CT for synchronization
Frequency upper limit setting
16 f_High_FreqAlm 50~65Hz 1 The device will issue an alarm [Alm_Freq], when
system frequency is higher than the setting.
Frequency lower limit setting
17 f_Low_FreqAlm 40~60Hz 1 The device will issue an alarm [Alm_Freq], when
system frequency is lower than the setting.
7.1 Protection Settings

Access path: "MainMenu" -> "Settings" -> "Prot Settings"
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7 Settings
7.1.1 FD Settings
Current setting of DPFC current fault detector
1 FD.DPFC.I_Set (0.050~30.000)×In 0.001 A
element
Current setting of residual current fault detector
2 FD.ROC.3I0_Set (0.050~30.000)×In 0.001 A
element
Current setting of negative-sequence current fault
3 FD.NOC.I2_Set (0.050~30.000)×In 0.001 A
detector element
fault detector element
4 FD.NOC.En 0 or 1
0: disable
1: enable
7.1.2 Direction Settings

The characteristic angle of directional phase overcurrent
1 RCA_OC 30~89 1 deg
element
The characteristic angle of directional earth fault
2 RCA_ROC 30~89 1 deg
element
The characteristic angle of directional
3 RCA_NegOC 30~89 1 deg
negative-sequence overcurrent element
4 Z0_Comp (0.000~4Unn)/In 0.001 ohm The compensated zero-sequence impedance
5 Z2_Comp (0.000~4Unn)/In 0.001 ohm The compensated negative-sequence impedance
7.1.3 ROC Settings

1 50/51G.K_Hm2 0.000~1.000 0.001
blocking earth fault elements
2 50/51G1.3I0_Set (0.050~30.000)×In 0.001 A
protection
3 50/51G1.t_Op 0.000~20.000 0.001 s
protection
protection
4 50/51G1.En 0 or 1
0: disable
1: enable
0: disable
1: enable
Non_Directional Direction option for stage 1 of earth fault
6 50/51G1.Opt_Dir
Forward protection
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7 Settings

Reverse
7 50/51G1.En_Hm2_Blk 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV earth fault protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
11 50/51G1.TMS 0.010~200.000 0.001
12 50/51G1.tmin 0.050~20.000 0.001 s
13 50/51G1.Alpha 0.010~5.000 0.001 inverse-time characteristic earth fault
protection
14 50/51G1.C 0.000~20.000 0.001 inverse-time characteristic earth fault
protection
15 50/51G1.K 0.050~20.000 0.001 inverse-time characteristic earth fault
protection
16 50/51G2.3I0_Set (0.050~30.000)×In 0.001 A Current setting for stage 2 of earth fault
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7 Settings

protection
17 50/51G2.t_Op 0.000~20.000 0.001 s
protection
18 50/51G2.t_ShortDly 0.000~20.000 0.001 s
protection
protection
19 50/51G2.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non_Directional
protection
Reverse
23 50/51G2.En_Hm2_Blk 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE Option of characteristic curve for stage 2 of
IECST earth fault protection
IECLT
ANSIE
ANSIV
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7 Settings

ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
27 50/51G2.TMS 0.010~200.000 0.001
28 50/51G2.tmin 0.050~20.000 0.001 s
29 50/51G3.3I0_Set (0.050~30.000)×In 0.001 A
protection
30 50/51G3.t_Op 0.000~20.000 0.001 s
protection
31 50/51G3.t_ShortDly 0.000~20.000 0.001 s
protection
protection
32 50/51G3.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non_Directional
protection
Reverse
36 50/51G3.En_Hm2_Blk 0 or 1
0: disable
1: enable
0: disable
1: enable
38 50/51G3.En_CTS_Blk 0 or 1 earth fault protection under CT failure
conditions
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7 Settings

0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
40 50/51G3.TMS 0.010~200.000 0.001
41 50/51G3.tmin 0.050~20.000 0.001 s
42 50/51G4.3I0_Set (0.050~30.000)×In 0.001 A
protection
43 50/51G4.t_Op 0.000~20.000 0.001 s
protection
44 50/51G4.t_ShortDly 0.000~20.000 0.001 s
protection
protection
45 50/51G4.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non_Directional
protection
Reverse
49 50/51G4.En_Hm2_Blk 0 or 1
Date: 2017-08-17
7 Settings

0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
53 50/51G4.TMS 0.010~200.000 0.001
54 50/51G4.tmin 0.050~20.000 0.001 s
7.1.4 OC Settings
1 50/51P.K_Hm2 0.000~1.000 0.001
blocking phase overcurrent elements
2 50/51P1.I_Set (0.050~30.000)×In 0.001 A
3 50/51P1.t_Op 0.000~20.000 0.001 s
protection
4 50/51P1.En 0 or 1
0: disable
1: enable
5 50/51P1.En_BlkAR 0 or 1 Enabling/Disabling auto-reclosing blocked
Date: 2017-08-17
7 Settings

operates
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
8 50/51P1.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
9 50/51P1.Opt_Curve
ANSIV phase overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
10 50/51P1.TMS 0.010~200.000 0.001
11 50/51P1.tmin 0.000~20.000 0.001 s
12 50/51P1.Alpha 0.010~5.000 0.001 inverse-time characteristic phase overcurrent
protection
13 50/51P1.C 0.000~20.000 0.001 inverse-time characteristic phase overcurrent
protection
14 50/51P1.K 0.050~20.000 0.001 inverse-time characteristic phase overcurrent
protection
Date: 2017-08-17
7 Settings

15 50/51P2.I_Set (0.050~30.000)×In 0.001 A
16 50/51P2.t_Op 0.000~20.000 0.001 s
protection
17 50/51P2.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
21 50/51P2.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
23 50/51P2.TMS 0.010~200.000 0.001
24 50/51P2.tmin 0.000~20.000 0.001 s
25 50/51P3.I_Set (0.050~30.000)×In 0.001 A Current setting for stage 3 of phase
Date: 2017-08-17
7 Settings

26 50/51P3.t_Op 0.000~20.000 0.001 s
protection
27 50/51P3.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
31 50/51P3.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
33 50/51P3.TMS 0.010~200.000 0.001
34 50/51P3.tmin 0.000~20.000 0.001 s
35 50/51P4.I_Set (0.050~30.000)×In 0.001 A
Date: 2017-08-17
7 Settings

36 50/51P4.t_Op 0.000~20.000 0.001 s
protection
37 50/51P4.En 0 or 1
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
Non-Directional
Reverse
41 50/51P4.En_Hm2_Blk 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
43 50/51P4.TMS 0.010~200.000 0.001
44 50/51P4.tmin 0.010~20.000 0.001 s
Date: 2017-08-17
7 Settings
7.1.5 BFP Settings

1 50BF.I_Set (0.050~30.000)×In 0.001 A Current setting of phase current criterion for BFP
Current setting of zero-sequence current
2 50BF.3I0_Set (0.050~30.000)×In 0.001 A
criterion for BFP
3 50BF.I2_Set (0.050~30.000)×In 0.001 A
criterion for BFP
4 50BF.t_ReTrp 0.000~10.000 0.001 s Time delay of re-tripping for BFP

Enabling/disabling breaker failure protection
7 50BF.En 0 or 1 0: disable
1: enable
Enabling/disabling re-trip function for BFP
8 50BF.En_ReTrp 0 or 1 0: disable
1: enable
criterion for BFP initiated by single-phase tripping
0: disable
1: enable
0: disable
1: enable
11 50BF.En_I2_3P 0 or 1 contact
0: disable
1: enable
Enabling/disabling breaker failure protection can
be initiated by normally closed contact of circuit
12 50BF.En_CB_Ctrl 0 or 1 breaker
0: disable
1: enable
7.1.6 PD Settings
Current setting of residual current criterion
1 62PD.3I0_Set (0.050~30.000)×In 0.001 A
for pole discrepancy protection
2 62PD.I2_Set (0.050~30.000)×In 0.001 A
criterion for pole discrepancy protection
3 62PD.t_Op 0.000~600.000 0.001 s Time delay of pole discrepancy protection
Enabling/disabling pole discrepancy
protection
4 62PD.En 0 or 1
0: disable
1: enable
Date: 2017-08-17
7 Settings

Enabling/disabling residual current criterion
and negative-sequence current criterion for
5 62PD.En_3I0/I2_Ctrl 0 or 1 pole discrepancy protection
0: disable
1: enable
7.1.7 FreqProt Settings

Frequency pickup setting for
1 81U.f_Pkp 45.000~60.000 0.001 Hz
Blocking voltage setting for
2 81U.U1_Set 0.150Un~1.000Un 0.001 V
Rate of frequency change for blocking
3 81U.df/dt_Blk 0.200~20.000 0.01 Hz/s
Frequency setting for stage 1 of
4 81U.UF1.f_Set 45.000~60.000 0.001 Hz
Time delay for stage 1 of underfrequency
5 81U.UF1.t_Op 0.000~30.000 0.001 s
protection
Enable stage 1 of underfrequency
6 81U.UF1.En 0 or 1
protection
Enable rate of frequency change to block
7 81U.UF1.En_df/dt_Blk 0 or 1
stage 1 of underfrequency protection
8 81U.UF2.f_Set 45.000~60.000 0.001 Hz
9 81U.UF2.t_Op 0.000~30.000 0.001 s
protection
10 81U.UF2.En 0 or 1
protection
12 81U.UF3.f_Set 45.000~60.000 0.001 Hz
13 81U.UF3.t_Op 0.000~30.000 0.001 s
protection
14 81U.UF3.En 0 or 1
protection
16 81U.UF4.f_Set 45.000~60.000 0.001 Hz
17 81U.UF4.t_Op 0.000~30.000 0.001 s
protection
18 81U.UF4.En 0 or 1 Enable stage 4 of underfrequency
Date: 2017-08-17
7 Settings

protection
Frequency pickup setting for
20 81O.f_Pkp 50.000~65.000 0.001 Hz
overfrequency protection
Blocking voltage setting for overfrequency
21 81O.U1_Set 0.150Un~1.000Un 0.001 V
protection
22 81O.OF1.f_Set 50.000~65.000 0.001 Hz
Time delay for stage 1 of overfrequency
23 81O.OF1.t_Op 0.000~20.000 0.001 s
protection
Enable stage 1 of overfrequency
24 81O.OF1.En 0 or 1
protection
25 81O.OF2.f_Set 50.000~65.000 0.001 Hz
26 81O.OF2.t_Op 0.000~20.000 0.001 s
protection
27 81O.OF2.En 0 or 1
protection
28 81O.OF3.f_Set 50.000~65.000 0.001 Hz
29 81O.OF3.t_Op 0.000~20.000 0.001 s
protection
30 81O.OF3.En 0 or 1
protection
31 81O.OF4.f_Set 50.000~65.000 0.001 Hz
32 81O.OF4.t_Op 0.000~20.000 0.001 s
protection
33 81O.OF4.En 0 or 1
protection
7.1.8 VTS/CTS Settings

1 VTS.t_DPU 0.200~100.000 0.001 s Pick-up time delay of VT circuit supervision
2 VTS.t_DDO 0.200~100.000 0.001 s Drop-off time delay of VT circuit supervision
No voltage used for protection calculation
1: enable
3 VTS.En_Out_VT 0 or 1 0: disable
In general, when VT is not connected to the device,
this logic setting should be set as “1”
Voltage selection for protection calculation from
4 VTS.En_LineVT 0 or 1
busbar VT or line VT
Date: 2017-08-17
7 Settings

1: line VT
0: busbar VT
Alarm function of VT circuit supervision
5 VTS.En 0 or 1 1: enable
0: disable
7.1.9 Trip Logic Settings

The dwell time of tripping command, empirical value is 0.04
1 t_Dwell_Trp 0.000~10.000 0.001 s The tripping contact shall drop off under conditions of no
current or protection tripping element drop-off.
7.1.10 AR/Syn Settings

1 79.N_Rcls 1~4 1 Maximum number of reclosing attempts
4 79.t_Dd_3PS2 0.000~600.000 0.001 s Dead time of second shot 3-pole reclosing
5 79.t_Dd_3PS3 0.000~600.000 0.001 s Dead time of third shot 3-pole reclosing
6 79.t_Dd_3PS4 0.000~600.000 0.001 s Dead time of fourth shot 3-pole reclosing
Time delay of circuit breaker in closed position

7 79.t_CBClsd 0.000~600.000 0.001 s
before reclosing
Time delay to wait for CB healthy, and begin to
timing when the input signal [79.CB_Healthy]
8 79.t_CBReady 0.000~600.000 0.001 s
is de-energized and if it is not energized within
this time delay, AR will be blocked.
9 79.t_Wait_Chk 0.000~600.000 0.001 s Maximum wait time for synchronism check
Time delay allow for CB status change to

10 79.t_Fail 0.000~600.000 0.001 s
conform reclosing successful
11 79.t_PW_AR 0.000~600.000 0.001 s Pulse width of AR closing signal
12 79.t_Reclaim 0.000~600.000 0.001 s Reclaim time of AR
Time delay of excessive trip signal to block

13 79.t_PersistTrp 0.000~600.000 0.001 s
auto-reclosing
Drop-off time delay of blocking AR, when
blocking signal for AR disappears, AR
14 79.t_DDO_BlkAR 0.000~600.000 0.001 s
blocking condition drops off after this time
delay
15 79.t_AddDly 0.000~600.000 0.001 s Additional time delay for auto-reclosing

Maximum wait time for reclosing permissive
16 79.t_WaitMaster 0.000~600.000 0.001 s
signal from master AR
Date: 2017-08-17
7 Settings

Time delay of discriminating another fault, and
begin to times after 1-pole AR initiated, 3-pole
17 79.t_SecFault 0.000~600.000 0.001 s AR will be initiated if another fault happens
during this time delay. AR will be blocked if
another fault happens after that.
Enabling/disabling auto-reclosing blocked
when a fault occurs under pole disagreement
18 79.En_PDF_Blk 0 or 1 condition
0: disable
1: enable
Enabling/disabling auto-reclosing with an
additional dead time delay
19 79.En_AddDly 0 or 1
0: disable
1: enable
Enabling/disabling adjust the length of
reclosing pulse
20 79.En_CutPulse 0 or 1
0: disable
1: enable
Enabling/disabling confirm whether AR is
successful by checking CB state
21 79.En_FailCheck 0 or 1
0: disable
1: enable
Enabling/disabling auto-reclosing
22 79.En 0 or 1 0: disable
1: enable
Enabling/disabling AR by external input signal
besides logic setting [79.En]
23 79.En_ExtCtrl 0 or 1
0: only logic setting
1: logic setting and external input signal
Enabling/disabling AR be initiated by open
state of circuit breaker
24 79.En_CBInit 0 or 1
0: disable
1: enable
Option of AR priority
None, High or None: single-breaker arrangement
25 79.Opt_Priority
Low High: master AR of multi-breaker arrangement
Low: slave AR of multi-breaker arrangement
Control option of AR mode
26 79.SetOpt 0 or 1 1: select AR mode by internal logic settings
0: select AR mode by external input signals
1: enable
Date: 2017-08-17
7 Settings

1: enable
Enabling/disabling 1/3-pole AR mode
29 79.En_1P/3PAR 0 or 1 0: disable
1: enable
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
Uab
Ubc
Uca
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
Uab
Ubc
Uca
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
Uab
Ubc
Uca
Ua
Ua: A-phase voltage
Ub
Ub: B-phase voltage
Uc
Uab
Ubc
Uca
34 25.U_Dd 0.05Un~0.8Un 0.001 V Voltage threshold of dead check
35 25.U_Lv 0.5Un~Un 0.001 V Voltage threshold of live check
Compensation coefficient for synchronism

36 25.K_Usyn 0.20-5.00
voltage
Phase difference limit of synchronism check
37 25.phi_Diff 0~ 89 1 Deg
for AR
Compensation for phase difference between
38 25.phi_Comp 0~359 1 Deg
two synchronism voltages
Date: 2017-08-17
7 Settings

Frequency difference limit of synchronism
39 25.f_Diff 0.02~1.00 0.01 Hz
check for AR
Voltage difference limit of synchronism check
40 25.U_Diff 0.02Un~0.8Un V
for AR
Time delay to confirm dead charge check
41 25.t_DdChk 0.010~25.000 s
condition
Time delay to confirm synchronism check
42 25.t_SynChk 0.010~25.000 s
condition
Synchrocheck mode selection
43 25.SetOpt 0 or 1 0: determined by external signal
1: determined by corresponding logic setting
Enabling/disabling frequency difference check
44 25.En_fDiffChk 0 or 1 0: disable
1: enable
Enabling/disabling synchronism check
45 25.En_SynChk 0 or 1 0: disable
1: enable
Enabling/disabling dead reference voltage
and dead synchronism voltage check
46 25.En_DdL_DdB 0 or 1
0: disable
1: enable
Enabling/disabling dead reference voltage
and live synchronism voltage check
47 25.En_DdL_LvB 0 or 1
0: disable
1: enable
Enabling/disabling live reference voltage and
dead synchronism voltage check
48 25.En_LvL_DdB 0 or 1
0: disable
1: enable
Enabling/disabling AR without any check
49 25.En_NoChk 0 or 1 0: disable
1: enable
Enabling/disabling live three-phase check of
line
50 25.En_3PLvChk 0 or 1
0: disable
1: enable
7.2 Measurement and Control Settings

Access path: "MainMenu" -> "Settings" -> "BCU Settings"
Date: 2017-08-17
7 Settings
7.2.1 FUN Settings
No. Name Range Step(Unit)
1 YYYY.Th_ZeroDrift 0.0 ~100.0 0.1(%)
2 YYYY.En_Alm_ROV 0 or 1 1
3 YYYY.UN_Alm_ROV (0~100)×Un 1(%)
4 YYYY.En_Alm_UV 0 or 1 1
5 YYYY.U_Alm_UV (0~100)×Un 1(%)
6 Cur3P.Opt_CT_Measmt 0 or 1 1
7 Vol3P.Opt_UN 0 or 1 1
8 Cur3P.Opt_IN 0 or 1 1
9 YYYY.En_Alm_VTS 0 or 1 1
10 YYYY.En_Alm_CTS 0 or 1 1
11 DPOS.t_Alm 0~60000 1(s)
 YYYY.Th_ZeroDrift
Zero drift threshold to limit the variation influence (of voltage and current) due to temperature
or other environmental factor. Variation less than this setting will be regarded as a zero drift
and ignored.
 YYYY.En_Alm_ROV
Logic link for residual voltage supervision
"1/0": Enable/Disable the alarm function to issue [YYYY.Alm_ROV]
 YYYY.UN_Alm_ROV
This setting is expressed as a percentage for the emission threshold of the alarm
[YYYY.Alm_ROV].
If (
[YYYY.En_Alm_ROV] = 1,
[YYYY.UN_Pri] > [YYYY.UN_Alm_ROV] * [YYYY.U1n_VT_Measmt],
Hold time > 10s
Then [YYYY.Alm_ROV] = 1; /* Issue [YYYY.Alm_ROV] */
If (
[YYYY.Alm_ROV] = 1,
[YYYY.UN_Pri] < [YYYY.UN_Alm_ROV] * [YYYY.U1n_VT_Measmt],
Hold time > 1s
Date: 2017-08-17
7 Settings
Then [YYYY.Alm_ROV] = 0; /* Return [YYYY.Alm_ROV] */
 YYYY.En_Alm_UV
Logic link for under voltage supervision
"1/0": Enable/Disable the alarm function to issue [YYYY.Alm_UV]
 YYYY.U_Alm_UV
This setting is expressed as a percentage for the emission threshold of the alarm
[YYYY.Alm_UV].
If (
[YYYY.En_Alm_UV] = 1,
Ua or Ub or Uc < [YYYY.U_Alm_UV] * [YYYY.U1n_VT_Measmt],
Hold time > 10s,
Then [YYYY.Alm_UV] = 1; /* Issue [YYYY.Alm_UV] */
If (
[YYYY.Alm_UV] = 1,
All Ua&Ub&Uc > [YYYY.U_Alm_UV] * [YYYY.U1n_VT_Measmt],
Hold time > 1s,
Then [YYYY.Alm_ROV] = 0; /* Return [YYYY.Alm_UV] */
 Cur3P.Opt_CT_Measmt
"1": Inputs Ia and Ic are enough for current measurement (i.e.: Ib is unnecessary).
"0": Inputs Ia, Ib & Ic are all necessary for current measurement.
 Vol3P.Opt_UN
If (
[Vol3P.Opt_UN] = 0
[YYYY.UN_Pri] is the voltage input from VT residual (primary value),
[YYYY.UN_Sec] is the voltage input from VT residual (secondary value),
Else if (
Date: 2017-08-17
7 Settings
[Vol3P.Opt_UN] = 1
[YYYY.UN_Pri] = YYYY.Ua_Pri + YYYY.Ub_Pri + YYYY.Uc_Pri;
YYYY.UN_Sec = YYYY.Ua_Sec + YYYY.Ub_Sec + YYYY.Uc_Sec
/* Vector summation */
[YYYY.UN_Pri] access path: "Measurements"->"Measurements3"->"Primary Values".
[YYYY.UN_Sec] access path: "Measurements"->"Measurements3"->"Secondary Values".
 Cur3P.Opt_IN
If (
[Cur3P.Opt_IN] = 0
[YYYY.IN_Pri] is the primary value of the residual current input,
[YYYY.IN_Sec] is the secondary value of the residual current input;
Else if (
[Cur3P.Opt_IN] = 1
[YYYY.IN_Pri] = YYYY.Ia_Pri + YYYY.Ib_Pri + YYYY.Ic_Pri;
YYYY.IN_Sec = YYYY.Ia_Sec + YYYY.Ib_Sec + YYYY.Ic_Sec
/* Vector summation */
[YYYY.IN_Pri] access path: "Measurements"->"Measurements3"->"Primary Values".
[YYYY.IN_Sec] access path: "Measurements"->"Measurements3"->"Secondary Values".
 YYYY.En_CTRevPolarity
"1/0": Enable/Disable reversion of the CT polarity for measurement.
 YYYY.En_Alm_VTS
"1/0": Enable/Disable alarm function of VT circuit supervision.
 YYYY.En_Alm_CTS
"1/0": Enable/Disable alarm function of CT circuit supervision.
 DPOS.t_Alm
Drop off time delay for [DPOS.Alm].
If alarm function for [DPOS**] is enabled, and corresponding NO contact & NC contact are
Date: 2017-08-17
7 Settings
both open or close for the duration which is greater than "[DPOS.t_DPU_**] + [DPOS.t_Alm]",
an alarm signal named [DPOS.Alm] will be issued.
7.2.2 Syn Settings
1 25.Opt_Mode_SynChk 0 or 1 1
2 25.U_UV 1%Un~100%Un 1%(Un)
3 25.U_UH 100%Un~180%Un 1%(Un)
4 25.U_Diff 1%Un~100%Un 1%(Un)
5 25.f_Diff 0.000~3.000 0.001 (Hz)
6 25.df/dt 0.10~5.00 0.01(Hz/s)
7 25.Opt_Mode_DdChk 1~7 1
8 25.En_VTS_Blk_DdChk 0 or 1 1
9 25.En_VTS_Blk_SynChk 0 or 1 1
10 25.t_Reset 5000~300000 1 (ms)
11 25.U_DdChk 1%Un~100%Un 1%(Un)
12 25.U_LvChk 1%Un~100%Un 1%(Un)
13 25.phi_Comp 0~360 1(Deg)
14 25.phi_Diff 0.10~180.00 0.01(Deg)
15 25.t_Close_CB 0~1000 1 (ms)
NoVoltSel, DblBusOneCB,
16 CBConfigMode
3/2BusCB, 3/2TieCB
 25.Opt_Mode_SynChk
Selection of synchro-check mode.
"0" Normal;
"1" The phase difference is fixed at 1 degree for the synchronization check
 25.U_UV
Threshold of under voltage to block CB closing, and it is expressed as a percentage.
If either side of CB voltage for synchronization check is less than this setting, CB closing will
be disabled.
CB closing will be disabled if any of the following events is met:
1) [YYYY.Uab_Pri] or [YYYY.Ubc_Pri] or [YYYY.Uca_Pri] < [25.U_UV_SynChk] *

[YYYY.U1n_VT_Measmt].
2) [YYYY.Uab_Sec] or [YYYY.Ubc_Sec] or [YYYY.Uca_Sec] < [25.U_UV_SynChk] *

Date: 2017-08-17
7 Settings
3) [YYYY.Ua_Pri] or [YYYY.Ub_Pri] or [YYYY.Uc_Pri] < [25.U_UV_SynChk] *

[YYYY.U1n_VT_Measmt]/√3
4) [YYYY.Ua_Sec] or [YYYY.Ub_Sec] or [YYYY.Uc_Sec] < [25.U_UV_SynChk] *

[YYYY.U2n_VT_Measmt]/√3.
5) [YYYY.Usyn_Pri] < [25.U_UV_SynChk] * [YYYY.U1n_VT_Syn].
6) [YYYY.Usyn_Sec] < [25.U_UV_SynChk]*[YYYY.U2n_VT_Syn].
 25.U_UH
Threshold of over voltage to block CB closing, and it is expressed as a percentage.
If either side of CB voltage for synchronization check is more than this setting, CB closing will
be disabled.
CB closing will be disabled if any of the following events is met:
1) [YYYY.Uab_Pri] or [YYYY.Ubc_Pri] or [YYYY.Uca_Pri] > [25.U_UH_SynChk] *

2) [YYYY.Uab_Sec] or [YYYY.Ubc_Sec] or [YYYY.Uca_Sec] > [25.U_UH_SynChk] *

3) [YYYY.Ua_Pri] or [YYYY.Ub_Pri] or [YYYY.Uc_Pri] > [25.U_UH_SynChk] *

[YYYY.U1n_VT_Measmt]/√3
4) [YYYY.Ua_Sec] or [YYYY.Ub_Sec] or [YYYY.Uc_Sec] > [25.U_UH_SynChk] *

[YYYY.U2n_VT_Measmt]/√3.
5) [YYYY.Usyn_Pri] > [25.U_UH_SynChk] * [YYYY.U1n_VT_Syn].
6) [YYYY.Usyn_Sec] > [25.U_UH_SynChk]*[YYYY.U2n_VT_Syn].
 25.U_Diff
Threshold of voltage difference to block CB closing, and it is expressed as a percentage.
If the voltage difference between both sides of the CB for synchronization check is greater
than this setting, CB closing will be disabled.
If [25.Opt_U_SynChk] is configured as phase voltage, CB closing will be disabled if any of the

following events is met:
1) [25.U_Diff_Pri] > [25.U_Diff_SynChk] * [YYYY.U1n_VT_Measmt]/√3.
2) [25.U_Diff_Sec] > [25.U_Diff_SynChk] * [YYYY.U2n_VT_Measmt]/√3.
If [25.Opt_U_SynChk] is configured as phase-to-phase voltage, CB closing will be disabled if

any of the following events is met:
1) [25.U_Diff_Pri] > [25.U_Diff_SynChk] * [YYYY.U1n_VT_Measmt].
2) [25.U_Diff_Sec] > [25.U_Diff_SynChk] * [YYYY.U2n_VT_Measmt].
Date: 2017-08-17
7 Settings
 25.f_Diff
Threshold of frequency difference between both sides of the CB (Δf = |f-fsyn|) for
synchronization check.
If the Δf between both sides of the CB is greater than this setting, CB closing will be disabled.
 25.df/dt
Threshold of df/dt (change rate of frequency difference) between both sides of the CB for
synchronization check.
If the df/dt between both sides of the CB is greater than this setting, CB closing will be
disabled.
 25.Opt_Mode_DdChk
The "Dead check mode" is determined by the setting [25.Opt_Mode_DeadChk].
[25.Opt_Mode_DeadChk] Corresponding dead check criterion
1 Both the incoming side and the reference side adopt dead check.
2 The incoming side adopts live check and the reference side adopts dead check.
3 The incoming side adopts dead check and the reference side adopts live check.
4 The reference side adopts dead check.
5 The incoming side adopts dead check.
The incoming side adopts live check and the reference side adopts dead check.
6 Or:
The incoming side adopts dead check and the reference side adopts live check.
The incoming side adopts live check and the reference side adopts dead check.
Or:
7 The incoming side adopts dead check and the reference side adopts live check.
Or:
Both the incoming side and the reference side adopt dead check.
[25.Opt_Mode_DeadChk] will only be valid when this device is set to work in "dead check
mode".
In the above table, the criterion for dead check is: a voltage will be regarded as dead if it is
less than [25.U_DeadChk]. The criterion for live check is: a voltage will be regarded as live if it
is greater than [25.U_LiveChk].
 25.phi_Diff
Threshold of phase-angle difference between both sides of the CB for synchronization check.
If the phase-angle difference between the 2 voltages on both sides of the CB is greater than
this setting, CB closing will be disabled.
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7 Settings
 25.En_VTS_Blk_DdChk
"1/0": Enable/Disable the block function of dead check mode if there is alarm of VT circuit
failure.
 25.En_VTS_Blk_SynChk
"1/0": Enable/Disable the block function of synchronization check mode if there is alarm of VT
circuit failure.
 25.t_Reset
Duration of synchronization check. The check will not precede any longer out of this range.
 25.U_DdChk
This setting is expressed as a percentage.
In "dead check mode", a voltage will be regarded as dead if it is less than this setting.
 25.U_LvChk
This setting is expressed as a percentage.
In "dead check mode", a voltage will be regarded as live if it is greater than this setting.
 25.phi_Comp
Compensation angle for incoming voltage during synchronization check. The summation of
the reference voltage angle and this setting will be compared with the incoming voltage angle.
1) For voltage adoption from different sides of transformer;
2) For voltage adoption of different phases;
3) Other factors.
 25.t_Close_CB
Closing time of circuit breaker.
It is the time from receiving closing command pulse until the CB is completely closed.
 CBConfigMode
Option of circuit breaker configuration, and it should be set as “NoVoltSel” if no voltage

selection is adopted.
DblBusOneCB: one circuit breaker for double busbar
3/2BusCB: bus side circuit breaker for one and a half breakers
3/2TieCB: line side circuit breaker for one and a half breakers
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7 Settings
7.2.3 BI Settings
1 CSWI**.t_DPU_DPS 0~60000 1 (ms)
2 Bxx.t_DPU_BI_** 0.000~500.000 1 (s)
"DPU" is the abbreviation of "Delay Pick Up". "t_DPU" refers to "debouncing time".
 CSWI**.t_DPU_DPS
In order to prevent the situation that NO contact & NC contact are both opened or closed
during CB/DS/ES operation process, these debouncing time settings should be configured
to be greater than the duration.
"DPOS" indicates the state of double point.
Access path of [DPOS**] is "MainMenu" -> "Status" -> "Inputs" -> "DPS Inputs".
For CB: NO contact refers to 52a contact; NC contact refers to 52b contact;
For DS: NO contact refers to 89a contact; NC contact refers to 89b contact;
For ES: NO contact refers to 57a contact; NC contact refers to 57b contact.
 Bxx.t_DPU_BI_**
In this device, each binary input has an independent debouncing time setting.
The debouncing time (also called delay pickup time) of binary input is the duration for
confirming binary input state, i.e.: if binary input state changes and remains unchanged
during the duration, and then the binary input state will be confirmed by the device.
7.2.4 Control Settings
No. Name Description Range Step(Unit)
The holding time of a normally open contact for opening

1 CSWI**.t_PW_Opn 0~60000 1(ms)
output
The holding time of a normally open contact for closing

2 CSWI**.t_PW_Cls 0~60000 1(ms)
output
7.2.5 TP Settings
1 84.Num_Tap_Pos 0~26 1
2 84.Code_Tap_Pos 0~3 1
3 84.t_DPU_Tap_Pos 0~6000 1(ms)
4 84.En_EmergStop_Tap_Pos 0 or 1 1
5 84.t_EmergStop_Tap_Pos 0~60000 1(ms)
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7 Settings
 84.Num_Tap_Pos
The maximum number of transformer’s tap position, it will take effect only when
[84.Code_Tap_Pos] =3:
 84.Code_Tap_Pos
This is the access mode selection of the tap position of the transformer.
There are 4 modes ("0", "1", "2" and "3") available.
1) "0": No binary inputs will be used for Tap Position Indication (abbreviated as TPI).
2) "1": Binary inputs 15 to 20 will be used as Binary-Coded Decimal code (abbreviated as

BCD) while binary inputs 21 to 40 will not be used.
Binary input 15 is the least significant bit however binary input 20 is the most significant
bit. The first 4 bits are for binary numbers while the 5th bit and the 6th bit represent ten
and twenty respectively.
Some examples are shown as follows:
a) If the transformer tap position is 5, then binary inputs 20 to 15 indicate as "00 0101".
b) If the transformer tap position is 15, then binary inputs 20 to 15 indicate as "01 0101".
c) If the transformer tap position is 25, then binary inputs 20 to 15 indicate as "10 0101".
3) "2": Binary inputs 15 to 24 will be used to indicate "0~9", binary inputs 25, 26 and 27
denote the tap position lower than 10 or between 10 to 19 or over 19 respectively. Binary
inputs 28 to 40 will not be used.
a) If the transformer tap-position is 5, then binary inputs 27 to 15 indicate as

"0010000100000".
b) If the transformer tap-position is 15, then binary inputs 27 to 15 indicate as

"0100000100000".
c) If the transformer tap-position is 25, then binary inputs 27 to 15 indicate as

"1000000100000".
4) "3": Binary inputs 15 to 40 represent tap positions 1 to 26 respectively. Only one binary
input would be set as 1 among binary inputs 15 to 40.
Binary input 15 indicates the lowest tap position of the transformer.
Binary input 40 indicates the highest tap position of the transformer.
a) If binary input 15 is configured as 1 and binary inputs 16 to 40 are all set as 0, it

indicate the tap position is 1.
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7 Settings
b) If binary input 40 is configured as 1 and binary inputs 15 to 39 are all set as 0, it

indicate the tap position is 26.
 84.t_DPU_Tap_Pos
This is the duration for confirming transformer tap position (abbreviated as TP). If TP changes
and remains unchanged for this duration, the TP will be confirmed. Otherwise, the binary
input state will not be confirmed.
 84.En_EmergStop_Tap_Pos
Enable/Disable the function to stop slip of TP immediately. During tap changer control
process, if "slip TP" occurs, the TP will be out of control, and it will step up or down
continuously.
An output contact "BO_EmergStopTP" is provided to issue an emergency stop command to

block the power source of the motor of the TP changer.
 84.t_EmergStop_Tap_Pos
This is used to configure the holding time of output contact "BO_EmergStopTP".
7.2.6 Interlock Settings
1 En_Hardware_Blk Enable/Disable hardware interlocking logic control function 0 or 1 1
Enable/Disable interlocking logic control function of opening

2 CSWI**.En_Opn_Blk 0 or 1 1
output.
Enable/Disable interlocking logic control function of closing

3 CSWI**.En_Cls_Blk 0 or 1 1
output.
7.2.7 AC Calbr Settings

This menu consists of the parameters to adjust the accuracy of AC analog inputs.
NOTICE!
The function is used to maintain this device and has already been configured by the
manufacturer. It is strongly recommended NOT to adjust it.
7.2.8 Misc Settings
No. Name Default Value Range Step(Unit)
1 CBWear.Th_Wear 8000 0~10000 1
2 CBWear.t_Stat 100 10~200 1(ms)
3 CBWear.Ibrk_01 0.0 0.0~1000.0 0.1(kA)
4 CBWear.Ibrk_02 4.0 0.0~1000.0 0.1(kA)
5 CBWear.Ibrk_03 8.0 0.0~1000.0 0.1(kA)
6 CBWear.Ibrk_04 12.0 0.0~1000.0 0.1(kA)
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7 Settings
No. Name Default Value Range Step(Unit)
7 CBWear.Ibrk_04 16.0 0.0~1000.0 0.1(kA)
8 CBWear.Ibrk_04 20.0 0.0~1000.0 0.1(kA)
9 CBWear.Ibrk_04 24.0 0.0~1000.0 0.1(kA)
10 CBWear.Ibrk_04 28.0 0.0~1000.0 0.1(kA)
11 CBWear.Ibrk_04 32.0 0.0~1000.0 0.1(kA)
12 CBWear.Ibrk_04 36.0 0.0~1000.0 0.1(kA)
13 CBWear.Ibrk_04 40.0 0.0~1000.0 0.1(kA)
14 CBWear.Ibrk_04 44.0 0.0~1000.0 0.1(kA)
15 CBWear.Ibrk_04 48.0 0.0~1000.0 0.1(kA)
16 CBWear.Ibrk_04 52.0 0.0~1000.0 0.1(kA)
17 CBWear.Ibrk_04 56.0 0.0~1000.0 0.1(kA)
18 CBWear.Ibrk_04 60.0 0.0~1000.0 0.1(kA)
19 CBWear.Wear_01 0 0~10000 1
20 CBWear.Wear_02 4 0~10000 1
21 CBWear.Wear_03 33 0~10000 1
22 CBWear.Wear_04 92 0~10000 1
23 CBWear.Wear_05 164 0~10000 1
24 CBWear.Wear_06 256 0~10000 1
25 CBWear.Wear_07 369 0~10000 1
26 CBWear.Wear_08 502 0~10000 1
27 CBWear.Wear_09 655 0~10000 1
28 CBWear.Wear_10 829 0~10000 1
29 CBWear.Wear_11 1024 0~10000 1
30 CBWear.Wear_12 1239 0~10000 1
31 CBWear.Wear_13 1475 0~10000 1
32 CBWear.Wear_14 1731 0~10000 1
33 CBWear.Wear_15 2007 0~10000 1
34 CBWear.Wear_16 2304 0~10000 1
 CBWear.Th_Wear
This is the CB wear alarm threshold. If one of the wear statistic status (i.e.: "CBWear.Stat",
"CBWear.Stat_A", "CBWear.Stat_B" and "CBWear.Stat_C") is greater than the threshold, the
alarm will be issued.
 CBWear.t_Stat
This is the CB position changing period (from closing to opening). It should be greater than
the arc-suppression time.
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7 Settings
 CBWear.Ibrk_**
The CB breaking current curve.
These parameters depend on the CB wear table provided by CB manufacturer.
 CBWear.Wear_**
The CB wear curve.
These parameters depend on the CB wear table provided by CB manufacturer.
7.3 Logic Link Settings

The logic link settings are used to determine whether the relevant function of device is enabled or
disabled.
Access path: "MainMenu" -> "Settings" -> "Logic Links"
7.3.1 Function Links
1 Link_BO 0 or 1 1
2 Link_IgnExtIntlck 0 or 1 1
3 25.Link_DdChk 0 or 1 1
4 25.Link_SynChk 0 or 1 1
5 Link_** 0 or 1 1
 Link_BO
Enable/Disable binary output function.
 Link_IgnExtIntlck
Enable/Disable interlock logic from external bay. If this setting is "0", all the interlock logic
from external bay will be considered as satisfied.
 25.Link_DdChk and 25.Link_SynChk
These logic links cooperate to determine Synchronism check mode for CB closing. Please
refer to "Synchronism check (25)" in Chapter 3 for more details.
 Link_**
Enable/Disable the corresponding customized logic link for protection functions.
7.3.2 GOOSE Recv Links
Enable/Disable the GOOSE channel message supervision in

1 GLink_SLRL_** 0 or 1 1
station layer.
2 GLink_PLRL_** Enable/Disable the GOOSE channel message supervision in 0 or 1 1
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7 Settings
process layer.
NOTICE!
These links are aim to avoid issuing disconnection alarms if the relevant GOOSE
channel is empty due to some situations such as remote device is out of service.
7.3.3 Misc Links
No. Name Range Description
1 Link_Spare* 0 or 1 Enable/Disable the corresponding customized logic link for BCU functions.
7.4 Device Setup

Access path: "MainMenu" -> "Settings" -> "Device Setup"
7.4.1 Device Settings
No. Item Range Step(Unit)

Current language
1 Opt_Caption_103 Fixed_Chinese
Fixed_English
2 En_RevCT_Prot 0 or 1 1
3 En_RevCT_Measmt 0 or 1 1
4 Un_BinaryInput 24, 48, 110, 220, 30, 125 (V)
5 En_MDisk 0 or 1 1
 Opt_Caption_103
Select the caption language sent to SAS via IEC 103 protocol.
 En_RevCT_Prot
"1/0": Enable/Disable reversion of the CT polarity for protection.
 En_RevCT_Measmt
"1/0": Enable/Disable reversion of the CT polarity for measurement.
 Un_BinaryInput
This setting is used to set the voltage level of binary input module.
 En_MDisk
1: Use moveable disk to realize the backup and recovery function.
0: Moveable disk will be disabled.
A moveable mdisk is implemented on the MON plug-in module to backup and restore
programs, settings and configurations.
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7 Settings
If MON plug-in module is broken, remove the mdisk and put it into a new MON plug-in
module, use the menu on HMI to restore the backup programs and configurations. If DSP
plug-in module is broken, after a new DSP plug-in module is installed, use the menu on HMI
to restore the backup programs and configurations. If the moveable mdisk is broken, after a
new mdisk is installed on the MON plug-in module, use the menu on HMI to back up the
current programs and configurations into the new mdisk. The default setting is 0
7.4.2 Communication Settings
No. Item Range

1 IP_LAN1 000.000.000.000~255.255.255.255
2 Mask_LAN1 000.000.000.000~255.255.255.255
3 IP_LAN2 000.000.000.000~255.255.255.255
4 Mask_LAN2 000.000.000.000~255.255.255.255
5 En_LAN2 Disable or enable
6 IP_LAN3 000.000.000.000~255.255.255.255
7 Mask_LAN3 000.000.000.000~255.255.255.255
9 IP_LAN4 000.000.000.000~255.255.255.255
10 Mask_LAN4 000.000.000.000~255.255.255.255
12 Gateway 000.000.000.000~255.255.255.255
13 En_Broadcast Disable or enable
14 Addr_RS485A 0~255
15 Baud_RS485A 4800,9600,19200,38400,57600,115200 (bps)
16 Protocol_RS485A IEC103, Modbus, DNP, DLT645, Resv*
17 Addr_RS485B 0~255
18 Baud_RS485B 4800,9600,19200,38400,57600,115200 (bps)
19 Protocol_RS485B IEC103, Modbus, DNP, DLT645, Resv*
20 Threshold_Measmt_Net 0~100%
21 Period_Measmt_Net 0~65535s
22 Format_Measmt 0, 1
23 Cfg_NetPorts_Bond 0, 3, 5, 6, 9, 10, 12
24 Opt_TimeSyn Conventional; SAS; Advanced; NoTImeSyn
25 IP_Server_SNTP 000.000.000.000~255.255.255.255
26 IP_StandbyServer_SNTP 000.000.000.000~255.255.255.255
27 En_Server_SNTP 0 or 1
28 OffsetHour_UTC -12~+12 (hrs)
29 OffsetMinute_UTC 0~60 (min)
30 Opt_Display_Status PriValue, SecValue
31 Num_Cyc_PreTrigDFR 0~140 (cycles)
32 Opt_NetMode STP, PRP, HSR, Resv*
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7 Settings
No. Item Range

33 IEDNAME
34 Opt_DualNetMode_MMS 0, 1 or 2
35 En_DualNet_SL_GOOSE 0 or 1
36 En_ComplexNet_GOOSE 0 or 1
37 En_TCPx_DNP 0 or 1
38 Addr_Slave_TCPx_DNP 0~65519
39 Addr_Master_TCPx_DNP 0~65519
40 IP_Master_TCPx_DNP 000.000.000.000~255.255.255.255
41 Opt_Map_TCPx_DNP 0~4
BISingleBit
42 Obj01DefltVar_TCPx_DNP
BIWithStatus
BIChWoutT
43 Obj02DefltVar_TCPx_DNP BIChWithAbsTime
BIChWithRelTime
AI32Int
AI16Int
44 Obj30DefltVar_TCPx_DNP AI32IntWoutF
AI16IntWoutF
AI32Flt
AI32IntEvWoutT
45 Obj32DefltVar_TCPx_DNP AI16IntEvWoutT
AI32FltEvWoutT
AO32Int
46 Obj40DefltVar_TCPx_DNP AO16Int
AO32Flt
47 t_AppLayer_TCPx_DNP 0~5 (s)
48 t_KeepAlive_TCPx_DNP 0~7200 (s)
49 En_UR_TCPx_DNP 0 or 1
50 Num_URRetry_TCPx_DNP 2~10
51 t_UROfflRetry_TCPx_DNP 1~5000 (s)
52 Class_BI_TCPx_DNP 0~3
53 Class_AI_TCPx_DNP 0~3
54 t_Select_TCPx_DNP 0~240 (s)
55 t_TimeSynIntvl_TCPx_DNP 0~3600 (s)
 IP_LAN1, IP_LAN2, IP_LAN3, IP_LAN4
IP address of Ethernet port 1, 2, 3 and 4.
 Mask_LAN1, Mask_LAN2, Mask_LAN3, Mask_LAN4
Subnet mask of Ethernet port 1, 2, 3 and 4.
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7 Settings
 En_LAN2, En_LAN3, En_LAN4
Enable/Disable Ethernet port 2, Ethernet port 3 and Ethernet port 4 in service.
They are used for Ethernet communication based on the IEC 60870-5-103 protocol. When
the IEC 61850 protocol is applied, the IP address of Ethernet A will be GOOSE source MAC
address.
Ethernet port 1 is always in service by default.
 Gateway
IP address of Gateway (router)
 En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as "1".
Enable/Disable the device to send UDP messages through network
 Addr_RS485A, Addr_RS485B
They are the device′s communication addresses via serial ports (port A and port B).
 Baud_RS485A, Baud_RS485B
Baud rate of rear RS-485 serial port A or B
 Protocol_RS485A, Protocol_RS485B
Communication protocol of rear RS-485 serial port A or B
NOTICE!
Above table listed all the communication settings, the device delivered to the user
maybe only show some settings of them according to the communication interface
configuration. If only the Ethernet ports are applied, the settings about the serial ports
(port A and port B) are not listed in this submenu. And the settings about the Ethernet
ports only listed in this submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined
when ordering). Set the IP address according to actual arrangement of Ethernet
numbers and the un-useful port/ports need not be configured. If PCS-Explorer
configuration tool is connected with this device through the Ethernet, the IP address of
PCS-Explorer must be set as one of the available IP address of this device.
 Threshold_Measmt_Net
This is the threshold to send measurement values to SCADA or gateway through IEC
60870-5-103 or IEC61850 protocol.
 Period_Measmt_Net
This is the timing period for this device to send measurement data to SCADA or gateway
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7 Settings
through IEC 60870-5-103 protocol.
 Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
 Cfg_NetPorts_Bond
Use this setting to set the channel bonding arrangement of two Ethernet ports in station level
communication link.
For redundancy or increased throughput of the communication, dual network structure may
be adopted along with channel bonding technology. These two bonded interfaces, who share
the identical IP address and MAC address, work in Active-Standby mode. If the link via active
interface fails, the link via original standby interface will be activated automatically to ensure a
reliable communication.
The value of this setting represents a 4-bits binary number. Each bit represents a
corresponding Ethernet port's bonding status. Use the following map to decide the specific
setting value. Additionally, the default value "0" means the channel bonding function is
deactivated.
Bonding Bonding Bonding
Ethernet port 1 Ethernet port 2 Ethernet port 1 Ethernet port 3 Ethernet port 1 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 0 1 1 3 0 1 0 1 5 1 0 0 1 9
Bonding Bonding Bonding
Ethernet port 2 Ethernet port 3 Ethernet port 2 Ethernet port 4 Ethernet port 3 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 1 1 0 6 1 0 1 0 10 1 1 0 0 12
Ethernet port 1: Bit0, Ethernet port 2: Bit1, Ethernet port 3: Bit2, Ethernet port 4: Bit3
The Active-Standby mode switching logic is:
Take the device Ethernet ports 1 & 2 for example and assume that P1 is connected to NET1
while P2 is connected to NET2.
 After the device is powered on, only P1 is activated when both NET1 and NET2 are
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7 Settings
normal.
 If NET1 is abnormal, P2 will be activated if NET2 is normal.
 If NET1 is abnormal, P2 cannot be activated if NET2 is also abnormal. The device will
keep trying on P1.
 If P2 is working, the device will maintain this state even if NET1 has been restored to
normal. It will be switched to P1 only if NET2 is abnormal.
 Opt_TimeSyn
There are four options for clock synchronization:
 Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via a configurable binary input
PPS (DIN): Pulse per second (PPS) via a configurable binary input
 SAS
SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
SNTP (BC): Broadcast SNTP mode via Ethernet network
Message (IEC103): Clock messages through IEC103 protocol
 Advanced
IRIG-B (Fiber): IRIG-B via optical-fiber interface
PPS (Fiber): Pulse per second (PPS) via optical-fiber interface
 NoTimeSyn
When no time synchronization signal is connected to the device, please select this
option and the alarm message [Alm_TimeSyn] will not be issued anymore.
"Conventional" mode and "SAS" mode are always supported, but "Advanced" mode is only
supported when NET-DSP module is equipped.
 When "Conventional" mode is selected, if there is no conventional clock synchronization

signal, "SAS" mode will be enabled automatically with the alarm signal [Alm_TimeSyn]
be issued simultaneously.
 When "SAS" is selected, if there is no conventional clock synchronization signal, the

device will not send the alarm signal [Alm_TimeSyn].
 When "Advanced" mode is selected, if there is no conventional clock synchronization

signal connected to NET-DSP module, "SAS" mode will be enabled automatically with
the alarm signal [Alm_TimeSyn] be issued simultaneously.
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7 Settings
 When "NoTimeSyn" mode is selected, the device will not send alarm signals without time
synchronization signal. However, the device can still be synchronized when receiving
time synchronization signal.
 IP_Server_SNTP
This is the address of the SNTP time synchronization server which sends SNTP timing
messages to the device.
 IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000",

the device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000",

the device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server
address and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast
SNTP synchronization message. If the device does not receive any server response after 30s,
it adopts the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast
SNTP synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly

if it does not receive any server response in 30s.
 OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted, the time tags of communication message are required
according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the
GMT (Greenwich Mean Time) zone; for example, if the device is applied in China, the time
zone of China is east 8th time zone, so this setting will be "8".
The setting [OffsetMinute_UTC] is used to set the minute offset of the current time zone to
the GMT zone.
Time zone GMT zone East 1st East 2nd East 3rd East 4th East 5th
Setting 0 1 2 3 4 5
Time zone East 6th East 7th East 8th East 9th East 10th East 11th
Setting 6 7 8 9 10 11
Time zone East/West 12th West 1st West 2nd West 3rd West 4th West 5th
Setting 12/-12 -1 -2 -3 -4 -5
Time zone West 6th West 7th West 8th West 9th West 10th West 11th
Setting -6 -7 -8 -9 -10 -11
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7 Settings
 Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value
or secondary value. The sampled values of current and voltage are displayed as secondary
value by default. When it is set as primary value, both secondary voltage and secondary
current are converted into primary voltage and primary current according to rated secondary
and primary value of VT and CT respectively.
 Num_Cyc_PreTrigDFR
The setting is used to set the cycle number recorded by the device before the trigger element
operating.
 Opt_NetMode
This setting is used to select network mode.
STP: Spanning Tree Protocol
PRP: Parallel Redundancy Protocol
HSR: High-availability Seamless Redundancy
Resv: Reserved
During the device initialization, the network mode is checked. If the actual network mode is
different with the setting, the alarm "Alm_Version" will be issued. When actual network mode
is correct, please modify the setting to the correct value. When actual network mode is wrong,
please modify the setting as “Resv” firstly and then modify the setting to the correct value.
NOTICE!
The adoption of moveable disk is obligatory for this setting.
 IEDNAME
IED name of this device. If this setting is modified, the IED name in ".cid" file will be changed
simultaneously and vice versa.
 Opt_DualNetMode_MMS
0: Single network;
1: Hot standby mode (always two ports in service);
2: Cold standby mode (only one port in service);
 En_DualNet_SL_GOOSE
Enable/Disable dual GOOSE network for station layer.
 En_ComplexNet_GOOSE
Enable/Disable mixed GOOSE network (especially for the condition that certain IEDs adopt
single network while others adopt dual network) for process layer.
Date: 2017-08-17
7 Settings
 En_TCP*_DNP
The logic setting is used to enable or disable network No.* DNP client. (x=1, 2, 3, 4)
1: enable
0: disable
When network No.* DNP client is not configured to be in service by PCS-Explorer, DNP client
settings corresponding to network No.* will be hidden.
 Addr_Slave_TCP*_DNP
It is the slave address of network No.* DNP client.
 Addr_Master_TCP*_DNP
It is the master address of network No.* DNP client.
 IP_Master_TCP*_DNP
It is the IP address of network No.* DNP client.
 Opt_Map_TCP*_DNP
It is the communication map number of network No.* DNP client.
 Obj01DefltVar_TCP*_DNP
It is the “OBJ1” default variation of network No.* DNP client.
BISingleBit: Binary Input format is packed with single bit
BIWithStatus: Binary Input with status flag
BIChWoutT: Binary Input Event without time-of-occurrence
BIChWithAbsTime: Binary Input Event with absolute time-of-occurrence
BIChWithRelTime: Binary Input Event with relative time-of-occurrence
AI32Int: Analog Input with a flag octet and a 32-bit, signed integer value
AI16Int: Analog Input with a flag octet and a 16-bit, signed integer value
AI32IntWoutF: Analog Input with a 32-bit, signed integer value (but without flags)
AI16IntWoutF: Analog Input with a 16-bit, signed integer value (but without flags)
AI32Flt: Analog Input with a flag octet and a single-precision, floating-point value
Date: 2017-08-17
7 Settings
AI32IntEvWoutT: Analog Input Event with a flag octet and a 32-bit, signed integer value (but
without time-of-occurence)
AI16IntEvWoutT: Analog Input Event with a flag octet and a 16-bit, signed integer value (but
without time-of-occurence)
AI32FltEvWoutT: Analog Input Event with single-precision, floating-point value (but without
time-of-occurence)
AO32Int: Analog Output with a flag octet and a 32-bit, signed integer value
AO16Int: Analog Output with a flag octet and a 16-bit, signed integer value
AO32Flt: Analog Output with a flag octet and a single-precision, floating-point value
 t_AppLayer_TCP*_DNP
It is the timeout of application layer of network No.* DNP client.
 t_KeepAlive_TCP*_DNP
It is the heartbeat time interval of network No.* DNP client.
 En_UR_TCP*_DNP
The logic setting is used to enable or disable the unsolicited message function of network
No.* DNP client.
1: enable
0: disable
 Num_URRetry_TCP*_DNP
It is the online retransmission number of the unsolicited message of network No.* DNP client.
(x=1, 2, 3, 4)
 t_UROfflRetry_TCP*_DNP
It is the offline timeout of the unsolicited message of network No.* DNP client.
 Class_BI_TCP*_DNP
It is the class level of the “Binary Input” of network No.* DNP client.
 Class_AI_TCP*_DNP
It is the class level of the “Analog Input” of network No.* DNP client.
Date: 2017-08-17
7 Settings
 t_Select_TCP*_DNP
It is the selection timeout of network No.* DNP client.
 t_TimeSynIntvl_TCP*_DNP
It is the time interval of the time synchronization function of network No.* DNP client.
7.4.3 Label Settings

The description name of GOOSE link (station level). It will affect the
BXX.Name_SL_**_GCommLink
displayed GOOSE link name in "GOOSE Superv" and other signals.
Date: 2017-08-17
7 Settings
Date: 2017-08-17
Table of Contents
8 Human Machine Interface .................................................................8-a
8.1 Overview .......................................................................................................... 8-1
8.1.1 Design .................................................................................................................................. 8-1
8.1.2 Keypad ................................................................................................................................. 8-1
8.1.3 LED Indicators...................................................................................................................... 8-2
8.1.4 Debugging Port .................................................................................................................... 8-3
8.1.5 Ethernet Port Setup ............................................................................................................. 8-3
8.2 Menu Tree ........................................................................................................ 8-4

8.2.1 Main Menu ........................................................................................................................... 8-4
8.2.2 Measurements ..................................................................................................................... 8-5
8.2.3 Status ................................................................................................................................. 8-12
8.2.4 Records .............................................................................................................................. 8-15
8.2.5 Settings .............................................................................................................................. 8-16
8.2.6 Local Cmd .......................................................................................................................... 8-18
8.2.7 Information ......................................................................................................................... 8-18
8.2.8 Test ..................................................................................................................................... 8-19
8.2.9 Clock .................................................................................................................................. 8-21
8.2.10 Language ......................................................................................................................... 8-21
8.3 LCD Display ................................................................................................... 8-21

8.3.1 Overview ............................................................................................................................ 8-21
8.3.2 Normal Display without SLD .............................................................................................. 8-22
8.3.3 Normal Display with SLD ................................................................................................... 8-23
8.3.4 Event Display ..................................................................................................................... 8-24
8.4 Keypad Operation ......................................................................................... 8-26

8.4.1 View Device Measurements .............................................................................................. 8-26
8.4.2 View Device Status ............................................................................................................ 8-26
Date: 2017-08-17
8.4.3 View Device Records ......................................................................................................... 8-26
8.4.4 View Device Setting ........................................................................................................... 8-27
8.4.5 Modify Device Setting ........................................................................................................ 8-28
8.4.6 Copy Device Setting .......................................................................................................... 8-29
8.4.7 Switch Setting Group ......................................................................................................... 8-30
8.4.8 Delete Device Records ...................................................................................................... 8-31
8.4.9 Remote Control .................................................................................................................. 8-31
8.4.10 Modify Device Clock ........................................................................................................ 8-32
8.4.11 View Module Information .................................................................................................. 8-33
8.4.12 Check Software Version................................................................................................... 8-33
8.4.13 Communication Test ........................................................................................................ 8-34
8.4.14 Select Language .............................................................................................................. 8-34
List of Figures
Figure 8.2-1 Main menu example (LCD 320×240) .................................................................... 8-4
Figure 8.2-2 Menu structure ....................................................................................................... 8-5
Figure 8.3-1 Normal display without SLD............................................................................... 8-22
Figure 8.3-2 Normal display with SLD .................................................................................... 8-23
Figure 8.3-3 Password for control operation on SLD ........................................................... 8-24
Figure 8.3-4 LCD display of supervision events.................................................................... 8-25
Figure 8.3-5 LCD display of IO events .................................................................................... 8-25
Figure 8.4-1 LCD display of "Device Logs"............................................................................ 8-27
Figure 8.4-2 Password to modify settings ............................................................................. 8-29
Figure 8.4-3 Confirmation to delete records .......................................................................... 8-31
Figure 8.4-4 Modification of device time ................................................................................ 8-33
Figure 8.4-5 Selection of display language ............................................................................ 8-35
List of Tables
Table 8.2-1 Menu description of "Measurements" .................................................................. 8-5
Table 8.2-2 Item description of "Measurements1" .................................................................. 8-6
Date: 2017-08-17
Table 8.2-3 Item description of "Measurements2" .................................................................. 8-7
Table 8.2-4 Menu description of "Measurements3" .................................................................... 8-7
Table 8.2-5 Item description of "Primary Values" .................................................................... 8-7
Table 8.2-6 Item description of "Secodnary Values" ............................................................... 8-8
Table 8.2-7 Item description of "Phase Angle" ...................................................................... 8-10
Table 8.2-8 Item description of "Primary Power" .................................................................. 8-10
Table 8.2-9 Item description of "Secondary Power" ............................................................. 8-10
Table 8.2-10 Item description of "Harmonics" ....................................................................... 8-11
Table 8.2-11 Item description of "Synchrocheck" ................................................................. 8-11
Table 8.2-12 Menu description of "Status" ............................................................................. 8-12
Table 8.2-13 Menu description of "Inputs" ............................................................................. 8-13
Table 8.2-14 Item description of "Contact Inputs"................................................................. 8-13
Table 8.2-15 Item description of "Tap Position" .................................................................... 8-13
Table 8.2-16 Item description of "DPS Inputs"....................................................................... 8-13
Table 8.2-17 Menu description of "Outputs" .......................................................................... 8-13
Table 8.2-18 Item description of "Contact Outputs".............................................................. 8-14
Table 8.2-19 Item description of "Interlock Status" ............................................................... 8-14
Table 8.2-20 Item description of "Trip Counter" .................................................................... 8-14
Table 8.2-21 Item description of "CBWear" ............................................................................ 8-14
Table 8.2-22 Menu description of "Superv Stat" .................................................................... 8-14
Table 8.2-23 Menu description of "Logic Links State" .......................................................... 8-15
Table 8.2-24 Menu description of "Records" ......................................................................... 8-15
Table 8.2-25 Menu description of "Settings" ......................................................................... 8-16
Table 8.2-26 Menu description of "Prot Settings" ................................................................. 8-16
Table 8.2-27 Menu description of "BCU Settings"................................................................. 8-17
Table 8.2-28 Menu description of "Logic Links".................................................................... 8-17
Table 8.2-29 Menu description of "Device Setup" ................................................................. 8-17
Table 8.2-30 Menu description of "Local Cmd" ..................................................................... 8-18
Table 8.2-31 Menu description of "Information" .................................................................... 8-18
Table 8.2-32 Menu description of "Test"................................................................................. 8-20
PCS-9705 Bay Control & Protection Unit 8-c
Date: 2017-08-17
Table 8.2-33 Item description of "MMS Comm Counter" ...................................................... 8-20
Table 8.2-34 Item description of "GOOSE Comm Counter" ................................................. 8-20
Table 8.2-35 Menu description of "Device Test" .................................................................... 8-20
Table 8.2-36 Item description of "AR Counter"...................................................................... 8-21
Table 8.2-37 Menu description of "HMI Setup" ...................................................................... 8-21
Table 8.4-1 Available device logs ............................................................................................ 8-27
8-d PCS-9705 Bay Control & Protection Unit
Date: 2017-08-17
8.1 Overview
Operator can access this device from the HMI panel. Local communication with the device is
possible in using a computer via the multiplex RJ-45 debugging port. Furthermore, remote
communication is also possible in using the SAS via communication ports in the MON module.
This chapter describes the human machine interface (HMI), and gives operator an instruction
about how to display or print event report, setting and so on through menu tree and display
metering value, including r.m.s. current, voltage, frequency, etc. through LCD. Procedure to
change active setting group or a settable parameter value through keypad is also described in
detail.
8.1.1 Design
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate an LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.

A 320×240 (full width chassis) or 240×128 (half width chassis) dot matrix
backlight LCD display is visible in dim lighting conditions. The
1 LCD
corresponding messages are displayed when there is any operation
implemented.
20 status indication LEDs, 2 LEDs are fixed as the signals of "HEALTHY"
2 LED (green) and "ALARM" (yellow), 18 LEDs are configurable with selectable
color among green, yellow and red.
3 Keypad Navigation keypad and command keys for full access to device.
4 Communication port A multiplex RJ-45 port for debugging.
8.1.2 Keypad
FUN
ENT
ESC
 "ESC"
 Cancel the operation
 Quit the current menu
 "ENT"
 Execute the operation
 Confirm the interface
Date: 2017-08-17
 "FUN"
 Switch the activating protection setting group
 "◄" and "►"
 Move the cursor horizontally
 Enter the next menu or return to the previous menu
 "▲" and "▼"
 Move the cursor vertically
 Select command menu within the same level of menu
 "＋" and "－"
 Modify the value
 Modify and display the message number
 Page up/down
8.1.3 LED Indicators
01 HEALTHY 11
02 ALARM 12
03 13
04 14
05 15
06 16
07 17
08 18
09 19
10 20
A brief explanation has been made as bellow.
LED Display Description
Off Device is out of service or any hardware error is defected during self-check.
HEALTHY
Steady Green Device is in service and ready for operating.
Off Device is in normal operating condition.

ALARM
Steady Yellow VT circuit failure, CT circuit failure or other abnormal alarm is issued.
"HEALTHY" LED can only be turned on by energizing the device and no abnormality detected.
"ALARM" LED is turned on as long as alarm exists. When all alarm signals disappear, it will be
turned off.
Date: 2017-08-17
Other 18 LED indicators with no labels are configurable and user can configure them to be lit by
signals of operation element, alarm element and binary output contact according to requirement
through PCS-Explorer software. These 18 LEDs are configurable with selectable color among
green, yellow and red.
All the 20 LED indicators refresh every 30s if there is no change of status.
8.1.4 Debugging Port

There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair Ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
P2
P1
P3
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair Ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Device side Computer side

No. Core color Function
(Left) (Right)
1 Orange & white TX+ of the ethernet port P1-1 P2-1
2 Orange TX- of the ethernet port P1-2 P2-2
3 Green & white RX+ of the ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the ethernet port P1-6 P2-6
7 Blue & white The ground connection of the RS-232 P1-7
P3-5
8 Brown port. P1-8
8.1.5 Ethernet Port Setup

MON plug-in module is equipped with several Ethernet port. The Ethernet port can be used to
communication with PC via auxiliary software PCS-Explorer or SAS, so as to fulfill on-line
configuration and debugging function. The IP address and subnet mask settings of the
corresponding Ethernet port locate in the menu "Settings -> Device Setup -> Comm Settings".
It should be ensured that the device and PC are in the same network segment.
Date: 2017-08-17
E.g.: PC: IP address "198.87.96.102", subnet mask "255.255.255.0".
The IP address and subnet mask of the device Ethernet port 1 (if connected) should be [IP_LAN1]
= 198.87.96.***, [Mask_LAN1] =255.255.255.0. (*** can be any value from 0 to 255 except 102)
For using a Ethernet port, the corresponding logic setting [En_LANx] (x = 2, 3, 4, etc.) must be "1".
8.2 Menu Tree

NOTICE!
According to different applications in different engineering requirements, the display of

menu in HMI may be different.
"YYYY" is the function name substitution for bay identification such as "BayMMXU",
"Bus1_MMXU", "Bay1_MMXU", "Sum_MMXU", etc.
"BXX" in the following tables signifies the module at the No.XX slot.
8.2.1 Main Menu

Press "▲" of any running interface and enter the main menu. Select different submenu by "▲"
and "▼". Enter the selected submenu by pressing "ENT" or "►". Press "◄" and return to the
previous menu. Press "ESC" back to main menu directly.
Press "▲" to enter the main menu with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Local Cmd
Information
Test
Clock
Language
Figure 8.2-1 Main menu example (LCD 320×240)
Date: 2017-08-17
Main Menu
Measurements
Status
Records
Settings
Local Cmd
Information
Test
Clock
Language
Figure 8.2-2 Menu structure
8.2.2 Measurements
Main Menu
Measurements
Measurements1
Measurements2
Measurements3
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the device′s status. This
menu comprises following submenus.
Table 8.2-1 Menu description of "Measurements"
No. Item Function description
1 Measurements1 Display measured values from protection calculation DSP
2 Measurements2 Display measured values from fault detector DSP
Display measured values and other calculated quantities for measurement

3 Measurements3
and control
Date: 2017-08-17
Table 8.2-2 Item description of "Measurements1"
No. Symbol Definition Resolution Unit
1 Ia The secondary value of phase-A current 0.000 A
2 Ib The secondary value of phase-B current 0.000 A
3 Ic The secondary value of phase-C current 0.000 A
4 I1 The secondary value of positive-sequence current 0.000 A
5 I2 The secondary value of negative-sequence current 0.000 A
6 3I0 The secondary value of calculated residual current 0.000 A
7 Ua The secondary value of phase-A protection voltage 0.000 V
8 Ub The secondary value of phase-B protection voltage 0.000 V
9 Uc The secondary value of phase-C protection voltage 0.000 V
10 Uab The secondary value of phase-AB protection voltage 0.000 V
11 Ubc The secondary value of phase-BC protection voltage 0.000 V
12 Uca The secondary value of phase-CA protection voltage 0.000 V
13 U1 The secondary value of positive-sequence voltage 0.000 V
14 U2 The secondary value of negative-sequence voltage 0.000 V
15 3U0 The secondary value of calculated residual voltage 0.000 V
16 UB1.Usyn The secondary value of synchronism voltage (bus 1) 0.000 V
17 UL2.Usyn The secondary value of synchronism voltage (line 2) 0.000 V
18 UB2.Usyn The secondary value of synchronism voltage (bus 2) 0.000 V
19 Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage 0 Deg
20 Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage 0 Deg
21 Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage 0 Deg
22 Ang (Ua-Ia) Phase angle between phase-A voltage and phase-A current 0 Deg
23 Ang (Ub-Ib) Phase angle between phase-B voltage and phase-B current 0 Deg
24 Ang (Uc-Ic) Phase angle between phase-C voltage and phase-C current 0 Deg
25 Ang (Ia-Ib) Phase angle between phase-A current and phase-B current 0 Deg
26 Ang (Ib-Ic) Phase angle between phase-B current and phase-C current 0 Deg
27 Ang (Ic-Ia) Phase angle between phase-C current and phase-A current 0 Deg
28 f Frequency of protection voltage 0.000 Hz
29 f_Ref Frequency of line synchronism voltage 0.000 Hz
30 f_Syn Frequency of bus synchronism voltage 0.000 Hz
31 f_Diff Frequency difference between line and bus voltages 0.000 Hz
32 phi_Diff Phase angle difference between line and bus voltages 0 V
33 U_Diff Voltage difference between line and bus voltages 0.000 V
Date: 2017-08-17
Table 8.2-3 Item description of "Measurements2"
No. Symbol Definition Resolution Unit
1 Ia The secondary value of phase-A current 0.000 A
2 Ib The secondary value of phase-B current 0.000 A
3 Ic The secondary value of phase-C current 0.000 A
Table 8.2-4 Menu description of "Measurements3"
No. Sign Description
1 Primary Values Display calculated primary values of AC analog input.
2 Secondary Values Display sampled secondary values of AC analog input.
3 Phase Angle Display calculated phase angles.
4 Primary Power Display calculated primary energy power.
5 Secondary Power Display calculated secondary energy power.
6 Harmonics Display sampled voltage harmonics (up to 15th).
7 Synchrocheck Display calculated relevant values for CB closing synchronization check.
Table 8.2-5 Item description of "Primary Values"
No. Sign Description Resolution Unit
1 YYYY.Ia_Pri
2 YYYY.Ib_Pri The primary values of three-phases currents. 0.00 A
3 YYYY.Ic_Pri
The primary value of residual current.

If [Cur3P.Opt_IN] =0, it is the residual current
input.
If [Cur3P.Opt_IN] =1, it is the residual current
4 YYYY.IN_Pri 0.00 A
calculated by the vector summation of
YYYY.Ia_Pri, YYYY.Ib_Pri and YYYY.Ic_Pri.
Access path of [Cur3P.Opt_IN]: "MainMenu" ->
"Settings" -> "BCU Settings" -> "FUN Settings".
5 YYYY.Ua_Pri
6 YYYY.Ub_Pri The primary values of three-phases voltages. 0.00 kV
7 YYYY.Uc_Pri
8 YYYY.U1_Pri The primary value of positive-sequence voltage. 0.00 kV
9 YYYY.U2_Pri The primary value of negative-sequence voltage. 0.00 kV
The primary value of residual voltage.

If [Vol3P.Opt_UN] =0, it is the residual voltage
10 YYYY.UN_Pri input. 0.00 kV

calculated by the vector summation of
Date: 2017-08-17
YYYY.Ua_Pri, YYYY.Ub_Pri and YYYY.Uc_Pri.

Access path of [Vol3P.Opt_UN]:: "MainMenu" ->
11 YYYY.Uab_Pri
12 YYYY.Ubc_Pri The primary values of phase-to-phase voltages. 0.00 kV
13 YYYY.Uca_Pri
14 YYYY.f System frequency 0.000 Hz
15 YYYY.P_Pri The primary value of active power. 0.00 MW
16 YYYY.Q_Pri The primary value of reactive power. 0.00 MVar
17 YYYY.S_Pri The primary value of apparent power. 0.00 MVA
18 YYYY.Cos Power factor. 0.000
The primary value of bus 1 voltage for

19 RSYN.UB1_Pri 0.00 kV
synchronism check.
The frequency of bus 1 voltage for synchronism

20 RSYN.UB1_f 0.000 Hz
check.
The primary value of line 1 voltage for

21 RSYN.UL1_Pri 0.00 kV
synchronism check.
The frequency of line 1 voltage for synchronism

22 RSYN.UL1_f 0.000 Hz
check.
The primary value of line 2 voltage for

23 RSYN.UL2_Pri 0.00 kV
synchronism check.

check.
The primary value of bus 2 voltage for

25 RSYN.UB2_Pri 0.00 kV
synchronism check.

check.
Table 8.2-6 Item description of "Secodnary Values"
1 YYYY.Ia_Sec
2 YYYY.Ib_Sec The secondary values of three-phases currents. 0.00 A
3 YYYY.Ic_Sec
The secondary value of residual current.

If [Cur3P.Opt_IN] =0, it is the residual current input.
4 YYYY.IN_Sec If [Cur3P.Opt_IN] =1, it is the residual current 0.00 A

calculated by the vector summation of YYYY.Ia_Sec,
YYYY.Ib_Sec and YYYY.Ic_Sec.
Date: 2017-08-17
Access path of [Cur3P.Opt_IN]: "MainMenu" ->

5 YYYY.Ua_Sec
6 YYYY.Ub_Sec The secondary values of three-phases voltages. 0.00 V
7 YYYY.Uc_Sec
8 YYYY.U1_Sec The secondary value of positive-sequence voltage. 0.00 V
9 YYYY.U2_Sec The secondary value of negative-sequence voltage. 0.00 V
The secondary value of residual voltage.

If [Vol3P.Opt_UN] =0, it is the residual voltage input.
10 YYYY.UN_Sec calculated by the vector summation of 0.00 V

YYYY.Ua_Sec, YYYY.Ub_Sec and YYYY.Uc_Sec.
Access path of [Vol3P.Opt_UN]:: "MainMenu" ->
11 YYYY.Uab_Sec
12 YYYY.Ubc_Sec The secondary values of phase-to-phase voltages. 0.00 V
13 YYYY.Uca_Sec
14 YYYY.f System frequency 0.000 Hz
15 YYYY.P_Sec The secondary value of active power. 0.00 W
16 YYYY.Q_Sec The secondary value of reactive power. 0.00 Var
17 YYYY.S_Sec The secondary value of apparent power. 0.00 VA
18 YYYY.Cos Power factor. 0.000
The secondary value of bus 1 voltage for

19 RSYN.UB1_Sec 0.00 V
synchronism check.

check.
The secondary value of line 1 voltage for

21 RSYN.UL1_Sec 0.00 V
synchronism check.

check.
The secondary value of line 2 voltage for

23 RSYN.UL2_Sec 0.00 V
synchronism check.

check.
The secondary value of bus 2 voltage for

25 RSYN.UB2_Sec 0.00 V
synchronism check.

check.
Date: 2017-08-17
Table 8.2-7 Item description of "Phase Angle"
Phase angle between phase-A and phase-B

1 YYYY.Ang (Ua-Ub) 0 Deg
voltages
Phase angle between phase-B and phase-C

2 YYYY.Ang (Ub-Uc) 0 Deg
voltages
Phase angle between phase-C and phase-A

3 YYYY.Ang (Uc-Ua) 0 Deg
voltages
Phase angle between phase-A voltage and

4 YYYY.Ang (Ua-Ia) 0 Deg
phase-A current
Phase angle between phase-B voltage and

5 YYYY.Ang (Ub-Ib) 0 Deg
phase-B current
Phase angle between phase-C voltage and

6 YYYY.Ang (Uc-Ic) 0 Deg
phase-C current
Table 8.2-8 Item description of "Primary Power"
1 YYYY.Pa_Pri
2 YYYY.Pb_Pri The primary values of three-phases active powers. 0.00 MW
3 YYYY.Pc_Pri
4 YYYY.Qa_Pri
5 YYYY.Qb_Pri The primary values of three-phases reactive powers. 0.00 MVar
6 YYYY.Qc_Pri
7 YYYY.Sa_Pri
The primary values of three-phases apparent
8 YYYY.Sb_Pri 0.00 MVA
powers.
9 YYYY.Sc_Pri
10 YYYY.Cosa
11 YYYY.Cosb Three-phases power factors. 0.000
12 YYYY.Cosc
13 YYYY.P_Pri The primary value of active power. 0.00 MW
14 YYYY.Q_Pri The primary value of reactive power. 0.00 MVar
15 YYYY.S_Pri The primary value of apparent power. 0.00 MVA
16 YYYY.Cos Power factor 0.000
Table 8.2-9 Item description of "Secondary Power"
1 YYYY.Pa_Sec The secondary values of three-phases active

0.00 W
2 YYYY.Pb_Sec powers.
Date: 2017-08-17
3 YYYY.Pc_Sec
4 YYYY.Qa_Sec
The secondary values of three-phases reactive
5 YYYY.Qb_Sec 0.00 Var
powers.
6 YYYY.Qc_Sec
7 YYYY.Sa_Sec
The secondary values of three-phases apparent
8 YYYY.Sb_Sec 0.00 VA
powers.
9 YYYY.Sc_Sec
10 YYYY.Cosa
11 YYYY.Cosb Three-phases power factors. 0.000
12 YYYY.Cosc
13 YYYY.P_Sec The secondary value of active power. 0.00 W
14 YYYY.Q_Sec The secondary value of reactive power. 0.00 Var
15 YYYY.S_Sec The secondary value of apparent power. 0.00 VA
16 YYYY.Cos Power factor 0.000
Table 8.2-10 Item description of "Harmonics"
The secondary value of the 1st~15th voltage

1 YYYY.U_Hm**_Sec 0.00 V
harmonic
2 YYYY.U_Hm**_Pri The primary value of the 1st~15th voltage harmonic 0.00 kV
Table 8.2-11 Item description of "Synchrocheck"
The frequency difference between reference side

1 YYYY.25.f_Diff 0.000 Hz
and incoming side for CB synchronism check.
The df/dt difference between reference side and

2 YYYY.25.df/dt 0.000 Hz/s
incoming side for CB synchronism check.
Phase-angle difference between reference side and

3 YYYY.25.phi_Diff 0.00 Deg
incoming side for CB synchronism check.
The secondary voltage difference between
4 YYYY.25.U_Diff reference side and incoming side for CB 0.000 V

synchronism check.
The voltage difference percentage between
5 YYYY.25.Pcnt_U_Diff reference side and incoming side for CB 0.000 %

synchronism check.
Date: 2017-08-17
8.2.3 Status
Main Menu
Status
Inputs
Contact Inputs
GOOSE Inputs
Tap Position
DPS Inputs
Outputs
Contact Outputs
Interlock Status
Trip Counter
CBWear
Superv State
Prot Superv
GOOSE Superv
BCU Superv
Logic Links State
BCU Links
GOOSE Recv Links
This menu is used to display real-time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the device′s status. This menu comprises following
submenus.
Table 8.2-12 Menu description of "Status"
1 Inputs Display all input signal states.
2 Outputs Display all output signal states.
3 Superv State Display supervision alarm states.
Date: 2017-08-17
8.2.3.1 Inputs
Table 8.2-13 Menu description of "Inputs"
1 Contact Inputs Display states of binary inputs derived from opto-isolated channels
2 GOOSE Inputs Display state and quality of binary inputs via GOOSE communication.
Display states of tap positions.

3 Tap Position
[84.Tap_Pos] is used to indicates transformer tap position.
4 DPS Inputs "DPS" is the abbreviation of "Double Point Status information".
Table 8.2-14 Item description of "Contact Inputs"
The binary input indicates that the power supply of BI module in slot XX is
1 BXX.Alm_OptoDC
abnormal.
2 BXX.BI_** The No. ** binary input status of BI module in slot XX.
Table 8.2-15 Item description of "Tap Position"
1 84.Tap_Pos Transformer tap position
Table 8.2-16 Item description of "DPS Inputs"
State indication of double position input

1 DPOS** "DPS_INT": Intermediate-state; "DPS_OFF": Open;
"DPS_ON": Close; "DPS_BAD": Bad state.
State indication of double position for normally open (abbreviated as NO)

2 NO_DPOS**
contact
State indication of double position for normally close (abbreviated as NC)

3 NC_DPOS**
contact
8.2.3.2 Outputs
Table 8.2-17 Menu description of "Outputs"
1 Contact Outputs Display states of contact binary outputs.
2 Interlock Status Display states of interlock result of each remote control.
3 Trip Counter Display switch trip times.
Date: 2017-08-17
Table 8.2-18 Item description of "Contact Outputs"
During tap changer control process, if "running tap" occurs, transformer tap
position will be out of control, and it will step up or down continuously.
This device provides an output contact "BO_EmergStopTP" to issue an
emergency stop command for transformer tap position control. Therefore,
1 84.BO_EmergStop_Tap_Pos
"running tap" can be avoided. Select-Before-Operate (abbreviated as SBO)
process is cancelled here so as to stop "running tap" immediately.
State of the output contact "BO_EmergStopTP" is displayed as
[84.BO_EmergStop_Tap_Pos].
Table 8.2-19 Item description of "Interlock Status"
1 CSWI**.CILO.EnaOpn State "1" indicates satisfaction of all interlock logics for remote opening
2 CSWI**.CILO.EnaCls State "1" indicates satisfaction of all interlock logics for remote closing
Table 8.2-20 Item description of "Trip Counter"
1 CSWI**.N_Trp Tripping times of the corresponding switch control output
2 CSWI**.N_TrpA Tripping times of the corresponding switch control output (phase A)
3 CSWI**.N_TrpB Tripping times of the corresponding switch control output (phase B)
4 CSWI**.N_TrpC Tripping times of the corresponding switch control output (phase C)
Table 8.2-21 Item description of "CBWear"
No. Sign Description
1 CBWear.Alm Status of CB wear alarm
2 CBWear.Stat The CB wear statistics value
3 CBWear.Stat_A The CB wear statistics value (phase A)
4 CBWear.Stat_B The CB wear statistics value (phase B)
5 CBWear.Stat_C The CB wear statistics value (phase C)
8.2.3.3 Superv State
Table 8.2-22 Menu description of "Superv Stat"
Display self-supervision of protection function.

1 Prot Superv
Please refer to the chapters 3 & 4 for detail.
Display GOOSE communication supervision.

2 GOOSE Superv
Please refer to the chapter 4 for detail.
3 BCU Superv Display self-supervision of measurement & control function.
Date: 2017-08-17
8.2.3.4 Logic Links State
Table 8.2-23 Menu description of "Logic Links State"
Display BCU logic links states.

1 BCU Links
Display GOOSE receiving links states.

2 GOOSE Recv Links
8.2.4 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
Table 8.2-24 Menu description of "Records"

1 Disturb Records Display disturbance records of the device.
2 Superv Events Display supervision events of the device.
3 IO Events Display binary events of the device.
4 Device Logs Display device logs of the device.
5 Control Logs Display control (binary output) logs of the device.
7 Clear Records Clear all records.
Date: 2017-08-17
8.2.5 Settings
Main Menu
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
NOTICE!
Please refer to the chapter 7 for the detail of setting description.
Table 8.2-25 Menu description of "Settings"
1 System Settings Check or modify the system parameters.
2 Prot Settings Check or modify the protection settings
3 BCU Settings Check or modify the measurement and control settings.
Check or modify the logic links settings, including function links and GOOSE
4 Logic Links
links.
5 Device Setup Check or modify the device setup.
The menu is hidden by default, and when itis visible, it can be used to
6 Confirm Settings
confirm all settings of this device.
Table 8.2-26 Menu description of "Prot Settings"
1 FD Settings Check or modify fault detector settings
2 Direction Settings Check or modify direction settings for ROC and OC protections
3 ROC Settings Check or modify earth fault protection settings
4 OC Settings Check or modify overcurrent protection settings
5 BFP Settings Check or modify breaker failure protection settings
6 PD Settings Check or modify pole discrepancy protection settings
7 FreqProt Settings Check or modify frequency protection settings
8 VTS/CTS Settings Check or modify VT circuit supervision and CT circuit supervision settings
9 Trip Logic Settings Check or modify trip logic settings
10 AR/Syn Settings Check or modify auto-reclosing and synchronism check settings
Date: 2017-08-17
11 Copy Settings Copy setting between different setting groups
Table 8.2-27 Menu description of "BCU Settings"
1 FUN Settings Check or modify miscellaneous functional settings.
2 Syn Settings Check or modify manual synchronism-check settings.
3 BI Settings Check or modify binary input settings.
4 Control Settings Check or modify control (binary output) settings.
5 TP Settings Check or modify tap position settings.
6 Interlock Settings Check or modify interlock settings.
7 AC Calbr Settings Check or modify AC calibration settings.
8 Misc Settings Check or modify settings for CB wear.
Table 8.2-28 Menu description of "Logic Links"
1 Function Links Check or modify function links
2 GOOSE Recv Links Check or modify GOOSE receiving links
3 Misc Links Check or modify miscellaneous links
Table 8.2-29 Menu description of "Device Setup"
1 Device Settings Check or modify the device settings.
2 Comm Settings Check or modify the communication settings.
3 Label Settings Check or modify the label settings.
Date: 2017-08-17
8.2.6 Local Cmd
Main Menu
Local Cmd
Reset Target
Trig Oscillograph
Download
Clear Counter
Manual Control
Clear AR Counter
Clear Trip Counter
Table 8.2-30 Menu description of "Local Cmd"
1 Reset Target Reset the local signal, indicator LED, LCD display, etc.
2 Trig Oscillograph Trigger waveform recording manually
3 Download Send out the program download request.
4 Clear Counter Clear statistic data for measurement & control.
5 Manual Control Send out control command locally and manually.
6 Clear AR Counter Clear auto-reclosing statistic data
7 Clear Energy Counter Clear trip statistic data
8.2.7 Information
Main Menu
Information
Version Info
Board Info
In this menu, the LCD displays software information and the configuration of all kinds of intelligent
plug-in modules.
Table 8.2-31 Menu description of "Information"
Display software information of DSP module, MON module and HMI module,
1 Version Info
which consists of version, creating time of software, CRC codes and
Date: 2017-08-17
management sequence number.
2 Board Info
8.2.8 Test
Main Menu
Test
MMS Comm Counter
GOOSE Comm Counter
Device Test
+ Disturb Events
+ Superv Events
+ IO Events
GOOSE Outputs
Internal Signal
AR Counter
AC Auto Calbr
Interlock Info
GOOSE Interlock
HMI Setup
Contrast
BacklitDur
SupervLCD
SupervLED
This menu is mainly used for developers to debug the program and for engineers to maintain the
device.
Date: 2017-08-17
Table 8.2-32 Menu description of "Test"
1 MMS Comm Counter Display statistical data of MMS communication.
2 GOOSE Comm Counter Display statistical data of GOOSE communication.
Automatically generate all kinds of reports or events to transmit to station

control or control center, including disturbance events, self-supervision
3 Device Test
events, binary events and measurements. It can realize the report uploading
by different classification, as well as the uploading of all kinds of reports.
4 Internal Signal Reserved for factory manufacture debugging
5 AR Counter Display statistical data of auto reclosing.
This menu consists of the parameters to adjust the accuracy of AC analog

input automatically.
6 AC Auto Calbr
This function is used to maintain this device and has already been set by the
manufacturer. It is strongly recommended not to adjust it.
7 Interlock Info Reserved for debugging engineer.
8 HMI Setup LCD display and LED indicators configuration
Table 8.2-33 Item description of "MMS Comm Counter"
"Client" refers to an object which is connected to PCS-9705 via MMS., it can

be a PC with PCS-Explorer tool, a gateway (e.g.: RCS-9698G/H), a station
1 Client_Exist control system (e.g.: PCS-9700 HMI system).
[Client_Exist]= "1": Client exists.
[Client_Exist]= "0": Client does not exist.
Table 8.2-34 Item description of "GOOSE Comm Counter"
1 N_GS_NetStorm Times of network storm in GOOSE network.
2 N_GS_SentFail Failure times to send data via GOOSE network.
3 N_GS_DecodeErr Failure times to decode the received data via GOOSE network.
Table 8.2-35 Menu description of "Device Test"
1 Disturb Events Simulate and issue disturbance event for protection element
2 Superv Events Simulate and issue self-supervision events.
3 IO Events Simulate and issue binary inputs.
4 GOOSE Outputs Simulate and issue GOOSE outputs.
Date: 2017-08-17
NOTICE!
"All Test" means test all the items in the submenu.
"Select Test" means test selectively an item in the submenu.
Table 8.2-36 Item description of "AR Counter"
1 79.N_Total_Rcls Recorded number of all reclosing attempts
2 79.N_1PS1 Recorded number of first 1-pole reclosing attempts
3 79.N_3PS1 Recorded number of first 3-pole reclosing attempts
4 79.N_3PS2 Recorded number of second 3-pole reclosing attempts
5 79.N_3PS3 Recorded number of third 3-pole reclosing attempts
6 79.N_3PS4 Recorded number of fourth 3-pole reclosing attempts
Table 8.2-37 Menu description of "HMI Setup"
1 Contrast To change de contrast of LCD display
2 BacklitDur To change the duration of LCD backlight
3 SupervLCD To find out dead pixel of LCD display
4 SupervLED To find out broken LED indicater 03~20
8.2.9 Clock
The current time of the internal clock can be viewed and modified here.
8.2.10 Language
This menu is mainly used to set LCD display language.
8.3 LCD Display

8.3.1 Overview
Three LCD display methods are provided in this device:
1. Normal display without single line diagram (abbreviated as SLD);
2. Normal display with SLD;
3. Event display.
If LCD configuration file has been downloaded successfully to this device, SLD will be displayed in
normal display. Otherwise, SLD will not be displayed. If any event is detected, the corresponding
event display will pop up automatically.
If SLD is not involved in normal display, user can keep pressing "ENT" and then press "ESC" to
switch between normal display (without SLD) and event display.
Date: 2017-08-17
If SLD is involved in normal display, user can keep pressing "ENT" and then press "ESC" to
switch between normal display (with SLD) and event display.
Three kinds of event display methods are provided:
1. Event display of disturbance records;
2. Event display of supervision events;
3. Event display of IO events.
Event display of disturbance records can be cleared manually in this way: keep pressing "ESC"
and then press "ENT";
Event display of supervision events cannot be cleared manually, and it will not be cleared until the
corresponding supervision events have disappeared;
Event display of IO events only keeps for several seconds and then it will disappear and return to
normal display automatically.
8.3.2 Normal Display without SLD

After the device is energized, it takes tens of seconds to complete the initialization of this device.
During the initialization of this device, the "HEALTHY" LED indicator of this device keeps being lit
off.
An example of normal display without SLD is shown in the following figure. The LCD adopts white
color as its backlight that will be activated in case of any keyboard operation. Moreover, the
backlight will be extinguished automatically if no keyboard operation is detected for duration.
S 2013-01-15 13:22:23
BayMMXU.Ia_Sec 0.0000 A
BayMMXU.Ib_Sec 0.0000 A
BayMMXU.Ic_Sec 0.0000 A
BayMMXU.Uab_Sec 0.10 V
BayMMXU.Ubc_Sec 0.10 V
BayMMXU.Uca_Sec 0.10 V
BayMMXU.Usyn_Sec 0.10 V
BayMMXU.f 0.000 Hz
BayMMXU.fsyn 0.000 Hz
Addr 24343
Figure 8.3-1 Normal display without SLD
S indicatess that device clock is synchronized. If "S" disappears, it

means that device clock is not synchronized.
Date: 2017-08-17
2013-01-15 13:22:23 shows current date and time of this device, the format is
"yyyy-mm-dd hh:mm:ss".
BayMMXU.Ia_Sec… shows main measurements of this device. If the measurements

cannot be displayed in one page, they will be displayed in several
pages alternately.
Addr 24343 shows address relevant to IP address of Ethernet A. If IP address

of Ethernet A is "xxx.xxx.a.b", the displayed address equals to
(a×256+b). E.g.: if IP address of Ethernet A is "198.087.095.023",
the displayed address will be "95×256+23=24343".
8.3.3 Normal Display with SLD

An example of normal display with SLD is shown in the following figure. LCD configuration file can
be downloaded to this device via network. Control operation through SLD is also supported.
Addr 24343 2013-01-01 10:10:00

Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Feeder M01
Ua_Pri: 132.00 kV Ua_Sec: 57.75 V

Ia_Pri: 606.0 A Ia_Sec: 1.01 A
Cos: 0.88
Figure 8.3-2 Normal display with SLD
Signs for the circuit breaker (abbreviated as CB) and switch (DS or ES) are listed in the following
table.
Sign Explanation Sign Explanation
Position of CB: Open Position of switch: Open
Position of CB: Closed Position of switch: Closed
? Position of CB: Intermediate state ? Position of switch: Intermediate state
× Position of CB: Bad state × Position of switch: Bad state
Date: 2017-08-17
8.3.3.1 Control via SLD
In SLD display, press "▼" continuously to select a CB/switch to be opened/closed, and then press
key "ENT" to control selected CB/switch. The control operation window will be valid for duration
after inputting correct password as shown in the following figure. The password for control
operation is fixed as "111".
Please refer to "Remote Control" (from the 4th step) for the following steps of control.
Please make sure that the switch is on the right position "Local" when operating;
Password:
0 00
Figure 8.3-3 Password for control operation on SLD
8.3.4 Event Display

8.3.4.1 Display of Supervision Events
This device can store up to 1024 supervision events. During the operation of the device, the
supervision event of hardware self-check errors or system operation abnormity will be displayed
immediately.
Date: 2017-08-17
S Superv Events
Alm_Device
Alm_Version
Figure 8.3-4 LCD display of supervision events
S indicatess that device clock is synchronized. If "S" disappears, it

means that device clock is not synchronized.
Superv Events shows the title of the supervision events.
Alm_Device, Alm_Version shows the contents of supervision events.
8.3.4.2 Display of IO Events
This device can store up to 1024 IO events (i.e.: binary events). During the operation of the device,
the binary input will be displayed once its state has changed, i.e.: from "0" to "1" or from "1" to "0".
NO.001 2013-01-15 13:31:23:669 IO Chg
BI_Maintenance 0 1
Figure 8.3-5 LCD display of IO events
NO.001 shows the No. of the binary event.
Date: 2017-08-17
2013-01-15 13:31:23:669 shows date and time when the report occurred, the format is
"yyyy-mm-dd hh:mm:ss:fff".
IO Chg shows the title of the binary event.
BI_Maintenance 0→1 shows the state change of binary input, including binary input
name, original state and final state.
8.4 Keypad Operation

8.4.1 View Device Measurements
1. Press "▲" to enter the main menu;
2. Press the "▲" or "▼" to move the cursor to the "Measurements" menu, and then press
"ENT" or "►" to enter the menu;
3. Press "▲" or "▼" to move the cursor to any command menu, and then press "ENT" to enter
the menu;
4. Press "▲" or "▼" to page up/down (if all information cannot be displayed in one display
screen, one screen can display 14 lines of information at most);
5. Press "◄" or "►" to select pervious or next command menu;
6. Press "ENT" or "ESC" to exit this menu (returning to the "Measurements" menu);
8.4.2 View Device Status

1. Press "▲" to enter the main menu.
2. Press "▲" or "▼" to move the cursor to the "Status" menu, and then press "ENT" or "►" to
enter the menu.
3. Press "▲" or "▼" to move the cursor to any command menu item, and then press "ENT" to
enter the submenu.
4. Press "▲" or "▼" to page up/down (if not all information can be displayed in one display
screen, one screen can display 14 lines of information at most).
5. Press "◄" or "►" to select pervious or next command menu.
6. Press "ENT" or "ESC" to exit this menu (returning to the "Status" menu).
8.4.3 View Device Records

2. Press "▲" or "▼" to move the cursor to the "Records" menu, and then press "ENT" or "►" to
enter the menu;
the menu;
4. Press "▲" or "▼" to page up/down;
Date: 2017-08-17
5. Press "＋" or "－" to select pervious or next record;
7. Press "ENT" or "ESC" to exit this menu (returning to the "Records" menu).
An example of the command menu "Device Logs" is shown in the following figure. Displays of
other command menus (for example, "Disturb Records") are similar.
Device Logs NO.60

2013-01-28 10:18:47:569ms
Reboot
Figure 8.4-1 LCD display of "Device Logs"
Device Logs NO. 60 shows the title and the No. of the device log. This device can
store up to 1024 device logs.
2013-01-28 10:18:47:569ms shows date and time when the report occurred, the format is
"yyyy-mm-dd hh:mm:ss:fff".
Reboot shows the content of the device log.
Available device logs are listed in the following table.
Table 8.4-1 Available device logs
No. Message Description

1 Report_Cleared All device records (except device logs) have been deleted.
2 Waveform_Cleared All waveforms have been deleted.
3 Reboot The device has been rebooted.
4 Settings_Chgd Device settings have changed.
5 Process_Exit One or more processes are out of service.
8.4.4 View Device Setting

Date: 2017-08-17
2. Press "▲" or "▼" to move the cursor to the "Settings" menu, and then press "ENT" or "►" to
enter the menu;
the menu;
4. Press "▲" or "▼" to move the cursor;
5. Press "+" or "-" to page up/down;
7. Press "ESC" to exit this menu (returning to the menu "Settings").
If the displayed information exceeds 14 lines, the scrollbar will appear on the right side of the
LCD to indicates the quantity of all displayed information of the command menu and the
relative location of information where the current cursor is pointing at.
8.4.5 Modify Device Setting

2. Press "▲" or "▼" to move the cursor to the "Settings" menu, and then press "ENT" or "►" to
enter the menu;
the menu;
4. Press "▲" or "▼" to move the cursor;
5. Press "+" or "-" to page up/down;
7. Press "ESC" to exit this menu (returning to the menu "Settings" );
8. If selecting the command menu "System Settings", move the cursor to the setting item to be
modified, and then press "ENT".
Press "＋" or "－" to modify the value (if the modified value is of multi-bit, press "◄" or "►" to
move the cursor to the digit bit, and then press "＋" or "－" to modify the value), press "ESC"
to cancel the modification and return to the displayed interface of the command menu
"System Settings". Press "ENT" to automatically exit this menu (returning to the displayed
interface of the command menu "System Settings").
Move the cursor to continue modifying other setting items. After all setting values are
modified, press "◄", "►" or "ESC", and the LCD will display "Save or Not?". Directly Press
"ESC" or Press "◄" or "►" to move the cursor. Select the "Cancel", and then press "ENT" to
automatically exit this menu (returning to the displayed interface of the command menu
"System Settings").
Press "◄" or "►" to move the cursor. Select "No" and Press "ENT", all modified setting item
will restore to its original value, exit this menu (returning to the menu "Settings").
Date: 2017-08-17
Press "◄" or "►" to move the cursor to select "Yes", and then press "ENT", the LCD will
display password input interface.
Password:
____
Figure 8.4-2 Password to modify settings
Input a 4-bit password ("＋", "◄", "▲" and "－"). If the password is incorrect, continue
inputting it, and then press "ESC" to exit the password input interface and return to the
displayed interface of the command menu "System Settings". If the password is correct,
LCD will display "Save Setting …", and then exit this menu (returning to the displayed
interface of the command menu "System Settings"), with all modified setting items as
modified values.
NOTICE!
After modifying settings of the device, the "HEALTHY" LED indicator of the device will
be off, and the device will automatically restart and re-check them. If the check does
not pass, the device will be blocked.
8.4.6 Copy Device Setting

The operation is as follows:
1. Press the "▲" to enter the main menu;
2. Press the "▲" or "▼" to move the cursor to the "Settings" menu, and then press the "ENT" or
"►" to enter the menu;
3. Press the "▲" or "▼" to move the cursor to the command menu "Copy Settings", and then
press the "ENT" to enter the menu.
Date: 2017-08-17
Copy Settings
Active Group: 01
Copy To Group: 02
Press the "+" or "-" to modify the value. Press the "ESC", and return to the menu "Settings".
Press the "ENT", the LCD will display the interface for password input, if the password is
incorrect, continue inputting it, press the "ESC" to exit the password input interface and return
to the menu "Settings". If the password is correct, the LCD will display "copy setting OK!",
and exit this menu (returning to the menu "Settings").
8.4.7 Switch Setting Group

The operation is as follows:
1. Exit the main menu;
2. Press the "GRP"
Change Active Group
Active Group: 01
Change To Group: 02
Press the "＋" or "－" to modify the value, and then press the "ESC" to exit this menu
(returning to the main menu). After pressing the "ENT", the LCD will display the password
input interface. If the password is incorrect, continue inputting it, and then press the "ESC" to
exit the password input interface and return to its original state. If the password is correct, the
Date: 2017-08-17
"HEALTHY" indicator lamp of the protection device will go out, and the protection device will
re-check the protection setting. If the check doesn’t pass, the protection device will be
blocked. If the check is successful, the LCD will return to its original state.
8.4.8 Delete Device Records

1. Exit the main menu;
2. Press "＋", "－", "＋", "－" and "ENT"; Press "ESC" to exit this menu (returning to the original
state). Press "ENT" to carry out the deletion.
Press <ENT> To Clear

Press <ESC> To Exit
Figure 8.4-3 Confirmation to delete records
NOTICE!
The operation of deleting device message will delete all messages saved by the device,
including disturbance records, supervision events, IO events, but not including device
logs. Furthermore, the message is irrecoverable after deletion, so the application of the
function shall be cautious.
8.4.9 Remote Control

2. Press "▲" or "▼" to move the cursor to the command menu "Local Cmd", and then press
"ENT" to enter submenus. Press "▲" or "▼" to move the cursor to the command menu
"Control", and then press "ENT" to enter the password.
3. Input a 3-bit password ("111"). If the password is incorrect, continue inputting it, and then
press "ESC" to exit the password input interface and return to the displayed interface of the
command menu "Control". If the password is correct, it will go to the following step.
4. Press "▲" or "▼" to move the cursor to the control object and press "ENT" to select the
control object.
5. Press "◄" or "►" to select control command press "ENT" or "ESC" to the next/previous step.
Date: 2017-08-17
Three control commands are optional:
1) Open(Lower) Remote open, or step down transformer tap position;
2) Close (Raise) Remote close, or step up transformer tap position;
3) (Stop) During transformer tap position control process, "Stop" is used to

send an emergency stop command to stop "running tap"
immediately.
6. Press "◄" or "►" to select RSYN check mode and Press "ENT" or "ESC" to the next/previous
step.
Five RSYN check modes are optional:
1) NoCheck Without any check
2) SynchroCheck Synchronism-check mode
3) DeadCheck Dead check mode
4) LoopCheck Reserved
5) EF Line Selection Reserved
7. Press "◄" or "►" to select interlock mode and Press "ENT" or "ESC" to the next/previous
step.
Two interlock check modes are optional:
1) InterlockChk Check interlocking criteria
2) InterlockNotChk Not check interlocking criteria.
8. Press "◄" or "►" to select control type and Press "ENT" or "ESC" to the next/previous step.
Three control types are optional:
1) Select Select control object
2) Execute Execute control operation
3) Cancel Cancel control operation
9. The result of control operation will be shown on LCD. Press "ESC" to return to the 7th step.
NOTICE!
"Execute" operation must be operated after "Select" operation in manual control mode.
8.4.10 Modify Device Clock

2. Press "▲" or "▼" to move the cursor to the "Clock" menu, and then press "ENT" to enter
clock display
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3. Press "▲" or "▼" to move the cursor to the date or time to be modified;
4. Press "+" or "-" to modify value, and then press "ENT" to save the modification and return to
the main menu;
5. Press "ESC" to cancel the modification and return to the main menu.
Clock
Year: 2012
Month: 12
Day: 25
Hour: 14
Minute: 26
Second: 54
Figure 8.4-4 Modification of device time
8.4.11 View Module Information

2. Press "▲" or "▼" to move the cursor to the "Information" menu, and then press "ENT" or
"►" to enter the menu.
3. Press "▲" or "▼" to move the cursor to the command menu "Board Info", and then press
"ENT" to enter the menu.
4. Press "▲" or "▼" to move the scroll bar.
5. Press "ESC" to exit this menu.
8.4.12 Check Software Version

2. Press "▲" or "▼" to move the cursor to the "Information" menu, and then press "ENT" to
enter the submenu.
3. Press "▲" or "▼" to move the cursor to the command menu "Version Info", and then press
"ENT" to display the software version.
4. Press "▲" or "▼" to check all the relative information about the software version (CRC code,
management code, programme time, etc.).
5. Press "ESC" to return to the main menu.
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8.4.13 Communication Test

2. Press "▲" or "▼" to move the cursor to the "Test" menu, and then press "ENT" or "►" to
enter the menu.
3. Press "▲" or "▼" to move the cursor to the submenu "Device Test", and then press "ENT" to
enter the submenu and select test item. If "Disturb Events", "Superv Events" or "IO Events"
is selected, two options "All Test" and "Select Test" are provided.
4. Press "▲" or "▼" to move the cursor to select the corresponding command menu "All Test"
or "Select Test".
5. If selecting the "All Test", press "ENT", and the device will successively carry out all
operation element message test one by one.
6. If "Select Test" is selected, press "ENT". Press "＋" or "－" to page up/down, and then press
"▲" or "▼" to move the scrollbar. Move the cursor to select the corresponding item. Press
"ENT" to execute the communication test of this item, station control or control center will
receive corresponding message.
7. Press "ESC" to exit this menu (returning to the menu "Select Test"), at this moment, the LCD
will display "Communication Test Exiting…".
NOTICE!
If no input operation is carried out within 60s, the communication test will exit and
return to the "Select Test" menu automatically, at this moment, the LCD will display
"Communication Test Timeout and Exiting...".
8.4.14 Select Language

2. Press "▲" or "▼" to move the cursor to the command menu "Language", and then press
"ENT" to enter the menu and the following display will be shown on LCD.
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Please Select Language:
1. 中文
2. English
Figure 8.4-5 Selection of display language
3. Press "▲" or "▼" to move the cursor to the language user preferred and Press "ENT" to
execute language switching. After language switching is finished, LCD will return to defaul
display. Otherwise, press "ESC" to cancel language switching and return to the menu
"Language".
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Table of Contents
9 Configurable Function ......................................................................9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Configurable Function of PCS-Explorer ........................................................ 9-1
9.3 Configurable Function of SCL Configurator ................................................. 9-1
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9.1 Overview
Two configuration tools are designed to realize the configurable functions of PCS-9705.
 PCS-Explorer
Support of device configuration, function configuration, LCD configuration, binary input and
binary output configuration, LED indicator configuration and programmable interlocking logic
 SCL Configurator:
Station level inter-bay interlocking configuration function
9.2 Configurable Function of PCS-Explorer
PCS-Explorer software is developed to meet customer’s demand on functions of UAPC platform

device such as device configuration and programmable design. It selects substation as the core of
data management and the device as fundamental unit, supporting one substation to govern many
devices. The software provides on-line and off-line functions: on-line mode: Ethernet connected
with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand.
After function configuration is finished, disabled function will be hidden in the device and in setting
configuration list of PCS-Explorer Software. The user can select to show or hide some setting by
this way, and modify the setting vale.
Please refer to the instruction manual “PCS-Explorer Auxiliary Software” for details.
Functions:
 Programmable logic
 Device configuration
 Function configuration
 LCD configuration
 LED indicators configuration
 Binary signals configuration
 Setting configuration
 Real-time display of analogue and digital quantity of device
 Display of sequence of report (SOE)
 Analysis of waveform
 File downloading/uploading
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 LCD function shortcut keys configuration
 DNP communication information map configuration
 Export RIO file
 Multi-user access authority management
9.3 Configurable Function of SCL Configurator
SCL configuration tool is developed for the engineered implementation IEC61850. It can be used
to create, edit and view SCL files which conform to IEC61850-6 regulations, and then construct
the substation configuration, structures, models, etc. Specially, it can be used to define the
message transmitted inter-bay (useful for interlocking).
Please refer to the instruction manual “SCL Configurator Auxiliary Software” for details.
Functions:
 Creation of SCD file in accordance with IEC61850-6 regulations
 Version management of SCD files
 Construction of substation structure and creation of complete system specification

description (SSD)
 Import of IED file into ICD file which conforms to IEC 61850-6
 Association of different intelligent electronic devices and their logical nodes (LN) to substation
details, and completion of substation system configuration according to IEC61850-6
 Edition and maintenance of functions and date elements in IED
 Definition of substation communication configuration (inter-device)
 Verification of data templates and handling of conflicts
 Verification of standard SCL schema
 Verification of expanded grammar and semantics
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10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................ 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port .......................................................................... 10-1
10.2.1 Ethernet Interface ............................................................................................................ 10-1
10.3 Message Description for IEC61850 Protocol ............................................ 10-2

10.3.1 Overview .......................................................................................................................... 10-2
10.3.2 Communication Profiles ................................................................................................... 10-3
10.3.3 MMS Communication Network Deployment .................................................................... 10-4
10.3.4 Server Data Organization ................................................................................................ 10-7
10.3.5 Server Features and Configuration ............................................................................... 10-11
10.3.6 ACSI Conformance ........................................................................................................ 10-12
10.3.7 Logical Nodes ................................................................................................................ 10-17
10.4 DNP3.0 Interface ........................................................................................ 10-20

10.4.1 Overview ........................................................................................................................ 10-20
10.4.2 Link Layer Functions ...................................................................................................... 10-21
10.4.3 Transport Functions ....................................................................................................... 10-21
10.4.4 Application Layer Functions ........................................................................................... 10-21
List of Figures
Figure 10.2-1 Ethernet communication cable ........................................................................ 10-1
Figure 10.2-2 Ethernet communication structure ................................................................. 10-2
Figure 10.3-1 Dual-net full duplex mode sharing the RCB block instance......................... 10-4
Figure 10.3-2 Dual-net hot-standby mode sharing the same RCB instance ...................... 10-5
Figure 10.3-3 Dual-net full duplex mode with 2 independent RCB instances .................... 10-6
Figure 10.4-1 Enable the configuration of DNP3.0 .............................................................. 10-20
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10 Communication
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10 Communication
10.1 Overview
This section outlines the remote communications interfaces of this device. This device supports a
choice of 2 protocols via the rear communication interface, selected via the model number by
setting. The protocol provided by the device can be chosen from the menu “Settings→Device
Setup→Comm Settings”.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the
device.
10.2 Rear Communication Port
10.2.1 Ethernet Interface

This device can provide four rear Ethernet interfaces (optional) and they are unattached each
other. Parameters of each Ethernet port can be configured in the menu “Settings→Device
Setup→Comm Settings”.
10.2.1.1 Ethernet Standardized Communication Cable
It is recommended to use twisted shielded eight-core cable as the communication cable. A picture
is shown below.
Figure 10.2-1 Ethernet communication cable
10.2.1.2 Connections and Topologies
Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
connected to the exchanger and will play a role as master station, other equipment connected to
the exchanger will play a role as slave unit.
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10 Communication
SCADA
Switch: Net A
Switch: Net B
……
Figure 10.2-2 Ethernet communication structure
10.3 Message Description for IEC61850 Protocol
10.3.1 Overview
The IEC61850 software module is adopted in the device.
The IEC61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
 IEC 61850-5: Communications and requirements for functions and device models
 IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs
 IEC 61850-7-1: Basic communication structure for substation and feeder equipment–
Principles and models
 IEC 61850-7-2: Basic communication structure for substation and feeder equipment -
Abstract communication service interface (ACSI)
Common data classes
Compatible logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
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10 Communication
 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC61850 implementation obtain this document set.
10.3.2 Communication Profiles

This device supports IEC61850 server services over TCP/IP communication protocol stacks. The
TCP/IP profile requires this device to have an IP address to establish communications. These
addresses are located in the submenu “Settings→Device Setup→Comm Settings”.
 MMS protocol
IEC61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
 Client/server
This is a connection-oriented type of communication. The connection and communication activity

is initiated and controlled by the client. Substation computers running HMI programs or SOE
logging software are considered as IEC61850 clients. Substation equipment such as protection
relays, meters, instrument transformers, tap changers, or bay control units are considered as
IEC61850 servers.
Please note that gateways can be considered as clients and servers subject to the communication
object. When retrieving data from IEDs within the substation, the gateways are considered as
servers whereas transmitting data to control centers, the gateways are considered as clients.
 Peer-to-peer
This is a non-connection-oriented, high-speed type of communication usually between substation

equipment, such as protection relays, bay control units. GOOSE is the method of peer-to-peer
communication.
 Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the following items: individual ICD files, SSD file, communication
system parameters (MMS, GOOSE control block, SV control block), as well as GOOSE/SV
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10 Communication
connection relationship amongst IEDs.
10.3.3 MMS Communication Network Deployment

To enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This section
is applied to introduce the details of dual-MMS Ethernet technology. Generally, single-MMS
Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels, while
dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above 110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
NOTICE!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is
broken.
 Mode 1: Dual-net full duplex mode sharing the same RCB instance
Client Client
Net A Net B Net A Net B
Report Instance 1 Report Instance 1
RptEna = true RptEna = true
Report Control Block Report Control Block

IED (Server) IED (Server)
Normal operation status Abnormal operation status
TCP Link
MMS Link
Figure 10.3-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
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10 Communication
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of mode 1, IED provides the same MMS service for Net A and Net B. If
one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the working
mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In mode 1, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
 Mode 2: Dual-net hot-standby mode sharing the same RCB instance
Client Client
Report Instance 1 Report Instance 1
RptEna = true RptEna = true

TCP Link
Main MMS Link
Standby MMS Link
Figure 10.3-2 Dual-net hot-standby mode sharing the same RCB instance
In mode 2, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
 Main MMS Link: Physically connected, TCP level connected, MMS report service
available.
 Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
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10 Communication
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
NOTICE!
In mode 1 and mode 2, Net A IED host address and Net B IED host address must be
the same. E.g.: if the subnet mask is 255.255.0.0, network prefix of Net A is
198.120.0.0, network prefix of Net B is 198.121.0.0, Net A IP address of the IED is
198.120.1.2, and then Net B IP address of the IED must be configured as 198.121.1.2,
i.e.: Net A IED host address =1x256+2=258, Net B IED host address =1x256+2=258,
Net A IED host address equals to Net B IED host address.
 Mode 3: Dual-net full duplex mode with 2 independent RCB instances
Client Client
Report Instance 1 Report Instance 2 Report Instance 1 Report Instance 2
RptEna = true RptEna = true RptEna = false RptEna = true

TCP Link
MMS Link
Figure 10.3-3 Dual-net full duplex mode with 2 independent RCB instances
In mode 3, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of one net will not affect the other net at all.
In this mode, 2 report instances are required for each client. Therefore, the IED may be unable to
provide enough report instances if there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
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10 Communication
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion:
In mode 2, it is difficult to realize seamless switchover between dual nets;
In mode 3, the IED may be unable to provide enough report instances if too many clients are
applied on site.
For the consideration of client treatment and IED implementation, mode 1 (Dual-net full duplex
mode sharing the same report instance) is recommended for MMS communication network
deployment.
10.3.4 Server Data Organization

IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical
device can contain one or more logical device(s) (for proxy). Each logical device can contain
many logical nodes. Each logical node can contain many data objects. Each data object is
composed of data attributes and data attribute components. Services are available at each level
for performing various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common
information about the IED logical device.
10.3.4.1 Digital Status Values
The GGIO logical node is available in this device to provide access to digital status points
(including general I/O inputs and warnings) and associated timestamps and quality flags. The
data content must be configured before the data can be used. GGIO provides digital status points
for access by clients. It is intended that clients use GGIO in order to access digital status values
from in this device. Clients can utilize the IEC61850 buffered reporting features available from
GGIO in order to build sequence of events (abbreviated as SOE) logs and HMI display screens.
Buffered reporting should generally be used for SOE logs since the buffering capability reduces
the chances of missing data state changes. All needed status data objects are transmitted to HMI
clients via buffered reporting, and the corresponding buffered reporting control block (abbreviated
as BRCB) is defined in LLN0.
10.3.4.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the others in MMXN, MSQI and so on. Each MMXU logical node provides data
from an IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2
provides data from CT/VT source 2 (usually for monitor and display purpose). All these analog
data objects are transmitted to HMI clients via unbuffered reporting periodically, and the
corresponding unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical
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10 Communication
nodes provide the following data for each source:
 MMXU.MX.TotW: three-phase active power
 MMXU.MX.TotVAr: three-phase reactive power
 MMXU.MX.TotPF: three-phase power factor
 MMXU.MX.Hz: frequency
 MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.MX.A.phsA: phase A current magnitude and angle
 MMXU.MX.A.phsB: phase B current magnitude and angle
 MMXU.MX.A.phsC: phase C current magnitude and angle
 MMXU.MX.A.neut: ground current magnitude and angle
10.3.4.3 Protection Logical Nodes
The following list describes the protection elements.
 PTOC: Phase overcurrent, zero-sequence overcurrent
 PTOF: Overfrequency
 PTUF: Underfrequency
 PPDP: Pole discrepancy
 RBRF:Breaker failure
 RREC: Automatic reclosure
 RSYN: Synchronism-check
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. These flags take their values from related module for the
corresponding element. Similar to digital status values, the protection trip information is reported
via BRCB, and BRCB also locates in LLN0.
10.3.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
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10 Communication
common issues for Logical Devices. In this device, most of the public services, the common
settings, control values and some device oriented data objects are available here. The public
services may be BRCB, URCB and GSE control blocks and similar global defines for the whole
device; the common settings include all the setting items of communication settings, system
settings and some of the setting items, which can be configured to 2 or more logical nodes. In
LLN0, the item Loc is a device control object, this Do item indicates the local operation for
complete logical device, when it is true, all the remote control commands to the IED will be
blocked and those commands make effective until the item Loc is changed to false. Besides the
logical nodes we describe above, there are some other logical nodes below in the IEDs.
 MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as RMS values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
accuracy for these functions has to be provided.
 CILO: This LN shall be used to “enable” a switching operation if the interlocking conditions
are fulfilled. One instance per switching device is needed. At least all related switchgear
positions have to be subscribed. The interlocking algorithm is a local issue.
This LN is used for the interlocking function at station level and/or at bay level.
Interlocking may be totally centralized or totally decentralized. Since the interlocking rules are
basically the same on bay and station level and based on all related position indications, the
different interlocking LNs may be seen as instances of the same LN class Interlocking (IL).
1) Interlocking of switchgear at bay level
All interlocking rules referring to a bay are included in this LN. Releases or blockings of
requested commands are issued. In the case of status changes affecting interlocking,
blocking commands are issued.
2) Interlocking of switchgear at station level
All interlocking rules referring to the station are included in this LN. Releases or
blockings of requested commands are issued. Information with the LN bay interlocking is
exchanged.
 MSQI: This LN is used for the sequences and imbalances, for example for stability purpose.
This LN is used to acquire values from CTs and VTs and to calculate the sequences and
imbalances in a three/multi-phase power system.
 RSYN: This LN is used for synchrocheck/synchronizing or synchronism check.
The voltage phasor difference from both sides of an open breaker is calculated and
compared with predefined switching conditions (synchrocheck). Included is the case that one
side is dead (example: energizing a dead line) and the case that the phasor on one side can
be actively controlled by “higher” or “lower” (means synchronizing).
Synchronizing or synchronism-check device is a device that operates when two AC circuits
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10 Communication
are within the desired limits of frequency, phase-angle and voltage, to permit or to cause the
paralleling of these two circuits (IEEE C37.2-1996).
To avoid stress for the switching device and the network, closing of the circuit breaker is
allowed by the synchrocheck only, if the differences of voltage, frequency and phase angle
are within certain limits.
 YLTC: This LN is used for tap changer.
Device allocated to YPTR allowing changing taps of the winding for voltage regulation.
 ATCC: This LN is used for automatic tap changer control.
This LN provides automatic function to keep the voltage of a busbar within a specific range
using tap changers. This node operates the tap changer automatically according to given
setpoints or by direct operator commands (manual mode).
 LPHD: Physical device information, the logical node to model common issues for physical
device.
 GAPC: Generic automatic process control, it is used to model in a generic way the
processing/automation of functions, for example the sequence control functions for this
device.
 CSWI: Switch controller. This class is used to control all switching conditions of XCBR and
XSWI. A remote switching command (for example Select-Before-Operate) arrives here firstly.
 XCBR: Breaker control. The XCBR logical node is directly associated with the breaker control
feature.
 XCBR1.ST.Pos: This is the position of the breaker. If the breaker control logic indicates that
the breaker, or any single pole of the breaker, is closed, then the breaker position state is “on”.
If the breaker control logic indicates that the breaker is open, then the breaker position state
is “off”.
 XCBR1.ST.BlkOpn: This is the state of the block open command logic. When true, breaker
open commands from IEC61850 clients will be rejected.
 XCBR1.ST.BlkCls: This is the state of the block close command logic. When true, breaker
close commands from IEC61850 clients will be rejected.
 XCBR1.CO.Pos: This is where IEC61850 clients can issue open or close commands to the
breaker. Select-Before-Operate (abbreviated as SBO) with enhanced security is the only
supported IEC61850 control model.
 PTRC: Protection trip conditioning, it shall be used to connect the “operate” outputs of one or
more protection functions to a common “trip” to be transmitted to XCBR. In addition or
alternatively, any combination of “operate” outputs of protection functions may be combined
to a new “operate” of PTRC.
 RDRE: Disturbance recorder function. It triggers fault wave recorder and its output refers to
the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System”
Date: 2017-08-17
10 Communication
(IEC 60255-24). All enabled channels are included in the recording and independent of the
trigger mode.
10.3.5 Server Features and Configuration

10.3.5.1 Buffered/Unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
 TrgOps: Trigger options
The following bits are supported by this device:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields
The following bits are supported by this device:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
 IntgPd: Integrity period
 BufTm: Buffer time
10.3.5.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from
this device.
10.3.5.3 Timestamps
The Universal Time Coordinated (abbreviated as UTC) timestamp associated with all IEC61850
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10 Communication
data items represents the latest change time of either the value or the quality flags of the data
item.
10.3.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.3.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic
link settings in device.
This device supports IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-9705 series bay control units.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must
be correct to achieve the successful transfer of data. It is critical that the configured datasets at
the transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
10.3.6 ACSI Conformance

10.3.6.1 ACSI Basic Conformance Statement
Client/ Server
Services PCS-9705
Subsrciber /Publisher
Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
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10 Communication
Client/ Server
Services PCS-9705
Subsrciber /Publisher
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC61850-8-1 used Y Y Y
B22 SCSM: IEC61850-9-1 used N N N
B23 SCSM: IEC61850-9-2 used Y N Y
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by this device
N: Currently not supported by this device
10.3.6.2 ACSI Models Conformance Statement
Services Client/Subsrciber Server/Publisher PCS-9705
M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y
M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
M7 Buffered report control O O Y
M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
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Services Client/Subsrciber Server/Publisher PCS-9705
M7-6 buffer-overflow Y Y Y
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N
M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N
M16 Time M M Y
M17 File transfer O O Y
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by this device
N: Currently not supported by this device
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10 Communication
10.3.6.3 ACSI Services Conformance Statement
Services Server/Publisher PCS-9705
Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O Y
S14 CreateDataSet O N
S15 DeleteDataSet O N
S16 GetDataSetDirectory M Y
Substitution
S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
S21 ConfirmEditSGValues M/O Y
S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
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10 Communication
S24-1 data-change M Y
S24-2 qchg-change M Y
S24-3 data-update M Y
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M Y
S27-3 data-update M N
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block
S30 GetLCBValues O N
S31 SetLCBValues O N
Log
S32 QueryLogByTime O N
S33 QueryLogAfter O N
S34 GetLogStatusValues O N
Generic substation event model (GSE)
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O Y
S37 GetGOOSEElementNumber O N
S38 GetGoCBValues M Y
S39 SetGoCBValuess M Y
Control
S51 Select O N
S52 SelectWithValue M Y
S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O N
File transfer
S57 GetFile M/O Y
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S58 SetFile O Y
S59 DeleteFile O N
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.3.7 Logical Nodes

10.3.7.1 Logical Nodes Table
This device supports IEC61850 logical nodes as indicated in the following table. Note that the
actual instantiation of each logical node is determined by the product order code.
Nodes PCS-9705
L: System Logical Nodes
LPHD: Physical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential －
PDIR: Direction comparison －
PDIS: Distance －
PDOP: Directional overpower －
PDUP: Directional underpower －
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint －
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent －
PMRI Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault －
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload －
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Nodes PCS-9705
PTUC: Undercurrent －
PTUV: Undervoltage YES
PPDP: Pole discrepancy YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent －
PVPH: Volts per Hz －
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure YES
RDIR: Directional element －
RFLO: Fault locator YES
RPSB: Power swing detection/blocking －
RREC: Autoreclosing YES
RSYN: Synchronism-check or synchronizing YES
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking YES
CPOW: Point-on-wave switching －
CSWI: Switch controller YES
G: Logical Nodes For Generic References
GAPC: Generic automatic process control YES
GGIO: Generic process I/O YES
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
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10 Communication
Nodes PCS-9705
ARCO: Reactive power control －
ATCC: Automatic tap changer controller YES
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements －
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering YES
MMXN: Non phase related measurement YES
MMXU: Measurement YES
MSQI: Sequence and imbalance YES
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer YES
YPSH: Power shunt －
YPTR: Power transformer －
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
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10 Communication
Nodes PCS-9705
ZREA: Reactor －
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.4 DNP3.0 Interface
10.4.1 Overview
The DNP3.0 (Distributed Network Protocol) protocol can support the OSI/EPA model of the ISO
(International Organization for Standards), and it includes four parts: application layer protocol,
transport functions, data link layer protocol and data object library. The DNP3.0 protocol is
recommended to use the Ethernet network. This relay operates as a slave in the system,
responding to commands from a master station.
NOTICE!
For the use of DNP3.0 protocol in this device, please make sure that this protocol is
enabled in device configuration file (DEV) to view and set all the related DNP3.0
communication settings via the menu "Settings" -> "Device Setup" -> "Comm
Settings".
Figure 10.4-1 Enable the configuration of DNP3.0
Date: 2017-08-17
10 Communication
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.4.2 Link Layer Functions

Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.4.3 Transport Functions

Please see the DNP3.0 protocol standard for the details about the transport functions.
10.4.4 Application Layer Functions

10.4.4.1 Function Code
Function Code Function

0 (0x00) Confirm
1 (0x01) Read
2 (0x02) Write
3 (0x03) Select
4 (0x04) Operate
5 (0x05) Direct Operate
6 (0x06) Direct Operate No Acknowledgment
13 (0x0D) Cold Restart
14 (0x0E) Warm Restart
20 (0x14) Enable Unsolicited Responses
21 (0x15) Disable Unsolicited Responses
22 (0x16) Assign Class
23 (0x17) Delay Measurement
10.4.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
Request: Master may issue/Outstation shall parse
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION REQUEST

Group/Variation No. Description Function code Qualifier code
1 (read) 00, 01 (start ~ stop)
1 0 Binary Input: Any Variation
22 (assign class) 06 (no range, or all)
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10 Communication

00, 01 (start ~ stop)
1 1 Binary Input: Packed format 1 (read)
06 (no range, or all)
1 2 Binary Input: With flags 1 (read)
2 0 Binary Input Event: Any Variation 1 (read)
07, 08 (limited qty)
2 1 Binary Input Event: Without time 1 (read)
2 2 Binary Input Event: With absolute time 1 (read)
2 3 Binary Input Event: With relative time 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 1 Binary output: Packed format 2 (write) 00, 01 (start ~ stop)
3 (select)
Binary Command: Control relay output 4 (operate) 17, 28 (index)
12 1
block (CROB) 5 (direct op)
6 (dir. op, no ack) 17, 28 (index)
1 (read) 00, 01 (start ~ stop)
30 0 Analog Input: Any Variation
22 (assign class) 06 (no range, or all)
30 1 Analog Input: 32 ~ bit with flag 1 (read)
30 2 Analog Input: 16 ~ bit with flag 1 (read)
30 3 Analog Input: 32 ~ bit without flag 1 (read)
30 4 Analog Input: 16 ~ bit without flag 1 (read)
Analog Input: Single ~ prec flt ~ pt with 00, 01 (start ~ stop)
30 5 1 (read)
flag 06 (no range, or all)
32 0 Analog Input Event: Any Variation 1 (read)
07,08 (limited qty)
32 1 Analog Input Event: 32 ~ bit without time 1 (read)
07,08 (limited qty)
32 2 Analog Input Event: 16 ~ bit without time 1 (read)
07,08 (limited qty)
Analog Input Event: Single ~ prec flt ~ pt 06 (no range, or all)
32 5 1 (read)
without time 07,08 (limited qty)
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10 Communication

34 0 Analog Input Deadband: Any Variation 1 (read)
1 (read)
34 1 Analog Input Deadband: 16 ~ bit
2 (write)
17,28 (index)
1 (read)
2 (write)
17,28 (index)
1 (read)
Analog Input Deadband: Single ~ prec flt 06 (no range, or all)
34 3
~ pt 00, 01 (start ~ stop)
2 (write)
17,28 (index)
40 0 Analog Output Status: Any Variation 1 (read)
40 1 Analog Output Status: 32 ~ bit with flag 1 (read)
40 2 Analog Output Status: 16 ~ bit with flag 1 (read)
Analog Output Status: single ~ prec flt ~ 00, 01 (start ~ stop)
40 3 1 (read)
pt with flag 06 (no range, or all)
3 (select)
4 (operate) 17,28 (index)
41 1 Analog Output: 32 ~ bit
5 (direct op)
6 (dir. Op, no ack) 17,28 (index)
3 (select)
41 2 Analog Output: 16 ~ bit
5 (direct op)
3 (select)
41 3 Analog Output: Single ~ prec ft ~ pt
5 (direct op)
1 (read) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
2 (write) 07 (limited qty = 1)
Time and Data: Absolute time at last
50 3 2 (write) 07 (limited qty = 1)
recorded time
Time and Data CTO: Absolute time,
51 1
synchronized
Time and Data CTO: Absolute time,
51 2
unsynchronized
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1 (read)
60 1 Class Objects: Class 0 data 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 2 Class Objects: Class 1 data 20 (enable unsol.)
21 (disable unsol.) 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 3 Class Objects: Class 2 data 20 (enable unsol.)
22 (assign class)
1 (read)
07,08 (limited qty)
60 4 Class Objects : Class 3 data 20 (enable unsol.)
22 (assign class)
Response: Master shall parse\Outstation may issue
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION RESPONSE

1 0 Binary Input: Any Variation
1 1 Binary Input: Packed format 129 (response) 00, 01 (start ~ stop)
1 2 Binary Input: With flags 129 (response) 00, 01 (start ~ stop)
2 0 Binary Input Event: Any Variation
129 (response)
2 1 Binary Input Event: Without time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 2 Binary Input Event: With absolute time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 3 Binary Input Event: With relative time 17, 28 (index)
130 (unsol. resp)
10 0 Binary output: Any Variation
10 0 Binary output: Any Variation
10 1 Binary output: Packed format
Binary Command: Control relay output 129 (response) echo of request
12 1
block (CROB)
30 0 Analog Input: Any Variation
30 1 Analog Input: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
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10 Communication

30 2 Analog Input: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 3 Analog Input: 32 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 4 Analog Input: 16 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
Analog Input: Single ~ prec flt ~ pt with
30 5 129 (response) 00, 01 (start ~ stop)
flag
32 0 Analog Input Event: Any Variation
129 (response)
32 1 Analog Input Event: 32 ~ bit without time 17,28 (index)
130 (unsol. resp)
129 (response)
32 2 Analog Input Event: 16 ~ bit without time 17,28 (index)
130 (unsol. resp)
Analog Input Event: Single ~ prec flt ~ pt 129 (response)
32 5 17,28 (index)
without time 130 (unsol. resp)
34 0 Analog Input Deadband: Any Variation
129 (response) 00, 01 (start ~ stop)
129 (response) 00, 01 (start ~ stop)

Analog Input Deadband: Single ~ prec flt 129 (response) 00, 01 (start ~ stop)
34 3
~ pt
40 0 Analog Output Status: Any Variation
40 1 Analog Output Status: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
40 2 Analog Output Status: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
Analog Output Status: single ~ prec flt ~
40 3 129 (response) 00, 01 (start ~ stop)
pt with flag
Analog Output: 129 (response) echo of request
41 1
32 ~ bit
41 2
16 ~ bit
41 3
Single ~ prec ft ~ pt
129 (response) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
Time and Data: Absolute time at last

50 3
recorded time
Time and Data CTO: Absolute time, 129 (response)
51 1 07 (limited qty = 1)
synchronized 130 (unsol. resp)
Time and Data CTO: Absolute time, 129 (response)
51 2 07 (limited qty = 1)
unsynchronized 130 (unsol. resp)
60 1 Class Objects: Class 0 data
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10 Communication

60 4 Class Objects : Class 3 data
10.4.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user-defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure
by the user.
The user can configure the user-defined communication table through the PCS-Explorer
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.4.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be
configured independently. To the analog outputs, only the attribute “factor” of each analog output
needs to be configured. If the integer mode is adopted for the data formats of analog values (to
“Analog Input”, “Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.),
the analog values will be multiplied by the “factor” respectively to ensure their accuracy. And if the
float mode is adopted for the data formats of analog values, the actual float analog values will be
sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be created.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.4.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.
Information Point Pulse On/Null Pulse On/Close Pulse On/Trip Latch On/Null Latch Off/Null
Remote Control Not supported Close Trip Close Trip
Logic Link Not supported Set Clear Set Clear
Extended Output See following description
To an extended output command, if a selected command is controlled remotely, this command

point will output a high ~ level pulse. The pulse width can be decided by the “On ~ time” in the
related “Binary Command” which is from the DNP3.0 master. If the “On ~ time” is set as “0”, the
Date: 2017-08-17
10 Communication
default pulse width is 500ms.
10.4.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages want to be transmitted, the related logic setting should be set as “1” or the
DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function Code
20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference value of
the “Analog Input” is greater than the “deadband” value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as “0” or through
the “Function Code 21” (Disable Unsolicited Messages).
10.4.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22”
(Assign Class).
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10 Communication
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11 Installation
11 Installation
Table of Contents
11 Installation ...................................................................................... 11-a
11.1 Overview ...................................................................................................... 11-1
11.2 Safety Information ....................................................................................... 11-1
11.3 Check Shipment .......................................................................................... 11-2
11.4 Material and Tools Required ....................................................................... 11-2
11.5 Device Location and Ambient Conditions ................................................. 11-2
11.6 Mechanical Installation ............................................................................... 11-3
11.7 Electrical Installation and Wiring ............................................................... 11-4
11.7.1 Grounding Guidelines ...................................................................................................... 11-4
11.7.2 Cubicle Grounding ........................................................................................................... 11-4
11.7.3 Ground Connection on the Device ................................................................................... 11-5
11.7.4 Grounding Strips and their Installation ............................................................................. 11-5
11.7.5 Guidelines for Wiring ........................................................................................................ 11-6
11.7.6 Wiring for Electrical Cables .............................................................................................. 11-6
List of Figures
Figure 11.6-1 Dimensions of full width PCS-9705 (unit: mm)............................................... 11-3
Figure 11.6-3 Demonstration of plugging a board into its corresponding slot .................. 11-3
Figure 11.7-1 Cubicle grounding system ............................................................................... 11-5
Figure 11.7-2 Ground terminal of this device......................................................................... 11-5
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7
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11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
11.2 Safety Information

Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the
equipment.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To
this end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
NOTICE!
Jumper links may ONLY be changed on a workbench for electronic equipment.

Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
NOTICE!
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
 Should boards have to be removed from this device installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
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11 Installation
 Only hold electronic boards at the edges, taking care not to touch the components.
 Only works on the board which has been removed from the cubicle on a workbench designed
for electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
 Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Check Shipment

Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required

The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this device is mounted in cubicles).
11.5 Device Location and Ambient Conditions

NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
 The location should not be exposed to excessive air pollution (dust, aggressive substances).
 Surge voltages of high amplitude and short rise time, extreme changes of temperature, high
levels of humidity, severe vibration and strong induced magnetic fields should be avoided as
far as possible.
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 Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
11.6 Mechanical Installation

NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
This device is made of a single layer 4U chassis. Following figure shows the dimensions and
cut-out size in the cubicle of this device for reference in mounting.
482.6 290
465
Front Side
101.6
177
465±0.2
451+0.4
-0
4-Φ 6.8
101.6±0.1
Cut-Out
179 -0
+0.4
Figure 11.6-1 Dimensions of full width PCS-9705 (unit: mm)
The Gollowing figure shows the installation way of a module being plugged into a corresponding
slot.
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot
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11 Installation
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring

11.7.1 Grounding Guidelines
NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding

The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
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Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device

There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main
thing is that the device is only grounded at one point. Grounding loops from unit to unit are not
allowed.
There are some ground terminals on some connectors of this device, and the sign is “GND”. All
the ground terminals are connected in the cabinet of this device. Therefore, the ground terminal
on the rear panel (see Figure 11.7-2) is the only ground terminal of this device.
Figure 11.7-2 Ground terminal of this device
11.7.4 Grounding Strips and their Installation

High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round
copper conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
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The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring

There are several types of cables that are used in the connection of this relay: braided copper
cable, serial communication cable etc. Recommendation of each cable:
 Grounding: braided copper cable, 2.5mm2 ~ 6.0mm 2
 Power supply, binary inputs & outputs: stranded conductor, 1.0mm 2 ~ 2.5mm 2
 AC voltage inputs: stranded conductor, 1.5mm 2
 AC current inputs: stranded conductor, 2.5mm 2
 Serial communication: 4-core shielded cable
 Ethernet communication: 4-pair twisted shielded cable (category 5E)
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously
high voltage that cause death.
A female connector is used for connecting the wires with it, and then a female connector plugs
into a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
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01 02
03 04
Tighten 05 06
07 08
09 10
11 12
01
13 14
15 16
17 18
19 20
21 22
23 24
Figure 11.7-4 Glancing demo about the wiring for electrical cables
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12 Commissioning
Table of Contents
12 Commissioning ............................................................................ 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-2
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-3
12.5.1 With the Device De-energized ......................................................................................... 12-3
12.5.2 With the Device Energized .............................................................................................. 12-5
12.5.3 On-load Checks ............................................................................................................... 12-7
12.6 Final Checks ................................................................................................ 12-7
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12.1 Overview
This device is numerical in their design, implementing all functions in software. The device
employs a high degree self-checking so in the unlikely event of a failure, it will give an alarm.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of
the safety and technical data sections and the ratings on the equipment’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current

leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This
personnel MUST be familiar with all safety regulations and service procedures
described in this manual. During operating of electrical device, certain part of the
device is under high voltage. Severe personal injury and significant device damage
could result from improper behavior.
Particular attention must be drawn to the following:
 The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
 Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
 Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
 The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
 When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
may be close commands to the circuit breakers and other primary switches are disconnected
from the device unless expressly stated.
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12.3 Commission Tools

NOTICE!
Modern test set may contain many of the above features in one unit.
 Minimum equipment required:
 Multifunctional dynamic current and voltage injection test set with interval timer.
 Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and
0~250V respectively.
 Continuity tester (if not included in the multimeter).
 Phase angle meter.
 Phase rotation meter.
 Optional equipment:
 An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
 A portable PC, with appropriate software (this enables the rear communications port to
be tested, if this is to be used, and will also save considerable time during
commissioning).
 EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being
tested).
 Tester: HELP-9000.
12.4 Setting Familiarization

When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this device is contained in the chapters 3 and 7.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 SAS software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
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12.5 Product Checks

These product checks cover all aspects of the device which should be checked to ensure that it
has not been physically damaged prior to commissioning, is functioning correctly and all input
quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the device prior to commissioning, it is
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the device itself via printer or manually creating a setting record.
12.5.1 With the Device De-energized
This device is fully numerical and the hardware is continuously monitored. Commissioning tests
can be kept to a minimum and need only include hardware tests and conjunctive tests. The
function tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
 Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
 User interfaces test
 Binary input circuits and output circuits test
 AC input circuits test
 Function tests
These tests are performed for the following functions that are fully software-based.
 Measuring elements test
 Timers test
 Conjunctive tests
The tests are performed after the device is connected with the primary equipment and other
external equipment.
 On load test.
 Phase sequence check and polarity check.
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the device case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed are
necessary.
 Device panel
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Carefully examine the device panel, device inside and other parts inside to see that no
physical damage has occurred since installation.
 Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
 Device plug-in modules
Check each plug-in module of the equipment on the panel to make sure that they are well
installed into the equipment without any screw loosened.
 Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
 Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons
work normally and smoothly.
12.5.1.2 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
 Voltage transformer circuits
 Current transformer circuits
 DC power supply
 Optic-isolated control inputs
 Output contacts
 Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this device, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly
reconnected to the device.
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12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant device diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
the chapter 2.
The device only can be operated under the auxiliary power supply depending on the device’s
nominal power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the device, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Device Energized

The following groups of checks verify that the device hardware and software is functioning
correctly and should be carried out with the auxiliary supply applied to the device.
The current and voltage transformer connections must remain isolated from the device for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the device to DC power supply correctly and turn the device on. Check program version
and forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “Clock”.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date
will be maintained. Therefore when the auxiliary supply is restored the time and date will be
correct and not need to set again.
To test this, remove the auxiliary supply from the device for approximately 30s. After being
re-energized, the time and date should be correct.
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12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the device is healthy.
The device has latched signal devices which remember the state of the trip, auto-reclose when
the device was last energized from an auxiliary supply. Therefore these indicators may also
illuminate when the auxiliary supply is applied. If any of these LEDs are on then they should be
reset before proceeding with further testing. If the LED successfully reset, the LED goes out.
There is no testing required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.6 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.7 Testing Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
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The status of each binary input can be viewed using device menu. Sign “1” denotes an energized
input and sign “0” denotes a de-energized input.
12.5.3 On-load Checks

The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the device in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and
voltage transformer wiring.
12.6 Final Checks

After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the device in order to perform the wiring
verification tests, it should be ensured that all connections are replaced in accordance with the
relevant external connection or scheme diagram.
Ensure that the device has been restored to service.
If the device is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the device is put into service.
Ensure that all event records, fault records and alarms have been cleared and LED’s has been
reset before leaving the device.
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13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................. 13-1
13.1 Appearance Check ...................................................................................... 13-1
13.2 Failure Tracing and Repair ......................................................................... 13-1
13.3 Replacing Failed Modules .......................................................................... 13-2
13.4 Cleaning ....................................................................................................... 13-3
13.5 Storage ......................................................................................................... 13-3

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13 Maintenance
This device is designed to require no special maintenance. All measurement and signal
processing circuit are fully solid state. All input modules are also fully solid state. The output relays
are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals
are not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.1 Appearance Check

 The device case should be clean without any dust stratification. Case cover should be sealed
well. No component has any mechanical damage and distortion, and they should be firmly
fixed in the case. Device terminals should be in good condition. The keys on the front panel
with very good feeling can be operated flexibly.
 It is only allowed to plug or withdraw device board when the supply is reliably switched off.
Never allow the CT secondary circuit connected to this equipment to be opened while the
primary system is live when withdrawing an AC module. Never try to insert or withdraw the
device board when it is unnecessary.
 Check weld spots on PCB whether they are well soldered without any rosin joint. All dual
inline components must be well plugged.
13.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “Superv State” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
 Test circuit connections are correct
 Modules are securely inserted in position
 Correct DC power voltage is applied
 Correct AC inputs are applied
 Test procedures comply with those stated in the manual

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13 Maintenance
13.3 Replacing Failed Modules
WARNING!
Module can ONLY be replaced while the device power supply is switched off.
ONLY appropriately trained and qualified personnel can perform the replacement by
strictly observing the precautions against electrostatic discharge.
WARNING!
Five seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Take anti-static measures such as wearing an earthed wristband and placing modules
on an earthed conductive mat when handling a module. Otherwise, electronic
components could be damaged.
CAUTION!
Check the device configuration after a replacement of module. Unintended operation of

device may occur.
If the failure is identified to be in the device module and the user has spare modules, the user can
recover the device by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level
is not recommended.
Check that the replacement module has an identical module name (AI, PWR, MON, BI, BO, etc.)
and hardware type-form as the removed module. Furthermore, the MON module replaced should
have the same software version. In addition, the AI and PWR module replaced should have the
same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Information”->“Version Info”.
 Replacing a module
1. Switch off the DC power supply
2. Disconnect the trip outputs
3. Short circuit all AC current inputs and disconnect all AC voltage inputs
4. Unscrew the module connector
5. Unplug the connector from the target module.
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13 Maintenance
6. Unscrew the module.
7. Pull out the module
8. Inset the replacement module in the reverser procedure.
9. After replacing the MON module, input the application-specific setting values again.
 Replacing the Human Machine Interface Module (front panel)
1. Open the device front panel
2. Unplug the ribbon cable on the front panel by pushing the catch outside.
3. Detach the HMI module from the device
4. Attach the replacement module in the reverse procedure.
13.4 Cleaning
Before cleaning the device, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.5 Storage
The spare device or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40°C to +70°C, but the temperature of from 0°C
to +40°C is recommended for long-term storage.

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Table of Contents
14 Decommissioning and Disposal ................................................. 14-a
14.1 Decommissioning ....................................................................................... 14-1
14.2 Disposal ....................................................................................................... 14-1
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14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1. Switching off
To switch off this device, switch off the external miniature circuit breaker of the power supply.
2. Disconnecting Cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3. Dismantling
The device rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.
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In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
R1.00 R1.00 2016-09-22 Form the original manual.
 Add CB wear statistic function
 Add frequency protection
 Add voltage selection function for auto-reclosing
 Update trip logic
 Update alarm list
R1.00 R1.10 R2.00.004 2017-08-18
 Update waveform recording function
 Update hardware description and module options
 Update setting list
 Update menu structure
 Update communication protocol
Date: 2017-08-17

Date: 2017-08-17

PCS-9705 - X - Instruction Manual - EN - Customized - ECKF162122 - R1.10 Bay Control N Protection Unit

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PCS-9705 - X - Instruction Manual - EN - Customized - ECKF162122 - R1.10 Bay Control N Protection Unit

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Bay Control & Protection Unit

NR Electric Co., Ltd.

Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

Instructions and Warnings

PCS-9705 Bay Control & Protection Unit i

Securely earthed the earthing terminal of the device.

ii PCS-9705 Bay Control & Protection Unit

 Printed circuit board

Carefully handle connection cables without applying excessive force.

The firmware may be upgraded to add new features or enhance/modify existing

Copyright © 2017 NR. All rights reserved.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888

P/N: ZL_PCS-9705_X_Instruction Manual_EN_Customized_ECKF162122 Version: R1.10

PCS-9705 Bay Control & Protection Unit iii

All contents provided by this manual are summarized as below.

8 Human Machine Interface

iv PCS-9705 Bay Control & Protection Unit

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols may be used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

XXX Output signal

PCS-9705 Bay Control & Protection Unit v

IDMT Timer (inverse-time characteristic)

Symbol Corresponding Relationship

vi PCS-9705 Bay Control & Protection Unit

1.2.2 Circuit Breaker Protection .................................................................................................... 1-2

1.2.3 Monitoring ............................................................................................................................ 1-2

1.2.4 Auxiliary Function ................................................................................................................. 1-2

1.2.5 Communication .................................................................................................................... 1-3

1.3 Feature ............................................................................................................. 1-3

PCS-9705 Bay Control & Protection Unit 1-a

1-b PCS-9705 Bay Control & Protection Unit

Ethernet cable Remote Control Center

Clock synchronization bus

100M/1000M Ethernet MMS/GOOSE Network

Clock Synchronization Bus

PCS-9705 PCS-900 PCS-9600 PCS-9705 PCS-900 PCS-9600

PCS-221 PCS-222 PCS-221 PCS-222

Figure 1.1-1 Typical application

PCS-9705 Bay Control & Protection Unit 1-1

 Configurable binary input

 Binary output for switch control

 CB closing synchronism check (25)

 Programmable interlocking logic

 Programmable LED indicators

1.2.2 Circuit Breaker Protection

 Pole discrepancy protection (62PD)

 Phase overcurrent protection (50/51P)

 Earth fault protection (50/51G)

 Frequency protection (81)

 DC power supply supervision

 VT circuit supervision (VTS)

 CT circuit supervision (CTS)

1.2.4 Auxiliary Function