PCS-921

PCS-921
Breaker Failure Relay

Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety

The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
Instructions and Warnings

The following indicators and standard definitions are used:
PCS-921 Breaker Failure Relay i

Date: 2017-12-12
Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
environment free of abnormal vibration.
ii PCS-921 Breaker Failure Relay

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Preface
 Ratings
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing

features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2017 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD. Tel: +86-25-87178888

Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrec.com/en
P/N: ZL_PCS-921_X_Instruction Manual_EN_Overseas General_X Version: R2.05
PCS-921 Breaker Failure Relay iii

Date: 2017-12-12
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Measurement and Recording

Introduce the measurment and recording function of this relay.
6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module, typical wiring is provided.
7 Settings
List settings including system settings, communication settings and etc.
8 Human Machine Interface

Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Brief introduction of configurable functions of the device and all configurable signals are listed.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
11 Installation
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Date: 2017-12-12
Preface
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal

A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History

List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
SIG Input of binary signal except those signals via opto-coupler
OTH Input of other signal
PCS-921 Breaker Failure Relay v

Date: 2017-12-12
Preface
XXX Output signal
Timer
t
Time (optional definite-time or inverse-time characteristic)
t
10ms 2ms
Timer [delay pickup (10ms), delay dropoff (2ms), non-settable]
[XXX] 0ms
Timer (delay pickup, settable)
0ms [XXX]
Timer (delay drop off, settable)
[XXX] [XXX]
Timer (delay pickup, delay drop off, settable)
IDMT Timer (inverse-time characteristic)
---xxx is the symbol
Symbol Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
vi PCS-921 Breaker Failure Relay

Date: 2017-12-12
1 Introduction
1 Introduction
Table of Contents
1.1 Application....................................................................................................... 1-1

1.2 Function ........................................................................................................... 1-2
1.3 Features ........................................................................................................... 1-4
List of Figures
Figure 1.1-1 Function diagram of PCS-921............................................................................... 1-1
PCS-921 Breaker Failure Relay 1-a

Date: 2016-07-15
1 Introduction
1-b PCS-921 Breaker Failure Relay

Date: 2016-07-15
1 Introduction
1.1 Application
The PCS-921 is a digital breaker protection device and can be applied for all kinds of busbar
arrangement. By default, breaker failure protection, voltage protection, frequency protection,
overcurrent protection, dead zone protection, pole discrepancy protection and automatic reclosing
function is taken as the standard function of PCS-921.
PCS-921 supports configurable binary inputs, binary outputs, LEDs and IEC 61850 protocol.
Bus 1
PCS-921
52
Line 1 50BF 62PD 50/51G 50/51P 59 27 59G
59Q 81 50DZ 25 79 50/51Q
52
Line 2
52
Bus 2
Figure 1.1-1 Function diagram of PCS-921
No. Function ANSI

1. Breaker failure protection 50BF
2. Three stages overvoltage protection 59
3. Negative sequence overvoltage protection 59Q
4. Three stages residual overvoltage protection 59G
5. Three stages undervoltage protection 27
6. Four stages negative sequence overcurrent protection 50/51Q
7. Frequency protection 81
8. Pole discrepancy protection 62PD
9. Four stages earth-fault protection 50/51G
10. Four stages phase overcurrent protection 50/51P
11. Dead zone protection 50DZ
12. Synchro-checking 25
13. Auto- reclosing 79
PCS-921 Breaker Failure Relay 1-1

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1 Introduction
1.2 Function
1. Protection Function
 Breaker failure protection (50BF)
 Three stages overvoltage protection (59)
 Three stages undervoltage protection (27)
 Negative sequence overvoltage protection (59Q)
 Residual overvoltage protection (59G)
 Frequency protection (81)
 Pole discrepancy protection (62PD)
 Dead zone protection (50DZ)
 Four stages overcurrent protection (50/51P)
 Four stages earth-fault protection (50/51G)
 Four stages negative sequence overcurrent protection (50/51Q)
2. Measurement and control function
 Remote control (open and closing)
 Synchronism check for remote and manual closing
 Energy metering (active and reactive energy are calculated in import respectively export
direction)
3. Logic
 User programmable logic
4. Additional function
 VT circuit supervision (VTS)
 CT circuit supervision (CTS)
 Self diagnostic
 DC power supply supervision
 Voltage and current drift auto regulation
 Auto-reclosing (79)
 Synchro-checking (25)
 Event recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
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1 Introduction
 Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
 Four kinds of clock synchronization methods
 Conventional
 PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
 IRIG-B (RS-485): IRIG-B via RS-485 differential level
 PPM (DIN): Pulse per minute (PPM) via the optical coupler
 PPS (DIN): Pulse per second (PPS) via the optical coupler
 SAS
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103): Clock messages through IEC103 protocol
 Advanced
 IEEE1588: Clock message via IEEE1588
 IRIG-B (Fiber): IRIG-B via optical-fibre interface
 PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface
 NoTimeSyn
5. Monitoring
 Number of circuit breaker operation (single-phase tripping, three-phase tripping and

reclosing)
 Frequency
6. Communication
 Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol
 1 RS-485 communication rear port for clock synchronization
 Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
 Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP
 GOOSE and SV communication function (optional NET-DSP plug-in module)
7. User Interface
 Friendly HMI interface with LCD and 9-button keypad on the front panel.

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1 Introduction
 1 front multiplex RJ45 port for testing and setting
 1 RS-232 or RS-485 rear ports for printer
 Language switchover—English+ selected language
 Auxiliary software—PCS-Explorer
1.3 Features
 The intelligent device integrated with protection, control and monitor provides powerful
protection function, flexible protection configuration, user programmable logic and
configurable binary input and binary output, which can meet with various application
requirements.
 High-performance hardware platform and modularized design, MCU (management control

unit)+DSP (digital signal processor). MCU manages general fault detector element and DSP
manages protection and metering. Their data acquisition system is completely independent in
electronic circuit. DC power supply of output relay is controlled by the operation of fault
detector element operates, this prevents maloperation due to error from ADC or damage of
any apparatus.
 Flexible automatic reclosure supports various initiation modes and check modes.
 Multiple setting groups with password protection and setting value saved permanently before
modification.
 Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.

Date: 2016-07-15
2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1

2.1.1 AC Current Input .................................................................................................................. 2-1
2.1.2 AC Voltage Input .................................................................................................................. 2-1
2.1.3 Power Supply....................................................................................................................... 2-1
2.1.4 Binary Input .......................................................................................................................... 2-2
2.1.5 Binary Output ....................................................................................................................... 2-2
2.2 Mechanical Specifications.............................................................................. 2-3

2.3 Ambient Temperature and Humidity Range .................................................. 2-4
2.4 Communication Port ....................................................................................... 2-4
2.4.1 EIA-485 Port ........................................................................................................................ 2-4
2.4.2 Ethernet Port ........................................................................................................................ 2-4
2.4.3 Optical Fibre Port ................................................................................................................. 2-4
2.4.4 Print Port .............................................................................................................................. 2-5
2.4.5 Clock Synchronization Port ................................................................................................. 2-5
2.5 Type Tests ........................................................................................................ 2-5

2.5.1 Environmental Tests............................................................................................................. 2-5
2.5.2 Mechanical Tests ................................................................................................................. 2-5
2.5.3 Insulation Tests .................................................................................................................... 2-5
2.5.4 Electromagnetic Compatibility ............................................................................................. 2-6
2.6 Certifications ................................................................................................... 2-7

2.7 Terminals ......................................................................................................... 2-7
2.8 Measurement Scope and Accuracy ............................................................... 2-7
2.9 Management Function .................................................................................... 2-8
2.9.1 Control Performance............................................................................................................ 2-8
2.9.2 Clock Performance .............................................................................................................. 2-8
PCS-921 Breaker Failure Protection 2-a

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2 Technical Data
2.9.3 Fault and Disturbance Recording ........................................................................................ 2-8
2.9.4 Binary Input Signal............................................................................................................... 2-8
2.10 Protective Functions..................................................................................... 2-8

2.10.1 Fault Detector .................................................................................................................... 2-8
2.10.2 Phase Overcurrent Protection ........................................................................................... 2-8
2.10.3 Earth Fault Protection ........................................................................................................ 2-9
2.10.4 Overvoltage Protection ...................................................................................................... 2-9
2.10.5 Negative-sequence Overvoltage Protection ...................................................................... 2-9
2.10.6 Residual Overvoltage Protection ....................................................................................... 2-9
2.10.7 Undervoltage Protection .................................................................................................... 2-9
2.10.8 Negative-sequence Overcurrent Protection .................................................................... 2-10
2.10.9 Overfrequency Protection ................................................................................................ 2-10
2.10.10 Underfrequency Protection ............................................................................................ 2-10
2.10.11 Dead Zone Protection .................................................................................................... 2-10
2.10.12 Breaker Failure Protection ............................................................................................. 2-10
2.10.13 Pole Discrepancy Protection ..........................................................................................2-11
2.10.14 Auto-reclosing .................................................................................................................2-11
2-b PCS-921 Breaker Failure Protection

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2 Technical Data
2.1 Electrical Specifications

NOTICE!
“System phase sequence”, which can be set by PCS-Explorer, this setting informs the
device of the actual system phase sequence, either ABC or ACB. CT and VT inputs on
the device, labeled as A, B and C, must be connected to system phase A, B and C for
correct operation.
2.1.1 AC Current Input

Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated current (In) 1A 5A
Linear to 0.05In~40In (It should measure current without beyond full scale
against 20 times of related current and value of DC offset by 100%.)
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden < 0.15VA/phase @In < 0.25VA/phase @In
Number Up to 6 current input according to various applications
2.1.2 AC Voltage Input

Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated voltage (Un) 100V~130V
Linear to 1V~170V
Thermal withstand
-continuously 200V
-10s 260V
-1s 300V
Burden at rated < 0.20VA/phase @Un
Number Up to 6 voltage input according to various applications
2.1.3 Power Supply

Standard IEC 60255-11:2008
Rated voltage 110Vdc/125Vdc/220Vdc/250Vdc or 110/220Vac
Permissible voltage range 88~300Vdc or 88V-265Vac
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <30W
Operating condition <35W
PCS-921 Breaker Failure Protection 2-1

Date: 2016-07-15
2 Technical Data
2.1.4 Binary Input

1. Settable pickup voltage and dropoff voltage
Rated voltage 110Vdc 220Vdc

Rated current drain 1.1mA 2.2mA
On value 85-132Vdc (default set) 170-264Vdc (default set)
Off value <66Vdc <132Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Up to 36 binary input according to various hardware configurations
2. Fixed pickup voltage and dropoff voltage
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc

Rated current drain 1.1mA 1.25mA 2.2mA 2.5mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 175-300Vdc
Off value <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Number Up to 36 binary input according to various hardware configurations
2.1.5 Binary Output

1. Tripping/signaling contact
Output mode Potential free contact

Maximal system voltage 380Vac, 250Vdc
Continuous carry 8A
Pickup time (Typical Value) <5ms
Dropoff time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
12A@3s
18A@1s
Short duration current
24A@0.5s
40A@0.2s
Durability (Loaded contact) 10000 operations
Number Up to 55 binary output according to various hardware configurations
2. Heavy-capacity tripping contact
2-2 PCS-921 Breaker Failure Protection

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2 Technical Data
Maximal system voltage 250Vdc

Continuous carry 10A
Pickup time <1ms
Dropoff time <10ms
Breaking capacity (L/R=40ms) 10A
15A@3s
30A@1s
3. Fast signaling contact

Maximal system voltage 380Vac, 250Vdc
Continuous carry 5A
Pickup time <1ms
Dropoff time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=0ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
8A@3s
12A@1s
16A@0.5s
30A@0.2s
2.2 Mechanical Specifications

Mounting Way Flush mounted
Chassis color Silver grey
Weight per device Approx. 15kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated frontplate
Protection class
Front side IP51
Other sides IP30
Rear side, connection terminals IP20

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2 Technical Data
2.3 Ambient Temperature and Humidity Range

Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage temperature
-40°C to +70°C
range
Permissible humidity 5%-95%, without condensation
Pollution degree 2
Altitude <3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Transmission distance <500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port

Connector type RJ-45 ST (Multi mode)
Transmission rate 100Mbits/s
Transmission standard 100Base-TX 100Base-FX
Transmission distance <100m <2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fibre Port

2.4.3.1 For Station Level
Characteristic Glass optical fiber

Connector type ST
Fibre type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.3.2 For Process Level

Connector type LC

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2 Technical Data
Transmission distance <2km

Wave length 1310nm
Transmission power Min. -20.0dBm
Margin Min +3.0dB
2.4.3.3 For Synchronization Port

Connector type ST
Wave length 850nm
Margin Min +3.0dB
2.4.4 Print Port

Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
®
Printer type EPSON 300K printer
2.4.5 Clock Synchronization Port

Type RS-485
Transmission distance <500m
Maximal capacity 32
Timing standard PPS, IRIG-B
2.5 Type Tests

2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007

Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration IEC 60255-21-1:1988 Class I

Shock and bump IEC 60255-21-2:1988 Class I
2.5.3 Insulation Tests

Standard IEC 60255-27-2013
Test voltage 2.8kV, dc, 1min
Dielectric tests
Test voltage 2kV, ac, 1min
Impulse voltage tests Impulse voltage 5kV (the rated insulation voltage > 63V)

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2 Technical Data
Impulse voltage 1kV (the rated insulation voltage < 63V)

Overvoltage category Ⅲ
Insulation resistance
Isolation resistance >100MΩ@500VdC
measurements
2.5.4 Electromagnetic Compatibility

IEC 60255-26-2013
1MHz burst disturbance test Common mode: class III 2.5kV
Differential mode: class III 1.0kV
IEC 60255-26-2013 class IV
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26-2013 class III
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-26-2013
Power supply, I/O, Earth: class IV, 4kV, 5kHz/15ms,
Fast transient disturbance tests
100kHz/0.75ms
Communication terminals: class IV, 2kV, 5kHz/15ms, 100kHz/0.75ms
IEC 60255-26-2013
Power supply, AC input, I/O port: class IV, 1.2/50us surge
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26-2013
Conducted RF Electromagnetic Power supply, AC, I/O, Communication terminal: Class III, 10Vrms, 150
Disturbance kHz~80MHz
Spot frequency: 27MHz/68MHz
Power Frequency Magnetic Field IEC 61000-4-8:2001
Immunity Class V, 100A/m (continuously), 1000A/m for 1~3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
Class V, 6.4/16μs, 1000A/m
Damped oscillatory magnetic field IEC 61000-4-10:2001
immunity Class V, 100kHz & 1MHz–100A/m

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2 Technical Data
Auxiliary power supply performance IEC 60255-26-2013

- Voltage dips Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions 100ms for interruption without rebooting
2.6 Certifications
 ISO9001:2008
 ISO14001:2004
 OHSAS18001:2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 Products safety(PS): 2014/35/EU, EN60255-27:2014
2.7 Terminals
Connection Type Wire Size
Crimp terminals, 1.5mm ~4.0mm2 lead
2
2
AC current If using 4.0mm lead, only dedicated terminal cable lug provided by NR
can be adopted.
AC voltage Crimp terminals, 1.0mm2~2.5mm2 lead
Power supply Crimp terminals, 1.0mm2~2.5mm2 lead
2 2
Contact I/O Crimp terminals, 1.0mm ~2.5mm lead
Grounding (Earthing) Connection BVR type, 2.5mm²~6.0mm2 lead
2.8 Measurement Scope and Accuracy

Item Range Accuracy
Phase range 0° ~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
Currents from protection measurement current transformers
≤ 2.0% of rating (0.05~1.00In)
Current 0.05~5.00In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50Un
≤ 1.0% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Active power (W)
0.05~5.00In ≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Reactive power (VAr)

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2 Technical Data
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)

Apparent power (VA)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Energy (Wh)
0.05~1.50Un ≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
Energy (VAh)
2.9 Management Function

2.9.1 Control Performance
Control mode Local or remote

Accuracy of local control ≤ 1s
Accuracy of remote control ≤ 3s
2.9.2 Clock Performance
Real time clock accuracy ≤ 3s/day

Accuracy of GPS synchronization ≤ 1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.9.3 Fault and Disturbance Recording
Maximum duration 10000 sampled points (24 sampled points per cycle)
Recording position 10 cycles before pickup of trigger element
2.9.4 Binary Input Signal
Resolution of binary input signal ≤ 1ms

Binary input mode Potential-free contact
Resolution of SOE ≤ 2ms
2.10 Protective Functions

2.10.1 Fault Detector
2.10.1.1 DPFC Current Element
Setting range 0.050In~30.000In (A)

Accuracy ≤2.5% of setting or 0.02In whichever is greater
2.10.1.2 Residual Current Element

2.10.2 Phase Overcurrent Protection


Date: 2016-07-15
2 Technical Data
Time delay 0.000~20.000s

Accuracy ≤1% of Setting+30ms (at 2 times current setting)
2.10.3 Earth Fault Protection

Time delay 0.000~20.000 (s)
2.10.4 Overvoltage Protection

Setting range Un~2Unn (V)
Accuracy ≤2.5% of setting or 0.01Un, whichever is greater
Resetting ratio 95%
Time delay 0.000~30.000 (s)
Accuracy (definite-time characteristic) ≤1% of Setting+30ms (at 1.2 times voltage setting)
≤2.5% operating time or 30ms, whichever is greater
Accuracy (inverse-time characteristic)
(for voltage between 1.2 and 2 multiples of pickup)
2.10.5 Negative-sequence Overvoltage Protection

Setting range 0~Un (V)
Resetting ratio 95%
Time delay 0.000~30.000 (s)
Accuracy (definite-time characteristic) ≤1% of Setting+30ms (at 1.2 times voltage setting)
2.10.6 Residual Overvoltage Protection

Setting range 0~Unn (V)
Accuracy ≤2.5% of setting or 0.1V, whichever is greater
Resetting ratio 95%
Time delay 0.000~3600.000 (s)
Accuracy (definite-time characteristic) ≤1%×Setting+30ms (at 1.2 times voltage setting)
≤2.5% of operating time or 30ms, whichever is greater
Accuracy (inverse-time characteristic) (for residual voltage between 1.2 and 2 multiples of
pickup)
2.10.7 Undervoltage Protection

Setting range 0~Unn (V)
Resetting ratio 105%
Time delay 0.000~30.000 (s)
Accuracy (definite-time characteristic) ≤1%Setting+30ms (at 1.2 times voltage setting)
(for voltage between 0.5 and 0.8 multiples of pickup)

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2 Technical Data
2.10.8 Negative-sequence Overcurrent Protection

Accuracy ≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio 95%
Time delay 0.000~20.000 (s)
Accuracy (definite-time characteristic) ≤1% of Setting+30ms (at 2 times current setting)
(for current between 1.2 and 20 multiples of pickup)
2.10.9 Overfrequency Protection

Setting range 50.00~65.00 (Hz)
Accuracy ≤ 0.02Hz
Resetting ratio 95%
Time delay 0.000~20.000 (s)
Accuracy ≤1%Setting+30ms (at 1.2 times frequency setting)
2.10.10 Underfrequency Protection

Setting range 45.00~ 60.00 (Hz)
Accuracy ≤ 0.02Hz
Resetting ratio 105%
Time delay 0.000s ~ 30.000 (s)
Accuracy ≤1%Setting+30ms (at 0.8 times frequency setting)
df/dt blocking setting range 0.200~20.000 (Hz/s)
Accuracy ≤ 0.02Hz/s
2.10.11 Dead Zone Protection

Setting range 0.050In~30.000In
Accuracy ≤2.5% or 0.02In whichever is greater
Time delay 0.000~10.000s
Accuracy ≤1% of Setting +30ms
2.10.12 Breaker Failure Protection

Pick-up time <20ms
Drop-off time <20ms
Setting range of phase current 0.050In~30.000In
Setting range of residual current 0.050In~30.000In
Setting range of negative-sequence current 0.050In~30.000In
Time delay (first) 0.000~10.000s
Time delay (second) 0.000~10.000s

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2 Technical Data
2.10.13 Pole Discrepancy Protection

Setting range (residual current) 0.050In~30.000In (A)
Setting range (negative-sequence current) 0.050In~30.000In (A)
Accuracy ≤2.5% of setting 0.02In whichever is greater
Resetting ratio 95%
Time delay 0.000~600.000 (s)
2.10.14 Auto-reclosing
Phase difference setting range 0~89 (Deg)
Accuracy 2.0Deg
0.02Un~0.8Un (V)
Voltage difference setting range
(Un:Secondary rated phase-to-ground voltage)
Accuracy Max(0.01Un, 2.5%)
Frequency difference setting range 0.02~1 (Hz)
Accuracy 0.01Hz
Operating time of synchronism check ≤1%Setting+20ms
Operating time of energizing check ≤1%Setting+20ms
Operating time of auto-reclosing ≤1%Setting+20ms

Date: 2016-07-15
2 Technical Data

Date: 2016-07-15
3 Operation Theory
3 Operation Theory
Table of Contents
3.1 System Parameters ......................................................................................... 3-1

3.1.1 General Application.............................................................................................................. 3-1
3.1.2 Function Description ............................................................................................................ 3-1
3.1.3 Settings ................................................................................................................................ 3-1
3.2 Circuit Breaker Position Supervision ............................................................ 3-1

3.2.3 Function Block Diagram ...................................................................................................... 3-2
3.2.4 I/O Signals ........................................................................................................................... 3-3
3.2.5 Logic .................................................................................................................................... 3-4
3.2.6 Settings ................................................................................................................................ 3-4
3.3 Fault Detector (FD) .......................................................................................... 3-5

3.3.2 Fault Detector in Fault Detector DSP .................................................................................. 3-5
3.3.3 Protection Fault Detector in Protection Calculation DSP .................................................... 3-8
3.3.4 Function Block Diagram ...................................................................................................... 3-9
3.3.5 I/O Signals ........................................................................................................................... 3-9
3.3.6 Logic .................................................................................................................................... 3-9
3.3.7 Settings ................................................................................................................................ 3-9
3.4 Auxiliary Element .......................................................................................... 3-10

3.4.1 General Application............................................................................................................ 3-10
3.4.2 Function Description .......................................................................................................... 3-10
3.4.3 Function Block Diagram .................................................................................................... 3-12
3.4.4 I/O Signals ......................................................................................................................... 3-13
3.4.5 Logic .................................................................................................................................. 3-15

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3 Operation Theory
3.4.6 Settings .............................................................................................................................. 3-18
3.5 Current Direction........................................................................................... 3-20

3.5.4 I/O Signals ......................................................................................................................... 3-25
3.5.5 Settings .............................................................................................................................. 3-26
3.6 Phase Overcurrent Protection ..................................................................... 3-26

3.6.4 I/O Signals ......................................................................................................................... 3-29
3.6.5 Logic .................................................................................................................................. 3-30
3.6.6 Settings .............................................................................................................................. 3-30
3.7 Earth Fault Protection................................................................................... 3-34

3.7.4 I/O Signals ......................................................................................................................... 3-37
3.7.5 Logic .................................................................................................................................. 3-38
3.7.6 Settings .............................................................................................................................. 3-40
3.8 Dead Zone Protection ................................................................................... 3-45

3.8.3 Protection Principle ............................................................................................................ 3-45
3.8.5 I/O Signal ........................................................................................................................... 3-45
3.8.6 Logic .................................................................................................................................. 3-46
3.8.7 Settings .............................................................................................................................. 3-46
3.9 Voltage Protection ......................................................................................... 3-46

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3 Operation Theory
3.9.1 Overvoltage Protection ...................................................................................................... 3-47
3.9.2 Negative Sequence Overvoltage Protection ..................................................................... 3-54
3.9.3 Residual Overvoltage Protection ....................................................................................... 3-56
3.9.4 Undervoltage Protection .................................................................................................... 3-61
3.10 Negative-sequence Overcurrent Protection ............................................. 3-70

3.10.1 General Application.......................................................................................................... 3-70
3.10.2 Function Description ........................................................................................................ 3-70
3.10.3 Function Block Diagram .................................................................................................. 3-72
3.10.4 I/O Signals ....................................................................................................................... 3-72
3.10.5 Logic ................................................................................................................................ 3-73
3.10.6 Settings ............................................................................................................................ 3-74
3.11 Frequency Calculation ................................................................................ 3-80

3.11.1 General Application .......................................................................................................... 3-80
3.11.3 Function Block Diagram ................................................................................................... 3-81
3.11.4 I/O Signal ......................................................................................................................... 3-81
3.11.5 Logic ................................................................................................................................. 3-81
3.11.6 Settings ............................................................................................................................ 3-82
3.12 Frequency Protection ................................................................................. 3-82

3.12.1 Overfrequency Protection ................................................................................................ 3-82
3.12.2 Underfrequency Protection .............................................................................................. 3-85
3.13 Breaker Failure Protection ......................................................................... 3-91

3.13.4 I/O Signals ....................................................................................................................... 3-92
3.13.5 Logic ................................................................................................................................ 3-93
3.13.6 Settings ............................................................................................................................ 3-94
3.14 Pole Discrepancy Protection...................................................................... 3-94

PCS-921 Breaker Failure Relay 3-c

Date: 2017-10-15
3 Operation Theory
3.14.4 I/O Signals ....................................................................................................................... 3-95
3.14.5 Logic ................................................................................................................................ 3-95
3.14.6 Settings ............................................................................................................................ 3-96
3.15 Synchrocheck.............................................................................................. 3-97

3.15.3 Function Block Diagram ................................................................................................ 3-106
3.15.4 I/O Signals ..................................................................................................................... 3-106
3.15.5 Logic .............................................................................................................................. 3-108
3.15.6 Settings ........................................................................................................................... 3-111
3.16 Automatic Reclosure ................................................................................. 3-113

3.16.1 General Application.........................................................................................................3-113
3.16.2 Function Description .......................................................................................................3-114
3.16.3 Function Block Diagram .................................................................................................3-115
3.16.4 I/O Signals ......................................................................................................................3-115
3.16.5 Logic ...............................................................................................................................3-117
3.16.6 Settings .......................................................................................................................... 3-129
3.17 Trip Logic ................................................................................................... 3-131

3.17.1 Application...................................................................................................................... 3-131
3.17.2 Function Description ...................................................................................................... 3-131
3.17.3 I/O Signals ..................................................................................................................... 3-132
3.17.4 Logic .............................................................................................................................. 3-132
3.17.5 Settings .......................................................................................................................... 3-134
3.18 VT Circuit Supervision.............................................................................. 3-134

3.18.1 General Application........................................................................................................ 3-134
3.18.4 I/O Signals ..................................................................................................................... 3-136
3-d PCS-921 Breaker Failure Relay

Date: 2017-10-15
3 Operation Theory
3.18.5 Logic .............................................................................................................................. 3-136
3.18.6 Settings .......................................................................................................................... 3-137
3.19 CT Circuit Supervision ............................................................................. 3-137

3.19.1 Application...................................................................................................................... 3-137
3.19.4 I/O Signals ..................................................................................................................... 3-138
3.19.5 Logic .............................................................................................................................. 3-138
3.20 Control and Synchrocheck for Manual Closing ..................................... 3-138

3.20.1 General Application........................................................................................................ 3-138
3.20.4 I/O Signals ..................................................................................................................... 3-149
3.20.5 Settings .......................................................................................................................... 3-150
List of Figures
Figure 3.2-1 Logic diagram of CB position supervision ......................................................... 3-4
Figure 3.2-2 Logic diagram of trip&closing circuit supervision ............................................ 3-4
Figure 3.3-1 Flow chart of protection program ........................................................................ 3-8
Figure 3.3-2 Logic diagram of fault detector ............................................................................ 3-9
Figure 3.4-1 Logic diagram of auxiliary element.................................................................... 3-18
Figure 3.5-1 Line fault description........................................................................................... 3-20
Figure 3.5-2 Vector diagram of current and voltage .............................................................. 3-21
Figure 3.5-3 Vector diagram of zero-sequence power .......................................................... 3-23
Figure 3.6-1 Logic diagram of phase overcurrent protection .............................................. 3-30
Figure 3.7-1 Logic diagram of earth fault protection (stage 1) ............................................. 3-38
Figure 3.7-2 Logic diagram of earth fault protection (stage x) ............................................. 3-39
Figure 3.8-1 Logic diagram of dead zone protection ............................................................ 3-46
Figure 3.9-1 Logic diagram of stage x of overvoltage protection ........................................ 3-51
Figure 3.9-2 Logic diagram of negative sequence overvoltage protection ........................ 3-55
PCS-921 Breaker Failure Relay 3-e

Date: 2017-10-15
3 Operation Theory
Figure 3.9-3 Logic diagram of stage 1 of residual overvoltage protection ......................... 3-58
Figure 3.9-6 Blocking logic of undervoltage protection........................................................ 3-65
Figure 3.9-7 Logic of having current condition...................................................................... 3-66
Figure 3.9-8 Logic diagram of stage x of undervoltage protection...................................... 3-66
Figure 3.10-1 Logic diagram of negative-sequence overcurrent protection ...................... 3-73
Figure 3.10-2 Logic diagram of stage 4 of negative-sequence overcurrent protection .... 3-74
Figure 3.11-1 Logic diagram of frequency calculation function .......................................... 3-81
Figure 3.12-1 Logic diagram of overfrequency protection (stage 1) ................................... 3-83
Figure 3.12-5 Logic diagram of overfrequency protection (start) ........................................ 3-84
Figure 3.12-6 Logic diagram of underfrequency protection (stag1) .................................... 3-87
Figure 3.12-10 Logic diagram of underfrequency protection (start) ................................... 3-89
Figure 3.13-1 Logic diagram of breaker failure protection ................................................... 3-93
Figure 3.14-1 Logic diagram of pole discrepancy protection............................................... 3-96
Figure 3.15-1 Relationship between reference voltage and synchronism voltage ............ 3-97
Figure 3.15-2 Voltage connection for single busbar arrangement....................................... 3-99
Figure 3.15-3 Voltage connection for single busbar arrangement..................................... 3-100
Figure 3.15-4 Voltage connection for double busbars arrangement ................................. 3-100
Figure 3.15-5 Voltage selection for double busbars arrangement ..................................... 3-101
Figure 3.15-6 Voltage connection for one and a half breakers arrangement ................... 3-102
Figure 3.15-7 Voltage selection for bus CB of one and a half breakers arrangement ..... 3-103
Figure 3.15-8 Voltage selection for tie CB of one and a half breakers arrangement ....... 3-104
Figure 3.15-9 Reference voltage circuit failure supervision logic ..................................... 3-105
3-f PCS-921 Breaker Failure Relay

Date: 2017-10-15
3 Operation Theory
Figure 3.15-10 Synchronism voltage circuit failure supervision logic .............................. 3-105
Figure 3.15-11 Synchronism check mode selection............................................................ 3-109
Figure 3.15-12 Synchronism check ....................................................................................... 3-109
Figure 3.15-13 Dead charge check mode selection............................................................. 3-110
Figure 3.15-14 Dead charge check logic ............................................................................... 3-110
Figure 3.15-15 No check mode selection ...............................................................................3-111
Figure 3.15-16 Synchrocheck logic ........................................................................................3-111
Figure 3.16-1 Logic diagram of AR block ............................................................................. 3-118
Figure 3.16-2 Logic diagram of AR ready ............................................................................. 3-119
Figure 3.16-3 Logic diagram of tripping condition output .................................................. 3-120
Figure 3.16-4 Single-phase tripping initiating AR ................................................................ 3-121
Figure 3.16-5 Three-phase tripping initiating AR ................................................................. 3-121
Figure 3.16-6 1-pole AR initiation .......................................................................................... 3-122
Figure 3.16-7 3-pole AR initiation .......................................................................................... 3-122
Figure 3.16-8 One-shot AR ..................................................................................................... 3-123
Figure 3.16-9 Extra time delay and blocking logic of AR .................................................... 3-123
Figure 3.16-10 Reclosing output logic .................................................................................. 3-124
Figure 3.16-11 Wait to slave signal ........................................................................................ 3-124
Figure 3.16-12 Reclosing failure and success ..................................................................... 3-125
Figure 3.16-13 Single-phase transient fault .......................................................................... 3-128
Figure 3.16-14 Single-phase permanent fault ([79.N_Rcls]=2) ........................................... 3-129
Figure 3.17-1 Simplified trip logic.......................................................................................... 3-133
Figure 3.17-2 Blocking AR logic ............................................................................................ 3-134
Figure 3.18-1 Logic diagram of VT circuit supervision ....................................................... 3-136
Figure 3.18-2 Logic diagram of VT neutral point supervision ............................................ 3-136
Figure 3.19-1 Logic diagram of CT circuit failure ................................................................ 3-138
Figure 3.20-1 Synchrocheck mode selection for manual closing...................................... 3-140
Figure 3.20-2 Logic diagram of closing circuit breaker ...................................................... 3-140
Figure 3.20-3 Logic diagram of closing switch (xx=02~15) ................................................ 3-141
Figure 3.20-4 Logic diagram of open circuit breaker .......................................................... 3-142
PCS-921 Breaker Failure Relay 3-g

Date: 2017-10-15
3 Operation Theory
Figure 3.20-5 Logic diagram of open switch (xx=02~15) .................................................... 3-142
Figure 3.20-6 Configuration page of control output 01 (default configration) ................. 3-144
Figure 3.20-7 Configuration page of control output 02 (default configration) ................. 3-145
List of Tables
Table 3.1-1 System parameters .................................................................................................. 3-1
Table 3.2-1 I/O signals of CB position supervision.................................................................. 3-3
Table 3.2-2 Internal settings of CB position supervision ........................................................ 3-4
Table 3.3-1 I/O signals of fault detector .................................................................................... 3-9
Table 3.3-2 Settings of fault detector ........................................................................................ 3-9
Table 3.4-1 I/O signals of auxiliary element ............................................................................ 3-13
Table 3.4-2 Settings of auxiliary element ................................................................................ 3-18
Table 3.5-1 Direction description ............................................................................................. 3-22
Table 3.5-2 I/O signals of current direction............................................................................. 3-25
Table 3.5-3 Settings of current direction................................................................................. 3-26
Table 3.6-1 Inverse-time curve parameters............................................................................. 3-28
Table 3.6-2 I/O signals of phase overcurrent protection ....................................................... 3-29
Table 3.6-3 Settings of phase overcurrent protection ........................................................... 3-30
Table 3.7-2 I/O signals of earth fault protection ..................................................................... 3-37
Table 3.7-3 Settings of earth fault protection ......................................................................... 3-40
Table 3.8-1 I/O signals of dead zone protection ..................................................................... 3-45
Table 3.8-2 Settings of dead zone protection ......................................................................... 3-46
Table 3.9-2 I/O signals of overvoltage protection .................................................................. 3-50
Table 3.9-3 Settings of overvoltage protection ...................................................................... 3-51
Table 3.9-4 I/O signals of negative sequence overvoltage protection................................. 3-55
Table 3.9-5 Settings of negative sequence overvoltage protection ..................................... 3-55
Table 3.9-6 Inverse-time curve parameters of residual overvoltage protection ................. 3-57
Table 3.9-7 I/O signals of residual overvoltage protection ................................................... 3-57
3-h PCS-921 Breaker Failure Relay

Date: 2017-10-15
3 Operation Theory
Table 3.9-8 Settings of residual overvoltage protection ....................................................... 3-59
Table 3.9-9 Inverse-time curve parameters of phase undervoltage protection .................. 3-63
Table 3.9-10 I/O signals of undervoltage protection .............................................................. 3-64
Table 3.9-11 Settings of undervoltage protection .................................................................. 3-66
Table 3.10-1 Inverse-time curve parameters........................................................................... 3-71
Table 3.10-2 I/O signals of negative-sequence overcurrent protection............................... 3-72
Table 3.10-3 Settings of negative-sequence overcurrent protection................................... 3-74
Table 3.11-1 I/O signals of frequency calculation function ................................................... 3-81
Table 3.12-1 I/O signals of overfrequency protection............................................................ 3-83
Table 3.12-2 Settings of overfrequency protection................................................................ 3-84
Table 3.12-3 I/O signals of underfrequency protection ......................................................... 3-87
Table 3.12-4 Settings of underfrequency protection ............................................................. 3-89
Table 3.13-1 I/O signals of breaker failure protection............................................................ 3-92
Table 3.13-2 Settings of breaker failure protection................................................................ 3-94
Table 3.14-1 I/O signals of pole discrepancy protection ....................................................... 3-95
Table 3.14-2 Settings of pole discrepancy protection ........................................................... 3-96
Table 3.15-1 I/O signals of synchrocheck ............................................................................. 3-106
Table 3.15-2 Settings of synchrocheck ..................................................................................3-111
Table 3.16-1 I/O signals of auto-reclosing ............................................................................ 3-115
Table 3.16-2 Reclosing number.............................................................................................. 3-127
Table 3.16-3 Settings of auto-reclosing ................................................................................ 3-129
Table 3.17-1 I/O signals of trip logic ...................................................................................... 3-132
Table 3.17-2 Settings of trip logic .......................................................................................... 3-134
Table 3.18-1 I/O signals of VT circuit supervision ............................................................... 3-136
Table 3.18-2 Settings of VT circuit supervision ................................................................... 3-137
Table 3.19-1 I/O signals of CT circuit supervision ............................................................... 3-138
Table 3.20-1 I/O signals of control ......................................................................................... 3-149
Table 3.20-2 Function Settings............................................................................................... 3-150
Table 3.20-3 Synchrocheck Settings ..................................................................................... 3-150
Table 3.20-4 Dual point binary input settings....................................................................... 3-152
PCS-921 Breaker Failure Relay 3-i

Date: 2017-10-15
3 Operation Theory
Table 3.20-5 Control settings ................................................................................................. 3-152
Table 3.20-6 Interlock settings ............................................................................................... 3-153
3-j PCS-921 Breaker Failure Relay

Date: 2017-10-15
3 Operation Theory
3.1 System Parameters

3.1.1 General Application
The device performs various protection functions by respective algorithms with the information
(currents and voltages) acquired from primary system through current transformer and voltage
transformer, so it is important to configure analog input channels correctly.
Further to correct configuration of analog input channels, other protected system information, such
as the parameters of voltage transformer and current transformer are also required.
3.1.2 Function Description
The device generally considers transmission line as its protected object, current flows from busbar
to line is considered as the forward direction.
3.1.3 Settings
Table 3.1-1 System parameters
No. Name Range Step Unit Remark

1 Active_Grp 1~2 1 Active setting group
2 Opt_SysFreq 50 or 60 Hz System frequency
3 PrimaryEquip_Name The description of the primary equipment
Primary rated value of VT
4 U1n 10.00~65500.00 0.01 kV
(phase-to-phase)
Secondary rated value of VT
5 U2n 80.00~220.00 0.01 V
(phase-to-phase)
6 I1n 100~30000 1 A Primary rated value of CT
7 I2n 1 or 5 A Secondary rated value of CT
Frequency upper limit setting
The device will issue an alarm
8 f_High_FreqAlm 50~65 1 Hz
[Alm_Freq], when system frequency is
higher than the setting.
Frequency lower limit setting
The device will issue an alarm
9 f_Low_FreqAlm 40~60 1 Hz
[Alm_Freq], when system frequency is
lower than the setting.
3.2 Circuit Breaker Position Supervision

The status of circuit breaker (CB) position is applied for protection and control functions in this
device, such as, auto-reclose and VT circuit supervision, etc. The status of CB position can be
applied as input signals for other features configured by user.

Date: 2017-10-15
3 Operation Theory
The signal reflecting CB position is acquired via opto-coupler with settable delay pickup and
dropoff, and forms digital signal used by protection functions. CB position can reflect the status of
each phase by means of phase-segregated inputs.
In order to prevent that wrong status of CB position is input into the device via binary input,
appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected but there is current detected in the line, the status of CB
position will be thought as incorrect and an alarm [Alm_52b] will be issued.
Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.
External manual closing binary input (ManCls) is only used for SOTF logic application, the control
of circuit breaker (CB) closing or opening should refer to section 3.29 (Control and Synchrocheck
for Manual Closing).
3.2.3 Function Block Diagram
1. For phase-segregated circuit breaker
CB Position Supervision
52b_PhA Alm_52b
52b_PhB
52b_PhC
ManCls
2. For non-phase segregated circuit breaker
CB Position Supervision
52b Alm_52b
ManCls
3. Trip&closing circuit supervision (TCCS)

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3 Operation Theory
TCCS
52a TCCS.Alm
52b
TCCS.Input
ManCls
TCCS will be disabled automatically when it is used for phase-segregated circuit breaker.
3.2.4 I/O Signals
Table 3.2-1 I/O signals of CB position supervision
No. Input Signal Description

1 52b_PhA Normally closed contact of A-phase of circuit breaker
2 52b_PhB Normally closed contact of B-phase of circuit breaker
3 52b_PhC Normally closed contact of C-phase of circuit breaker
External manual closing input signal, it is applied to manual closing
4 ManCls
switch-onto-fault logic
5 52b Normally closed contact of three-phase of circuit breaker
6 52a Normally open contact of three-phase of circuit breaker
Control circuit failure (normally closed contact and normally open contact of
7 TCCS.Input three-phase circuit breaker are all de-energized due to DC power loss of control
circuit)
No. Output Signal Description
1 Alm_52b CB position is abnormal
2 TCCS.Alm Control circuit of circuit breaker is abnormal
NOTICE!
The signal [52a] only take effect in the tripping/closing circuit supervision and not affect
any protection function. ONLY IF tripping/closing circuit supervision is configured, this
signal needs to be connected to the device.

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3 Operation Theory
3.2.5 Logic
BI [52b_PhA] >=1
&
&
BI [52b_PhB] >=1
& &
BI [52b_PhC] >=1 >=1

&
BI [52b]
&
SIG Ia>I_Line
>=1
& >=1 10s 10s Alm_52b
SIG Ib>I_Line
&
SIG Ic>I_Line
Figure 3.2-1 Logic diagram of CB position supervision
BI [52a] >=1
>=1
BI [52b] [TCCS.t_DPU] [TCCS.t_DDO] TCCS.Alm
BI [TCCS.Input]
Figure 3.2-2 Logic diagram of trip&closing circuit supervision
I_Line is threshold value used to determine whether line is on-load or no-load. Default value
0.06In.
3.2.6 Settings
Table 3.2-2 Internal settings of CB position supervision
No. Name Default Value Unit Remark

1 TCCS.t_DPU 0.5 s Pickup delay time of control circuit failure alarm
2 TCCS.t_DDO 0.5 s Dropoff delay time of control circuit failure alarm

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3 Operation Theory
3.3 Fault Detector (FD)

The device has one DSP module with fault detector DSP and protection DSP for fault detector and
protection calculation respectively. Protection DSP with protection fault detector element is
responsible for calculation of protection elements, and fault detector DSP is responsible to
determine fault appearance on the protected power system. Fault detector in fault detector DSP
picks up to provide positive supply to output relays. The output relays can only operate when both
the fault detector in fault detector DSP and a protection element operate simultaneously.
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
outputs if a protection element operates while the fault detector does not operate.
3.3.2 Fault Detector in Fault Detector DSP
Main part of FD is DPFC current detector element that detects the change of phase-to-phase
power frequency current, and residual current fault detector element that calculates the vector
sum of 3 phase currents as supplementary. They are continuously calculating the analog input
signals.
All fault detectors in this device include:
1. Fault detector based on DPFC current: DPFC current is greater than the setting value
2. Fault detector based on residual current: Residual current is greater than the setting value
3. Fault detector based on negative-sequence current: Negative-sequence current is greater

than the setting value
4. Fault detector based on phase current: Phase current is greater than the setting value
5. Fault detector based on voltage: Phase voltage or phase-to-phase voltage is greater than the
setting value
6. Fault detector based on circuit breaker position: Circuit breaker position discrepancy
7. Fault detector based on auxiliary element: Auxiliary element pickup
If any of the above conditions is complied, FD will operate to activate the output circuit providing
DC power supply to the output relays, then all protection functions are permitted to operate when
FD operate. The fault detector based on DPFC current and the fault detector based on residual
current are always enabled.
3.3.2.1 Fault Detector Based on DPFC Current (pickup condition 1)
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before.
ΔI = I(k)-I(k-24)
Where:
I(k) is the sampling value at a point.

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I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.3-1.
For multi-phase short-circuit fault, the DPFC phase-to-phase current has high sensitivity to ensure
the pickup of protection device. For usual single phase to earth fault, it also has sufficient
sensitivity to pick up except the earth fault with very large fault resistance. Under this condition the
DPFC current is relative small, however, residual current is also used to judge pickup condition
(pickup condition 2).
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steadily under normal or power swing
condition, the adaptive floating threshold with the ΔISet is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
ΔIΦΦMAX>1.25ΔITh+ΔISet Equation 3.3-1
Where:
ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC, CA)
ΔISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ΔITh: The floating threshold value
The coefficient “1.25” is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operating condition is met, the fault detector based on DPFC current will operate to provide DC
power supply for output relays, the pickup signal will maintain 7s after the fault detector based on

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DPFC current drops off.
3.3.2.2 Fault Detector Based on Residual Current (pickup condition 2)
The operation condition will be met when 3I0 is greater than the setting [FD.ROC.3I0_Set]. The
fault detector based on residual current is always in service.
Where:
3I0: residual current calculates from the vector sum of Ia, Ib and Ic
When the fault detector based on residual current operates and lasts for longer than 10 seconds,
an alarm [Alm_Pkp_I0] will be issued.
If operation condition is met, the fault detector based on residual current will operate to provide DC
power supply for output relay, and the pickup signal will maintain 7s after the fault detector based
on residual current drops off.
3.3.2.3 Fault detector Based on Negative-sequence Current
The operation condition will be met when negative-sequence current (I2) is greater than the
setting [FD.NOC.I2_Set]. It can be enabled or disabled by the logic setting [FD.NOC.En].
If operation condition is met, the fault detector based on negative-sequence current will operate to
provide DC power supply for output relay, and the pickup signal will maintain 7s after the fault
detector based on negative-sequence current drops off.
3.3.2.4 Fault Detector Based on Phase Current
The fault detector based on phase current will operate to provide DC power supply for output relay
when phase overcurrent protection is enabled and meets the operation condition, and the pickup
signal will maintain 500ms after the fault detector based on phase current drops off.
3.3.2.5 Fault Detector Based on Voltage
This fault detector based on voltage includes the fault detectors of overvoltage protection,
undervoltage protection and frequency protection. The fault detector based on voltage will operate
to provide DC power supply for output relay when corresponding voltage element is enabled and
meets the operation condition, and the pickup signal will maintain 500ms after the fault detector
based on voltage drops off.
3.3.2.6 Fault Detector Based on Circuit Breaker Position
When pole discrepancy protection is enabled, i.e. the logic setting [62PD.En] is set as “1”, and if
three phases of circuit breaker are not in the same status, the fault detector based on circuit
breaker position will operate to provide DC power supply for output relays, and the pickup signal
will maintain 500ms after the the fault detector based on circuit breaker position drops off.
3.3.2.7 Fault Detector Based on Auxiliary Element
The fault detector based on auxiliary element will operate to provide DC power supply for output
relay when auxiliary element is enabled and meets the operation condition, and the pickup signal
will maintain 500ms after the fault detector based on auxiliary element drops off.

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3.3.3 Protection Fault Detector in Protection Calculation DSP
The protection device is running either of the two programs: one is “Regular program” for normal
state, and the other is “Fault calculation program” after protection fault detector picks up.
Under the normal state, the protection device will perform the following tasks:
1. Calculate analog quantity
2. Read binary input
3. Hardware self-check
4. Circuit breaker position supervision
5. Analog quantity input supervision
Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of phase overcurrent
protection, and to determine logic. If the fault is within the protected zone, the protection device will
send tripping command.
The protection program flow chart is shown as Figure 3.3-1.
Main program
Sampling program
No Yes
Pickup?
Regular program Fault calculation program
Figure 3.3-1 Flow chart of protection program
The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
refer to section 3.3.2 for details.

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FD
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
FD.NOC.Pkp
3.3.5 I/O Signals
Table 3.3-1 I/O signals of fault detector

1 FD.Pkp The device picks up
2 FD.DPFC.Pkp DPFC current fault detector element operates.
3 FD.ROC.Pkp Residual current fault detector element operates.
4 FD.NOC.Pkp Negative-sequence fault detector element operates.
3.3.6 Logic
SIG Ia Calculate DPFC phase-to- ΔIab>[FD.DPFC.I_Set]

phase current: >=1
ΔIab=Δ(Ia-Ib)
SIG Ib ΔIbc>[FD.DPFC.I_Set] FD.DPFC.Pkp
ΔIbc=Δ(Ib-Ic)
ΔIca=Δ(Ic-Ia)
SIG Ic ΔIca>[FD.DPFC.I_Set] >=1
0s 7s FD.Pkp
Calculate residual current:

3I0>[FD.ROC.3I0_Set] FD.ROC.Pkp
3I0=Ia+Ib+Ic
Calculate negative-
I2>[FD.NOC.I2_Set] &
sequence current: I2
FD.NOC.Pkp
EN FD.NOC.En
Figure 3.3-2 Logic diagram of fault detector
3.3.7 Settings
Table 3.3-2 Settings of fault detector

Current setting of DPFC current fault
1 FD.DPFC.I_Set (0.050~30.000)×In 0.001 A
detector element
Current setting of residual current fault
2 FD.ROC.3I0_Set (0.050~30.000)×In 0.001 A
detector element

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Current setting of negative-sequence

3 FD.NOC.I2_Set (0.050~30.000)×In 0.001 A
current fault detector element
Enabling/disabling negative-sequence
current fault detector element
4 FD.NOC.En 0 or 1
0: disable
1: enable
3.4 Auxiliary Element

Auxiliary element (AuxE) is mainly used to program logics to meet users’ applications or further
improve operating reliability of protection elements. Reliability of protective elements is assured,
auxiliary element is usually not required to configure. Auxiliary elements including current change
auxiliary element (AuxE.OCD), residual current auxiliary element (AuxE.ROC), phase current
auxiliary element (AuxE.OC), voltage change auxiliary element (AuxE.UVD), phase under voltage
auxiliary element (AuxE.UVG), phase-to-phase under voltage auxiliary element (AuxE.UVS) and
residual voltage auxiliary element (AuxE.ROV), and they can be enabled or disabled by
corresponding logic setting or binary inputs. Users can configure them according to applications
via PCS-Explorer software.
1. Current change auxiliary element AuxE.OCD
It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates
(FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary
element operates.
2. Residual current auxiliary element AuxE.ROC
There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and
AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual
current amplitude is larger than corresponding current setting
The criteria are:
AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set]
Where:
3I0: The calculated residual current
3. Phase current auxiliary element AuxE.OC
There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3).
Each phase current auxiliary element will operate instantly if phase current amplitude is larger than

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corresponding current setting.
The criteria are:
AuxE.OC1: IΦMAX>[AuxE.OC1.I_Set]
Where:
IΦMAX: The maximum phase current among three phases
4. Voltage change auxiliary element AuxE.UVD
AuxE.UVD is based on phase-to-ground voltage change measured in all three phases.
The criterion is:
ΔUΦMAX>[AuxE.UVD.U_Set]
Where:
ΔUΦMAX: The maximum phase-to-ground voltage change among three phases
5. Phase under voltage auxiliary element AuxE.UVG
AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding
voltage setting.
The criterion is:
UΦMIN<[ AuxE.UVG.U_Set]
Where:
UΦMIN: The minimum value among three phase-to-ground voltages
6. Phase-to-phase under voltage auxiliary element AuxE.UVS
AuxE.UVS will operate instantly if any phase-to-phase voltage is lower than corresponding voltage
setting.
The criterion is:
UΦΦMIN<[ AuxE.UVS.U_Set]
Where:
UΦΦMIN: The minimum value among three phase-to-phase voltages
7. Residual voltage auxiliary element AuxE.ROV
AuxE.ROV will operate instantly if calculated residual voltage is larger than corresponding voltage
setting.
The criterion is:

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3U0>[ AuxE.ROV.3U0_Set]
Where:
3U0: The calculated residual voltage
AuxE
AuxE.OCD.En AuxE.St
AuxE.OCD.Blk AuxE.OCD.St_DDO
AuxE.ROCx.En AuxE.OCD.On
AuxE.ROCx.Blk AuxE.ROCx.St
AuxE.OCx.En AuxE.ROCx.On
AuxE.OCx.Blk AuxE.OCx.St
AuxE.UVD.En AuxE.OCx.StA
AuxE.UVD.Blk AuxE.OCx.StB
AuxE.UVG.En AuxE.OCx.StC
AuxE.UVG.Blk AuxE.OCx.On
AuxE.UVS.En AuxE.UVD.St
AuxE.UVS.Blk AuxE.UVD.St_DDO
AuxE.ROV.En AuxE.UVD.On
AuxE.ROV.Blk AuxE.UVG.St
AuxE.UVG.StA
AuxE.UVG.StB
AuxE.UVG.StC
AuxE.UVG.On
AuxE.UVS.St
AuxE.UVS.StAB
AuxE.UVS.StBC
AuxE.UVS.StCA
AuxE.UVS.On
AuxE.ROV.St
AuxE.ROV.On
Where:

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x can be 1, 2 or 3
3.4.4 I/O Signals
Table 3.4-1 I/O signals of auxiliary element

Current change auxiliary element enabling input, it is triggered from binary input
1 AuxE.OCD.En
or programmable logic etc.
Current change auxiliary element blocking input, it is triggered from binary input
2 AuxE.OCD.Blk
Stage 1 of residual current auxiliary element enabling input, it is triggered from
3 AuxE.ROC1.En
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element blocking input, it is triggered from
4 AuxE.ROC1.Blk
5 AuxE.ROC2.En
6 AuxE.ROC2.Blk
7 AuxE.ROC3.En
8 AuxE.ROC3.Blk
Stage 1 of phase current auxiliary element enabling input, it is triggered from
9 AuxE.OC1.En
Stage 1 of phase current auxiliary element blocking input, it is triggered from
10 AuxE.OC1.Blk
11 AuxE.OC2.En
12 AuxE.OC2.Blk
13 AuxE.OC3.En
14 AuxE.OC3.Blk
Voltage change auxiliary element enabling input, it is triggered from binary input
15 AuxE.UVD.En
Voltage change auxiliary element blocking input, it is triggered from binary input
16 AuxE.UVD.Blk
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
17 AuxE.UVG.En
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
18 AuxE.UVG.Blk
Phase-to-phase under voltage auxiliary element enabling input, it is triggered
19 AuxE.UVS.En

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Phase-to-phase under voltage auxiliary element blocking input, it is triggered

20 AuxE.UVS.Blk
Residual voltage auxiliary element enabling input, it is triggered from binary
21 AuxE.ROV.En
input or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary
22 AuxE.ROV.Blk
1 AuxE.St Any auxiliary element of the device operates
2 AuxE.OCD.St_DDO Current change auxiliary element operates (7s delayed drop off).
3 AuxE.OCD.On Current change auxiliary element is enabled
4 AuxE.ROC1.St Stage 1 of residual current auxiliary element operates.
5 AuxE.ROC1.On Stage 1 of residual current auxiliary element is enabled
10 AuxE.OC1.St Stage 1 of phase current auxiliary element operates.
11 AuxE.OC1.StA Stage 1 of phase current auxiliary element operates (phase A).
12 AuxE.OC1.StB Stage 1 of phase current auxiliary element operates (phase B).
13 AuxE.OC1.StC Stage 1 of phase current auxiliary element operates (phase C).
14 AuxE.OC1.On Stage 1 of phase current auxiliary element is enabled
25 AuxE.UVD.St Voltage change auxiliary element operates.
26 AuxE.UVD.St_DDO Voltage change auxiliary element operates (7s delayed drop off).
27 AuxE.UVD.On Voltage change auxiliary element is enabled
28 AuxE.UVG.St Phase-to-ground under voltage auxiliary element operates.
29 AuxE.UVG.StA Phase-to-ground under voltage auxiliary element operates (phase A).
30 AuxE.UVG.StB Phase-to-ground under voltage auxiliary element operates (phase B).
31 AuxE.UVG.StC Phase-to-ground under voltage auxiliary element operates (phase C).
32 AuxE.UVG.On Phase-to-ground under voltage auxiliary element is enabled
33 AuxE.UVS.St Phase-to-phase under voltage auxiliary element operates.
34 AuxE.UVS.StAB Phase-to-phase under voltage auxiliary element operates (phase AB).
35 AuxE.UVS.StBC Phase-to-phase under voltage auxiliary element operates (phase BC).
36 AuxE.UVS.StCA Phase-to-phase under voltage auxiliary element operates (phase CA).

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37 AuxE.UVS.On Phase-to-phase under voltage auxiliary element is enabled

38 AuxE.ROV.St Residual voltage auxiliary element operates.
39 AuxE.ROV.On Residual voltage auxiliary element is enabled
3.4.5 Logic
SIG FD.DPFC.Pkp
SIG AuxE.OCD.En
&
& 0s [AuxE.OCD.t_DDO] AuxE.OCD.St_DDO
SIG AuxE.OCD.Blk
AuxE.OCD.On
En AuxE.OCD.En
SIG Ia
Calculate residual
SIG Ib current:
3I0=Ia+Ib+Ic
SIG Ic
3I0>[AuxE.ROC1.3I0_Set] &
SIG AuxE.ROC1.En
& AuxE.ROC1.St
SIG AuxE.ROC1.Blk
AuxE.ROC1.On
En AuxE.ROC1.En
SIG AuxE.ROC2.En
& AuxE.ROC2.St
SIG AuxE.ROC2.Blk
AuxE.ROC2.On
En AuxE.ROC2.En
SIG AuxE.ROC3.En
& AuxE.ROC3.St
SIG AuxE.ROC3.Blk
AuxE.ROC3.On
En AuxE.ROC3.En

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SIG Ia Ia>[AuxE.OC1.I_Set] &

AuxE.OC1.StA
SIG Ib Ib>[AuxE.OC1.I_Set] &

AuxE.OC1.StB
SIG Ic Ic>[AuxE.OC1.I_Set] &

AuxE.OC1.StC
>=1
SIG AuxE.OC1.En
&
& AuxE.OC1.St
SIG AuxE.OC1.Blk
En AuxE.OC1.En AuxE.OC1.On

AuxE.OC2.StA

AuxE.OC2.StB

AuxE.OC2.StC
>=1
SIG AuxE.OC2.En
&
& AuxE.OC2.St
SIG AuxE.OC2.Blk

AuxE.OC3.StA

AuxE.OC3.StB

AuxE.OC3.StC
>=1
SIG AuxE.OC3.En
&
& AuxE.OC3.St
SIG AuxE.OC3.Blk

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SIG Ua Calculate DPFC phase ΔUa>[AuxE.UVD.U_Set]

voltage >=1
SIG Ub △Ua=△(Ua-Ufa) ΔUb>[AuxE.UVD.U_Set] &
△Ub=△(Ub-Ufb)
AuxE.UVD.St
SIG Uc △Uc=△(Uc-Ufc) ΔUc>[AuxE.UVD.U_Set]
0s [AuxE.UVD.t_DDO] AuxE.UVD.St_DDO
SIG AuxE.UVD.En
&
SIG AuxE.UVD.Blk AuxE.UVD.On
En AuxE.UVD.En
SET UA<[AuxE.UVG.U_Set] &

AuxE.UVG.StA
SET UB<[AuxE.UVG.U_Set] &

AuxE.UVG.StB
SET UC<[AuxE.UVG.U_Set] &

AuxE.UVG.StC
>=1
SIG AuxE.UVG.En
&
& AuxE.UVG.St
SIG AuxE.UVG.Blk
En AuxE.UVG.En
AuxE.UVG.On
SET UAB<[AuxE.UVS.U_Set] &

AuxE.UVS.StAB
SET UBC<[AuxE.UVS.U_Set] &

AuxE.UVS.StBC
SET UCA<[AuxE.UVS.U_Set] &

AuxE.UVS.StCA
>=1
SIG AuxE.UVS.En
&
& AuxE.UVS.St
SIG AuxE.UVS.Blk
En AuxE.UVS.En
AuxE.UVS.On
SIG Ua 3U0>[AuxE.ROV.3U0_Set] &

Calculate residual voltage AuxE.ROV.St
SIG Ub
3U0=Ua+Ub+Uc
SIG Uc
SIG AuxE.ROV.En
&
SIG AuxE.ROV.Blk AuxE.ROV.On
En AuxE.ROV.En

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SIG AuxE.OCD.St_DDO
SIG AuxE.ROC1.St
>=1
SIG AuxE.ROC2.St
SIG AuxE.ROC3.St
>=1
SIG AuxE.OC1.St
>=1 AuxE.St
SIG AuxE.OC2.St
SIG AuxE.OC3.St
SIG AuxE.UVD.St_DDO >=1

>=1
SIG AuxE.UVG.St
SIG AuxE.UVS.St >=1
SIG AuxE.ROV.St
Figure 3.4-1 Logic diagram of auxiliary element
3.4.6 Settings
Table 3.4-2 Settings of auxiliary element

Extended time delay of current change
1 AuxE.OCD.t_DDO 0.000~10.000 0.001 s
auxiliary element
Enabling/disabling current change
auxiliary element
2 AuxE.OCD.En 0 or 1
0: disable
1: enable
Current setting of stage 1 residual
3 AuxE.ROC1.3I0_Set (0.050~30.000)×In 0.001 A
current auxiliary element
Enabling/disabling stage 1 residual
4 AuxE.ROC1.En 0 or 1
0: disable
1: enable
5 AuxE.ROC2.3I0_Set (0.050~30.000)×In 0.001 A
0: disable
1: enable
7 AuxE.ROC3.3I0_Set (0.050~30.000)×In 0.001 A
0: disable
1: enable
9 AuxE.OC1.I_Set (0.050~30.000)×In Current setting of stage 1 phase current

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auxiliary element
Enabling/disabling stage 1 phase
10 AuxE.OC1.En 0 or 1
0: disable
1: enable
Current setting of stage 2 phase current
11 AuxE.OC2.I_Set (0.050~30.000)×In
auxiliary element
0: disable
1: enable
Current setting of stage 3 phase current
13 AuxE.OC3.I_Set (0.050~30.000)×In
auxiliary element
0: disable
1: enable
Voltage setting for voltage change
15 AuxE.UVD.U_Set 0~Un 0.001 V
auxiliary element
Extended time delay of voltage change
16 AuxE.UVD.t_DDO 0.000~10.000 0.001 s
auxiliary element
Enabling/disabling voltage change
auxiliary element
17 AuxE.UVD.En 0 or 1
0: disable
1: enable
Voltage setting for phase-to-ground
18 AuxE.UVG.U_Set 0~Un 0.001 V
under voltage auxiliary element
Enabling/disabling phase-to-ground
19 AuxE.UVG.En 0 or 1
0: disable
1: enable
Voltage setting for phase-to-phase
20 AuxE.UVS.U_Set 0~Unn 0.001 V
Enabling/disabling phase-to-phase
21 AuxE.UVS.En 0 or 1
0: disable
1: enable
Voltage setting for residual voltage
22 AuxE.ROV.3U0_Set 0~Un 0.001 V
auxiliary element
Enabling/disabling residual voltage
auxiliary element
23 AuxE.ROV.En 0 or 1
0: disable
1: enable

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3.5 Current Direction

Overcurrent protection is widely used in the power system as backup protection, but in some
cases, the direction of current is necessary to aid to complete the selective tripping. As shown
below:
L M N
EM C D A B EN
Fault
Figure 3.5-1 Line fault description
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
cannot clear the fault quickly.
The module computes direction of phase current and phase-to-phase current, zero-sequence
current and negative-sequence current.
The direction of phase current and phase-to-phase current equips with an under-voltage direction
function to ensure that phase or phase-to-phase overcurrent protection has explicit directionality
when the polarized voltage is too low for close up fault.
The direction of zero-sequence current and negative-sequence current direction equips with an
impedance compensation function to ensure that zero-sequence or negative-sequence
overcurrent protection has explicit directionality when the zero-sequence voltage or the
negative-sequence voltage is too low.
3.5.2.1 Phase/Phase-to-phase Current Direction
By setting the characteristic angle [RCA_OC] to determine the most sensitive forward angle of
phase current and phase-to-phase current, power value is calculated using phase current with
phase polarized voltage or phase-to-phase current with phase-to-phase polarized voltage to
determine the direction of phase current or phase-to-phase current respectively in forward
direction or reverse direction. When the power value is zero, neither forward direction nor reverse
direction is considered. As shown below:

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jX
U
φ
θ I
R
O
Forward direction
Reverse direction
Figure 3.5-2 Vector diagram of current and voltage
Where:
φ is the setting [RCA_OC]
θ is the phase angle between polarized voltage and current
The power value is calculated as below:
P=U×[I×COS(θ-φ)]
1. If P>0, the current direction polarized by U is forward direction
2. If P<0, the current direction polarized by U is reverse direction
From above diagram can be seen, when θ=φ, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, φ is called as sensitivity angle of phase
overcurrent protection.
1. Polarized voltage of phase or phase-to-phase current direction
In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
cycles pre-fault positive-sequence voltage.
2. Phase or phase-to-phase current direction under normal polarized voltage condition
When using normal polarized voltage to calculate phase and phase-to-phase current direction,

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there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.5-1 Direction description
Direction Polarized Voltage Current

Forward direction U1a Ia
Phase A
Reverse direction U1a Ia
Forward direction U1b Ib
Phase B
Reverse direction U1b Ib
Forward direction U1c Ic
Phase C
Reverse direction U1c Ic
Forward direction U1ab Iab
Phase AB
Reverse direction U1ab Iab
Forward direction U1bc Ibc
Phase BC
Reverse direction U1bc Ibc
Forward direction U1ca Ica
Phase CA
Reverse direction U1ca Ica
3. Phase or phase-to-phase current direction for under-voltage conditions
When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
3.5.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.

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jX 3U0
θ-180°
-3I0
φ
R
O
3I0
θ Reverse direction
Forward direction
Figure 3.5-3 Vector diagram of zero-sequence power
Vector diagram of negative-sequence power is similar to that of zero-sequence power.
Where:
φ is the setting [RCA_ROC] or the setting [RCA_NegOC]
θ is the phase angle between zero/negative-sequence voltage and zero/negative-sequence

current
3I0: calculated zero-sequence current by vector sum of Ia, Ib and Ic
The power value is calculated as below:
P=U×[I×COS(θ-φ)]
 If P>0, the direction of zero /negative-sequence current is reverse direction
 If P<-0.1InVA, the direction of zero /negative-sequence current is forward direction
1. The direction of zero-sequence current
Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
to determine the direction of zero-sequence current
According to the equation:
The zero-sequence current and the zero-sequence voltage can be gained by calculation

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Zero-sequence power is: P=3U0×[3I0×COS(θ-φ)]
2. The direction of negative-sequence current
Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:
The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2×[3I2×COS(θ-φ)]
3. The direction of zero-sequence/negative-sequence current with impedance compensation
When zero-sequence impedance or negative-sequence impedance behind the device is very

small, if the fault in forward direction happens, the measured zero-sequence voltage or
negative-sequence voltage by the device may be relatively small to determine correct direction. In
order to solve this problem, compensated zero-sequence voltage and negative-sequence voltage
are used for power calculation.
The compensation formula is as follows:
is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line

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DIR
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
FwdDir_C
RevDir_A
RevDir_B
RevDir_C
FwdDir_AB
FwdDir_BC
FwdDir_CA
RevDir_AB
RevDir_BC
RevDir_CA
3.5.4 I/O Signals
Table 3.5-2 I/O signals of current direction

1 FwdDir_ROC The forward direction of zero-sequence power
2 RevDir_ROC The reverse direction of zero-sequence power
3 FwdDir_NegOC The forward direction of negative-sequence power
4 RevDir_NegOC The reverse direction of negative-sequence power
5 FwdDir_A The forward direction of phase-A current
6 FwdDir_B The forward direction of phase-B current
7 FwdDir_C The forward direction of phase-C current
8 RevDir_A The reverse direction of phase-A current
9 RevDir_B The reverse direction of phase-B current
10 RevDir_C The reverse direction of phase-C current
11 FwdDir_AB The forward direction of phase-AB current
12 FwdDir_BC The forward direction of phase-BC current
13 FwdDir_CA The forward direction of phase-CA current

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14 RevDir_AB The reverse direction of phase-AB current

15 RevDir_BC The reverse direction of phase-BC current
16 RevDir_CA The reverse direction of phase-CA current
3.5.5 Settings
Table 3.5-3 Settings of current direction

The characteristic angle of directional
1 RCA_OC 30.00~89.00 0.01 Deg
phase overcurrent element
The characteristic angle of directional earth
2 RCA_ROC 30.00~89.00 0.01 Deg
fault element
3 RCA_NegOC 30.00~89.00 0.01 Deg
negative-sequence overcurrent element
The compensated zero-sequence
4 Z0_Comp (0.000~4Unn)/In 0.001 ohm
impedance
The compensated negative-sequence
5 Z2_Comp (0.000~4Unn)/In 0.001 ohm
impedance
3.6 Phase Overcurrent Protection

When a fault occurs in power system, usually the fault current would be very large and phase
overcurrent protection operates monitoring fault current is then adopted to avoid further damage to
protected equipment. Directional element can be selected to improve the sensitivity and selectivity
of the protection. For application on feeder-transformer circuits, second harmonic can also be
selected to block phase overcurrent protection to avoid the effect of inrush current on the
protection.
Phase overcurrent protection has following functions:
1. Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
2. All stages can be selected as definite-time or inverse-time characteristic. The inverse-time

characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of phase overcurrent protection.
3. Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.
4. Second harmonic can be selected to block each stage of phase overcurrent protection.
3.6.2.1 Overview
Phase overcurrent protection consists of following three elements:

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1. Overcurrent element: each stage is independent overcurrent element.
2. Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3. Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.
3.6.2.2 Overcurrent Element
The operation criterion for each stage of overcurrent element is:
Ip> [50/51Px.I_Set] Equation 3.6-1
Where:
Ip is measured phase current.
[50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element.
3.6.2.3 Direction Control Element
Please refer to section 3.5 for details.
3.6.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder transformer circuits harmonic
blocking function can be selected for each stage of phase overcurrent element by configuring logic
setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled.
Operation criterion:
Equation 3.6-2
Where:
is second harmonic of phase current
is fundamental component of phase current.
[50/51P.K_Hm2] is harmonic blocking coefficient.
If fundamental component of any phase current is lower than the minimum operating current
(0.1In), then harmonic calculation is not carried out and harmonic blocking element does not
operate.

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3.6.2.5 Characteristic Curve
All stages can be selected as definite-time or inverse-time characteristic, inverse-time operating

characteristic is as follows.
Where:
Iset is current setting [50/51Px.I_Set].
Tp is time multiplier setting [50/51Px.TMS].
α is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.6-1 Inverse-time curve parameters
50/51Px.Opt_Curve Time Characteristic K α C

DefTime Definite time
IECN IEC Normal inverse 0.14 0.02 0
IECV IEC Very inverse 13.5 1.0 0
IECE IEC Extremely inverse 80.0 2.0 0
IECST IEC Short-time inverse 0.05 0.04 0
IECLT IEC Long-time inverse 120.0 1.0 0
ANSIE ANSI Extremely inverse 28.2 2.0 0.1217
ANSIV ANSI Very inverse 19.61 2.0 0.491
ANSI ANSI Inverse 0.0086 0.02 0.0185
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114
ANSILTE ANSI Long-time extremely inverse 64.07 2.0 0.25
ANSILTV ANSI Long-time very inverse 28.55 2.0 0.712
ANSILT ANSI Long-time inverse 0.086 0.02 0.185
UserDefine Programmable user-defined
If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic with constants α, K and C. (only
stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting

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[50/51Px.tmin], then the operating time of the protection changes to the value of setting
[50/51Px.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.
50/51Px
50/51Px.En1 50/51Px.On
50/51Px.En2 50/51Px.StA
50/51Px.Blk 50/51Px.StB
50/51Px.StC
50/51Px.St
50/51Px.Op
3.6.4 I/O Signals
Table 3.6-2 I/O signals of phase overcurrent protection

Stage x of phase overcurrent protection enabling input 1, it is triggered from binary
1 50/51Px.En1
Stage x of phase overcurrent protection enabling input 2, it is triggered from binary
2 50/51Px.En2
Stage x of phase overcurrent protection blocking input, it is triggered from binary
3 50/51Px.Blk
1 50/51Px.On Stage x of phase overcurrent protection is enabled.
2 50/51Px.Op Stage x of phase overcurrent protection operates.
3 50/51Px.St Stage x of phase overcurrent protection starts.
4 50/51Px.StA Stage x of phase overcurrent protection starts (A-Phase).
5 50/51Px.StB Stage x of phase overcurrent protection starts (B-Phase).
6 50/51Px.StC Stage x of phase overcurrent protection starts (C-Phase).

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3.6.5 Logic
SET Ia>[50/51Px.I_Set] &

50/51Px.StA
SET Ib>[50/51Px.I_Set]
SET Ic>[50/51Px.I_Set]
&
SET [50/51Px.Opt_Dir]=Foward & 50/51Px.StB
SIG Forward DIR
SET [50/51Px.Opt_Dir]=Reverse & &

50/51Px.StC
SIG Reverse DIR
>=1
SET [50/51Px.Opt_Dir]=Non_Directional
>=1
SIG VTS.Alm & 50/51Px.St
Timer
EN [50/51P1.En_VTS_Blk] t
50/51Px.Op
t
SIG I3P 2nd Hm Detect & &
SET [50/51Px.En_Hm2_Blk]
EN [50/51Px.En]
&
SIG 50/51Px.En1 &
50/51Px.On
SIG 50/51Px.En2
&
SIG 50/51Px.Blk
SIG FD.Pkp
Figure 3.6-1 Logic diagram of phase overcurrent protection
x=1, 2, 3, 4
3.6.6 Settings
Table 3.6-3 Settings of phase overcurrent protection

Setting of second harmonic
1 50/51P.K_Hm2 0.000~1.000 0.001 component for blocking phase
overcurrent elements
Current setting for stage 1 of phase
2 50/51P1.I_Set (0.050~30.000)×In 0.001 A
overcurrent protection
Time delay for stage 1 of phase
3 50/51P1.t_Op 0.000~20.000 0.001 s
Enabling/disabling stage 1 of phase
4 50/51P1.En 0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing
5 50/51P1.En_BlkAR 0 or 1
blocked when stage 1 of phase

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overcurrent protection operates

0: disable
1: enable
Enabling/Disabling stage 1 of phase
overcurrent protection been blocked
6 50/51P1.En_VTS_Blk 0 or 1 by VT circuit failure
0: disable
1: enable
Non_Directional
Direction option for stage 1 of phase
7 50/51P1.Opt_Dir Forward
Reverse
Enabling/disabling second harmonic
blocking for stage 1 of phase
8 50/51P1.En_Hm2_Blk 0 or 1 overcurrent protection
0: disable
1: enable
DefTime, IECN,
IECV, IECE, IECST,
IECLT, ANSIE, Option of characteristic curve for
9 50/51P1.Opt_Curve ANSIV, ANSI, 1 stage 1 of phase overcurrent
ANSIM, ANSILTE, protection
ANSILTV, ANSILT,
UserDefine
Time multiplier setting for stage 1 of
10 50/51P1.TMS 0.010~20000.000 0.001 inverse-time phase overcurrent
protection
Minimum operating time for stage 1
11 50/51P1.tmin 0.010~20.000 0.001 s of inverse-time phase overcurrent
protection
Constant “α” for stage 1 of
customized inverse-time
12 50/51P1.Alpha 0.010~5.000 0.001
characteristic phase overcurrent
protection
Constant “C” for stage 1 of
13 50/51P1.C 0.000~20000.000 0.001
protection
Constant “K” for stage 1 of
14 50/51P1.K 0.050~20.000 0.001
protection
15 50/51P2.I_Set (0.050~30.000)×In 0.001 A
16 50/51P2.t_Op 0.000~20.000 0.001 s Time delay for stage 2 of phase

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17 50/51P2.En 0 or 1
0: disable
1: enable
18 50/51P2.En_BlkAR 0 or 1 overcurrent protection operates
0: disable
1: enable
0: disable
1: enable
Non_Directional
Reverse
0: disable
1: enable
DefTime, IECN,
IECV, IECE, IECST,
Option of characteristic curve for
IECLT, ANSIE,
22 50/51P2.Opt_Curve stage 2 of phase overcurrent
ANSIV, ANSI,
protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
protection.
protection
25 50/51P3.I_Set (0.050~30.000)×In 0.001 A
26 50/51P3.t_Op 0.000~20.000 0.001 s
27 50/51P3.En 0 or 1
0: disable
1: enable
28 50/51P3.En_BlkAR 0 or 1 Enabling/Disabling auto-reclosing

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overcurrent protection operates
0: disable
1: enable
0: disable
1: enable
Non_Directional
Reverse
0: disable
1: enable
DefTime, IECN,
IECV, IECE, IECST,
IECLT, ANSIE,
ANSIV, ANSI,
protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
protection.
protection
35 50/51P4.I_Set (0.050~30.000)×In 0.001 A
36 50/51P4.t_Op 0.000~20.000 0.001 s
37 50/51P4.En 0 or 1
0: disable
1: enable
38 50/51P4.En_BlkAR 0 or 1 overcurrent protection operates
0: disable
1: enable
39 50/51P4.En_VTS_Blk 0 or 1

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by VT circuit failure
0: disable
1: enable
Non_Directional
Reverse
0: disable
1: enable
DefTime, IECN,
IECV, IECE, IECST,
IECLT, ANSIE,
ANSIV, ANSI,
protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
protection.
protection
3.7 Earth Fault Protection

During normal operation of power system, there is trace residual current, whereas a fault current
flows to earth will result in greater residual current. Therefore, residual current is adopted for the
calculation of earth fault protection.
In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
line-transformer unit, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.
Earth fault protection has following functions:
1. Four-stage earth fault protection with independent logic, current and time delay settings.

characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of earth fault protection.
3. Directional element can be selected to control each stage of earth fault protection with three

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options: no direction, forward direction and reverse direction.
4. Second harmonic can be selected to block each stage of earth fault protection.
5. Stage 2, 3 or 4 of earth fatul protection can select short time delay to accelerate to trip.
6. All stages will operate to trip three-phase for any fault.
3.7.2.1 Overview
Earth fault protection consists of following three elements:
1. Overcurrent element: each stage equipped with one independent overcurrent element.
2. Directional control element: one direction control element shared by all overcurrent elements,
3. Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.
3.7.2.2 Directional Earth-fault Element
The operation criterion for each stage of earth fault protection is:
3I0>[50/51Gx.3I0_Set] Equation 3.7-1
Where:
3I0 is the calculated residual current.
[50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection.
3.7.2.4 Harmonic Blocking Element
In order to prevent effects of inrush current on earth fault protection, harmonic blocking function
can be selected for each stage of earth fault element by configuring logic setting
[50/51Gx.En_Hm2_Blk] (x=1, 2, 3 or 4).
When the percentage of second harmonic component to fundamental component of residual

current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled
Operation criterion:
Equation 3.7-2
Where:
is second harmonic of residual current

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is fundamental component of residual current.
[50/51G.K_Hm2] is harmonic blocking coefficient.
If fundamental component of residual current is lower than the minimum operating current (0.1In)
then harmonic calculation is not carried out and harmonic blocking element does not operate.
All 4 stages earth fault protection can be selected as definite-time or inverse-time characteristic,
and inverse-time operating time curve is as follows.
Equation 3.7-3
Where:
Iset is residual current setting [50/51Gx.3I0_Set].
Tp is time multiplier setting [50/51Gx.TMS].
K is a constant
C is a constant.
α is a constant.
3I0 is the calculated residual current.
setting [50/51Gx.Opt_Curve], and parameters of available characteristics for selection are shown
50/51Gx.Opt_Curve Time Characteristic K α C


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UserDefine Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with
configuration tool software. (only stage 1)
[50/51Gx.tmin], then the operating time of the protection changes to the value of setting
[50/51Gx.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.
50/51Gx
50/51Gx.En1 50/51Gx.On
50/51Gx.En2 50/51Gx.On_ShortDly
50/51Gx.Blk 50/51Gx.St
50/51Gx.En_ShortDly 50/51Gx.Op
50/51Gx.Blk_ShortDly
3.7.4 I/O Signals
Table 3.7-2 I/O signals of earth fault protection

Stage x of earth fault protection enabling input 1, it is triggered from binary
1 50/51Gx.En1
Stage x of earth fault protection enabling input 2, it is triggered from binary
2 50/51Gx.En2
Stage x of earth fault protection blocking input, it is triggered from binary input
3 50/51Gx.Blk
4 50/51Gx.En_ShortDly Enable accelerating stage x of earth fault protection. (x=2, 3, 4)
5 50/51Gx.Blk_ShortDly Accelerating stage x of earth fault protection is disabled. (x=2, 3, 4)
1 50/51Gx.On Stage x of earth fault protection is enabled.
2 50/51Gx.On_ShortDly Stage x of earth fault protection with short time delay is enabled. (x=2, 3, 4)
3 50/51Gx.St Stage x of earth fault protection starts.
4 50/51Gx.Op Stage x of earth fault protection operates.

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3.7.5 Logic
EN [50/51G1.En]
&
SIG 50/51G1.En1 &
50/51G1.On
SIG 50/51G1.En2
SIG 50/51G1.Blk
SET 3I0>[50/51G1.3I0_Set]
EN [50/51G1.En_Abnor_Blk] >=1
SIG No abnormal conditions
&
SET [50/51G1.Opt_Dir]=Forward &

& &
& 50/51G1.St
SIG Forward DIR
>=1
SET [50/51G1.Opt_Dir]=Reverse & >=1
& Timer
t
SIG Reverse DIR
SET [50/51G1.Opt_Dir]=Non_Directional
SIG CTS.Alm &
EN [50/51G1.En_CTS_Blk]
>=1 >=1
SIG I3P 2nd Hm Detect & & 50/51G1.Op
[50/51G1.t_Op] 0
SET [50/51G1.En_Hm2_Blk]
SET [50/51G1.Opt_Curve]=DefTime
Figure 3.7-1 Logic diagram of earth fault protection (stage 1)

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EN [50/51Gx.En]
&
SIG 50/51Gx.En1 &
50/51Gx.On
SIG 50/51Gx.En2
SIG 50/51Gx.Blk
SET 3I0>[50/51Gx.3I0_Set]
EN [50/51Gx.En_Abnor_Blk] >=1
SIG No abnormal conditions
&
SET [50/51Gx.Opt_Dir]=Forward &

& &
& 50/51Gx.St
SIG Forward DIR
>=1
SET [50/51Gx.Opt_Dir]=Reverse & >=1
& Timer
t
SIG Reverse DIR
SET [50/51Gx.Opt_Dir]=Non_Directional
SIG CTS.Alm &
EN [50/51Gx.En_CTS_Blk]
>=1
SIG I3P 2nd Hm Detect & &
[50/51Gx.t_Op] 0
SET [50/51Gx.En_Hm2_Blk]
>=1
SET [50/51Gx.Opt_Curve]=DefTime & 50/51Gx.Op
[50/51Gx.t_ShortDly] 0
EN [50/51Gx.En_ShortDly]
&
SIG [50/51Gx.En_ShortDly] 50/51Gx.On_ShortDly
SIG [50/51Gx.Blk_ShortDly]
Figure 3.7-2 Logic diagram of earth fault protection (stage x)
Where:
x=2, 3, 4
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by
direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”,
the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is
set as “0”, earth fault protection is not controlled by direction element.

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3.7.6 Settings
Table 3.7-3 Settings of earth fault protection

Setting of second harmonic
1 50/51G.K_Hm2 0.000~1.000 0.001 component for blocking earth
fault elements
Current setting for stage 1 of
2 50/51G1.3I0_Set (0.050~30.000)×In 0.001 A
earth fault protection
Time delay for stage 1 of earth
3 50/51G1.t_Op 0.000~20.000 0.001 s
fault protection
Enabling/disabling stage 1 of
4 50/51G1.En 0 or 1
0: disable
1: enable
blocked when stage 1 of earth
5 50/51G1.En_BlkAR 0 or 1 fault protection operates
0: disable
1: enable
Non_Directional
Direction option for stage 1 of
6 50/51G1.Opt_Dir Forward
Reverse
Enabling/disabling second
harmonic blocking for stage 1 of
7 50/51G1.En_Hm2_Blk 0 or 1 earth fault protection
0: disable
1: enable
Enabling/disabling blocking for
stage 1 of earth fault protection
8 50/51G1.En_Abnor_Blk 0 or 1 under abnormal conditions
0: disable
1: enable
9 50/51G1.En_CTS_Blk 0 or 1 under CT failure conditions
0: disable
1: enable
DefTime, IECN,
IECV, IECE,
IECST, IECLT, Option of characteristic curve for
10 50/51G1.Opt_Curve 1
ANSIE, ANSIV, stage 1 of earth fault protection
ANSI, ANSIM,
ANSILTE,

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ANSILTV, ANSILT,
UserDefine
Time multiplier setting for stage 1
11 50/51G1.TMS 0.010~200.000 0.001 of inverse-time earth fault
protection
Minimum operating time for stage
12 50/51G1.tmin 0.050~20.000 0.001 s 1 of inverse-time earth fault
protection
13 50/51G1.Alpha 0.010~5.000 0.001
characteristic earth fault
protection
14 50/51G1.C 0.000~20.000 0.001
protection
15 50/51G1.K 0.050~20.000 0.001
protection
16 50/51G2.3I0_Set (0.050~30.000)×In 0.001 A
17 50/51G2.t_Op 0.000~20.000 0.001 s
fault protection
Short time delay for stage 2 of
18 50/51G2.t_ShortDly 0.000~20.000 0.001 s
19 50/51G2.En 0 or 1
0: disable
1: enable
Enabling/disabling accelerate
20 50/51G2.En_ShortDly 0 or 1
0: disable
1: enable
0: disable
1: enable
Non_Directional
Reverse
23 50/51G2.En_Hm2_Blk 0 or 1

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0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime, IECN,
IECV, IECE,
IECST, IECLT,
26 50/51G2.Opt_Curve ANSIE, ANSIV,
ANSI, ANSIM,
ANSILTE,
ANSILTV, ANSILT
protection
protection
29 50/51G3.3I0_Set (0.050~30.000)×In 0.001 A
30 50/51G3.t_Op 0.000~20.000 0.001 s
fault protection
31 50/51G3.t_ShortDly 0.000~20.000 0.001 s
Non_Directional
32 50/51G3.En Forward
Reverse
0: disable
1: enable
0: disable
1: enable

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35 50/51G3.Opt_Dir 0 or 1 0: no direction
1: forward direction
2: reverse direction
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime, IECN,
IECV, IECE,
IECST, IECLT,
ANSI, ANSIM,
ANSILTE,
ANSILTV, ANSILT
protection
protection
42 50/51G4.3I0_Set (0.050~30.000)×In 0.001 A
43 50/51G4.t_Op 0.000~20.000 0.001 s
fault protection
44 50/51G4.t_ShortDly 0.000~20.000 0.001 s
Non_Directional
45 50/51G4.En Forward
Reverse

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0: disable
1: enable
0: disable
1: enable
48 50/51G4.Opt_Dir 0 or 1 0: no direction
1: forward direction
2: reverse direction
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
DefTime, IECN,
IECV, IECE,
IECST, IECLT,
ANSI, ANSIM,
ANSILTE,
ANSILTV, ANSILT
protection
protection

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3.8 Dead Zone Protection

Generally, fault current is very large when multi-phase fault occurs between CT and circuit breaker
(i.e. dead zone) and it will have a greater impact on the system. Breaker failure protection can
operate after a longer time delay, in order to clear the dead zone fault quickly and improve the
system stability, dead zone protection with shorter time delay (compared with breaker failure
protection) is adopted.
For some wiring arrangement (for example, circuit breaker is located between CT and the line), if
fault occurs between CT and circuit breaker, line protection can operate to trip circuit breaker
quickly, but the fault have not been cleared since local circuit breaker is tripped. Here dead zone
protection is needed in order to trip relevant circuit breaker.
3.8.3 Protection Principle
The criterion for dead zone protection is: when dead zone protection is enabled, binary input of
initiating dead zone protection is energized (by default, three-phase tripping signal is used to
initiate dead zone protection), if overcurrent element for dead zone protection operates, then
corresponding circuit breaker is tripped and three phases normally closed contact of the circuit
breaker are energized, dead zone protection will operate to trip adjacent circuit breaker after a
time delay.
50DZ
50DZ.En1 50DZ.On
50DZ.En2
50DZ.St
50DZ.Blk
50DZ.Op
50DZ.Init
3.8.5 I/O Signal
Table 3.8-1 I/O signals of dead zone protection

Dead zone protection enabling input 1, it is triggered from binary input or
1 50DZ.En1
programmable logic etc.
Dead zone protection enabling input 2, it is triggered from binary input or
2 50DZ.En2
Dead zone protection blocking input, it is triggered from binary input or
3 50DZ.Blk
programmable logic etc
4 50DZ.Init Initiation signal input of the dead zone protection.

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1 50DZ.On Dead zone protection is enabled.
2 50DZ.St Dead zone protection starts.
3 50DZ.Op Dead zone protection operates.
3.8.6 Logic
The logic diagram of dead zone protection is shown as below.
EN [50DZ.En]
&
SIG 50DZ.En1 &
50DZ.On
SIG 50DZ.En2
SIG 50DZ.Blk
BI [52b_PhA]
&
BI [52b_PhB]
BI [52b_PhC]
50DZ.St
SET Ia > [50DZ.I_Set]
&
>=1 & [50DZ.t_Op] 0ms 50DZ.Op
SET Ib > [50DZ.I_Set]
SET Ic > [50DZ.I_Set]
SIG 50DZ.Init
Figure 3.8-1 Logic diagram of dead zone protection
3.8.7 Settings
Table 3.8-2 Settings of dead zone protection

Current setting for dead zone
protection. This setting shall ensure
1 50DZ.I_Set (0.050~30.000)×In 0.001 A
the protection being sensitive
enough if dead zone fault occurs.
Time delay of dead zone
2 50DZ.t_Op 0.000~10.000 0.001 s
protection.
Enabling/disabling dead zone
protection
3 50DZ.En 0 or 1 -
0: disable
1: enable
3.9 Voltage Protection

Voltage protection has the function of protecting device against undervoltage and overvoltage.
Both operational states are unfavorable as overvoltage may cause insulation breakdown while

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undervoltage may cause stability problem. Each voltage protection function has three individual
stages with respective time delay. These voltage protection functions can be enabled or disabled
separately. Selectable definite-time characteristic and multiple inverse-time characteristics are
available.
3.9.1 Overvoltage Protection
3.9.1.1 General Application
Abnormal high voltages often occur e.g. in low loaded, long distance transmission lines, in
islanded systems when generator voltage regulation fails, or load rejection of a generator. Even if
compensation reactors are provided to avoid line overvoltage by compensation of the line
capacitance and thus reduction of the overvoltage, the overvoltage will endanger the insulation if
the reactors fail. The line must be de-energized within a very short time.
The overvoltage protection in this device detects the phase voltages Ua, Ub and Uc or the
phase-to-phase voltages Uab, Ubc and Uca with an option of any phase or all phases operation
for output. The overvoltage protection can be used for tripping purpose as well as to initiate
transfer trip, which selectable controlled by local circuit breaker.
3.9.1.2 Function Description
Phase overvoltage protection has following functions:
1. Three-stage phase overvoltage protection with independent logic, voltage and time delay
settings.
2. Stage 1, stage 2 and stage 3 can be selected as definite-time or inverse-time characteristic.
The inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard
inverse-time characteristics.
3. Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4. “1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1. Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[59Px.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [59Px.Opt_Up/Upp] is
set to “1”, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting,
the stage protection picks up and operates after delay, which will drop off instantaneously when
fault voltage disappears.
 Phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].

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UΦ_max>[59Px.U_Set] Equation 3.9-1
or
Ua>[59Px.U_Set] & Ub>[59Px.U_Set] & Uc>[59Px.U_Set] Equation 3.9-2
Where:
UΦ_max is the maximum value among three phase-voltage.
Ua, Ub, Uc are three phase voltages.
[59Px.U_Set] is the setting of stage x (x=1, 2 or 3) overvoltage protection.
When [59Px.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.9-1) is selected as operation
criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.9-2) is selected.
 Phase-to-phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
UΦΦ_max>[ 59Px.U_Set] Equation 3.9-3
or
Uab>[59Px.U_Set] & Ubc>[59Px.U_Set] & Uca>[59Px.U_Set] Equation 3.9-4
[59Px.U_Set] is the setting of stage x (x =1, 2 or 3) overvoltage protection.
2. Characteristic Curve
Phase overvoltage protection stage x (x =1, 2 or 3) can be selected as definite-time or inverse-time

characteristic, and inverse-time operating time curve is as follows.
Where:
Uset is the voltage setting [59Px.U_Set] (x=1, 2 or 3).
Tp is time multiplier setting [59Px.TMS].
K is a constant.
C is a constant.
α is a constant.
U is the measured voltage

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For stage x (x =1, 2 or 3) of overvoltage protection, operating characteristic can be chosen from
definite-time characteristic and 12 inverse-time characteristics by setting the logic setting
[59Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
59Px.Opt_Curve Time Characteristic K α C
Def_Time Definite time
[59Px.tmin], then the operating time changes to the value of setting [59Px.tmin] automatically.
Define-time or inverse-time phase overvoltage protection drops off instantaneously when

measured voltage is lower than reset voltage.

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3.9.1.3 Function Block Diagram
59Px
59Px.En1 59Px.On
59Px.En2 59Px.St
59Px.Blk 59Px.St1
59Px.St2
59Px.St3
59Px.Op
59Px.Alm
59Px.Op_InitTT
3.9.1.4 I/O Signals
Table 3.9-2 I/O signals of overvoltage protection

Stage x of overvoltage protection enabling input 1, it is triggered from binary input
1 59Px.En1
Stage x of overvoltage protection enabling input 2, it is triggered from binary input
2 59Px.En2
Stage x of overvoltage protection blocking input, it is triggered from binary input or
3 59Px.Blk
1 59Px.On Stage x of overvoltage protection is enabled.
2 59Px.Op Stage x of overvoltage protection operates.
3 59Px.St Stage x of overvoltage protection starts.
4 59Px.St1 Stage x of overvoltage protection starts (A or AB).
5 59Px.St2 Stage x of overvoltage protection starts (B or BC).
6 59Px.St3 Stage x of overvoltage protection starts (C or CA).
7 59Px.Op_InitTT Stage x of overvoltage protection operates to initiate transfer trip.
8 59Px.Alm Stage x of overvoltage protection alarms.

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3.9.1.5 Logic
EN [59Px.En]
&
SIG 59Px.En1 &
59Px.On
SIG 59Px.En2
SIG 59Px.Blk
BI [52b_PhA]
&
BI [52b_PhB] &
BI [52b_PhC]
EN [59Px.En_52b_TT]
&
>=1
EN [59Px.En_TT] 59Px.Op_InitTT
EN [59Px.En_Alm] &
SIG FD.Pkp &
SIG 59Px.On
[59Px.Opt_Up/Upp] Timer
EN & & t
>=1 t
&
SET UA>[59Px.U_Set] &
&
SET UAB>[59Px.U_Set]
Timer
& & t
>=1
SET UB>[59Px.U_Set]
t &
59Px.Op
&
SET UBC>[59Px.U_Set]
&
>=1 >=1 59Px.Alm
Timer
& & t
&
>=1 t
SET UC>[59Px.U_Set]
&
>=1
59Px.St
SET UCA>[59Px.U_Set]
59Px.St1
59Px.St2
EN [59Px.Opt_1P/3P] 59Px.St3
Figure 3.9-1 Logic diagram of stage x of overvoltage protection
x=1, 2 or 3
3.9.1.6 Settings
Table 3.9-3 Settings of overvoltage protection

Voltage setting for stage 1 of overvoltage
1 59P1.U_Set Un~2Unn 0.001 V
protection
Time delay for stage 1 of overvoltage
2 59P1.t_Op 0.000~30.000 0.001 s
protection
Enabling/disabling stage 1 of overvoltage
protection
3 59P1.En 0 or 1
0: disable
1: enable

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Option of 1-out-of-3 mode or 3-out-of-3

mode
4 59P1.Opt_1P/3P 0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase
voltage
5 59P1.Opt_Up/Upp 0 or 1
0: phase voltage
1: phase-to-phase voltage
protection for alarm purpose
6 59P1.En_Alm 0 or 1
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage 1 of
7 59P1.En_52b_TT 0 or 1 overvoltage protection
0: disable
1: enable
protection operate to initiate transfer trip
8 59P1.En_TT 0 or 1
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
Option of characteristic curve for stage 1 of
9 59P1.Opt_Curve ANSIV, ANSI,
overvoltage protection
ANSIM,
ANSILTE,
ANSILTV,
ANSILT
10 59P1.TMS 0.010~200.000 0.001
inverse-time overvoltage protection
Minimum delay for stage 1 of inverse-time
11 59P1.tmin 0.050~20.000 0.001 s
12 59P2.U_Set Un~2Unn 0.001 V
protection
13 59P2.t_Op 0.000~30.000 0.001 s
protection
protection
14 59P2.En 0 or 1
0: disable
1: enable
15 59P2.Opt_1P/3P 0 or 1
mode

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0: 3-out-of-3 mode
1: 1-out-of-3 mode
voltage
0: phase voltage
17 59P2.En_Alm 0 or 1
0: disable
1: enable
0: disable
1: enable
19 59P2.En_TT 0 or 1
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
ANSIM,
ANSILTE,
ANSILTV,
ANSILT
21 59P2.TMS 0.010~200.000 0.001
22 59P2.tmin 0.050~20.000 0.001 s
23 59P3.U_Set Un~2Unn 0.001 V
protection
24 59P3.t_Op 0.000~30.000 0.001 s
protection
protection
25 59P3.En 0 or 1
0: disable
1: enable
mode
26 59P3.Opt_1P/3P 0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode

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voltage
0: phase voltage
28 59P3.En_Alm 0 or 1
0: disable
1: enable
0: disable
1: enable
30 59P3.En_TT 0 or 1
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
ANSIM,
ANSILTE,
ANSILTV, Option of characteristic curve for stage 3 of
ANSILT overvoltage protection
32 59P3.TMS 0.010~200.000 0.001
33 59P3.tmin 0.050~20.000 0.001 s
3.9.2 Negative Sequence Overvoltage Protection
One stage negative sequence overvoltage protection is available for the device, it can be applied
according to the actual requirement.
59Q
59Q.En1 59Q.On
59Q.En2 59Q.Op
59Q.Blk 59Q.St

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3.9.2.2 I/O Signal
Table 3.9-4 I/O signals of negative sequence overvoltage protection

Negative sequence overvoltage protection enabling input 1, it is triggered from
1 59Q.En1
Negative sequence overvoltage protection enabling input 2, it is triggered from
2 59Q.En2
Negative sequence overvoltage protection blocking input, it is triggered from
3 59Q.Blk
binary input or programmable logic etc
1 59Q.On Negative sequence overvoltage protection is enabled.
2 59Q.St Negative sequence overvoltage protection starts.
3 59Q.Op Negative sequence overvoltage protection operates.
3.9.2.3 Logic
The logic diagram of negative sequence overvoltage protection is shown as below.
SIG 59Q.En1 &

SIG 59Q.En2 &
EN [59Q.En] 59Q.On
SIG 59Q.Blk
[59Q.t_Op] 59Q.Op
&
59Q.StA
SET U2>[59Q.U_Set]
Figure 3.9-2 Logic diagram of negative sequence overvoltage protection
3.9.2.4 Settings
Table 3.9-5 Settings of negative sequence overvoltage protection

Voltage setting for negative
1 59Q.U_Set 0~Unn 0.001 V
sequence overvoltage protection.
Time delay of negative sequence
2 59Q.t_Op 0.000~30.000 0.001 s
overvoltage protection.
Enabling/disabling negative
sequence overvoltage protection
3 59Q.En 0 or 1 -
0: disable
1: enable

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3.9.3 Residual Overvoltage Protection
A single phase earth fault occurrence in ungrounded system or Peterson coil grounded system will
result in residual overvoltage, so residual overvoltage protection is equipped to prevent protected
equipment being damaged by residual overvoltage in this condition.
Residual overvoltage protection has following functions
1. Three-stage residual overvoltage protection with independent logic, voltage and time delay
settings.
2. Stage 1 is definite-time characteristic, stage 2 and 3 can be selected as definite-time or

inverse-time characteristic, only stage 3 can be defined for trip purpose or alarm purpose. The
inverse-time characteristic is selectable among IEC and ANSI/IEEE standard inverse-time
characteristics and a user-defined inverse-time curve.
3. Define-time or inverse-time residual overvoltage protection drops off instantaneously.
 Operation Criterion
3U0> [59Gx.3U0_Set] Equation 3.9-5
Where:
3U0 is calculated residual voltage.
[59Gx.3U0_Set] is the voltage setting of stage x (x=1, 2 or 3) of residual overvoltage protection.
If residual voltage is greater than the setting of any stage enabled residual overvoltage protection,
the stage residual overvoltage protection will operate after time delay and the stage protection will
drop off instantaneously after fault voltage disappears.
 Time Curve
Stage 1 of residual overvoltage protection is definite-time characteristic and can perform

instantaneous operation with the corresponding time delay being set as “0”. Stage 2 and 3 can be
selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as
follows.
Equation 3.9-6
Where:
Uset is residual voltage setting [59Gx.3U0_Set].
Tp is time setting [59Gx.TMS].

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K and C are constants.
α is a constant.
U is actual measured residual voltage.
setting [59Gx.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
Table 3.9-6 Inverse-time curve parameters of residual overvoltage protection
59Gx.Opt_Curve (x=2 or 3) Time Characteristic K α C

UserDefine Programmable user-defined
If all available curves do not comply with user application, user may configure setting
[59Gx.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C.
59G
59Gx.En1 59Gx.On
59Gx.En2 59Gx.St
59Gx.Blk 59Gx.Op
59G3.Alm
3.9.3.4 I/O Signals
Table 3.9-7 I/O signals of residual overvoltage protection
No. Signal Description

1 59Gx.En1 Stage x of residual overvoltage protection enabling input 1, it is triggered from binary

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input or programmable logic etc. (x=1, 2, 3)
Stage x of residual overvoltage protection enabling input 2, it is triggered from binary
2 59Gx.En2
input or programmable logic etc. (x=1, 2, 3)
Stage x of overvoltage protection blocking input, it is triggered from binary input or
3 59Gx.Blk
programmable logic etc. (x=1, 2, 3)
1 59G x.On Stage x of residual overvoltage protection is enabled. (x=1, 2, 3)
2 59G x.Op Stage x of residual overvoltage protection operates. (x=1, 2, 3)
3 59Gx.St Stage x of residual overvoltage protection start. (x=1, 2, 3)
4 59G3.Alm Stage 3 of residual overvoltage protection operates to alarm.
3.9.3.5 Logic
EN [59G1.En]
&
SIG 59G1.En1 &
59G1.On
SIG 59G1.En2
SIG 59G1.Blk
&
59G1.St
SET 3U0>[59G1.3U0_Set]
[59G1.t_Op] 0 59G1.Op
Figure 3.9-3 Logic diagram of stage 1 of residual overvoltage protection
EN [59G2.En]
&
SIG 59G2.En1 &
59G2.On
SIG 59G2.En2
SIG 59G2.Blk
&
59G2.St
& Timer
t
t
>=1
& 59G2.Op
[59G2.t_Op] 0
SET [59G2.Opt_Curve]=DefTime

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EN [59G3.En]
&
SIG 59G3.En1 &
59G3.On
SIG 59G3.En2
SIG 59G3.Blk
&
59G3.St
& Timer
t
t
>=1
&
[59G3.t_Op] 0
SET [59G3.Opt_Curve]=DefTime
&
59G3.Op
EN [59G3.En_Trp]
&
59G3.Alm
3.9.3.6 Settings
Table 3.9-8 Settings of residual overvoltage protection

Voltage setting of stage 1 of residual
1 59G1.3U0_Set 0~Unn 0.001 V
Time delay of stage 1 of residual
2 59G1.t_Op 0.000~3600.000 0.001 s
Enabling/disabling stage 1 of residual
3 59G1.En 0 or 1
0: disable
1: enable
4 59G2.3U0_Set 0~Unn 0.001 V
5 59G2.t_Op 0.000~3600.000 0.001 s
6 59G2.En 0 or 1
0: disable
1: enable
DefTime
IECN
IECV Option of characteristic curve for stage 2
7 59G2.Opt_Curve
IECE of residual overvoltage protection
IECST
IECLT

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ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
8 59G2.TMS 0.010~200.00 0.001
residual overvoltage protection
Minimum operating time for stage 2 of
9 59G2.tmin 0.050~20.000 0.001 s
Constant “α” for stage 2 of customized
10 59G2.Alpha 0.010~5.000 0.001 inverse-time characteristic residual
Constant “C” for stage 2 of customized
11 59G2.C 0.000~20.000 0.001 inverse-time characteristic residual
Constant “K” for stage 2 of customized
12 59G2.K 0.050~20.000 0.001 inverse-time characteristic residual
13 59G3.3U0_Set 0~Unn 0.001 V
14 59G3.t_Op 0.000~3600.000 0.001 s
15 59G3.En 0 or 1
0: disable
1: enable
overvoltage protection for trip purpose.
16 59G3.En_Trp 0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST Option of characteristic curve for stage 3
17 59G3.Opt_Curve
IECLT of residual overvoltage protection
ANSIE
ANSIV
ANSI
ANSIM

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ANSILTE
ANSILTV
ANSILT
UserDefine
18 59G3.TMS 0.010~200.00 0.001
19 59G3.tmin 0.050~20.000 0.001 s
20 59G3.Alpha 0.010~5.000 0.001 inverse-time characteristic residual
21 59G3.C 0.000~20.000 0.001 inverse-time characteristic residual
22 59G3.K 0.050~20.000 0.001 inverse-time characteristic residual
3.9.4 Undervoltage Protection
The undervoltage protection can be applied to trip when fault occurs in a system. Three stages of
undervoltage protection are available measuring phase voltages UA, UB and UC or phase-to-phase
voltages UAB, UBC and UCA. The protection output can be selected for either any phase or all
phases operation. The undervoltage protection is normally used as decoupling system rather than
load shedding.
Phase undervoltage protection has following functions:
1. Three-stage phase undervoltage protection with independent logic, voltage and time delay
settings.
2. Stage x (x=1, 2 or 3) can be selected as definite-time or inverse-time characteristic. The

inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics.
3. Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4. “1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1. Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[27Px.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [27Px.Opt_Up/Upp] is

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set to “1”, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is less than any enabled stage voltage setting, the
stage protection picks up and operates after delay, which will drop off instantaneously when fault
voltage disappears.
 Phase voltage criterion
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
UΦ_min<[27Px.U_Set] Equation 3.9-7
or
Ua<[ 27Px.U_Set] & Ub<[27Px.U_Set] & Uc<[27Px.U_Set] Equation 3.9-8
Where:
UΦ_min is the minimum value among three phase voltages.
Ua, Ub and Uc are three phase voltages.
[27Px.U_Set] is the setting of stage x (x=1, 2 or 3) undervoltage protection.
 Phase-to-phase voltage criterion
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_Up/Upp].
UΦΦ_min<[ 27Px.U_Set] Equation 3.9-9
or
Uab<[27Px.U_Set] & Ubc<[27Px.U_Set] & Uca<[27Px.U_Set] Equation 3.9-10
Where:
UΦΦ_min is the minimum value among three phase-to-phase voltages.
Uab, Ubc and Uca are three phase-to-phase voltages.
[27Px.U_Set] is the setting of stage x (x =1, 2 or 3) undervoltage protection.
When the setting [27Px.Opt_1P/3P] is set as “0”, “1-out-of-3” logic (Equation 3.9-9) is selected as
operation criterion, and when it is set as “1”, “3-out-of-3” logic (Equation 3.9-10) is selected.
2. Characteristic Curve
Undervoltage protection stage x (x =1, 2 or 3) can be selected as definite-time or inverse-time

characteristic, and inverse-time operating time curve is as follows.

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Where:
Uset is the setting [27Px.U_Set] (x=1, 2 or 3).
Tp is time multiplier setting [27Px.TMS].
K is a constant.
C is a constant.
α is a constant.
U is the measured voltage
For stage x (x =1, 2 or 3) of undervoltage protection, operating characteristic can be chosen from
definite-time characteristic and twelve inverse-time characteristics by setting the logic setting
[27Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
Table 3.9-9 Inverse-time curve parameters of phase undervoltage protection
27Px.Opt_Curve Time Characteristic K α C
Def_Time Definite time
[27Px.tmin], then the operating time changes to the value of setting [27Px.tmin] automatically.

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Define-time or inverse-time phase undervoltage protection drops off instantaneously when

measured voltage is higher than reset voltage.
27Px
27Px.En1 27Px.On
27Px.En2 27Px.Alm
27Px.Blk 27Px.Op
27Px.St
27Px.St1
27Px.St2
27Px.St3
27Px.U_Absent
3.9.4.4 I/O Signals
Table 3.9-10 I/O signals of undervoltage protection

Stage x of undervoltage protection enabling input 1, it is triggered from binary
1 27Px.En1
Stage x of undervoltage protection enabling input 2, it is triggered from binary
2 27Px.En2
Stage x of undervoltage protection blocking input, it is triggered from binary input
3 27Px.Blk
1 27Px.On Stage x of undervoltage protection is enabled.
2 27Px.Op Stage x of undervoltage protection operates.
3 27Px.Alm Stage x of undervoltage protection alarms.
4 27Px.St Stage x of undervoltage protection starts.
5 27Px.St1 Stage x of undervoltage protection starts (A or AB).
6 27Px.St2 Stage x of undervoltage protection starts (B or BC).
7 27Px.St3 Stage x of undervoltage protection starts (C or CA).
8 27Px.U_Absent No voltage is detected after the device is powered.
3.9.4.5 Logic
According to different application requirement, the undervoltage protection can be blocked or

released by following conditions.
1. Current FD element: including DPFC current element, residual current element and other FD
element that related to current (the blocking condition can enabled or disabled by the logic
setting [27Px.En_FD_Ctrl])

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2. Having current condition (>0.06In) (the blocking condition can enabled or disabled by the
logic setting [27Px.En_Curr_Ctrl])
3. VT circuit failure signal (the blocking condition can enabled or disabled by the logic setting
[27Px.En_VTS_Blk])
4. If any phase of circuit breaker is open (binary input of normal close contact of breaker is
energized and the corresponding phase current is smaller than 0.06In), the undervoltage
protection will be blocked.
After the device is powered, if any phase current is larger than 0.06In or the circuit breaker is
closed, the undervoltage protection is enabled with a time delay of 100ms only when any phase
voltage is larger than 0.1Un, otherwise the alarm signal [27Px.U_Absent] will be issued after the
device is powered.
SIG VTS.Alm &

>=1
EN [27Px.En_VTS_Blk] Block UV
EN [27Px.En_FD_Ctrl] &
SIG FD.Pkp
SIG CB Open
SIG 27Px.U_Absent
Figure 3.9-6 Blocking logic of undervoltage protection
SIG Ia>0.06In >=1

UV_PhA_Curr_Rls
SIG Ib>0.06In >=1

UV_PhB_Curr_Rls
SIG Ic>0.06In >=1

UV_PhC_Curr_Rls
&
>=1
UV_PhAB_Curr_Rls
&
>=1
UV_PhBC_Curr_Rls
&
>=1
UV_PhCA_Curr_Rls
En 27Px.En_Curr_Ctrl

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Figure 3.9-7 Logic of having current condition
EN [27Px.En]
&
SIG 27Px.En1 &
27Px.On
SIG 27Px.En2
SIG 27Px.Blk
EN [27Px.En_Alm]
SET [27P1.Opt_1P/3P]
SIG 27Px.On
SIG Block UV
SET [27Px.Opt_Up/Upp] & & Timer &

t
SIG UV_PhA_Curr_Rls >=1 &
t
SET UA<[27Px.U_Set]
&
SIG UV_PhB_Curr_Rls
SET UAB<[27Px.U_Set]
Timer &
& &
t 27Px.Op
SIG UV_PhC_Curr_Rls >=1
t
SET UB<[27Px.U_Set]
&
&
>=1 27Px.Alm
SIG UV_PhAB_Curr_Rls
&
SET UBC<[27Px.U_Set]
>=1
& & Timer
t
SIG UV_PhBC_Curr_Rls >=1
t
SET UC<[27Px.U_Set]
& >=1
SIG UV_PhCA_Curr_Rls 27Px.St
SET UCA<[27Px.U_Set]
27Px.St1
27Px.St2
27Px.St3
Figure 3.9-8 Logic diagram of stage x of undervoltage protection
x=1, 2 or 3
3.9.4.6 Settings
Table 3.9-11 Settings of undervoltage protection

Voltage setting for stage 1 of undervoltage
1 27P1.U_Set 0~Unn 0.001 V
protection
Time delay for stage 1 of undervoltage
2 27P1.t_Op 0.000~30.000 0.001 s
protection
undervoltage protection
3 27P1.En 0 or 1
0: disable
1: enable
4 27P1.Opt_1P/3P 0 or 1
mode

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0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of voltage criterion adopting
phase-to-phase voltage or phase voltage
0: phase voltage
undervoltage protection operate to alarm
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
Option of characteristic curve for stage 1
7 27P1.Opt_Curve ANSIV, ANSI, 1
of undervoltage protection
ANSIM,
ANSILTE,
ANSILTV,
ANSILT
8 27P1.TMS 0.010~200.000 0.001
inverse-time undervoltage protection
9 27P1.tmin 0.050~20.000 0.001 s
undervoltage protection been controlled
10 27P1.En_FD_Ctrl 0 or 1 by current related fault detector element
0: disable
1: enable
11 27P1.En_Curr_Ctrl 0 or 1 by having current condition
0: disable
1: enable
undervoltage protection been blocked by
12 27P1.En_VTS_Blk 0 or 1 VT circuit failure
0: disable
1: enable
13 27P2.U_Set 0~Unn 0.001 V
protection
14 27P2.t_Op 0.000~30.000 0.001 s
protection
15 27P2.En 0 or 1

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0: disable
1: enable
mode
16 27P2.Opt_1P/3P 0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
0: phase voltage
18 27P2.En_Alm 0 or 1
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
ANSIM,
ANSILTE,
ANSILTV,
ANSILT
20 27P2.TMS 0.010~200.000 0.001
21 27P2.tmin 0.050~20.000 0.001 s
0: disable
1: enable
0: disable
1: enable
undervoltage protection been blocked by
24 27P2.En_VTS_Blk 0 or 1 VT circuit failure
0: disable
1: enable
25 27P3.U_Set 0~Unn 0.001 V
protection

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26 27P3.t_Op 0.000~30.000 0.001 s
protection
27 27P3.En 0 or 1
0: disable
1: enable
mode
28 27P3.Opt_1P/3P 0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
0: phase voltage
30 27P3.En_Alm 0 or 1
0: disable
1: enable
DefTime,
IECN, IECV,
IECE, IECST,
IECLT, ANSIE,
ANSIM,
ANSILTE,
ANSILTV,
ANSILT
32 27P3.TMS 0.010~200.000 0.001
33 27P3.tmin 0.050~20.000 0.001 s
0: disable
1: enable
0: disable
1: enable
36 27P3.En_VTS_Blk 0 or 1 undervoltage protection been blocked by
VT circuit failure

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0: disable
1: enable
3.10 Negative-sequence Overcurrent Protection

When an asymmetric short-circuit fault happens to the power system or the power system is under
asymmetrical three-phase operation, the power system will generate negative-sequence current.
Negative-sequence current will cause serious damage to generator, motor and other equipments,
so negative-sequence overcurrent protection is used to prevent the damage. In order to make
sure the selectivity of negative-sequence overcurrent protection in multiplex power supply system,
negative-sequence overcurrent protection can be controlled by direction control element.
Negative-sequence overcurrent has following functions:
1. Four-stage negative-sequence overcurrent protection with independent logic, current and

time delay settings.
2. Each stage can be selected to block AR by the setting and stage 4 of negative-sequence
overcurrent protection can be selected to operate to trip or alarm.

characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of negative-sequence
overcurrent protection.
4. Directional element can be selected to control each stage of negative-sequence overcurrent

protection with three options: no direction, forward direction and reverse direction.
5. CT circuit failure can be selected to block each stage of negative-sequence overcurrent

protection.
6. Each stage can select independent releasing threshold based on the ratio of
negative-sequence current to positive-sequence current to prevent negative-sequence
overcurrent protection from undesired operation for three-phase fault with asymmetrical
position exchange of three-phase.
3.10.2.1 Overview
Negative-sequence overcurrent protection consists of following four elements:
1. Fault detector: each stage is controlled by the fault detector based on negative-sequence
current. Negative-sequence overcurrent protection can operate when the fault detector based
on negative-sequence current operate and it is enabled.
2. Overcurrent element: each stage equipped with one independent overcurrent element.
3. Directional control element: one direction control element shared by all overcurrent elements,

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4. Ratio element: each stage is equipped with one independent ratio element (I2/I1), usually the
same setting is applied for all stages.
3.10.2.2 Negative-sequence Overcurrent Element
The operation criterion for each stage of negative-sequence overcurrent protection is:
I2>[50/51Qx.I2_Set] Equation 3.10-1
Where:
I2 is the calculated negative-sequence current.
[50/51Qx.I2_Set] is the current setting of stage x (x=1, 2, 3 or 4) of negative-sequence overcurrent

protection.
All four stages negative-sequence overcurrent protection can be selected as definite-time or

inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.10-2
Where:
Iset is negative-sequence curren setting [50/51Qx.I2_Set].
Tp is time multiplier setting [50/51Qx.TMS].
K is a constant
C is a constant.
α is a constant.
I2 is the calculated negative-sequence current.
setting [50/51Qx.Opt_Curve], and parameters of available characteristics for selection are shown


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UserDefine Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Qx.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with
configuration tool software. (only stage 1)
[50/51Qx.tmin], then the operating time of the protection changes to the value of setting
[50/51Qx.tmin] automatically.
Define-time or inverse-time directional negative-sequence overcurrent protection drops off

instantaneously after fault current disappears.
50/51Qx
50/51Gx.En1 50/51Qx.On
50/51Gx.En2 50/51Qx.St
50/51Qx.Blk 50/51Qx.Op
50/51Q4.Alm
3.10.4 I/O Signals
Table 3.10-2 I/O signals of negative-sequence overcurrent protection

Stage x of negative-sequence overcurrent protection enabling input 1, it is
1 50/51Qx.En1
triggered from binary input or programmable logic etc.
Stage x of negative-sequence overcurrent protection enabling input 2, it is
2 50/51Qx.En2

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Stage x of negative-sequence overcurrent protection blocking input, it is triggered

3 50/51Qx.Blk
1 50/51Qx.On Stage x of negative-sequence overcurrent protection is enabled.
2 50/51Qx.St Stage x of negative-sequence overcurrent protection starts.
3 50/51Qx.Op Stage x of negative-sequence overcurrent protection operates.
4 50/51Q4.Alm Stage 4 of negative-sequence overcurrent protection operates to alarm.
3.10.5 Logic
EN [50/51Qx.En]
&
SIG 50/51Qx.En1 &
50/51Qx.On
SIG 50/51Qx.En2
SIG 50/51Qx.Blk
SET I2/I1>[50/51Qx.I2/I1_Set] &
SET I2>[50/51Qx.I2_Set]
EN [50/51Qx.En_Abnor_Blk] >=1
& & &
SIG No abnormal conditions 50/51Qx.St
& Timer
t
50/51Qx.Op
t
SET [50/51Qx.Opt_Dir]=Forward &
SIG Forward DIR

>=1
SET [50/51Qx.Opt_Dir]=Reverse & >=1
SIG Reverse DIR
SET [50/51Qx.Opt_Dir]=Non_Directional
SIG CTS.Alm &
EN [50/51Qx.En_CTS_Blk]
SIG FD.NOC.Pkp
Figure 3.10-1 Logic diagram of negative-sequence overcurrent protection
x=1, 2 or 3
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR,
negative-sequence overcurrent protection will operate. If the logic setting [50/51Qx.En_Abnor_Blk]
is set as “1”, the stage x of negative-sequence overcurrent protection will be blocked. If the logic
setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not
controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting

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[50/51Qx.En_Abnor_Blk] is set as “1”, the stage x of negative-sequence overcurrent protection will

be blocked. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence
overcurrent protection is not controlled by direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “1”,
the stage x of negative-sequence overcurrent protection will be blocked. If the logic setting
[50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not controlled
by direction element.
EN [50/51Q4.En]
&
SIG 50/51Q4.En1 &
50/51Q4.On
SIG 50/51Q4.En2
SIG 50/51Q4.Blk
SET I2/I1>[50/51Q4.I2/I1_Set] &
SET I2>[50/51Q4.I2_Set]
EN [50/51Q4.En_Abnor_Blk] >=1
& & &
SIG No abnormal conditions 50/51Q4.St
&
SET [50/51Q4.Opt_Dir]=Forward &
SIG Forward DIR

>=1
SET [50/51Q4.Opt_Dir]=Reverse & >=1
SIG Reverse DIR
& Timer
SET [50/51Q4.Opt_Dir]=Non_Directional t
50/51Q4.Alm
t
SIG CTS.Alm &
EN [50/51Q4.En_CTS_Blk]
& Timer
SIG FD.NOC.Pkp t
50/51Q4.Op
t
EN [50/51Q4.En_Trp]
Figure 3.10-2 Logic diagram of stage 4 of negative-sequence overcurrent protection
3.10.6 Settings
Table 3.10-3 Settings of negative-sequence overcurrent protection

1 50/51Q1.I2_Set (0.050~30.000)×In 0.001 A negative-sequence overcurrent
protection
Ratio coefficient (I2/I1) for stage 1
2 50/51Q1.I2/I1_Set 0.00~1.00 0.01
of negative-sequence overcurrent

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protection
Time delay for stage 1 of
3 50/51Q1.t_Op 0.000~20.000 0.001 s negative-sequence overcurrent
protection
negative-sequence overcurrent
4 50/51Q1.En 0 or 1 protection
0: disable
1: enable
blocked when stage 1 of
5 50/51Q1.En_BlkAR 0 or 1
protection operates
0: disable
1: enable
Non_Directional Direction option for stage 1 of
6 50/51Q1.Opt_Dir Forward negative-sequence overcurrent
Reverse protection
stage 1 of negative-sequence
overcurrent protection under
7 50/51Q1.En_Abnor_Blk 0 or 1
abnormal conditions
0: disable
1: enable
overcurrent protection under CT
8 50/51Q1.En_CTS_Blk 0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT Option of characteristic curve for
9 50/51Q1.Opt_Curve ANSIE stage 1 of negative-sequence
ANSIV overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT

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UserDefine
of inverse-time
10 50/51Q1.TMS 0.010~200.000 0.001
protection
1 of inverse-time
11 50/51Q1.tmin 0.050~20.000 0.001 s
protection
12 50/51Q1.Alpha 0.010~5.000 0.001
characteristic negative-sequence
13 50/51Q1.C 0.000~20.000 0.001
14 50/51Q1.K 0.050~20.000 0.001
protection
16 50/51Q2.I2/I1_Set 0.00~1.00 0.01 of negative-sequence overcurrent
protection
protection
0: disable
1: enable
19 50/51Q2.En_BlkAR 0 or 1
protection operates
0: disable
1: enable
20 50/51Q2.Opt_Dir
Forward negative-sequence overcurrent

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Reverse protection
abnormal conditions
0: disable
1: enable
22 50/51Q2.En_CTS_Blk 0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
of inverse-time
24 50/51Q2.TMS 0.010~200.000 0.001
protection
2 of inverse-time
25 50/51Q2.tmin 0.050~20.000 0.001 s
protection
protection
protection
protection

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0: disable
1: enable
30 50/51Q3.En_BlkAR 0 or 1
protection operates
0: disable
1: enable
Reverse protection
abnormal conditions
0: disable
1: enable
33 50/51Q3.En_CTS_Blk 0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
of inverse-time
35 50/51Q3.TMS 0.010~200.000 0.001
protection

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3 of inverse-time
36 50/51Q3.tmin 0.050~20.000 0.001 s
protection
protection
protection
protection
0: disable
1: enable
Enabling/Disabling stage 4 of
41 50/51Q4.En_Trp 0 or 1 protection operate to trip or alarm.
0: alarm
1: trip
42 50/51Q4.En_BlkAR 0 or 1
protection operates
0: disable
1: enable
Reverse protection
abnormal conditions
0: disable
1: enable
45 50/51Q4.En_CTS_Blk 0 or 1 overcurrent protection under CT
failure conditions
0: disable

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1: enable
DefTime
IECN
IECV
IECE
IECST
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
of inverse-time
47 50/51Q4.TMS 0.010~200.000 0.001
protection
4 of inverse-time
48 50/51Q4.tmin 0.050~20.000 0.001 s
protection
3.11 Frequency Calculation

The frequency is an important parameter to characterize power system, and the measurement and
calculation of frequency are the basis of many protection functions. The frequency calculation
module can accurately calculate the frequency of voltage component.
Protection device can be applied to the power system within frequency range of 40Hz~63Hz, the
reference frequency can be set as 50Hz or 60Hz via the system setting [Opt_SysFreq].
Protection device provide frequency tracing function, which can improve the accuracy of protection
algorithm and the performance of protection devices. For the power system using 50Hz or 60Hz
as reference frequency, the frequency tracing function can be disabled if the fluctuation of the
frequency range is not great. For the power system that the fluctuation of the frequency range is
great, the frequency tracing function can be enabled to improve protection performance.
Frequency tracing module adopts the positive-sequence voltage which derived from protection
used voltage as the calculation reference, the positive-sequence voltage can be calculated as
following:

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U 1 = (U a + U b e j120 + U c e j 240 ) / 3
When no VT is connected to the protection device, the frequency tracing function is disabled
automatically, then the protection device calculates protection algorithm using the system
reference frequency. When the protection device detects a fault happening to the power system or
the voltage is smaller than 0.15Un, the frequency tracing function is disabled.
This module, which combines all aboving cases, outputs system frequency to the various
protection functions.
FreqCal
FreqTrack f
fn Alm_Freq
3.11.4 I/O Signal
Table 3.11-1 I/O signals of frequency calculation function

It is used to enabled or disable frequency track function by the configuration
1 FreqTrack
software PCS-Explorer.
2 fn It is the system frequency, which is decided by the setting [Opt_SysFreq].
1 f Frequency calculation result
2 Alm_Freq Frequency abnormality alarm
3.11.5 Logic
The logic diagram of frequency calculation function is shown as below.
SIG U3P
fn Freqence
SIG f
calulation
SIG FreqTrace
SIG f<[f_Low_FreqAlm] >=1

Alm_Freq
SIG f>[f_High_FreqAlm]
Figure 3.11-1 Logic diagram of frequency calculation function
FreqTrance: Frequency calculation function is enabled.

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3.11.6 Settings
Refer to the settings of system parameter module.
3.12 Frequency Protection

3.12.1 Overfrequency Protection
If the power frequency of regional rises due to the active power excess demand, overfrequency
protection operates to perform generator rejection to shed part of the generators automatically
according to the rising frequency so that power supply and the load are re-balanced.
Overfrequency protection consists of the four stages (stage 1 to stage 4). When system frequency
is greater than the setting [81O.f_Pkp], overfrequency protection will put into service.
In order to prevent possible maloperation of overfreqency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1. Blocking in undervoltage condition
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2. Frequency abnormality condition
When f<40Hz or f>65Hz, overfrequency protection will be blocked
Operation criteria of overfrequency protection is shown in the following equation.
f>[81O.OFx.f_Set] Equation 3.12-1
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection.
81O.OFx
81O.En1 81O.OFx.On
81O.En2 81O.St
81O.Blk 81O.OFx.Op

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3.12.1.4 I/O Signals
Table 3.12-1 I/O signals of overfrequency protection

Overfrequency protection enabling input 1, it is triggered from binary input or
1 81O.En1
Overfrequency protection enabling input 2, it is triggered from binary input or
2 81O.En2
Overfrequency protection blocking input, it is triggered from binary input or
3 81O.Blk
1 81O.OFx.On Stage x of overfrequency protection is enabled (x=1, 2, 3 or 4).
2 81O.OFx.Op Stage x of overfrequency protection operates (x=1, 2, 3 or 4).
3 81O.St Overfrequency protection starts.
3.12.1.5 Logic
SIG 81O.En1
&
SIG 81O.En2 &
81O.OF1.On
EN [81O.OF1.En]
SIG 81O.Blk
&
SIG FD.Pkp
OTH U1<0.15Un ≥1
SIG f＜40 or f＞65

&
OTH f>[81O.f_Pkp] 50ms 0ms

81O.St1
&
SET f>[81O.OF1.f_Set] & [81O.OF1.t_Op] 0ms 81O.OF1.Op
EN [81O.OF1.En]
Figure 3.12-1 Logic diagram of overfrequency protection (stage 1)
SIG 81O.En1
&
SIG 81O.En2 &
81O.OF2.On
EN [81O.OF2.En]
SIG 81O.Blk
&
SIG FD.Pkp
OTH U1<0.15Un ≥1

&

81O.St2
&
EN [81O.OF2.En]

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SIG 81O.En1
&
SIG 81O.En2 &
EN [81O.OF3.En]
81O.OF3.On
SIG 81O.Blk
&
SIG FD.Pkp
OTH U1<0.15Un ≥1

&

81O.St3
&
EN [81O.OF3.En]
SIG 81O.En1
&
SIG 81O.En2 &
81O.OF4.On
EN [81O.OF4.En]
SIG 81O.Blk
&
SIG FD.Pkp
OTH U1<0.15Un ≥1

&

81O.St4
&
EN [81O.OF4.En]
SIG 81O.St1 ≥1
SIG 81O.St2
≥1
SIG 81O.St3 ≥1 81O.St
SIG 81O.St4
Figure 3.12-5 Logic diagram of overfrequency protection (start)
3.12.1.6 Settings
Table 3.12-2 Settings of overfrequency protection

1 81O.f_Pkp 50.000~65.000 (Hz) 0.001 Hz Frequency pickup setting for

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overfrequency protection
Frequency setting for stage 1 of
2 81O.OF1.f_Set 50.000~65.000 (Hz) 0.001 Hz
3 81O.OF1.t_Op 0.000~20.000 (s) 0.001 s
4 81O.OF1.En 0 or 1
0: disable
1: enable
5 81O.OF2.f_Set 50.000~65.000 (Hz) 0.001 Hz
6 81O.OF2.t_Op 0.000~20.000 (s) 0.001 s
7 81O.OF2.En 0 or 1
0: disable
1: enable
8 81O.OF3.f_Set 50.000~65.000 (Hz) 0.001 Hz
9 81O.OF3.t_Op 0.000~20.000 (s) 0.001 s
10 81O.OF3.En 0 or 1
0: disable
1: enable
11 81O.OF4.f_Set 50.000~65.000 (Hz) 0.001 Hz
12 81O.OF4.t_Op 0.000~20.000 (s) 0.001 s
13 81O.OF4.En 0 or 1
0: disable
1: enable
3.12.2 Underfrequency Protection
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to
re-balance the power supply and the load.
Underfrequency protection consists of the four stages (stage 1 to stage 4). When system
frequency is smaller than the setting [81U.f_Pkp], underfrequency protection will put into service.

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In order to prevent possible maloperation of underfrequency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1. Blocking in undervoltage condition
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2. df/dt blocking element
If －df/dt≥[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
3. Frequency abnormality condition
When f<40Hz or f>65Hz, underfrequency protection will be blocked
Operation criteria of underfrequency protection is shown in the following equation.
f<[81U.UFx.f_Set] Equation 3.12-2
Where:
f is system frequency.
[81U.UFx.f_Set] is the frequency settings of stage x (x=1, 2, 3 or 4) of underfrequency protection.
The equation of df/dt blocking function is as follows.
df/dt≥[81U.df/dt_Blk] Equation 3.12-3
Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calucation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[81U.UFx.En_df/dt_Blk] (x=1, 2, 3 or 4) is set as “1”, when Equation 3.12-2 and Equation 3.12-3
are met, it is decided that a fault occurred and the corresponding stage underfrequency protection
is blocked at the same time for the purpose of waiting for operation of other related protection. The
blocking signal will not reset until the system frequency recovers, i.e. the system frequency is
greater than the setting [81U.f_Pkp]. If the logic setting is set as “0”, when Equation 3.12-2 and
Equation 3.12-3 are met, the stage underfrequency protection will be released to operate.

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81U.UFx
81U.En1 81U.UFx.On
81U.En2 81U.St
81U.Blk 81U.UFx.Op
3.12.2.4 I/O Signals
Table 3.12-3 I/O signals of underfrequency protection

Underfrequency protection enabling input 1, it is triggered from binary input or
1 81U.En1
Underfrequency protection enabling input 2, it is triggered from binary input or
2 81U.En2
Underfrequency protection blocking input, it is triggered from binary input or
3 81U.Blk
1 81U.UFx.On Stage x of underfrequency protection is enabled (x=1, 2, 3 or 4).
2 81U.UFx.Op Stage x of underfrequency protection operates (x=1, 2, 3 or 4).
3 81U.St Underfrequency protection starts.
3.12.2.5 Logic
SIG 81U.En1
&
SIG 81U.En2
EN [81U.UF1.En]
&
81U.UF1.On
SIG 81U.Blk
&
SIG FD.Pkp &
OTH U1<0.15Un ≥1
SIG f<40 or f>65
OTH f<[81U.f_Pkp] 50ms 0ms

81U.St1
SET -df/dt>[81U.df/dt_Blk] >=1 &
[81U.UF1.t_Op] 0ms 81U.UF1.Op
EN 81U.UF1.En_df/dt_Blk
SET f<[81U.UF1.f_Set] &
EN [81U.UF1.En]
Figure 3.12-6 Logic diagram of underfrequency protection (stag1)

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SIG 81U.En1
&
SIG 81U.En2
EN [81U.UF2.En]
&
81U.UF2.On
SIG 81U.Blk
&
SIG FD.Pkp &
OTH U1<0.15Un ≥1
SIG f<40 or f>65

81U.St2
EN [81U.UF2.En]
SIG 81U.En1
&
SIG 81U.En2
EN [81U.UF3.En]
&
81U.UF3.On
SIG 81U.Blk
&
SIG FD.Pkp &
OTH U1<0.15Un ≥1
SIG f<40 or f>65

81U.St3
EN [81U.UF3.En]

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SIG 81U.En1
&
SIG 81U.En2
EN [81U.UF4.En]
&
81U.UF4.On
SIG 81U.Blk
&
SIG FD.Pkp &
OTH U1<0.15Un ≥1
SIG f<40 or f>65

81U.St4
EN [81U.UF4.En]
SIG 81U.St1 >=1
SIG 81U.St2
>=1
SIG 81U.St3 >=1 81U.St
SIG 81U.St4
Figure 3.12-10 Logic diagram of underfrequency protection (start)
3.12.2.6 Settings
Table 3.12-4 Settings of underfrequency protection

Frequency pickup setting for
1 81U.f_Pkp 45.000~60.000 0.01 Hz
underfrequency protection
Rate of frequency change for
2 81U.df/dt_Blk 0.200~20.000 0.01 Hz/s
blocking underfrequency protection
3 81U.UF1.f_Set 45.000~60.000 0.001 Hz
4 81U.UF1.t_Op 0.000~30.000 0.01 s
5 81U.UF1.En 0 or 1
0: disable
1: enable
6 81U.UF1.En_df/dt_Blk 0 or 1 Enabling/disabling rate of frequency

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change to block stage 1 of

0: disable
1: enable
7 81U.UF2.f_Set 45.000~60.000 0.001 Hz
8 81U.UF2.t_Op 0.000~30.000 0.01 s
9 81U.UF2.En 0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
10 81U.UF2.En_df/dt_Blk 0 or 1 underfrequency protection
0: disable
1: enable
11 81U.UF3.f_Set 45.000~60.000 0.001 Hz
12 81U.UF3.t_Op 0.000~30.000 0.01 s
13 81U.UF3.En 0 or 1
0: disable
1: enable
0: disable
1: enable
15 81U.UF4.f_Set 45.000~60.000 0.001 Hz
16 81U.UF4.t_Op 0.000~30.000 0.01 s
17 81U.UF4.En 0 or 1
0: disable
1: enable
0: disable
1: enable

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3.13 Breaker Failure Protection

Duplicated protection configurations are usually adopted for EHV power system, but the primary
equipment, circuit breaker, is not duplicated. Breaker failure protection is adopted to cater circuit
breaker tripping failure.
Breaker failure protection issues a back-up trip command to trip adjacent circuit breakers in case
of a tripping failure of the circuit breaker, and clears the fault as requested by the device. To utilize
the protection information of faulty equipment and the electrical information of failure circuit
breaker to constitute the criterion of breaker failure protection, it can ensure that the adjacent
circuit breakers of failure circuit breaker are tripped with a shorter time delay, so that the affected
area is minimized, and ensure stable operation of the entire power grid to prevent generators,
transformers and other components from seriously damaged.
The instantaneous re-tripping function, after receiving tripping signal from other device and the
corresponding phase overcurrent element operating, is available and provides phase-segregated
binary output contact, which can ensure the circuit breaker is still tripped in case the secondary
circuit between the device and the circuit breaker is abnormal, to avoid undesired tripping of
breaker failure protection and the expansion of the affected area. Instantaneous re-tripping
function does not block AR.
When both the phase-segregated tripping contact from line protection and the corresponding
phase overcurrent element operate, or both the three-phase tripping contact and any phase
overcurrent element operate, breaker failure protection will send three-phase tripping command to
trip local circuit breaker after time delay of [50BF.t1_Op] and trip all adjacent circuit breakers after
time delay of [50BF.t2_Op].
When the protection element except undervoltage element within this device operates and issues
tripping signal, breaker failure protection will also be initiated.
Taking into account that the faulty current is too small for generator or transformer fault, the
sensitivity of phase current element may not meet the requirements, residual current criterion and
negative-sequence current criterion are provided in addition to the phase overcurrent element for
breaker failure protection initiated by input signal [50BF.ExTrp3P_GT] from generator and
transformer protection. They can be enabled or disabled by logic settings [50BF.En_3I0_3P] and
[50BF.En_I2_3P] respectively.
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal [50BF.ExTrp_WOI] is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact (52b) as an option criterion for breaker failure check.

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50BF
50BF.ExTrp3P_L 50BF.On
50BF.ExTrp3P_GT 50BF.Op_ReTrpA
50BF.ExTrp_WOI 50BF.Op_ReTrpB
50BF.ExTrpA 50BF.Op_ReTrpC
50BF.ExTrpB 50BF.Op_ReTrp3P
50BF.ExTrpC 50BF.Op_t1
50BF.En 50BF.Op_t2
50BF.Blk
3.13.4 I/O Signals
Table 3.13-1 I/O signals of breaker failure protection

1 50BF.ExTrp3P_L Input signal of three-phase tripping contact from line protection
Input signal of three-phase tripping contact from generator or transformer
2 50BF.ExTrp3P_GT
protection
3 50BF.ExTrpA Input signal of phase-A tripping contact from external device
4 50BF.ExTrpB Input signal of phase-B tripping contact from external device
5 50BF.ExTrpC Input signal of phase-C tripping contact from external device
Input signal of three-phase tripping contact from external device. Once it is
6 50BF.ExTrp_WOI energized, normally closed auxiliary contact of circuit breaker is chosen in
addition to breaker failure current check to trigger breaker failure timers.
Breaker failure protection enabling input, it is triggered from binary input or
7 50BF.En
Breaker failure protection blocking input, it is triggered from binary input or
8 50BF.Blk
1 50BF.On Breaker failure protection is enabled
2 50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker
3 50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker
4 50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker
5 50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phase circuit breaker
6 50BF.Op_t1 Stage 1 breaker failure protection operates
7 50BF.Op_t2 Stage 2 breaker failure protection operates

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3.13.5 Logic
SIG 50BF.En
&
EN [50BF.En] 50BF.On
SIG 50BF.Blk
SIG 50BF.On
&
SIG FD.Pkp
EN [50BF.En_ReTrp]
EN [50BF.En_3I0_1P] >=1
SET 3I0>[50BF.3I0_Set]
&
SIG BFI_A >=1 & [50BF.t_ReTrp] 0ms 50BF.Op_ReTrpA
BI [50BF.ExTrpA]
SET IA>[50BF.I_Set]
&
SIG BFI_B >=1 & [50BF.t_ReTrp] 0ms 50BF.Op_ReTrpB
BI [50BF.ExTrpB]
SET IB>[50BF.I_Set]
&
SIG BFI_C >=1 & [50BF.t_ReTrp] 0ms 50BF.Op_ReTrpC
BI [50BF.ExTrpC] >=1
SET IC>[50BF.I_Set] >=1
SIG BFI_3P >=1

&
& >=1
BI [50BF.ExTrp3P_L]
>=1 [50BF.t_ReTrp] 0ms [50BF.Op_ReTrp3P]
BI [50BF.ExTrp3P_GT] >=1
&
BI [50BF.ExTrp_WOI]
&
EN [50BF.En_3I0_3P] &
SET 3I0>[50BF.3I0_Set]
& >=1 >=1 [50BF.t1_Op] 0ms 50BF.Op_t1
EN [50BF.En_I2_3P] & &
[50BF.t2_Op] 0ms 50BF.Op_t2
SET I2>[50BF.I2_Set]
&
EN [50BF.En_CB_Ctrl]
BI [52b_PhA]
&
BI [52b_PhB]
BI [52b_PhC]
SIG 50BF.On &
SIG FD.Pkp
Figure 3.13-1 Logic diagram of breaker failure protection
Where:
BFI_A, BFI_B, BFI_C: A-phase, B-phase and C-phase breaker failure protection initiating signal,
please refer to Figure 3.17-1.

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3.13.6 Settings
Table 3.13-2 Settings of breaker failure protection

Current setting of phase current
1 50BF.I_Set (0.050~30.000)×In 0.001 A
criterion for BFP
Current setting of zero-sequence
2 50BF.3I0_Set (0.050~30.000)×In 0.001 A
current criterion for BFP
Current setting of
3 50BF.I2_Set (0.050~30.000)×In 0.001 A negative-sequence current
criterion for BFP
4 50BF.t_ReTrp 0.000~10.000 0.001 s Time delay of re-tripping for BFP
5 50BF.t1_Op 0.000~10.000 0.001 s Time delay of stage 1 for BFP
6 50BF.t2_Op 0.000~10.000 0.001 s Time delay of stage 2 for BFP

Enabling/disabling breaker failure
protection
7 50BF.En 0 or 1
0: disable
1: enable
Enabling/disabling re-trip function
for BFP
8 50BF.En_ReTrp 0 or 1
0: disable
1: enable
Enabling/disabling zero-sequence
current criterion for BFP initiated by
9 50BF.En_3I0_1P 0 or 1 single-phase tripping contact
0: disable
1: enable
Enabling/disabling zero-sequence
current criterion for BFP initiated by
10 50BF.En_3I0_3P 0 or 1 three-phase tripping contact
0: disable
1: enable
Enabling/disabling
negative-sequence current criterion
for BFP initiated by three-phase
11 50BF.En_I2_3P 0 or 1
tripping contact
0: disable
1: enable
Enabling/disabling breaker failure
protection can be initiated by
normally closed contact of circuit
12 50BF.En_CB_Ctrl 0 or 1
breaker
0: disable
1: enable
3.14 Pole Discrepancy Protection

The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated

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operating gears for the three phases. The reason could be an interruption in the tripping/closing
circuits, or mechanical failure. A pole discrepancy can only be tolerated for a limited period. When
there is loading, zero-sequence or negative-sequence current will be generated in the power
system, which will result in overheat of the generator or the motor. With the load current increasing,
overcurrent elements based on residual current or negative-sequence current may operate. Pole
discrepancy protection is required to operate before the operation of these overcurrent elements.
Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its
phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy
protection, the asymmetrical current component can be selected as addition criteria when needed.
62PD
62PD.En1 62PD.On
62PD.En2 62PD.St
62PD.Blk 62PD.Op
62PD.In_PD
3.14.4 I/O Signals
Table 3.14-1 I/O signals of pole discrepancy protection

1 I3P Three-phase current input
Pole discrepancy protection enabling input 1, it is triggered from binary input or
2 62PD.En1
Pole discrepancy protection enabling input 2, it is triggered from binary input or
3 62PD.En2
Pole discrepancy protection blocking input, it is triggered from binary input or
4 62PD.Blk
5 62PD.In_PD Pole discrepancy binary input
1 62PD.On Pole discrepancy protection is enabled
2 62PD.St Pole discrepancy protection starts
3 62PD.Op Pole discrepancy protection operates to trip
3.14.5 Logic
Pole discrepancy protection can be initiated following method.
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy

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protection will be started and initiate output after a time delay [62PD.t_Op].
Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.
SIG 62PD.En1
&
SIG 62PD.En2 &
62PD.On
EN [62PD.En]
SIG 62PD.Blk
&
SIG FD.Pkp
62PD.St
EN [62PD.En_3I0/I2_Ctrl] >=1 &
[62PD.t_Op] 0ms 62PD.Op
SET 3I0>[62PD.3I0_Set] >=1
SET I2>[62PD.I2_Set]
BI [52b_PhA] &
&
SIG Ia<0.06In
BI [52b_PhB] & &
SIG Ib<0.06In
>=1
BI [52b_PhC] &
SIG Ic<0.06In
Figure 3.14-1 Logic diagram of pole discrepancy protection
Where:
3I0: Calculated residual current by vector sum of Ia, Ib and Ic.
3.14.6 Settings
Table 3.14-2 Settings of pole discrepancy protection

Current setting of residual
1 62PD.3I0_Set (0.050~30.000)×In 0.001 A current criterion for pole
discrepancy protection
Current setting of
negative-sequence current
2 62PD.I2_Set (0.050~30.000)×In 0.001 A
criterion for pole discrepancy
protection
Time delay of pole
3 62PD.t_Op 0.000~600.000 0.001 s
Enabling/disabling pole
4 62PD.En 0 or 1 discrepancy protection
0: disable

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1: enable
Enabling/disabling residual
current criterion and
negative-sequence current
5 62PD.En_3I0/I2_Ctrl 0 or 1 criterion for pole discrepancy
protection
0: disable
1: enable
3.15 Synchrocheck
The purpose of synchrocheck is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchrocheck to avoid this situation and maintain the system
stability. The synchrocheck includes synchronism check and dead charge check.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits.
The dead charge check function measures the amplitude of reference voltage and synchronism
voltage, and then compare them with the live check setting [25.U_Lv] and the dead check setting
[25.U_Dd]. The output is only given when the measured quantities comply with the criteria.
Synchrocheck in this device can be used for auto-reclosing and manual closing for both
single-breaker and dual-breakers. Details are described in the following sections.
When used for the synchrocheck of single-breaker, comparative relationship between reference
voltage (Uref) and synchronism voltage (Usyn) for synchrocheck is as follows.
Uref Usyn
Figure 3.15-1 Relationship between reference voltage and synchronism voltage
Figure 3.15-1 shows the characteristics of synchronism check element used for the auto-reclosing

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3 Operation Theory
if both reference voltage and synchronism voltage are live. The synchronism check element
operates if voltage difference, phase angle difference and frequency difference are all within their
setting values.
1. The voltage difference is checked by the following equations.
Usyn≥[25.U_Lv]
Uref≥[25.U_Lv]
|Usyn- Uref|≤[25.U_Diff]
2. The phase difference is checked by the following equations.
Usyn×Uref×cosØ≥0
Usyn×Uref×sin([25.phi_Diff]) ≥Usyn×Uref×|sinØ|
Where,
Ø is phase difference between Usyn and Uref
3. The frequency difference is checked by the following equations.
|f(Usyn)-f(Uref)|≤[25.f_Diff]
If frequency check is disabled (i.e. [25.En_fDiffChk] is set as “0”), a detected maximum slip cycle
can also be determined by the following equation based on phase difference setting and the
synchronism check time setting:
f =[25.phi_Diff]/(180×[25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [25.En_fDiffChk] is set as “1”), then [25.t_SynChk] can be set to
be a very small value (default value is 50ms).
This function module supports voltage switching. In general, voltage switching is fulfilled by
external circuit (the setting [CBConfigMode]=NoVoltSel); if using this module to fulfill voltage
switching, the busbar arrangement should be determined (determined by the setting
[CBConfigMode]), including double busbars arrangement ([CBConfigMode]=DblBusOneCB) and
1½ breakers arrangement ([CBConfigMode]=3/2BusCB or [CBConfigMode]=3/2TieCB).
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on. According to the voltage switching result,
synchrocheck logic choose one voltage to be used for synchrocheck function, synchrocheck
function requires to judgment the phase identification information of the voltage, which is
determined by the setting [25.Opt_Source_UL1], please refer to the setting description of
[25.Opt_Source_UL1] for details. If voltage switching function is not used, the reference voltage
will be selected from UL1 fixedly.

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UB1: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting [25.Opt_Source_UB1],
please refer to the setting description of [25.Opt_Source_UB1] for details. If voltage switching
function is not used, UB1 will be taken as the synchronism voltage.
UL2: according to the voltage switching result, synchrocheck logic determined whether the voltage
identification information of the voltage, which is determined by the setting [25.Opt_Source_UL2],
please refer to the setting description of [25.Opt_Source_UL2] for details. When voltage switching
is available, it is only used for 1½ breakers arrangement, it is fixedly connected to the voltage of
the other line of the same diameter in 1½ breakers arrangement.
identification information of the voltage, which is determined by the setting [25.Opt_Source_UB2],
please refer to the setting description of [25.Opt_Source_UB2] for details. When voltage switching
is available, it is connected to synchronism voltage for double busbars arrangement or 1½
breakers arrangement.
3.15.2.1 Single Busbar Arrangement
Voltage selection function is not required for this busbar arrangement, the connection of the
voltage signals and respective VT MCB auxiliary contacts to the device is shown in the Figure
3.15-2 and Figure 3.15-3.
1. Three-phase bus voltage used for protection ([VTS.En_LineVT]=0)
Bus
} Ua
UL1 Ub CB
Uc
25.MCB_VT_UL1
UB1
25.MCB_VT_UB1
Line
Figure 3.15-2 Voltage connection for single busbar arrangement
Three-phase protection voltages are from busbar VT. As shown in above figure, the reference
voltage (Uref) is selected among three-phase protection voltages, and synchronism voltage (Usyn)
is from line VT.
2. Three-phase line voltage used for protection ([VTS.En_LineVT]=1)

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Bus
UB1 CB
25.MCB_VT_UB1
} Ua
UL1 Ub
Uc
25.MCB_VT_UL1 Line
Figure 3.15-3 Voltage connection for single busbar arrangement
In the figures, the setting [VTS.En_LineVT] is used to determine protection voltage signals (Ua, Ub,
Uc) from line VT or bus VT according to the condition. This setting is only used for VT circuit failure
logic, and it does not affect the synchrocheck mode. Three-phase protection voltages are from line
VT, as shown in above figure, the reference voltage (Uref) is selected among UL1 three-phase
protection voltages, and synchronism voltage (Usyn) is from busbar VT.
3.15.2.2 Double Busbars Arrangement
Bus2
Bus1
B1D B2D
UB1
25.MCB_VT_UB1
UB2
25.MCB_VT_UB2
25.NC_UB1DS
25.NO_UB1DS } CB
25.NC_UB2DS
25.NO_UB2DS }
} Ua
UL1 Ub
Line
Uc
25.MCB_VT_UL1
Figure 3.15-4 Voltage connection for double busbars arrangement
For double busbars arrangement, selection of appropriate voltage signals from Bus 1 and Bus 2
for synchronizing are required. Line VT signal is taken as reference voltage (Uref) to check

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synchronizing with the voltage after voltage selection function. Selection approach is as follows.
For the disconnector positions, the normally open (NO) and normally closed (NC) contacts of the
disconnector for bus 1 and bus 2 are required to determine the disconnector open and closed
positions. The voltage selection logic is as follows.
BI 25.NO_UB1DS &
UB1_Sel
BI 25.NC_UB1DS
Voltage
Selection Logic
BI 25.NO_UB2DS &
UB2_Sel
BI 25.NC_UB2DS
&
Alm_Invalid_Sel
UB1 UB(Usyn)
UB2
Figure 3.15-5 Voltage selection for double busbars arrangement
After acquiring the disconnector open and closed positions of double busbars, use the following
logic to acquire the feeder voltage of double busbars.
DS2 CLOSED DS2 OPEN

DS1 CLOSED Keep original value Voltage from Bus 1 VT (UB1_Sel=1)
DS1 OPEN Voltage from Bus 2 VT (UB2_Sel=1) Keep original value
DS1 is disconnector of Bus 1
DS2 is disconnector of Bus 2
If voltage selection is invalid (Alm_Invalid_Sel=1), keep original selection and without switchover.
3.15.2.3 One and A Half Breakers Arrangement
For one and a half breakers arrangement, selection of appropriate voltage signals among Line1
VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1 voltage signal
for closing breaker at Bus 1 side.

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Bus1
UB1
25.MCB_VT_UB1
25.NC_UB1DS
25.NO_UB1DS } B1D
} Ua Line 1
UL1 Ub
Uc
25.MCB_VT_UL1
L1D
25.NC_UL1DS
25.NO_UL1DS } Line 2
UL2
25.MCB_VT_UL2
25.NC_UL2DS
25.NO_UL2DS }
}
L2D
25.NC_UB2DS
25.NO_UB2DS
UB2
25.MCB_VT_UB2
B2D
Bus2
Figure 3.15-6 Voltage connection for one and a half breakers arrangement
For the circuit breaker at bus side (take bus breaker of Bus 1 as an example), the device acquires
the disconnector open and closed positions of two feeders and Bus 2. The voltage selection logic
is as follows.

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3 Operation Theory
BI 25.NO_UL1DS &
UL1_Sel
BI 25.NC_UL1DS
&
BI 25.NO_UL2DS & UL2_Sel
BI 25.NC_UL2DS
&
BI 25.NO_UB2DS & UB2_Sel
BI 25.NC_UB2DS
&
Alm_Invalid_Sel
UL1 UL(Uref)
UL2
UB2
UB1 UB(Usyn)
Figure 3.15-7 Voltage selection for bus CB of one and a half breakers arrangement
For the tie breaker, the device acquires the disconnector open and closed positions of two feeders
and two busbars. Either Line 1 VT or Bus 1 VT signal is selected as reference voltage to check
synchronizing with the selected voltage between Line 2 VT and Bus 2 VT. The voltage selection
logic is as follows.

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BI 25.NO_UL1DS &
UL1_Sel
BI 25.NC_UL1DS
&
BI 25.NC_UB1DS
&
UL1 UL(Uref)
UB1
BI 25.NO_UL2DS &
UL2_Sel
BI 25.NC_UL2DS
&
BI 25.NC_UB2DS
>=1
& Alm_Invalid_Sel
UL2 UB(Usyn)
UB2
Figure 3.15-8 Voltage selection for tie CB of one and a half breakers arrangement
When the voltage selection fails (including VT circuit failure and MCB failure), the device will issue
the corresponding failure signal. If the voltage selection is invalid (Alm_Invalid_Sel=1), keep
original selection and without switchover.
In order to simplify description, one of the two voltages used in the synchrocheck (synchronism check
and dead charge check) which obtained after voltage selection function is regarded as reference
voltage, and another is synchronism voltage.
3.15.2.4 Synchronism Voltage Circuit Failure Supervision
If voltage from synchronism voltage VT or reference voltage VT is used for auto-reclosing with
synchronism or dead reference voltage or synchronism voltage check, the synchronism voltage
circuit and reference voltage circuit are monitored.
During normal operation, the circuit breaker is in closed state (52b of three phases are
de-energized), if automatic reclosing cycle is in progress and no fault detector operates, then the
synchronism voltage is lower than the setting [25.U_Lv], it means that synchronism voltage circuit
fails and the synchronism voltage alarm [25.Alm_VTS_Usyn] or reference voltage alarm
[25.Alm_VTS_Uref] will be issued with a time delay of 10s. If the MCB of synchronism voltage or
reference voltage is open, the corresponding alarm signal [25.Alm_VTS_Usyn] or
[25.Alm_VTS_Uref] will be issued instantaneously.
If no check mode is enabled (the signal [25.On_NoChk] is “1”), synchrocheck used voltage circuit

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3 Operation Theory
failure supervision will be disabled.
When synchronism voltage circuit failure is detected, function of dead check in auto-reclosing logic
will be disabled.
After synchronism voltage reverted to normal condition, the alarm will be reset automatically with a
time delay of 10s.
SIG FD.Pkp >=1
SIG 79.Inprog
&
10s 10s
SIG Uref<[25.U_Lv]
>=1
&
BI 25.MCB of Uref 25.Alm_VTS_Uref
SIG 25.On_SynChk >=1

SIG 25.On_DdL_DdB &
SIG 25.On_DdL_LvB
SIG 25.On_LvL_DdB
SIG 25.Blk_VTS_UL
Figure 3.15-9 Reference voltage circuit failure supervision logic
SIG FD.Pkp >=1
SIG 79.Inprog
&
10s 10s >=1
SIG Usyn<[25.U_Lv] &
25.Alm_VTS_Usyn
BI 25.MCB of Usyn
SIG 25.On_SynChk >=1

SIG 25.On_DdL_DdB &
SIG 25.On_DdL_LvB
SIG 25.On_LvL_DdB
SIG 25.Blk_VTS_UB
Figure 3.15-10 Synchronism voltage circuit failure supervision logic
Where:
“25.MCB of Uref” means binary input for VT MCB auxiliary contact of the reference voltage after
voltage switching.
“25.MCB of Usyn” means binary input for VT MCB auxiliary contact of the synchronism voltage
after voltage switching.

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25
25.Blk_Chk UL1_Sel
UL2_Sel
25.Blk_SynChk
UB1_Sel
25.Blk_DdChk UB2_Sel
Alm_Invalid_Sel
25.Start_Chk
25.On_SynChk
25.Start_3PLvChk 25.On_DdL_DdB
25.Sel_SynChk 25.On_DdL_LvB
25.On_LvL_DdB
25.Sel_DdL_DdB
25.On_NoChk
25.Sel_DdL_LvB 25.Ok_fDiffChk
25.Ok_UDiffChk
25.Sel_LvL_DdB
25.Ok_phiDiffChk
25.Sel_NoChk
25.Ok_DdL_DdB
25.Blk_VTS_Uref 25.Ok_DdL_LvB
25.Ok_LvL_DdB
25.Blk_VTS_Usyn
25.Chk_LvL
25.MCB_VT_UL1 25.Chk_DdL
25.MCB_VT_UL2 25.Chk_LvB
25.Chk_DdB
25.MCB_VT_UB1
25.Ok_DdChk
25.MCB_VT_UB2 25.Ok_SynChk
25.NC_UL1DS 25.Ok_Chk
25.Ok_3PLvChk
25.NO_UL1DS
25.Alm_VTS_Uref
25.NC_UB1DS
25.Alm_VTS_Usyn
25.NO_UB1DS
25.f_Ref
25.NC_UL2DS 25.f_Syn
25.NO_UL2DS 25.U_Diff
25.f_Diff
25.NC_UB2DS
25.Phi_Diff
25.NO_UB2DS
3.15.4 I/O Signals
Table 3.15-1 I/O signals of synchrocheck

1 25.Blk_Chk Input signal of blocking synchrocheck function for AR
Input signal of blocking synchronism check for AR. If the value is “1”, the output
2 25.Blk_SynChk
of synchronism check is “0”
3 25.Blk_DdChk Input signal of blocking dead charge check for AR
4 25.Start_Chk Input signal of starting synchronism check, usually it was starting signal of AR

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from auto-reclosing module

Input signal of starting live three-phase check, usually it was starting signal of
5 25.Start_3PLvChk
1-pole AR (internal signal, i.e. the output signal [79.Inprog_1P] inTable 3.16-1)
6 25.Sel_SynChk Selecting synchronism check
7 25.Sel_DdL_DdB Selecting dead line and dead bus check
8 25.Sel_DdL_LvB Selecting dead line and live bus check
9 25.Sel_LvL_DdB Selecting live line and live line check
10 25.Sel_NoChk Selecting no check
11 25.Blk_VTS_Usyn VT circuit supervision of the synchronism voltage (Usyn) is blocked
12 25.Blk_VTS_Uref VT circuit supervision of the reference voltage (Uref) is blocked
13 25.MCB_VT_UL1 Binary input for VT MCB auxiliary contact (UL1)
15 25.MCB_VT_UB1 Binary input for VT MCB auxiliary contact (UB1)
17 25.NC_UL1DS Normally closed contact of disconnector (UL1)
18 25.NO_UL1DS Normally open contact of disconnector (UL1)
19 25.NC_UB1DS Normally closed contact of disconnector (UB1)
20 25.NO_UB1DS Normally open contact of disconnector (UB1)

1 UL1_Sel To select voltage of Line 1
3 UB1_Sel To select voltage of Bus 1
5 Alm_Invalid_Sel Synchronism voltage selection is invalid.
6 25.On_SynChk Synchronism check is enabled.
7 25.On_DdL_DdB Dead line and dead bus check is enabled.
8 25.On_DdL_LvB Dead line and live bus check is enabled.
9 25.On_LvL_DdB Live line and dead bus check is enabled.
10 25.On_NoChk No check is enabled.
To indicate that frequency difference condition for synchronism check of AR is
11 25.Ok_fDiffChk
met, frequency difference between Usyn and Uref is smaller than [25.f_Diff].
To indicate that voltage difference condition for synchronism check of AR is
12 25.Ok_UDiffChk
met, voltage difference between Usyn and Uref is smaller than [25.U_Diff]
To indicate phase difference condition for synchronism check of AR is met,
13 25.Ok_phiDiffChk
phase difference between Usyn and Uref is smaller than [25.phi_Diff].
Dead reference voltage and dead synchronism voltage condition is met (both
14 25.Ok_DdL_DdB
reference voltage and synchronism voltage are low than voltage threshold of

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dead check)
Dead reference voltage and live synchronism voltage condition is met
15 25.Ok_DdL_LvB (reference voltage is low than voltage threshold of dead check and
synchronism voltage is higher than voltage threshold of live check)
Live reference voltage and dead synchronism voltage condition is met
16 25.Ok_LvL_DdB (reference voltage is higher than voltage threshold of live check and
synchronism voltage is low than voltage threshold of dead check)
17 25.Chk_LvL Reference voltage is greater than the voltage threshold of live check [25.U_Lv]
Reference voltage is smaller than the voltage threshold of dead check
18 25.Chk_DdL
[25.U_Dd]
Synchronism voltage is greater than the voltage threshold of live check
19 25.Chk_LvB
[25.U_Lv]
Synchronism voltage is smaller than the voltage threshold of dead check
20 25.Chk_DdB
[25.U_Dd]
21 25.Ok_DdChk To indicate that dead charge check condition of AR is met
22 25.Ok_SynChk To indicate that synchronism check condition of AR is met
23 25.Ok_Chk To indicate that synchrocheck condition of AR is met
24 25.Ok_3PLvChk To indicate that live three-phase check condition is met
25 25.Alm_VTS_Uref Reference voltage circuit is abnormal
26 25.Alm_VTS_Usyn Synchronism voltage circuit is abnormal
27 25.f_Ref Frequency of the voltage used by protection calculation
28 25.f_Syn Frequency of the voltage used by synchrocheck
29 25.U_Diff Voltage difference for synchronism check
30 25.f_Diff Frequency difference for synchronism check
31 25.phi_Diff Phase difference for synchronism check
3.15.5 Logic
These logic diagrams give the introduction to the working principles of the synchronism check and
dead charge check.
3.15.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check.
When the synchronism check function is enabled and the voltages of both ends meets the
requirements of the voltage difference, phase difference, and frequency difference, and there is no
synchronism check blocking signal, it is regarded that the synchronism check conditions are met.
Synchronism check logic is usually used for 3-pole AR, and 1-pole AR is usually adopts no check
logic. However, the circuit breaker at local end can not reclosed unless the circuit breaker at
remote end is reclosed successfully. In order to meet this requirement, live three-phase check can
be used for 1-pole AR, determined by the setting [25.En_3PLvChk], ensure that three-phase
voltages is restored to normal at local end after the circuit breaker at remote end is reclosed.

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3 Operation Theory
Synchronism check mode can be determined by corresponding logic setting [25.En_SynChk] or

external signal. As shown in following figure, when the setting [25.SetOpt] is set as “1”,
synchronism check mode is determined by the setting [25.En_SynChk]. Otherwise, synchronism
check mode is determined by external signal.
1
EN [25.En_SynChk]
25.On_SynChk
SIG 25.Sel_SynChk
0
EN [25.SetOpt]
Figure 3.15-11 Synchronism check mode selection
EN [25.En_3PLvChk]
SIG Uref.a>[25.U_Lv]
>=1
&
SIG Uref.b>[25.U_Lv]
SIG Uref.c>[25.U_Lv]
&
SIG 25.Start_3PLvChk 200ms 0ms 25.Ok_3PLvChk
SIG 25.Blk_Chk >=1
SIG 25.Blk_SynChk
&
SIG [25.On_SynChk]
&
SIG 25.Start_Chk
SIG Usyn>[25.U_Lv]
& &
SIG Uref>[25.U_Lv] 50ms 0ms & [25.t_SynChk] 0ms 25.Ok_SynChk
SIG 25.Ok_UdiffChk
SIG 25.Ok_phiDiffChk
SIG 25.Ok_fDiffChk
Figure 3.15-12 Synchronism check
3.15.5.2 Dead Charge Check Logic
The dead charge check conditions have three types, namely, live-synchronism voltage and
dead-reference voltage check, dead-synchronism voltage and live-reference voltage check and
dead-synchronism voltage and dead-reference voltage check. The above three modes can be
enabled and disabled by the corresponding logic settings ([25.En_DdL_DdB], [25.En_LvL_DdB]
and [25.En_DdL_LvB]) or external signal, when the setting [25.SetOpt] is set as “1”, dead charge
check mode is determined by corresponding logic settings. Otherwise, dead charge check mode is
determined by external signal.
The device can calculate the measured synchronism voltage and reference voltage and compare

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3 Operation Theory
them with the settings [25.U_Lv] and [25.U_Dd]. When the voltage is higher than [25.U_Lv], the
synchronism voltage/reference voltage is regarded as live. When the voltage is lower than
[25.U_Dd], the synchronism voltage/reference voltage is regarded as dead.
1
EN [25.En_DdL_DdB]
25.On_DdL_DdB
SIG 25.Sel_SynChk
0
EN [25.SetOpt]
1
EN [25.En_LvL_DdB]
25.On_LvL_DdB
SIG 25.Sel_LvL_DdB
0
EN [25.SetOpt]
1
EN [25.En_DdL_LvB]
25.On_DdL_LvB
SIG 25.Sel_DdL_LvB
0
EN [25.SetOpt]
Figure 3.15-13 Dead charge check mode selection
SIG 25.Blk_Chk >=1

&
SIG 25.Blk_DdChk &
>=1 [25.t_DdChk] 0ms 25.Ok_DdChk
SIG 25.Start_Chk
SIG [25.On_DdL_DdB] &

25.Ok_DdL_DdB
SIG Uref<[25.U_Dd] &
SIG Usyn>[25.U_Lv]
SIG [25.On_DdL_LvB] &

25.Ok_DdL_LvB
SIG Uref<[25.U_Dd] &
SIG Usyn>[25.U_Lv]
SIG [25.On_LvL_DdB] &

25.Ok_LvL_DdB
SIG Uref>[25.U_Lv] &
SIG Usyn<[25.U_Dd]
SIG 25.Alm_VTS_Usyn >=1
SIG 25.Alm_VTS_Uref
Figure 3.15-14 Dead charge check logic

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3.15.5.3 No Check Logic
No check mode is provided for synchrocheck logic, no check mode can be determined by
corresponding logic setting [25.En_NoChk] or external signal. As shown in following figure, when
the setting [25.SetOpt] is set as “1”, no check mode is determined by the setting [25.En_NoChk].
Otherwise, synchronism check mode is determined by external signal.
1
EN [25.En_NoChk]
25.On_NoChk
SIG 25.Sel_NoChk
0
EN [25.SetOpt]
Figure 3.15-15 No check mode selection
3.15.5.4 Synchrocheck Logic
SIG 25.Ok_SynChk
>=1
EN 25.On_NoChk 25.Ok_Chk
SIG 25.Ok_DdChk
Figure 3.15-16 Synchrocheck logic
3.15.6 Settings
Table 3.15-2 Settings of synchrocheck

Voltage selecting mode for
0: Va; UL1.
1: Vb; 0: A-phase voltage
2: Vc; 1: B-phase voltage
1 25.Opt_Source_UL1 1
3: Vab; 2: C-phase voltage
4: Vbc; 3: AB-phase voltage
5: Vca 4: BC-phase voltage
5: CA-phase voltage
0: Va; UB1.
2 25.Opt_Source_UB1 1
5: CA-phase voltage
0: Va; Voltage selecting mode for
3 25.Opt_Source_UL2 1
1: Vb; UL2.

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2: Vc; 0: A-phase voltage

3: Vab; 1: B-phase voltage
4: Vbc; 2: C-phase voltage
5: Vca 3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
0: Va; UB2.
4 25.Opt_Source_UB2 1
5: CA-phase voltage
Configuration mode of
breaker, it should be set
according to the actual
breaker configuration mode.
NoVoltSel- No voltage
NoVoltSel selection function;
DblBusOneCB DblBusOneCB- Double
5 CBConfigMode 1
3/2BusCB busbar connection;
3/2TieCB 3/2BusCB- Bus breaker for
one and a half breakers
connection;
3/2TieCB- Tie breaker for one
and a half breakers
connection.
Voltage threshold of dead
6 25.U_Dd 0.05Un~0.8Un 0.001 V
check
Voltage threshold of live
7 25.U_Lv 0.5Un~Un 0.001 V
check
Compensation coefficient for
8 25.K_Usyn 0.20~5.00
synchronism voltage
Phase difference limit of
9 25.phi_Diff 0~ 89 1 Deg
synchronism check for AR
Compensation for phase
10 25.phi_Comp 0~359 1 Deg difference between two
synchronism voltages
Frequency difference limit of
11 25.f_Diff 0.02~1.00 0.01 Hz
Voltage difference limit of
12 25.U_Diff 0.02Un~0.8Un V
13 25.t_DdChk 0.010~25.000 s Time delay to confirm dead

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3 Operation Theory
charge check condition

Time delay to confirm
14 25.t_SynChk 0.010~25.000 s
synchronism check condition
Synchrocheck mode selection
0: determined by external
15 25.SetOpt 0 or 1 signal
1: determined by
corresponding logic setting
Enabling/disabling frequency
difference check
16 25.En_fDiffChk 0 or 1
0: disable
1: enable
Enabling/disabling
synchronism check
17 25.En_SynChk 0 or 1
0: disable
1: enable
Enabling/disabling dead
reference voltage and dead
18 25.En_DdL_DdB 0 or 1 synchronism voltage check
0: disable
1: enable
Enabling/disabling dead
reference voltage and live
19 25.En_DdL_LvB 0 or 1 synchronism voltage check
0: disable
1: enable
Enabling/disabling live
reference voltage and dead
20 25.En_LvL_DdB 0 or 1 synchronism voltage check
0: disable
1: enable
Enabling/disabling AR without
any check
21 25.En_NoChk 0 or 1
0: disable
1: enable
Enabling/disabling live
three-phase check of line
22 25.En_3PLvChk 0 or 1
0: disable
1: enable
3.16 Automatic Reclosure

To maintain the integrity of the overall electrical transmission system, the device is installed on the

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3 Operation Theory
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. Auto-reclosing systems are installed to restore the faulted
section of the transmission system once the fault is extinguished (providing it is a transient fault).
For certain transmission systems, auto-reclosure is used to improve system stability by restoring
critical transmission paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and auto-reclosing is not initiated after faulty feeder is tripped.
For some mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines,
etc., it is required to ensure that auto-reclosing is only initiated for faults overhead line section, or
make a choice according to the situation.
This auto-reclosing logic can be used with either integrated device or external device. When the
auto-reclosure is used with integrated device, the internal protection logic can initiate AR,
moreover, a tripping contact from external device can be connected to the device via opto-coupler
input to initiate integrated AR function.
When external auto-reclosure is used, the device can output some configurable output to initiate
external AR, such as, contact of initiating AR, phase-segregated tripping contact, single-phase
tripping contact, three-phase tripping contact and contact of blocking AR. According to
requirement, these contacts can be selectively connected to external auto-reclosure device to
initiate AR.
For phase-segregated circuit breaker, AR mode can be 1-pole AR for single-phase fault and
3-pole AR for multi-phase fault, or always 3-pole AR for any kinds of fault according to system
requirement. For persistent fault or multi-shot AR number preset value is reached, the device will
send final tripping command. The device will provide appropriate tripping command based on
faulty phase selection if adopting 1-pole AR.
AR can be enabled or disabled by logic setting or external signal via binary input. When AR is
enabled, the device will output contact [79.On], otherwise, output contact [79.Off]. After some
reclosing conditions, such as, CB position, CB pressure and so on, is satisfied, the device will
output contact [79.Ready].
According to requirement, the device can be set as one-shot or multi-shot AR. When adopting
multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole
AR. The rest AR mode is only 3-pole AR and its number is determined by the maximum 3-pole
reclosing number.
For one-shot AR or first reclosing of multi-shot AR, AR mode can be selected by logic setting
[79.En_1PAR], [79.En_3PAR] and [79.En_1P/3PAR] or external signal via binary inputs. When
3-pole or 1/3-pole AR mode is selected, the following three types of check modes can be selected:
dead charge check, synchronism check and no check.

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3 Operation Theory
79
79.En 79.On
79.Blk 79.Off
79.Sel_1PAR 79.Close
79.Sel_3PAR 79.Ready
79.Sel_1P/3PAR 79.AR_Blkd
79.Trp 79.Active
79.Trp3P 79.Inprog
79.TrpA 79.Inprog_1P
79.TrpB 79.Inprog_3P
79.TrpC 79.Inprog_3PS1
79.LockOut 79.Inprog_3PS2
79.PLC_Lost 79.Inprog_3PS3
79.WaitMaster 79.Inprog_3PS4
79.CB_Healthy 79.WaitToSlave
79.Clr_Counter 79.Perm_Trp1P
79.Ok_Chk 79.Perm_Trp3P
79.Ok_3PLvChk 79.Rcls_Status
79.Fail_Rcls
79.Succ_Rcls
79.Fail_Chk
79.Mode_1PAR
79.Mode_3PAR
79.Mode_1/3PAR
3.16.4 I/O Signals
Table 3.16-1 I/O signals of auto-reclosing

Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
1 79.En
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
2 79.Blk
disabling AR will be controlled by the external input

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Input signal for selecting 1-pole AR mode of corresponding circuit

3 79.Sel_1PAR
breaker
4 79.Sel_3PAR
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
5 79.Sel_1P/3PAR
breaker
6 79.Trp Input signal of single-phase tripping from line protection to initiate AR
7 79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
8 79.TrpA Input signal of A-phase tripping from line protection to initiate AR
9 79.TrpB Input signal of B-phase tripping from line protection to initiate AR
10 79.TrpC Input signal of C-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the
11 79.LockOut operating signals of definite-time protection, transformer protection
and busbar differential protection, etc.
12 79.PLC_Lost Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master
13 79.WaitMaster
AR (when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
14 79.CB_Healthy
perform the close function
15 79.Clr_Counter Clear the reclosing counter
16 79.Ok_Chk Synchrocheck condition of AR is met
Live three-phase check condition of AR is met (internal signal, i.e.
17 79.Ok_3PLvChk
the output signal [25.Ok_3PLvChk] in Table 3.15-1)
1 79.On Automatic reclosure is enabled
2 79.Off Automatic reclosure is disabled
3 79.Close Output of auto-reclosing signal
4 79.Ready Automatic reclosure have been ready for reclosing cycle
5 79.AR_Blkd Automatic reclosure is blocked
6 79.Active Automatic reclosing logic is actived
7 79.Inprog Automatic reclosing cycle is in progress
8 79.Inprog_1P The first 1-pole AR cycle is in progress
9 79.Inprog_3P 3-pole AR cycle is in progress
10 79.Inprog_3PS1 First 3-pole AR cycle is in progress
11 79.Inprog_3PS2 Second 3-pole AR cycle is in progress
12 79.Inprog_3PS3 Third 3-pole AR cycle is in progress
13 79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
Waiting signal of automatic reclosing which will be sent to slave
14 79.WaitToSlave
(when reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
15 79.Perm_Trp1P
operates
Three-phase circuit breaker will be tripped once protection device
16 79.Perm_Trp3P
operates

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3 Operation Theory
Automatic reclosure status

0: AR is ready.
17 79.Rcls_Status
1: AR is in progress.
2: AR is successful.
18 79.Fail_Rcls Auto-reclosing fails
19 79.Succ_Rcls Auto-reclosing is successful
20 79.Fail_Chk Synchrocheck for AR fails
21 79.Mode_1PAR Output of 1-pole AR mode
23 79.Mode_1/3PAR Output of 1/3-pole AR mode
Automatic reclosure counter
24 79.N_Total_Rcls Recorded number of all reclosing attempts
25 79.N_Total_Rcls 1-pole Shot 1 Recorded number of first 1-pole reclosing attempts
26 79.N_Total_Rcls 3-pole Shot 1 Recorded number of first 3-pole reclosing attempts
27 79.N_Total_Rcls 3-pole Shot 2 Recorded number of second 3-pole reclosing attempts
28 79.N_Total_Rcls 3-pole Shot 3 Recorded number of third 3-pole reclosing attempts
29 79.N_Total_Rcls 3-pole Shot 4 Recorded number of fourth 3-pole reclosing attempts
3.16.5 Logic
3.16.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR.
When logic setting [79.SetOpt] is set as “1”, AR mode is determined by logic settings. When logic
setting [79.SetOpt] is set as “0”, AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[79.Ready] means that the auto-reclosure can perform at least one time of reclosing function, i.e.,
breaker open-close-open.
When the device is energized or after the settings are modified, the following conditions must be
met before the reclaim time begins:
1. AR function is enabled.
2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3. The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [79.t_CBClsd].
4. There is no block signal of auto-reclosing.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [79.Active]=0, in addition to
the above conditions for reclosing again.
The logic of AR ready is shown in Figure 3.16-2.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.

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3 Operation Theory
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [79.t_PersistTrp], AR will be blocked, as shown in the following figure.
SIG Any tripping signal [79.t_PersistTrp] 0ms

>=1
SIG 79.LockOut 0ms [79.t_DDO_BlkAR]
SIG 1-pole AR Initiation [79.t_SecFault] 0ms

&
SIG Any tripping signal
En [79.En_PDF_Blk]
SIG 79.Sel_1PAR &
En [79.N_Rcls]=1
>=1
& 79.AR_Blkd
SIG Three phase trip
SIG Phase A open &
SIG Phase B open
& >=1
&
SIG Phase C open
Figure 3.16-1 Logic diagram of AR block
The input signal [79.CB_Healthy] must be energized before auto-reclosure gets ready. Because
most circuit breakers can finish one complete process: open-closed-open, it is necessary that
circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR
will be blocked if the input signal [79.CB_Healthy] is still not energized within time delay
[79.t_CBReady]. If this function is not required, the input signal [79.CB_Healthy] can be not to
configure, and its state will be thought as “1” by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input of blocking AR, when the circuit breaker is open by manually and there is CB position
input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initiated
and no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is

reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [79.LockOut] is energized, auto-reclosure will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the

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3 Operation Theory
blocking flag of AR is valid, auto-reclosure will be blocked immediately.
SIG CB closed position [79.t_CBClsd] 100ms &

>=1
SIG 79.Active >=1
SIG Any tripping signal

& &
100ms 0 79.Ready
SIG 79.Inprog
BI [79.CB_Healthy] 0ms [79.t_CBReady] &

SIG 79.AR_Blkd >=1
>=1
SIG BlockAR &
SIG 79.Fail_Rcls
>=1
SIG 79.Fail_Chk
SIG Last shot is made
EN [79.En] &
EN [79.En_ExtCtrl]
>=1
79.On
&
SIG 79.En &
SIG 79.Blk
Figure 3.16-2 Logic diagram of AR ready
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [79.t_SecFault] is used to discriminate another fault which begins after 1-pole AR
initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[79.En_PDF_Blk] is set as “1”, and 3-pole AR will be initiated if [79.En_PDF_Blk] is set as “1”.
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [79.t_DDO_BlkAR] after blocking signal disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop off (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [79.En]. When logic setting [79.En_ExtCtrl] is set as “1”,
AR enable are determined by external signal via binary inputs and logic settings. When logic
setting [79.En_ExtCtrl] set as “0”, AR enable are determined only by logic settings.

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For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
SIG 79.On
SIG 79.Mode_3PAR
SIG 79.Ready
SIG 79.Trp
SIG 79.Trp3P
SIG 79.TrpA Logic 79.Perm_Trp3P
SIG 79.TrpB 79.Perm_Trp1P
SIG 79.TrpC
SIG Phase A open
SIG Phase B open
SIG Phase C open
Figure 3.16-3 Logic diagram of tripping condition output
When AR is enabled, the device will output the signal [79.Perm_Trp3P] if AR is not ready, or AR
mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.16.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [79.SetOpt] set as “1”, AR mode is determined by the internal logic settings. If the logic
settings [79.SetOpt] set as “0”, AR mode is determined by the external inputs.
1. AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing (“79.Ready”=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.16-4.

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3 Operation Theory
SIG Reset Command &

>=1
SIG Single-phase Trip
&
SIG 79.Ready
&
1-pole AR Initiation
SIG 79.Sel_1PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.16-4 Single-phase tripping initiating AR
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing (“79.Ready”=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device will
be cleared after the completion of auto-reclosing sequence. (Reset Command) Its logic is shown
in Figure 3.16-5.
SIG Reset Command &

>=1
SIG Three-phase Trip
&
SIG 79.Ready
&
SIG 79.Sel_3PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.16-5 Three-phase tripping initiating AR
2. AR initiated by CB state
A logic setting [79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing (“79.Ready”=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.16-6 and Figure 3.16-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.

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SIG Phase A open >=1
SIG Phase B open &

& &
&
SIG Phase C open 1-pole AR Initiation
EN [79.En_CBInit]
SIG 79.Ready
SIG 79.Sel_1PAR >=1
SIG 79.Sel_1P/3PAR
Figure 3.16-6 1-pole AR initiation
SIG Phase A open

&
SIG Phase B open
SIG Phase C open
EN [79.En_CBInit] & &

SIG 79.Ready
EN [79.Sel_1PAR] >=1
EN [79.Sel_1P/3PAR]
Figure 3.16-7 3-pole AR initiation
3.16.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of “1-pole AR initiation” can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, when the setting
[25.En_3PLvChk] is set as “0”, the result of synchronism check will not be judged, and reclosing
command will be output directly. When the setting [25.En_3PLvChk] is set as “1”, the reclosing is
not permissible unless live three-phase check is met. As far as the 3-pole AR, if the synchronism
check is enabled, the release of reclosing command shall be subject to the result of synchronism
check. After the dead time delay of AR expires, if the synchronism check is still unsuccessful within
the time delay [79.t_wait_Chk], the signal of synchronism check failure (79.Fail_Syn) will be output
and the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of synchronism
check success (25.Ok_Chk) will always be established. And the signal of synchronism check
success (25.Ok_Chk) from the synchronism check logic can be applied by auto-reclosing function
inside the device or external auto-reclosure device.

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3 Operation Theory
79.Inprog_1P
SIG 1-pole AR Initiation >=1
79.Inprog
SIG 3-pole AR Initiation
79.Inprog_3P
SIG 1-pole AR Initiation [79.t_Dd_1PS1] 0ms &

>=1
AR Pulse
&
SIG 79.Ok_3PLvChk
SIG 3-pole AR Initiation [79.t_Dd_3PS1] 0ms &
>=1
& [79.t_Wait_Chk] 0ms 79.Fail_Chk
SIG 79.Ok_Chk
Figure 3.16-8 One-shot AR
In case pilot protection adopting permissive scheme, when the communication channel is
abnormal, pilot protection will be disabled. In the process of channel abnormality, an internal fault
occurs on the transmission line, backup protection at both ends of line will operate to trip the circuit
breaker of each end. The operation time of backup protection at both ends of the line is possibly
non-accordant, whilst the time delay of AR needs to consider the arc-extinguishing and insulation
recovery ability for transient fault, so the time delay of AR shall be considered comprehensively
according to the operation time of the device at both ends. When the communication channel of
main protection is abnormal (input signal [79.PLC_Lost] is energized), and the logic setting
[79.En_AddDly] is set as “1”, then the dead time delay of AR shall be equal to the original dead
time delay of AR plus the extra time delay [79.t_AddDly], so as to ensure the recovery of insulation
intensity of fault point when reclosing after transient fault. This extra time delay [79.t_AddDly] is
only valid for the first shot AR.
>=1
SIG Any tripping signal &
BI [79.PLC_Lost]
&
SIG 79.Active
&
Extend AR time
EN [79.En_AddDly]
Figure 3.16-9 Extra time delay and blocking logic of AR

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3 Operation Theory
Reclosing pulse length may be set through the setting [79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, a logic setting [79.En_CutPulse] is available to control the reclosing
pulse. When this function is enabled, if the device operates to trip during reclosing, the reclosing
pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing
command is issued, AR will drop off with time delay [79.t_Reclaim], and can carry out next
reclosing.
SIG WaitMasterValid &

0ms 50ms >=1
SIG AR Pulse 79.AR_Out
0ms [79.t_PW_AR]
SIG Single-phase Trip >=1

&
SIG Three-phase Trip &
EN [79.En_CutPulse]
>=1
&
SIG 79.AR_Out [79.t_Reclaim] 0ms Reset Command
Figure 3.16-10 Reclosing output logic
The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG 1-pole AR Initiation >=1

0ms [79.t_Fail] >=1
SIG 3-pole AR Initiation &
79.WaitToSlave
SIG 79.Fail_Rcls
SET [79.Opt_Priority] =1
Figure 3.16-11 Wait to slave signal
The output signal “79.WaitToSlave” is usually configured to the signal “79.WaitMaster” of slave AR.
Slave AR is permissible to reclosing only if master AR is reclosed successfully.
3.16.5.4 Reclosing Failure and Success
For transient fault, the fault will be cleared after the device operates to trip. After the reclosing
command is issued, AR will drop off after time delay [79.t_Reclaim], and can carry out next
reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR
initiated, the reclosing will be considered as unsuccessful, including the following cases.

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3 Operation Theory
1. If any protection element operates to trip when AR is enabled ([79.On]=1) and AR is not ready
([79.Ready]=0), the device will output the signal (79.Fail_Rcls).
2. For one-shot AR, if the tripping command is received again within reclaim time after the
reclosing pulse is issued, the reclosing shall be considered as unsuccessful.
3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4. The logic setting [79.En_FailCheck] is available to judge whether the reclosing is successful
by CB state, when it is set as “1”. If CB is still in open position with a time delay [79.t_Fail] after
the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this case,
the device will issue a signal (79.Fail_Rcls) to indicate that the reclosing is unsuccessful, and
this signal will drop off after (Reset Command). AR will be blocked if the reclosing shall be
considered as unsuccessful.
SET [79.Opt_Priority]=2 &

WaitMaster Valid
SIG 79.WaitMaster
SIG 79.On
&
SIG 79.Ready
SIG Any tripping command & >=1

0ms 200ms >=1
SIG Last shot is made 79.Fail_Rcls
SIG 79.Inprog &
SIG 79.AR_Blkd
SIG WaitMasterValid &

[79.t_WaitMaster] 0ms
>=1
SIG AR Pulse
&
[79.t_Fail] 0ms &
SIG CB closed
EN [79.En_FailCheck] &
& 79.Succ_Rcls
0 [79.t_Fail]
Figure 3.16-12 Reclosing failure and success
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.

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3 Operation Theory
3.16.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.N_Rcls], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
1. 1-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be initiated
only for single-phase fault and respective faulty phase selected, otherwise, AR will be blocked. For
single-phase transient fault on the line, line protection device will operate to trip and 1-pole AR is
initiated. After the dead time delay for 1-pole AR is expired, the device will send reclosing pulse,
and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the first
reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse.
The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting [79.t_Dd_3PS1].
For the possible reclosing times of 3-pole AR in 1-pole AR mode, please refer to Table 3.16-2.
2. 3-pole AR
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection device will
operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the
dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then the
auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next reclosing. For
permanent fault, the device will operate to trip again after the reclosing is performed, and the
device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached.
3. 1/3-pole AR

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3 Operation Theory
[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated for
single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead time
delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop
off after the time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the
device will operate to trip again after the reclosing is performed, and the device will output the
signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached. For the
possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.16-2 .
The table below shows the number of reclose attempts with respect to the settings and AR modes.
Table 3.16-2 Reclosing number
1-pole AR 3-pole AR 1/3-pole AR

Setting Value
N-1AR N-3AR N-1AR N-3AR N-1AR N-3AR
1 1 0 0 1 1 1
2 1 1 0 2 1 2
3 1 2 0 3 1 3
4 1 3 0 4 1 4
N-1AR: the reclosing number of 1-pole AR
N-3AR: the reclosing number of 3-pole AR
4. Coordination between dual auto-reclosures
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number [79.N_Rcls] is
reached, the auto-reclosure will drop off after the time delay [79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter

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3 Operation Theory
may be cleared by the submenu “Clear Counter”. If the circuit breaker is reclosed by other
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
3.16.5.6 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.
Signal
Fault
Trip
CB 52b
Open
79.t_Reclaim [79.t_Reclaim]
79.Active
79.Inprog [79.t_Dd_1PS1]
79.Inprog_1P [79.t_Dd_1PS1]
79.Ok_Chk
AR Out [79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls
Time
Figure 3.16-13 Single-phase transient fault

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3 Operation Theory
Signal
Fault
Trip
Open Open
52b
79.t_Reclaim [79.t_Reclaim]
79.Active
79.Inprog
79.Inprog_1P [79.t_Dd_1PS1]
79.Inprog_3PS2 [79.t_Dd_3PS2]
79.Ok_Chk
AR Out [79.t_PW_AR] [79.t_PW_AR]
79.Perm_Trp3P
79.Fail_Rcls 200ms
Time
Figure 3.16-14 Single-phase permanent fault ([79.N_Rcls]=2)
3.16.6 Settings
Table 3.16-3 Settings of auto-reclosing

1 79.N_Rcls 1~4 1 Maximum number of reclosing attempts
2 79.t_Dd_1PS1 0.000~600.000 0.001 s Dead time of first shot 1-pole reclosing
3 79.t_Dd_3PS1 0.000~600.000 0.001 s Dead time of first shot 3-pole reclosing
Dead time of second shot 3-pole

4 79.t_Dd_3PS2 0.000~600.000 0.001 s
reclosing
5 79.t_Dd_3PS3 0.000~600.000 0.001 s Dead time of third shot 3-pole reclosing
Dead time of fourth shot 3-pole

6 79.t_Dd_3PS4 0.000~600.000 0.001 s
reclosing
Time delay of circuit breaker in closed
7 79.t_CBClsd 0.000~600.000 0.001 s
position before reclosing
Time delay to wait for CB healthy, and
begin to timing when the input signal
8 79.t_CBReady 0.000~600.000 0.001 s
[79.CB_Healthy] is de-energized and if
it is not energized within this time delay,

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3 Operation Theory
AR will be blocked.
Maximum wait time for synchronism
9 79.t_Wait_Chk 0.000~600.000 0.001 s
check
Time delay allow for CB status change
10 79.t_Fail 0.000~600.000 0.001 s
to conform reclosing successful
11 79.t_PW_AR 0.000~600.000 0.001 s Pulse width of AR closing signal
12 79.t_Reclaim 0.000~600.000 0.001 s Reclaim time of AR
Time delay of excessive trip signal to

13 79.t_PersistTrp 0.000~600.000 0.001 s
block auto-reclosing
Drop-off time delay of blocking AR,
when blocking signal for AR
14 79.t_DDO_BlkAR 0.000~600.000 0.001 s
disappears, AR blocking condition
drops off after this time delay
15 79.t_AddDly 0.000~600.000 0.001 s Additional time delay for auto-reclosing
Maximum wait time for reclosing

16 79.t_WaitMaster 0.000~600.000 0.001 s
permissive signal from master AR
Time delay of discriminating another
fault, and begin to times after 1-pole AR
initiated, 3-pole AR will be initiated if
17 79.t_SecFault 0.000~600.000 0.001 s
another fault happens during this time
delay. AR will be blocked if another fault
happens after that.
Enabling/disabling auto-reclosing
blocked when a fault occurs under pole
18 79.En_PDF_Blk 0 or 1 disagreement condition
0: disable
1: enable
Enabling/disabling auto-reclosing with
an additional dead time delay
19 79.En_AddDly 0 or 1
0: disable
1: enable
Enabling/disabling adjust the length of
reclosing pulse
20 79.En_CutPulse 0 or 1
0: disable
1: enable
Enabling/disabling confirm whether AR
is successful by checking CB state
21 79.En_FailCheck 0 or 1
0: disable
1: enable
Enabling/disabling auto-reclosing
22 79.En 0 or 1 0: disable
1: enable

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3 Operation Theory
Enabling/disabling AR by external input

signal besides logic setting [79.En]
23 79.En_ExtCtrl 0 or 1
0: only logic setting
1: logic setting and external input signal
Enabling/disabling AR be initiated by
open state of circuit breaker
24 79.En_CBInit 0 or 1
0: disable
1: enable
Option of AR priority
None: single-breaker arrangement
None, High or High: master AR of multi-breaker
25 79.Opt_Priority
Low arrangement
Low: slave AR of multi-breaker
arrangement
Control option of AR mode
1: select AR mode by internal logic
26 79.SetOpt 0 or 1 settings
0: select AR mode by external input
signals
Enabling/disabling 1-pole AR mode
27 79.En_1PAR 0 or 1 0: disable
1: enable
Enabling/disabling 3-pole AR mode
28 79.En_3PAR 0 or 1 0: disable
1: enable
Enabling/disabling 1/3-pole AR mode
29 79.En_1P/3PAR 0 or 1 0: disable
1: enable
3.17 Trip Logic

3.17.1 Application
For any enabled protection tripping elements, their operation signal will convert to appropriate
tripping signals through trip logics and then trigger output contacts by configuration.
This module gathers signals from phase selection and protection tripping elements and then
converts the operation signal from protection tripping elements to appropriate tripping signals. The
device can implement phase-segregated tripping or three-phase tripping, and may output the
contact of blocking AR and the contact of initiating breaker failure protection.

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3.17.3 I/O Signals
Table 3.17-1 I/O signals of trip logic

1 TRP.En Trip enabling input, it is triggered from binary input or programmable logic etc.
2 TRP.Blk Trip blocking input, it is triggered from binary input or programmable logic etc.
Protection operation elements, includes phase overcurrent protection, earth fault
3 Op_CBProt protection, pole discrepancy protection, dead zone protection, breaker failure
protection and etc (internal signal).
Input signal of permitting three-phase tripping
4 PrepTrp3P When this signal is valid, three-phase tripping will be adopted for any kind of
faults.
1 TRP.On Trip output is enabled
2 TRP.BlkAR Blocking auto-reclosing
3 TrpA Tripping phase-A circuit breaker
4 TrpB Tripping phase-B circuit breaker
5 TrpC Tripping phase-C circuit breaker
6 Trp Tripping any phase of circuit breaker
7 Trp3P Tripping three-phase circuit breaker
A-phase breaker failure protection initiating (BFI) signal, BFI signal shall be reset
8 BFI_A
immediately after tripping signal drops off (internal signal).
B-phase breaker failure protection initiating (BFI) signal, BFI signal shall be reset
9 BFI_B
C-phase breaker failure protection initiating (BFI) signal, BFI signal shall be reset
10 BFI_C
Breaker failure protection initiating (BFI) signal, BFI signal shall be reset
11 BFI
3.17.4 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at
least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.

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SIG TRP.En &

TRP.On
SIG TRP.Blk
0 t_Dwell_Trp
&
&
>=1 TrpA
50BF.Op_ReTrpA t_Dwell_Trp 0
SIG &
SIG Ia>0.06In
0 t_Dwell_Trp
&
&
>=1 TrpB
50BF.Op_ReTrpB t_Dwell_Trp 0
SIG &
SIG Ib>0.06In
0 t_Dwell_Trp
&
&
>=1 TrpC
50BF.Op_ReTrpC t_Dwell_Trp 0
SIG &
SIG Ic>0.06In
>=1
>=1 Trp
0 t_Dwell_Trp
&
&
SIG Prep3PTrp >=1 >=1

t_Dwell_Trp 0
& Trp3P
SIG Op_CBProt
SIG Max(Ia,Ib,Ic)>0.06In
SIG TrpA &

BFI_A
SIG TrpB &

BFI_B
Internal breaker failure protection

TrpC
initiating (BFI) signal
SIG
&
BFI_C
SIG Trp &

BFI
SIG 50/51Gx.Op
>=1
SIG 50/51Px.Op
SIG 81U.UFx.Op >=1

SIG 81O.OFx.Op
SIG 50/51Qx.Op
>=1
SIG 59Px.Op
SIG 59Q.Op
SIG 62PD.Op
Figure 3.17-1 Simplified trip logic

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All operation elements (except for re-tripping element) are 3 phase tripping elements.
SIG 50/51Px.Op &
EN [50/51Px.En_BlkAR]
SIG 50/51Qx.Op & >=1
EN [50/51Qx.En_BlkAR]
SIG 50/51Gx.Op &
EN 50/51Gx.En_BlkAR
SIG 59Px.Op
SIG 27Px.Op
>=1 >=1 >=1
SIG 81U.UFx.Op TRP.BlkAR
SIG 81O.OFx.Op
SIG 50BF.Op_t1 >=1
SIG 50BF.Op_t2
SIG 50DZ.Op >=1

SIG 62PD.Op
SIG 59Q.Op
Figure 3.17-2 Blocking AR logic
3.17.5 Settings
Table 3.17-2 Settings of trip logic

The dwell time of tripping command, empirical
value is 0.04
1 t_Dwell_Trp 0.000~10.000 0.001 s The tripping contact shall drop off under
conditions of no current or protection tripping
element drop-off.
3.18 VT Circuit Supervision

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should

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not be issued when the following cases happen.
1. Line VT is used as protection VT and the protected line is out of service.
2. Only current protection functions are enabled and VT is not connected to the device.
VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detect residual voltage greater than 8% of Unn to determine
single-phase or two-phase VT circuit failure, and detect three times positive-sequence voltage less
than Unn to determine three-phase VT circuit failure. Upon detecting abnormality on VT circuit, an
alarm will comes up after a time delay of [VTS.t_DPU] and drop off with a time delay of
[VTS.t_DDO] after VT circuit restored to normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay. If the
auxiliary contact is not connected to the device, VT circuit supervision will be issued with time
delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm will be not issued if the logic setting
[VTS.En_Out_VT] is set as “1”. However, the alarm is still issued if the binary input [VTS.MCB_VT]
is energized, no matter that the logic setting [VTS.En_Out_VT] is set as “1” or “0”.
When VT neutral point fails, third harmonic of residual voltage is comparatively large. If third
harmonic amplitude of residual voltage is larger than 0.2Unn and without operation of fault
detector element, VT neutral point failure alarm signal [VTNS.Alm] will be issued after a time delay
of [VTS.t_DPU] and drop off with a time delay of [VTS.t_DDO] after three phases voltage restored
to normal.
VTS VTNS
VTS.En VTS.Alm VTNS.En VTNS.Alm
VTS.Blk VTNS.Blk
VTS.MCB_VT

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3.18.4 I/O Signals
Table 3.18-1 I/O signals of VT circuit supervision

VT supervision enabling input, it is triggered from binary input or programmable
1 VTS.En
logic etc.
VT supervision blocking input, it is triggered from binary input or programmable
2 VTS.Blk
logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
3 VTNS.En
VT neutral point supervision blocking input, it is triggered from binary input or
4 VTNS.Blk
5 VTS.MCB_VT Binary input for VT MCB auxiliary contact
1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTNS.Alm Alarm signal to indicate VT neutral point fails
3.18.5 Logic
SIG FD.Pkp >=1

&
SIG 79.Inprog
SIG 3U0>0.08Unn
>=1
SIG 3U1<Unn &
>=1 If FD.Pkp OR 79.Inprog operate, then
EN [VTS.En_LineVT] & circuit of time delay will be interrupted.
[VTS.t_DPU] [VTS.t_DDO] &

SIG 52b_3P
>=1
EN [VTS.En_Out_VT]
BI [VTS.MCB_VT]
>=1
& VTS.Alm
EN [VTS.En]
&
SIG [VTS.En]
SIG [VTS.Blk]
Figure 3.18-1 Logic diagram of VT circuit supervision
&
SIG FD.Pkp >=1
SIG 79.Inprog
If FD.Pkp OR 79.Inprog operate, then
circuit of time delay will be interrupted.
OTH U03>0.2Unn & >=1
[VTS.t_DPU] [VTS.t_DDO] & VTNS.Alm
EN [VTS.En_Out_VT]
EN [VTS.En]
&
SIG [VTNS.En]
SIG [VTNS.Blk]
Figure 3.18-2 Logic diagram of VT neutral point supervision

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Unn: rated phase-to-phase voltage
U03: third harmonic amplitude of neutral point residual voltage
If fault detector element operates or automatic reclosing cycle is in progress, and VT circuit failure
signal have been detected, then the VT circuit failure signal will be maintained, only when the fault
detector element and automatic reclosing element are all drop-off, VT circuit supervision will return
to normal operation.
3.18.6 Settings
Table 3.18-2 Settings of VT circuit supervision

1 VTS.t_DPU 0.200~100.000 0.001 s Pick-up time delay of VT circuit supervision
Drop-off time delay of VT circuit
2 VTS.t_DDO 0.200~100.000 0.001 s
supervision
No voltage used for protection calculation
1: enable
0: disable
3 VTS.En_Out_VT 0 or 1
In general, when VT is not connected to the
device, this logic setting should be set as
“1”
Voltage selection for protection calculation
from busbar VT or line VT
4 VTS.En_LineVT 0 or 1
1: line VT
0: busbar VT
Alarm function of VT circuit supervision
5 VTS.En 0 or 1 1: enable
0: disable
3.19 CT Circuit Supervision

3.19.1 Application
The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.
Under normal conditions, CT secondary signal is continuously supervised by detecting the

residual current and voltage. If residual current is larger than 10%In whereas residual voltage is
less than 3V, an error in CT circuit is considered, the concerned protection functions are blocked
and an alarm is issued with a time delay of 10s and drop off with a time delay of 10s after CT
circuit is restored to normal condition.

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CTS
CTS.En CTS.Alm
CTS.Blk
3.19.4 I/O Signals
Table 3.19-1 I/O signals of CT circuit supervision

1 U3P Three-phase voltage input
2 I3P Three-phase current input
CT circuit supervision enabling input, it is triggered from binary input or
3 CTS.En
CT circuit supervision blocking input, it is triggered from binary input or
4 CTS.Blk
1 CTS.Alm Alarm signal to indicate CT circuit fails
3.19.5 Logic
SIG CTS.En &

&
SIG CTS.Blk 10s 10s CTS.Alm
SIG 3I0>0.1In
&
SIG 3U0<3V
SIG IA<0.06In
>=1
SIG IB<0.06In
SIG IC<0.06In
Figure 3.19-1 Logic diagram of CT circuit failure
3.20 Control and Synchrocheck for Manual Closing

The purpose of control is to open or close primary equipment, including circuit breaker (CB),
disconnector (DS) and earth switch (ES), or to issue outputs for signaling purpose. Synchronism
check and dead check are also provided for the control processes as below:
1. Local manual closing CB

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2. Local closing CB by access the menu “Local Cmd→Control”
3. Remote closing CB from SCADA (i.e., local HMI system) or control center (CC)
Programmable interlocking logics within a bay and amongst different bays are provided by using
PCS-Explorer.
1. Control
High reliability is ensured by adopting the principle of selection before operation (abbreviated
SBO). When the binary input [BI_Maintenance] is energized as “1”, remote control from
SCADA/CC will be disabled, but local control will not be influenced.
The integrated control process is as follow:
1) The control source (SCADA/CC, or local LCD control operation, or manual control operation)
sends control selection command to this device
2) This device sends back the control selection result (success or failure) to the control source
after logic judgment
3) The control source sends control operation command to this device if the control selection
result is “success”. The control source will send control cancellation command to this device if
the control selection result is “failure”.
4) This device sends back the control operation result (success or failure) to the control source
after logic judgment.
Logic calculation result of interlocking is input to the remote control module as a criterion of remote
operation. When the enabling parameter of remote open/close interlock is “1”, remote control
module determines whether it can be output according to the calculation result of interlocking. If
the current breaker position or programmable part can meet the interlocking condition, remote
control can be output normally, otherwise remote operation is blocked. When the enabling
parameter of remote open/close interlock is “0”, interlocking function is disabled and remote
control will be output directly without the judgment of interlocking.
Holding time of each binary output contact can be set by configuring corresponding settings and is
often configured as 250ms. However, for the control circuits without latched relays, the holding
time must be longer to ensure successful control operation.

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1
EN [MCBrd.25.En_SynChk]
MCBrd.25.On_SynChk
SIG MCBrd.25.Sel_SynChk
0
EN [MCBrd.25.SetOpt]
1
EN [MCBrd.25.En_NoChk]
MCBrd.25.On_NoChk
SIG MCBrd.25.Sel_NoChk
0
EN [MCBrd.25.SetOpt]
Figure 3.20-1 Synchrocheck mode selection for manual closing
SIG CSWI01.CILO.Disable >=1
SIG BIinput.CILO.Disable
>=1
EN [CSWI01.En_Cls_Blk]
SIG CSWI01.CILO.EnCls
SIG CSWI01.RmtCtrl >=1

&
SIG BIinput.RmtCtrl >=1 &
[CSWI01.t_PW_Cls] 0ms CSWI01.Op_Cls
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl >=1
&
SIG BIinput.LocCtrl
SIG CSWI01.ManSynCls >=1
SIG CSWI01.Cmd_LocCtrl
SIG MCBrd.25.On_SynChk >=1
SIG MCBrd.25.Ok_Chk
SIG MCBrd.Alm_VTS & &

&
EN [MCBrd.En_Alm_VTS]
EN [MCBrd.25.En_VTS_Blk_SynChk]
EN [MCBrd.En_Alm_VTS] &
&
SIG MCBrd.Alm_VTS
EN [MCBrd.25.En_VTS_Blk_DdChk]
EN [MCBrd.25.En_LvL_DdB]
>=1 & >=1
EN [MCBrd.25.En_DdL_LvB] >=1
EN [MCBrd.25.En_DdL_DdB]
SIG MCBrd.25.Ok_Chk
SIG MCBrd.25.On_NoChk
Figure 3.20-2 Logic diagram of closing circuit breaker

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Only the first closing command “CSWI01.Op_Cls” controlled by synchrocheck logic can be used
for CB closing.
After receiving a closing command, this device will continuously check whether the 2 voltages
(Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet
the criteria. Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check (or dead
check) criteria are not met, the signal “MCBrd.25.Ok_Chk” will be set as “0”; if the synchronism
check (or dead check) criteria are met, the signal “MCBrd.25.Ok_Chk” will be set as “1”.
When any of the following criteria is fulfilled, an alarm signal [MCBrd.Alm_VTS] will be issued with
a time delay of 1.25s, and drop off with a time delay of 10s after three phases voltage restored to
normal. The alarm signal will block the closing command for circuit breaker.
1. The negative-sequence voltage is greater than 8V.
2. The positive-sequence voltage is smaller than 30V, and any phase current is greater than
0.04In.
SIG CSWIxx.CILO.Disable >=1
>=1
EN [CSWIxx.En_Cls_Blk] &
[CSWIxx.t_PW_Cls] 0ms [CSWIxx.Op_Cls]
SIG CSWIxx.CILO.EnCls
SIG CSWIxx.RmtCtrl >=1

&
SIG BIinput.RmtCtrl >=1
SIG CSWIxx.Cmd_RmtCtrl
SIG CSWIxx.LocCtrl >=1

&
SIG BIinput.LocCtrl
SIG CSWIxx.Cmd_LocCtrl
Figure 3.20-3 Logic diagram of closing switch (xx=02~15)
Access the menu “Local Cmd→Control” to issue control command locally, and this signal
“CSWIxx.Cmd_LocCtrl” will be set as “1”.
Remote control commands from SCADA/CC can be transmitted via IEC 60870-5-103 protocol or
IEC 61850 protocol, and this signal “CSWIxx.Cmd_RmtCtrl” will be set as “1”.

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SIG CSWI01.CILO.Disable >=1
>=1
EN [CSWI01.En_Opn_Blk] &
[CSWI01.t_PW_Opn] 0ms CSWI01.Op_Opn
SIG CSWI01.CILO.EnOpn
SIG CSWI01.RmtCtrl >=1

&
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl >=1

&
SIG BIinput.LocCtrl
SIG CSWI01.ManOpn >=1
SIG CSWI01.Cmd_LocCtrl
Figure 3.20-4 Logic diagram of open circuit breaker
SIG CSWIxx.CILO.Disable >=1
>=1
EN [CSWIxx.En_Opn_Blk] &
[CSWIxx.t_PW_Opn] 0ms CSWIxx.Op_Opn
SIG CSWIxx.CILO.EnOpn
SIG CSWIxx.RmtCtrl >=1

&
SIG CSWIxx.Cmd_RmtCtrl
SIG CSWIxx.LocCtrl >=1

&
SIG BIinput.LocCtrl
SIG CSWIxx.Cmd_LocCtrl
Figure 3.20-5 Logic diagram of open switch (xx=02~15)
Where:
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector
and earth switch according to the control command. Object manipulation strictly performs three
steps: selection, check and excute, and perform output relay check, to ensure that the remote
control can be excuted safely and reliably.
When logic interlock is enabled, the device can receive the programmable interlock logic. The
device can automatically initiate the interlock logic to determine whether to allow control
operations. The device provides corresponding settings ([CSWIxx.En_Opn_Blk] and
[CSWIxx.En_Cls_Blk]) for each control object. When they are set as “1”, the interlock function of

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the corresponding control object is enabled. The interlock logic can be configured by using
PCS-Explorer, and downloaded to the device via the Ethernet port. If the interlock function is
enabled, but it is not configured the interlock logic, the result of the logic output is 0.
The control record is a file which is used to store remote control command records of this device
circularly. If the record number is to 256, the storage area of the control record will be full. If this
device has received a new remote command, this device will delete the oldest remote control
record, and then store the latest remote control record.
There are 15 configuration page corresponding to 15 control outputs in totall respectively. Each
configuration page can finish some signals configuration, including remote control, local control,
disable interlock blocking, and so on.
In order to conveniently configure control output, the same output signals, including
“BIinput.RmtCtrl”, “BIinput.LocCtrl” and “BIinput.CILO.Disable”, are available after processing
binary signals internally, as shown in figure below.

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Figure 3.20-6 Configuration page of control output 01 (default configration)

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Figure 3.20-7 Configuration page of control output 02 (default configration)
Control output 03~15 is as same as control output 02.
The configuration rule about remote control and local control to binary outputs is as bellow:
X means that it is not configured.

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Remot Local
CSWIxx. BIinput. CSWIxx. BIinput. Control Mode
RmtCtrl RmtCtrl LocCtrl LocCtrl
X X X X Neither Local control nor remote control are permissible.
0 X X X
Only local control is permissible.
X 0 X X
1 X X X
Only remote control is permissible.
X 1 X X
X X 0 X
X X X 0
X X 1 X
X X X 1
0 X 0 X
0 X X 0
Neither Local control nor remote control are permissible.
X 0 0 X
X 0 X 0
0 X 1 X
X 0 1 X
0 X X 1
X 0 X 1
1 X 0 X
1 X X 0
X 1 0 X
X 1 X 0
1 X 1 X
1 X X 1
Both Local control and remote control are permissible.
X 1 1 X
X 1 X 1
For remote control or local control, they can be configured by either of “CSWIxx.RmtCtrl” and
“BIinput.RmtCtrl”, or either of “CSWIxx.LocCtrl” and “BIinput.LocCtrl”.
2. Synchrocheck
Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and
synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then
synchrocheck signal “MCBrd.25.Ok_Chk” will be asserted.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an
additional criterion is applied to check the rate of frequency change (df/dt) between both sides of
the CB.
When the following four conditions are all met, the synchronism check is successful.

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1) Phase angle difference between incoming voltage and reference voltage is less than the
setting [MCBrd.25.phi_Diff]
2) Frequency difference between incoming voltage and reference voltage is less than
[MCBrd.25.f_Diff]
3) Voltage difference between between incoming voltage and reference voltage is less than
[MCBrd.25.U_Diff]
4) Rate of frequency change between incoming voltage and reference voltage is less than
[MCBrd.25.df/dt]
The dead check function measures the amplitude of line voltage and bus voltage at both sides of
the circuit breaker, and then compare them with the live check setting [MCBrd.25.U_Lv] and the
dead check setting [MCBrd.25.U_Dd]. The dead check is successful when the measured
quantities comply with the criteria.
When this device is set to work in no check mode and receives a closing command, CB will be
closed without synchronism check and dead check.
Synchrocheck for manual closing also supports voltage switching. In general, voltage switching is
fulfilled by external circuit (the setting [CBConfigMode]=NoVoltSel); using this module to fulfill
voltage switching, the busbar arrangement should be determined by the setting [CBConfigMode]),
including
 Double busbars arrangement ([CBConfigMode]=DblBusOneCB)
 1½ breakers arrangement ([CBConfigMode]=3/2BusCB or [CBConfigMode]=3/2TieCB).
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on. According to the voltage switching result,
synchrocheck logic choose one voltage to be used for synchrocheck function, synchrocheck
function requires to judgment the phase identification information of the voltage, which is
determined by the setting [MCBrd.25.Opt_Source_UL1]. If voltage switching function is not used,
the reference voltage will be selected from UL1 fixedly.
identification information of the voltage, which is determined by the setting
[MCBrd.25.Opt_Source_UB1]. If voltage switching function is not used, UB1 will be taken as the
synchronism voltage.
UL2: according to the voltage switching result, synchrocheck logic determined whether the voltage
[MCBrd.25.Opt_Source_UL2]. When voltage switching is available, it is only available for 1½
breakers arrangement, it is fixedly connected to the voltage of the other line of the same diameter
in 1½ breakers arrangement.

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[MCBrd.25.Opt_Source_UB2]. When voltage switching is available, it is connected to synchronism
voltage for double busbars arrangement or 1½ breakers arrangement.
Synchrocheck for manual closing supports voltage switching function, and the switching logic is as
same as that of synchrocheck for protection closing. The setting [CBConfigMode] should be set
according to the actual primary busbar arrangement, otherwise, the voltage switching of
synchrocheck for manual closing will fail, so as to block manual closing with synchrocheck.
During dead charge check, when only single-phase voltage is connected to UL1, live voltage is
valid if the setting [VTS.En] should be set as “0” and the connected single-phase voltage is higher
than the setting [MCBrd.25.U_Lv], otherwise, live voltage is regarded as live only when three
phases voltages are all higher than [MCBrd.25.U_Lv].
CSWI01
CSWI01.CILO.EnOpn CSWI01.Op_Opn
CSWI01.CILO.EnCls CSWI01.Op_Cls
CSWI01.RmtCtrl
CSWI01.LocCtrl
CSWI01.CILO.Disable
CSWIxx
CSWIxx.CILO.EnOpn CSWIxx.Op_Opn
CSWIxx.CILO.EnCls CSWIxx.Op_Cls
CSWIxx.RmtCtrl
CSWIxx.LocCtrl
CSWIxx.CILO.Disable

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BIinput
BIinput.RmtCtrl BIinput.RmtCtrl
BIinput.LocCtrl BIinput.LocCtrl
BIinput.CILO.Disable BIinput.CILO.Disable
CSWI01.ManSynCls
CSWI01.ManOpn
CSWI02.ManSynCls
CSWI02.ManOpn
xx can be from 02 to 15
3.20.4 I/O Signals
Table 3.20-1 I/O signals of control

From receiving a closing command, this device will continuously check
whether the 2 voltages (Incoming voltage and reference voltage) involved
in synchronism check (or dead check) can meet the criteria.
1 MCBrd.25.Ok_Chk Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check
(or dead check) criteria are not met, [MCBrd.25.Ok_Chk] will be set as “0”;
if the synchronism check (or dead check) criteria are met,
[MCBrd.25.Ok_Chk] will be set as “1”.
It is used to indicate the interlock status of open output for binary output
2 CSWIxx.CILO.EnOpn
No.xx. (xx=01~15)
It is used to indicate the interlock status of closing output for binary output
3 CSWIxx.CILO.EnCls
No.xx. (xx=01~15)
It is used to select the local control to binary output No.xx. When the local
4 CSWIxx.LocCtrl control is active, binary output No.xx can only be locally controlled.
(xx=01~15)
It is used to select the remote control to binary output No.xx. When the
5 CSWIxx.RmtCtrl remote control is active, binary output No.xx can only be remotely
controlled from SCADA or control centers. (xx=01~15)
It is used to disable the interlock blocking function for control output. If the
6 CSWIxx.CILO.Disable signal “CSWIxx.CILO.Disable” is “1”, binary output No.xx will not be
blocked by interlock conditions. (xx=01~15)
It is used to select the remote control to all binary outputs. When the
7 BIinput.RmtCtrl remote control is active, all binary outputs can only be remotely controlled
from SCADA or control centers.
It is used to select the local control to all binary outputs. When the local
8 BIinput.LocCtrl
control is active, all binary outputs can only be locally controlled.

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3 Operation Theory
It is used to disable the interlock blocking function for control output. If the
9 BIinput.CILO.Disable signal “BIinput.CILO.Disable” is “1”, all binary outputs will not be blocked
by interlock conditions.
When the condition of local control is met and the signal
10 CSWI01.ManSynCls “CSWI01.ManSynCls” is “1”, the output contact [BO_CtrlCls01] is closed
to execute manually closing the circuit breaker with synschrochcek.
11 CSWI01.ManOpn “CSWI01.ManOpn” is “1”, the output contact [BO_CtrlOpn01] is closed to
execute manually open the circuit breaker.
12 MCBrd.25.Sel_SynChk Synchronism check for manual closing is selected.
13 MCBrd.25.Sel_NoChk No check for manual closing is selected.
1 CSWIxx.Op_Opn Open output of binary output No.xx. (xx=01~15)
2 CSWIxx.Op_Cls Closing output of binary output No.xx. (xx=01~15)
3 BIinput.RmtCtrl In order to be convenient to user configure control output, three same
output signals with input signals are available. The relationship with 15
4 BIinput.LocCtrl
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can be
5 BIinput.CILO.Disable gained. If some binary output need not be controlled by three signals,
please cancle the configuration by PCS-Explorer, and configure it
independently.
6 MCBrd.Alm_VTS VT circuit of circuit breaker No.x is abnormal.
3.20.5 Settings
Table 3.20-2 Function Settings

Enabling/disabling alarm function
when VT circuit is abnormal
1 MCBrd.En_Alm_VTS 0 or 1
0: disable
1: enable
Table 3.20-3 Synchrocheck Settings

Voltage selecting mode for line 1
Va
Ua: A-phase voltage
Vb
Ub: B-phase voltage
Vc
1 MCBrd.25.Opt_Source_UL1 Uc: C-phase voltage
Vab
Uab: AB-phase voltage
Vbc
Ubc: BC-phase voltage
Vca
Uca: CA-phase voltage
Va Voltage selecting mode for bus 1
2 MCBrd.25.Opt_Source_UB1 Vb Ua: A-phase voltage
Vc Ub: B-phase voltage

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3 Operation Theory
Vab Uc: C-phase voltage

Vbc Uab: AB-phase voltage
Vca Ubc: BC-phase voltage
Voltage selecting mode for line 2
Va
Ua: A-phase voltage
Vb
Ub: B-phase voltage
Vc
3 MCBrd.25.Opt_Source_UL2 Uc: C-phase voltage
Vab
Vbc
Vca
Voltage selecting mode for bus 2
Va
Ua: A-phase voltage
Vb
Ub: B-phase voltage
Vc
4 MCBrd.25.Opt_Source_UB2 Uc: C-phase voltage
Vab
Vbc
Vca
5 MCBrd.25.U_Dd 0.05Un~0.8Un 0.001 V Voltage threshold of dead check
6 MCBrd.25.U_Lv 0.5Un~Un 0.001 V Voltage threshold of live check
Compensation coefficient for
7 MCBrd.25.K_Usyn 0.20-5.00
synchronism voltage
Phase difference limit of
8 MCBrd.25.phi_Diff 0~ 89 1 Deg
Compensation for phase
9 MCBrd.25.phi_Comp 0~359 1 difference between two
synchronous voltages
Frequency difference limit of
10 MCBrd.25.f_Diff 0.02~1.00 0.01 Hz
Voltage difference limit of
11 MCBrd.25.U_Diff 0.02Un~0.8Un 0.01 V
Synchrocheck mode selection
for manual closing
12 MCBrd.25.SetOpt 0, 1 1
0: determined by external signal
1: determined by the setting
13 MCBrd.25.En_SynChk 0 or 1 Enable synchronism check
Enable dead line and dead bus
14 MCBrd.25.En_DdL_DdB 0 or 1
(DLDB) check
Enable dead line and live bus
15 MCBrd.25.En_DdL_LvB 0 or 1
(DLLB) check
Enable live line and dead bus
16 MCBrd.25.En_LvL_DdB 0 or 1
(LLDB) check
17 MCBrd.25.En_NoChk 0 or 1 Enable AR without any check
18 MCBrd.25.df/dt 0.00~3.00 0.01 Hz/s Threshold of rate of frequency

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3 Operation Theory
change between both sides of

CB for synchronism-check.
Circuit breaker closing time. It is
the time from receiving closing
19 MCBrd.25.t_Close_CB 20~1000 1 ms
command pulse till the CB is
completely closed.
From receiving a closing
command, this device will
continuously check whether
between incoming voltage and
reference voltage involved in
synchronism check (or dead
20 MCBrd.25.t_Wait_Chk 5~30 0.001 s check) can meet the criteria. If
the synchronism check (or dead
check) criteria are not met within
the duration of this time delay,
the failure of synchronism-check
(or dead check) will be
confirmed.
Enabling/disabling block
synchronism check for manual
closing when VT circuit is
21 MCBrd.25.En_VTS_Blk_SynChk 0 or 1
abnormal
0: disable
1: enable
Enabling/disabling block dead
check for manual closing when
22 MCBrd.25.En_VTS_Blk_DdChk 0 or 1 VT circuit is abnormal
0: disable
1: enable
Table 3.20-4 Dual point binary input settings

It is applied to configure the debouncing time
1 CSWIxx.t_DPU_DPS 0~60000 1 ms for dual-point binary input No.xx. (xx=01,
02….15)
Table 3.20-5 Control settings

It is applied to configure the holding time to
1 CSWIxx.t_PW_Opn 0~65535 1 ms open CB or disconnector for binary output
No.xx. (xx=01, 02….15)
It is applied to configure the holding time to
2 CSWIxx.t_PW_Cls 0~65535 1 ms
close CB or disconnector for binary output

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3 Operation Theory

No.xx. (xx=01, 02….15)
Table 3.20-6 Interlock settings

Enabling/disabling open output of binary
output No.xx controlled by the interlocking
1 CSWIxx.En_Opn_Blk 0 or 1 logic (xx=01, 02….15)
0: disable
1: enable
Enabling/disabling closing output of binary
output No.xx controlled by the interlocking
2 CSWIxx.En_Cls_Blk 0 or 1 logic (xx=01, 02….15)
0: disable
1: enable

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4 Supervision
4 Supervision
Table of Contents
4.1 Overview .......................................................................................................... 4-1

4.2 Supervision Alarms ......................................................................................... 4-1
4.3 Relay Self-supervision.................................................................................... 4-7
4.3.1 Relay Hardware Monitoring ................................................................................................. 4-7
4.3.2 Fault Detector Monitoring .................................................................................................... 4-7
4.3.3 Check Setting ...................................................................................................................... 4-7
4.4 AC Input Monitoring ........................................................................................ 4-7

4.4.1 Voltage/Current Drift Monitoring and Auto-adjustment ........................................................ 4-7
4.4.2 Sampling Monitoring ............................................................................................................ 4-7
4.5 Secondary Circuit Monitoring ........................................................................ 4-7

4.5.1 Opto-coupler Power Supervision......................................................................................... 4-7
4.5.2 Circuit Breaker Supervision ................................................................................................. 4-7
4.6 GOOSE Alarm .................................................................................................. 4-8
List of Tables
Table 4.2-1 Alarm description..................................................................................................... 4-1
Table 4.2-2 Troubleshooting ....................................................................................................... 4-5

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4 Supervision

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4 Supervision
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults which occurr on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
4.2 Supervision Alarms

Hardware circuit and operation status of the device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts BO_FAIL will be given. The
protective device then can not work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
NOTICE!
If the device is blocked or alarm signal is sent during operation, please do find out its
reason with the help of self-diagnostic record. If the reason can not be found at site,
please notify the factory NR. Please do not simply press button “TARGET RESET” on
the protection panel or re-energize on the device.
Table 4.2-1 Alarm description
Blocking
No. Item Description
Device
Fail Signals
The device fails.
1 Fail_Device This signal will be pick up if any fail signal picks up Blocked
and it will drop off when all fail signals drop off.
2 Fail_Setting_OvRange Set value of any setting is out of scope. Blocked

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4 Supervision
This signal will pick up instantaneously and will be

latched unless the recommended handling
suggestion is adopted.
Mismatch between the configuration of plug-in
3 Fail_BoardConfig modules and the designing drawing of an Blocked
applied-specific project.
After config file is updated, settings of the file and
settings saved on the device are not matched.
4 Fail_SettingItem_Chgd This signal will pick up instantaneously and will be Blocked
Error is found during checking memory data.
5 Fail_Memory Blocked
Error is found during checking settings.
6 Fail_Settings Blocked
DSP chip is damaged.
7 Fail_DSP Blocked
Communication between two DSP chips is
abnormal
8 Fail_DSP_Comm Blocked
This signal will pick up instantaneously and will
drop off instantaneously.
Software configuation is incorrect.
9 Fail_Config Blocked
AC current and voltage samplings are abnormal.
This signal will pick up with a time delay of 200ms
10 Fail_Sample Blocked
and will be latched unless the recommended
handling suggestion is adopted.
For DSP plug-in module for measurement and
11 MCBrd.Fail_Sample control in slot 06, AC current and voltage samplings Blocked
are abnormal
Error is found during checking the settings of DSP
12 MCBrd.Fail_Settings plug-in module for measurement and control in slot Blocked
06.
Alarm Signals
The device is abnormal.
13 Alm_Device Unblocked
This signal will be pick up if any alarm signal picks

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4 Supervision
up and it will drop off when all alarm signals drop

off.
14 Alm_Insuf_Memory The memory of MON plug-in module is insufficient. Unblocked
The device is in the communication test mode.
15 Alm_CommTest This signal will pick up instantaneously and will Unblocked
The error is found during MON module checking
settings of device.
16 Alm_Settings_MON This signal will pick up with a time delay of 10s and Unblocked
will be latched unless re-powering or rebooting the
device.
The error is found during checking the version of
software downloaded to the device.
17 Alm_Version Unblocked
The active group set by settings in device and that
set by binary input are not matched.
18 Alm_BI_SettingGrp Unblocked
Data frame is abnormal between two DSP
modules.
19 Alm_DSP_Frame Unblocked
The power supply of BI plug-in module in slot xx is
abnormal.
20 Bxx.Alm_OptoDC Unblocked
This signal will pick up with a time delay of 10s and
will drop off with a time delay of 10s.
Fault detector element operates for longer than
50s.
21 Alm_Pkp_FD Unblocked
Neutral current fault detector element operates for
longer than 10s.
22 Alm_Pkp_I0 Unblocked
Protection VT circuit fails.
This signal will pick up with a time delay of
23 VTS.Alm Unblocked
[VTS.t_DPU] and drop off with a time delay of
[VTS.t_DDO].
Protection VT circuit of neutral point fails.
This signal will pick up with a time delay of
24 VTNS.Alm Unblocked
[VTS.t_DPU] and drop off with a time delay of
[VTS.t_DDO].
25 CTS.Alm CT circuit of corresponding circuit breaker fails. Unblocked

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4 Supervision

drop off with a time delay of 10s.
The auxiliary normally closed contact (52b) of
corresponding circuit breaker is abnormal.
26 Alm_52b Unblocked
drop off with a time delay of 10s.
The device is in maintenance state.
27 BI_Maintenance This signal will pick up with a time delay of 150ms Unblocked
and will drop off with a time delay of 150ms.
28 Alm_TimeSyn Time synchronization abnormality alarm. Unblocked
Frequency of the system is higher than 65Hz or

lower than 45Hz.
29 Alm_Freq Unblocked
This signal will pick up with a time delay of 100ms
and will drop off with a time delay of 10s.
Spare alarm signals
30 Alm_Sparexx (xx=01~08) The time delay of pickup and dropoff for these Unblocked
alarm signals can be set by PCS-Explorer.
Protection Element Alarm Signals
Stage 1 of overvoltage protection operates to
31 59P1.Alm Unblocked
alarm.
alarm.
alarm.
Stage 1 of undervoltage protection operates to
alarm.
alarm.
alarm.
Stage 4 of negative-sequence overcurrent
37 50/51Q4.Alm Unblocked
protection operates to alarm.
38 Alm_Invalid_Sel Synchronism voltage selection is invalid. Unblocked
Synchronism voltage circuit is abnormal.
39 25.Alm_VTS_Usyn This signal will pick up with a time delay of 1.25s Unblocked
Reference voltage circuit is abnormal.
40 25.Alm_VTS_Uref This signal will pick up with a time delay of 1.25s Unblocked
41 79.Fail_Rcls Auto-reclosing fails. Unblocked
42 79.Fail_Chk Synchrocheck for AR fails. Unblocked

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4 Supervision
Table 4.2-2 Troubleshooting
No. Item Handling suggestion

Fail Signals
The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the instruction
2 Fail_Setting_OvRange manual, then re-power or reboot the device and the device will restore to
normal operation state.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if
the board is used, then check whether the board is installed properly and work
normally.
Please check the settings mentioned in the prompt message on the LCD, and
4 Fail_SettingItem_Chgd go to the menu “Settings” and select “Confirm_Settings” item to comfirm
settings. Then, the device will restore to normal operation stage.
5 Fail_Memory Please inform the manufacture or the agent for repair.
6 Fail_Settings Please inform the manufacture or the agent for repair.
Chips are damaged and please inform the manufacture or the agent replacing
7 Fail_DSP
the module.
8 Fail_DSP_Comm Please inform the manufacture or the agent for repair.
Please inform configuration engineers to check and confirm visualization
9 Fail_Config
functions of the device
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors
10 Fail_Sample connected to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation
state.
1. Please make the device out of service.
2. Then check if analog input modules and wiring connectors connected to
11 MCBrd.Fail_Sample
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
12 MCBrd.Fail_Settings Please inform the manufacturer or the agent for repair.
Alarm Signals
The signal is issued with other specific alarm signals, and please refer to the
13 Alm_Device
handling suggestion other specific alarm signals.
14 Alm_Insuf_Memory Please replace MON plug-in module.
No special treatment is needed, and disable the communication test function
15 Alm_CommTest
after the completion of the test.
16 Alm_Settings_MON Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project commissioning
17 Alm_Version stage, but it is needed to download the latest package file (including correct
version checksum file) provided by R&D engineer to make the alarm signal

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4 Supervision
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service. the
devices having being put into service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of indiating
active group, and make them matched. Then the “ALARM” LED will be
18 Alm_BI_SettingGrp
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
19 Alm_DSP_Frame Please inform the manufacture or the agent for repair.
1. check whether the binary input module is connected to the power supply.
2. check whether the voltage of power supply is in the required range.
20 Bxx.Alm_OptoDC 3. After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
Please check secondary values and protection settings. If settings are not set
reasonable to make fault detectors pick up, please reset settings, and then
21 Alm_Pkp_FD
the alarm message will disappear and the device will restore to normal
operation state.
Please check secondary values and protection settings. If settings are not set
reasonable to make fault detectors pick up, please reset settings, and then
22 Alm_Pkp_I0
the alarm message will disappear and the device will restore to normal
operation state.
Please check the corresponding VT secondary circuit. After the abnormality is
23 VTS.Alm
eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit of neutral point. After
24 VTNS.Alm
the abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding CT secondary circuit. After the abnormality is
25 CTS.Alm
eliminated, the device returns to normal operation state.
Please check the auxiliary contact of CB. After the abnormality is eliminated,
26 Alm_52b
the device returns to normal operation state.
After maintenance is finished, please de-energized the binary input
27 BI_Maintenance [BI_Maintenance] and then the alarm will disappear and the device restore to
normal operation state.
1. check whether the selected clock synchronization mode matches the

clock synchronization source;
2. check whether the wiring connection between the device and the clock
synchronization source is correct
28 Alm_TimeSyn 3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSync] as ”No TimeSync”.
4. After the abnormality is removed, the “ALARM” LED will be extinguished

and the corresponding alarm message will disappear and the device will
restore to normal operation state.

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4 Supervision
29 Alm_Freq Adjust the system operating mode

Alm_Sparexx Find the reason according to specific problem. (These signals are
30
(xx=01~08) user-defined.)
4.3 Relay Self-supervision
4.3.1 Relay Hardware Monitoring

All chips on DSP module are monitored to ensure whether they are damaged or having errors. If
any one of them is detected damaged or having error, the alarm signal [Fail_DSP] is issued with
the device being blocked.
4.3.2 Fault Detector Monitoring

When neutral current fault detector picks up and lasts for longer than 10 seconds, an alarm
[Alm_Pkp_I0] will be issued without the device blocked.
When any fault detector picks up for longer than 50s, an alarm will be issued [Alm_Pkp_FD]
without the device blocked.
4.3.3 Check Setting

This relay has 10 setting groups, only one setting group could be activiated (is active) at a time.
The settings of active setting group are checked to ensure they are reasonable. If settings are
checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,
and the device is also blocked.
4.4 AC Input Monitoring

4.4.1 Voltage/Current Drift Monitoring and Auto-adjustment
Zero point of voltage and current may drift due to variation of temperature or other environment
factors. The device continually traces the drift and adjust it to normal value automatically.
4.4.2 Sampling Monitoring

AC current and voltage samplings of protection DSP and fault detector DSP are monitored and if
the samples of protection DSP and fault detector DSP are detected to be wrong or inconsistent
between them, the alarm signal [Fail_Sample] will be issued and the device will be blocked.
4.5 Secondary Circuit Monitoring

4.5.1 Opto-coupler Power Supervision
Positive power supply of opto-coupler is continually monitored. If an error or damage has occurred,
an alarm [Bxx.Alm_OptoDC] will be issued.
4.5.2 Circuit Breaker Supervision

If 52b of three phases are energized ,which indicates circuit breaker is open and there is no
current detected in the line, the line will be considered to be out of service.

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4 Supervision
If 52b of three phases are energized that indicates circuit breaker is open but current is still
detected in the line (the measured current is greater than a settable threshold value) or
three-phase circuit breaker is in pole disagreement condition, an alarm signal [Alm_52b] will be
issued after 10s.
4.6 GOOSE Alarm
GOOSE alarm signal indicating that there is a network storm occurring on the
1 GAlm_AStorm_SL
network A.
GOOSE alarm signal indicating that there is a network storm occurring on the
2 GAlm_BStorm_SL
network B.
GOOSE alarm signal indicating that there is an error in the GOOSE

3 GAlm_CfgFile_SL
configuration file
4 Namexx.GAlm_ADisc_SL_xx GOOSE alarm signal indicating that network A for Namexx is disconnected.
5 Namexx.GAlm_BDisc_SL_xx GOOSE alarm signal indicating that network B for Namexx is disconnected.
Between GOOSE control blocks received on network and GOOSE control

6 Namexx.GAlm_Cfg_SL_xx
blocks defined in GOOSE.txt file are unmatched for Namexx.
These are GOOSE alarm reports. When any alarm message is issued, the LED “ALARM” is lit without
the device being blocked. After the abnormality is removed, the device will return to normal with the
LED “ALARM” being distinguished automatically.
No. Output Signal Handling suggestion
1 GAlm_AStorm_SL Please check the related switches
2 GAlm_BStorm_SL Please check the related switches
3 GAlm_CfgFile_SL Please check the GOOSE configuration file (i.e. GOOSE.txt)
4 Namexx.GAlm_ADisc_SL_xx Please check the network
5 Namexx.GAlm_BDisc_SL_xx Please check the network
6 Namexx.GAlm_Cfg_SL_xx Please check the GOOSE configuration file and the network
Namexx is the name defined by the setting [Linkxx], xx=01, 02, 03, …, 64

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5 Management
5 Management
Table of Contents
5.1 Measurement ................................................................................................... 5-1

5.1.1 Root-Mean-Square Values .................................................................................................. 5-1
5.1.2 Phase Angle ......................................................................................................................... 5-2
5.1.3 Primary Value....................................................................................................................... 5-3
5.1.4 Metering Value ..................................................................................................................... 5-4
5.2 Recording ........................................................................................................ 5-4

5.2.1 Overview .............................................................................................................................. 5-4
5.2.2 Event Recording .................................................................................................................. 5-5
5.2.3 Disturbance Recording ........................................................................................................ 5-5
5.2.4 Present Recording ............................................................................................................... 5-6

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5 Management
5.1 Measurement
PCS-921 performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
This device can be used for one or two circuit breaker configuration. If it is used for two circuit
breakers configuration, some corresponding metering will be suffixed by CBn (n is the number of
the CB and it can be 1 and 2).
5.1.1 Root-Mean-Square Values

Access path:
MainMenu  “Measurements”  “Measurements1”
“Measurement1” is use to display measured values from protection calculation DSP. The
measurement values can be displayed in primary value or secondary value by the setting
[Opt_Display_Status].
“Measurement2” is used to display measured values from fault detector DSP. The measurement
values can be displayed in primary value or secondary value by the setting [Opt_Display_Status].
No. Symbol Definition Resolution Unit
1 Ia The secondary value of phase-A current 0.000 A
2 Ib The secondary value of phase-B current 0.000 A
3 Ic The secondary value of phase-C current 0.000 A
4 I1 The secondary value of positive-sequence current 0.000 A
5 I2 The secondary value of negative-sequence current 0.000 A
6 3I0 The secondary value of calculated residual current 0.000 A
7 Ua The secondary value of phase-A protection voltage 0.000 V
8 Ub The secondary value of phase-B protection voltage 0.000 V
9 Uc The secondary value of phase-C protection voltage 0.000 V
10 Uab The secondary value of phase-AB protection voltage 0.000 V
11 Ubc The secondary value of phase-BC protection voltage 0.000 V
12 Uca The secondary value of phase-CA protection voltage 0.000 V
13 U1 The secondary value of positive-sequence voltage 0.000 V
14 U2 The secondary value of negative-sequence voltage 0.000 V
15 3U0 The secondary value of calculated residual voltage 0.000 V

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5 Management
16 UB1 The voltage of busbar No.1 0.000 V
17 UL2 The voltage of line No.2 0.000 V
18 UB2 The voltage of busbar No.2 0.000 V
19 f Frequency of protection voltage 0.000 Hz
20 25.f_Syn Frequency of synchronism voltage 0.000 Hz
Frequency difference between protection voltage and

21 25.f_Diff 0.000 Hz
Phase angle difference between protection voltage and

22 25.phi_Diff 0 V
Voltage difference between protection voltage and

23 25.U_Diff 0.000 V
5.1.2 Phase Angle

Access path:
“Measurement1” is use to display measured values from protection calculation DSP
“Measurement2” is used to display measured values from fault detector DSP
Phase angle between phase-A voltage and

1 Ang (Ua-Ub) 0 Deg
phase-B voltage
Phase angle between phase-B voltage and

2 Ang (Ub-Uc) 0 Deg
phase-C voltage
Phase angle between phase-C voltage and

3 Ang (Uc-Ua) 0 Deg
phase-A voltage
Phase angle between phase-A voltage and

4 Ang (Ua-Ia) 0 Deg
phase-A current
Phase angle between phase-B voltage and

5 Ang (Ub-Ib) 0 Deg
phase-B current
Phase angle between phase-C voltage and

6 Ang (Uc-Ic) 0 Deg
phase-C current
Phase angle between phase-A current and

7 Ang (Ia-Ib) 0 Deg
phase-B current
Phase angle between phase-B current and

8 Ang (Ib-Ic) 0 Deg
phase-C current
Phase angle between phase-C current and

9 Ang (Ic-Ia) 0 Deg
phase-A current

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5 Management
5.1.3 Primary Value

Access path:
“Measurement3” is used to display measured primary values and other calculated quantities
related to the measurement and control.
1 Ia The primary value of phase-A current 0.000 A
2 Ib The primary value of phase-A current 0.000 A
3 Ic The primary value of phase-A current 0.000 A
4 I1 The primary value of positive-sequence current 0.000 A
5 I2 The primary value of negative-sequence current 0.000 A
6 3I0 The primary value of calculated residual current 0.000 A
7 Ua The primary value of phase-A voltage 0.000 kV
8 Ub The primary value of phase-B voltage 0.000 kV
9 Uc The primary value of phase-C voltage 0.000 kV
10 Uab The primary value of phase-AB voltage 0.000 kV
11 Ubc The primary value of phase-BC voltage 0.000 kV
12 Uca The primary value of phase-CA voltage 0.000 kV
13 U1 The primary value of positive-sequence voltage 0.000 kV
14 U2 The primary value of negative-sequence voltage 0.000 kV
15 3U0 The primary value of calculated residual voltage 0.000 kV
16 UB1 The primary value of voltage of busbar No.1 0.000 kV
17 UL2 The primary value of voltage of line No.2 0.000 kV
18 UB2 The primary value of voltage of busbar No.2 0.000 kV
19 f Frequency of protection voltage 0.000 Hz
20 UB1.f Frequency of busbar 1 voltage 0.000 Hz
21 UL2.f Frequency of line 2 voltage 0.000 Hz
22 UB2.f Frequency of busbar 2 voltage 0.000 Hz
23 P The primary value of active power 0.000 MW
24 Q The primary value of reactive power 0.000 MVar
25 S The primary value of apparent power 0.000 MVA
26 Cos The value of power factor 0.000 -
27 Pa The primary value of phase-A active power 0.000 MW
28 Pb The primary value of phase-B active power 0.000 MW
29 Pc The primary value of phase-C active power 0.000 MW

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5 Management
30 Qa The primary value of phase-A reactive power 0.000 MVar
31 Qb The primary value of phase-B reactive power 0.000 MVar
32 Qc The primary value of phase-C reactive power 0.000 MVar
33 Sa The primary value of phase-A apparent power 0.000 MVA
34 Sb The primary value of phase-B apparent power 0.000 MVA
35 Sc The primary value of phase-C apparent power 0.000 MVA
36 Cosa The value of phase-A power factor 0.000 -
37 Cosb The value of phase-B power factor 0.000 -
38 Cosc The value of phase-C power factor 0.000 -
The frequency difference between reference side and

39 25.f_Diff 0.000 Hz
incoming side for manual closing synchrocheck
The rate of frequency change between reference side and

40 25.df/dt 0.000 Hz/s
incoming side for manual closing synchrocheck
Phase angle difference between reference side and incoming

41 25.phi_Diff 0.00 Deg
side for manual closing synchrocheck
The primary value of voltage difference between reference

42 25.U_Diff 0.000 kV
side and incoming side for manual closing synchrocheck
5.1.4 Metering Value

Access path: MainMenu  “Measurements”  “Metering”
“Metering” is used to display metering values of active and reactive energy. The metering values
are always displayed in primary value.
1 PHr+_Pri The primary positive active energy 0.000 MWh
2 PHr-_Pri The primary negative active energy 0.000 MWh
3 QHr+_Pri The primary positive reactive energy 0.000 MVAh
4 QHr-_Pri The primary negative reactive energy 0.000 MVAh
5.2 Recording
5.2.1 Overview
PCS-921 provides the following recording functions:
1. Event recording
2. Disturbance recording
3. Present recording
All the recorded information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform

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5 Management
analysis software.
5.2.2 Event Recording

5.2.2.1 Overview
The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs. All the records are stored in non-volatile memory,
and when the available space is exhausted, the oldest record is automatically overwritten by the
latest one.
5.2.2.2 Disturbance Records
When any protection element operates or drops off, such as fault detector, distance protection etc.,
they will be logged in event records.
5.2.2.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records.
5.2.2.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records.
5.2.2.5 Control Logs
When the total number of control command records reaches 256, “Control_Logs” memory area
will be full. If the device receives a new control command now, the oldest control command record
will be deleted, and then the latest control command record will be stored and displayed.
5.2.2.6 Device Logs
If an operator implements some operations on the device, such as reboot protective device,
modify setting, etc., they will be logged in event records.
5.2.3 Disturbance Recording

5.2.3.1 Application
Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
5.2.3.2 Design
A disturbance record consists of fault record and fault waveform. A disturbance record can be
initiated by fault detector element, tripping element, reclosing element or configurable signal
[BI_TrigDFR].

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5 Management
5.2.3.3 Capacity and Information of Disturbance Records
The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.
For each disturbance record, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record.
4. Faulty phase
5. Protection elements
5.2.3.4 Capacity and Information of Fault Waveform
MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
Each time recording includes several-cycle pre-disturbance waveform (the waveform cycle
number is configured via the communication setting [Num_Cyc_PreTrigDFR], the default value is
12-cycle), and 250 cycles at least and 500 cycles at most can be recorded. Each cycle waveform
is high-frequency recording at a rate of 1200Hz or 1440Hz (24 poingts per cycle).
5.2.4 Present Recording

Present recording is a waveform triggered manually on on the device′s LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.
Each time recording includes several-cycle waveform before triggering (the waveform cycle
number is configured via the communication setting [Num_Cyc_PreTrigDFR], the default value is
12-cycle), and 250 cycles at most can be recorded. Each cycle waveform is high-frequency
recording at a rate of 1200Hz or 1440Hz (24 poingts per cycle).

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6 Hardware
6 Hardware
Table of Contents
6.1 General Description ........................................................................................ 6-1

6.2 Typical Wiring .................................................................................................. 6-4
6.2.1 Conventional CT/VT (For reference only) ........................................................................... 6-4
6.2.2 ECT/EVT (For reference only) ............................................................................................. 6-6
6.2.3 CT Requirement .................................................................................................................. 6-8
6.3 Plug-in Module Description............................................................................ 6-9

6.3.1 PWR Plug-in Module (Power Supply) ................................................................................. 6-9
6.3.2 MON Plug-in Module (Monitor) ...........................................................................................6-11
6.3.3 AI Plug-in Module (Analog Input) ....................................................................................... 6-14
6.3.4 DSP Plug-in Module (Logic Proces) .................................................................................. 6-22
6.3.5 NET-DSP Plug-in Module (GOOSE and SV) .................................................................... 6-22
6.3.6 BI Plug-in Module (Binary Input)........................................................................................ 6-26
6.3.7 BO Plug-in Module (Binary Output) ................................................................................... 6-35
6.3.8 HMI Module........................................................................................................................ 6-38
List of Figures
Figure 6.1-1 Rear view of fixed module position ..................................................................... 6-1
Figure 6.1-2 Hardware diagram .................................................................................................. 6-2
Figure 6.1-3 Front view of PCS-921 ........................................................................................... 6-3
Figure 6.1-4 Typical rear view of PCS-921 ................................................................................ 6-4
Figure 6.2-1 Typical wiring of PCS-921 (conventional CT/VT) ................................................ 6-5
Figure 6.2-2 Typical wiring of PCS-921 (ECT/EVT) .................................................................. 6-7
Figure 6.3-1 View of PWR plug-in module .............................................................................. 6-10
Figure 6.3-2 Output contacts of PWR plug-in module........................................................... 6-10
Figure 6.3-3 View of MON plug-in module .............................................................................. 6-12

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6 Hardware
Figure 6.3-4 Connection of communication terminal ............................................................ 6-14
Figure 6.3-5 Schematic diagram of CT circuit automatically closed ....................................... 6-15
Figure 6.3-6 Current connection of AI plug-in module .......................................................... 6-16
Figure 6.3-7 Voltage connection 1 of AI plug-in module ....................................................... 6-16
Figure 6.3-8 Voltage connection 2 of AI plug-in module ....................................................... 6-17
Figure 6.3-9 View of AI plug-in module (without synchronism voltage switchover) ......... 6-17
Figure 6.3-10 View of AI plug-in module (with synchronism voltage switchover) ............. 6-19
Figure 6.3-11 View of AI plug-in module NR1408 ................................................................... 6-20
Figure 6.3-12 View of DSP plug-in module ............................................................................. 6-22
Figure 6.3-13 View of NET-DSP plug-in module ..................................................................... 6-23
Figure 6.3-14 Voltage dependence for binary inputs............................................................. 6-27
Figure 6.3-15 Debounce technique.......................................................................................... 6-27
Figure 6.3-16 View of BI plug-in module (NR1503) ................................................................ 6-30
Figure 6.3-17 View of BI plug-in module (NR1504) ................................................................ 6-31
Figure 6.3-18 View of BI plug-in module (NR1508A).............................................................. 6-32
Figure 6.3-19 View of BO plug-in module (NR1521A) ............................................................ 6-36
Figure 6.3-20 View of BO plug-in module (NR1521C) ............................................................ 6-36
Figure 6.3-21 View of BO plug-in module (NR1521F) ............................................................ 6-37
Figure 6.3-22 View of BO plug-in module (NR1580A) ............................................................ 6-38
List of Tables
Table 6.3-1 Terminal definition and description of PWR plug-in module ............................ 6-11
Table 6.3-2 Terminal definition of NR1401 module (without synchronism voltage switchover)
.............................................................................................................................................. 6-18
Table 6.3-3 Terminal definition of NR1401 module (with synchronism voltage switchover)
.............................................................................................................................................. 6-19
.............................................................................................................................................. 6-21
Table 6.3-5 Encoding of IEC 61850-7-3 quality .......................................................................... 6-23

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6 Hardware
6.1 General Description

PCS-921 adopts 32-bit microchip processor CPU as control core for management and monitoring
function, meanwhile, adopts high-speed digital signal processor DSP for all the protection
calculation. 24 points are sampled in every cycle and parallel processing of sampled data can be
realized in each sampling interval to ensure ultrahigh reliability and safety of the device.
PCS-921 is comprised of intelligent plug-in modules, except that few particular plug-in modules’
position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),
other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly
configured in the remaining slot positions.
MON module
PWR module
DSP module
DSP module
BO module
BO module
BO module
BO module
BO module
AI module
BI module
BI module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Figure 6.1-1 Rear view of fixed module position
PCS-921 has 16 slots, PWR plug-in module, MON plug-in module and DSP plug-in module are
assigned at fixed slots.
Besides 4 fixed modules are shown in above figure, there are 12 slots can be flexibly configured.
AI plug-in module can be configured at position between slot 02-03, BI plug-in module can be
configured at position between slot B08~B10, and BO plug-in module can be configured at
position between slot B11~B15.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 6.1-2 for hardware diagram.

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6 Hardware
Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP
ECVT
Fault
A/D Detector Pickup
DSP Relay
ECVT
ETHERNET
LCD +E
Clock SYN
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT
Figure 6.1-2 Hardware diagram
The working process of the device is as shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent
to the device without small signal and A/D convertion). When DSP module completes all the
protection calculation, the result will be recorded in 32-bit CPU on MON module. DSP module
carries out fault detector, protection logic calculation, tripping output, and MON module perfomes
SOE (sequence of event) record, waveform recording, printing, communication between the
device and SAS and communication between HMI and CPU. When fault detector detects a fault
and picks up, positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-900 series based on microcomputer
are classified into standard and optional modules.
Table 6.1-1 PCS-921 module configuration
No. ID Module description Remark

1 NR1101/NR1102 Management and monitor module (MON module) standard
2 NR1401/1408 Analog input module (AI module ) standard
Protection calculation and fault detector module (DSP
3 NR1161 standard
module)
4 NR1503/NR1504/1508 Binary input module (BI module) standard
5 NR1521/1580 Binary output module (BO module) standard
6 NR1301 Power supply module (PWR module) standard
7 NR1136 GOOSE and SV from merging unit by IEC61850-9-2 option

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6 Hardware
No. ID Module description Remark

(NET-DSP module)
8 Human machine interface module (HMI module) standard
 MON module provides functions like communication with SAS, event record, setting
management etc.
 AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
 DSP module performs filtering, sampling, protection calculation and fault detector calculation.
 BI module provides binary inputs via opto-couplers with rating voltage among
24V/110V/125V/220V/250V (configurable).
 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
 PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.
 HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
 NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.
PCS-921 series is made of a 4U height 19” chassis for flush mounting. Components mounted on
its front include a 320×240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex
RJ45 port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-921 respectively.
1 11
HEALTHY PCS-9 21
2 12
ALARM BREAKER FAILURE RELAY
3 13
4 14
GRP
5 15
6 16 ENT
ESC
7 17
8 18
9 19
10 20
Figure 6.1-3 Front view of PCS-921
20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable.
For the 9-button keypad, “ENT” is “enter”, “GRP” is “group number” and “ESC” is “escape”.

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6 Hardware
NR1102 NR1401 NR1161 NR1504 NR1521 NR1521 NR1521 NR1301

5V OK ALM
BO_ALM BO_FAIL
ON
OFF
DANGER
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.1-4 Typical rear view of PCS-921
6.2 Typical Wiring

6.2.1 Conventional CT/VT (For reference only)
NR1102 NR1401 NR1161 NR1161 NR1504 NR1521A NR1521C NR1521C NR1521F NR1301
MON module
PWR module
DSP module
DSP module
BO module
BO module
BO module
BO module
AI module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
The following typical wiring is given based on above hardware configuration

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6 Hardware
0201 Power supply supervision 0801

0202 Ia
0203
Ib BI_01 + 0802
0204
*BI plug-in module can be independent common terminal

0205
…
0206 Ic
BI_06 + 0807
Not used 0808
0213
BI_07 + 0809
Protection Voltage
0214 Ua
0215
…
0216 Ub
0217 BI_12 + 0814
0218 Uc
Not used 0815
0219 BI_13 + 0816

Synchronism Voltage
0220 UB1
0221
…
0222 UL2
BI_18 + 0821
0223
0224 UB2 0822
-
1101
Controlled by fault
BO_01
detector element
1102
P110 1103
PWR+
External DC power Power BO_02 1104
supply P111 Supply
PWR-
…
1121
OPTO+ P107 BO_11 1122
Power supply for
opto-coupler (24V) P108
OPTO-
1201
Signal Binary Output
BO_01 1202
1203
BO_02 1204
P102 BO_FAIL
…
P103 1221
BO_ALM
BO_11 1222
P101 COM
P105 BO_FAIL
P106 1301
BO_ALM
BO_01 1302
P104 COM
(option)
1303
BO_02 1304
…
1321
BO_11 1322
A 0101
cable with single point earthing
To the screen of other coaxial
B 0102
COM
SGND 0103 1501

BO_CtrlOpn1 1502
0104
Signal Binary Output (option)
1503
SYN+ 0101 BO_CtrlCls1 1504
Clock SYN
SYN- 0102
…
SGND 0103 1517

0104 BO_CtrlOpn5 1518
RTS 0105 1519

PRINTER
BO_CtrlCls5
PRINT
TXD 0106 1520

Multiplex
SGND 0107 1521
RJ45 (Front)
BO_Ctrl 1522
P112
0225
Grounding
Bus
Figure 6.2-1 Typical wiring of PCS-921 (conventional CT/VT)

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6 Hardware
PCS-921 (conventional CT/VT and conventional binary input and binary output)
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1401 NR1161 NR1504 NR1504 NR1521 NR1521 NR1521 NR1521 NR1301
MON AI DSP BI BI BO BO BO BO PWR
PCS-921 (conventional CT/VT and GOOSE binary input and binary output)
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1401 NR1161 NR1136 NR1504 NR1301

NET-
MON AI DSP BI PWR
DSP
6.2.2 ECT/EVT (For reference only)
NR1102 NR1161 NR1161 NR1136 NR1503 NR1521A NR1521C NR1301
NET-DSP Module
MON module
PWR module
DSP module
DSP module
BO module
BO module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
The following typical wiring is given based on above hardware configuration

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6 Hardware
BI_01 + 0801
*BI plug-in module can be common negative

Phase A RX - 0802
FO interface for SV channel

SV from
ECT/EVT
MU
Phase B BI_02 + 0803
(LC Type)
Up to 8
Phase C TX - 0804
terminal
BI_03 + 0805
…
- 0806
…
BI_11 + 0821
- 0822
PWR+ P110
External DC power Power 1101
Controlled by fault
BO_01
detector element
supply P111 Supply 1102
PWR-
OPTO+ P107 1103
Power supply for BO_02 1104
opto-coupler (24V) P108
OPTO-
…
1121
BO_11 1122
1201

P102 BO_FAIL BO_01 1202
P103 BO_ALM 1203
P101 COM BO_02 1204
P105 BO_FAIL
…
1221
P106 BO_ALM BO_11 1222
P104 COM
1501
BO_CtrlOpn1 1502
Signal Binary Output (option)
1503
A 0101 BO_CtrlCls1 1504
B 0102
COM
…
SGND 0103
1517
0104 BO_CtrlOpn5 1518
SYN+ 0101 1519
Clock SYN
SYN- 0102 BO_CtrlCls5 1520

SGND 0103 1521
0104 BO_Ctrl 1522
RTS 0105
PRINTER
IRIG-B
PRINT
TXD 0106
Multiplex
SGND 0107 RJ45 (Front) P112
0225 Grounding
Bus
Figure 6.2-2 Typical wiring of PCS-921 (ECT/EVT)
PCS-921 ECT/EVT, GOOSE binary input and binary output
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1161 NR1136 NR1504 NR1301

NET-
MON DSP BI PWR
DSP
PCS-921 ECT/EVT, conventional binary input and binary output
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Module ID NR1102 NR1161 NR1136 NR1504 NR1504 NR1521 NR1521 NR1521 NR1521 NR1301
NET-
MON DSP BI BI BO BO BO BO PWR
DSP

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6 Hardware
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fibre
interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor ()Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl′
Rated secondary limiting e.m.f (volts)

Esl
Esl = kalf×Isn×(Rct+Rbn)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)

IPal Rated accuracy limit primary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Rated resistance burden (ohms)
Rbn 2
Rbn=Sbn/Isn
Sbn Rated burden (VAs)

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6 Hardware
Required secondary limiting e.m.f (volts)

Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance (ohms)
Real resistance burden (ohms)
Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)

RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
For example:
1. Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)
= 30×5×(1+60/25)=510V
2. Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.3 Plug-in Module Description

The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module and NET-DSP plug-in module. Terminal definitions
and application of each plug-in module are introduced as follows.
6.3.1 PWR Plug-in Module (Power Supply)

PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2 “Technical Data”. The standardized output voltages
are +5V and +24V DC. The tolerances of the output voltages are continuously monitored.

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6 Hardware
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.
NR1301A
5V OK ALM
BO_ALM BO_FAIL
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.3-1 View of PWR plug-in module
The power switch in the dotted box of above figure maybe is not existed.
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06
Figure 6.3-2 Output contacts of PWR plug-in module
Terminal definition and description is shown as follows:

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6 Hardware
Table 6.3-1 Terminal definition and description of PWR plug-in module
Terminal No. Symbol Description
01 BO_COM1 Common terminal 1
02 BO_FAIL Device failure output 1 (01-02, NC)
03 BO_ALM Device abnormality alarm output 1 (01-03, NO)
04 BO_COM2 Common terminal 2
05 BO_FAIL Device failure output 2 (04-05, NC)
06 BO_ALM Device abnormality alarm output 2 (04-06, NO)
07 OPTO+ Positive power supply for BI module (24V)
08 OPTO- Negative power supply for BI module (24V)
09 Blank Not used
10 PWR+ Positive input of power supply for the device (250V/220V/125V/110V)
11 PWR- Negative input of power supply for the device (250V/220V/125V/110V)
12 GND Grounded connection of the power supply
NOTICE!
The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For non-standard
rated voltage power supply module please specify when place order, and check if the
rated voltage of power supply module is the same as the voltage of power source
before the device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal
12 shall be connected to grounding screw and then connected to the earth copper bar
of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so
effective grounding must be ensured before the device is put into service.
PCS-921, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not
applied periodically. Deterioration can be avoided by powering the relays up once a
year.
6.3.2 MON Plug-in Module (Monitor)
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.

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MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces that exchange information with above system by
using IEC 61850, PPS/IRIG-B differential time synchronization interface and RS-232 printing
interface.
Modules with various combinations of memory and interface are available as shown in the table
below.
NR1102D NR1102I NR1101E
TX
ETHERNET ETHERNET
RX
TX
RX
ETHERNET
Figure 6.3-3 View of MON plug-in module
Module ID Memory Interface Terminal No. Usage Physical Layer

4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock Twisted pair wire
RS-485
03 SGND synchronization
NR1102D 128M DDR
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
NR1102I 128M DDR
2 FO Ethernet To SCADA Optical fibre ST

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01 SYN+
02 SYN- To clock
RS-485 Twisted pair wire
04
05 RTS
07 SGND
2 RJ45 Ethernet To SCADA
01 A
02 B
RS-485 To SCADA
03 SGND
04
05 A
06 B Twisted pair wire
RS-485 To SCADA
07 SGND
NR1101E 128M DDR 08
09 SYN+
10 SYN- To clock
RS-485
12
13 RTS
15 SGND
16
The correct connection is shown in Figure 6.3-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.

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Twisted pair wire

A 01
B 02
COM
SGND 03

04
Twisted pair wire

SYN+ 01
Clock SYN
SYN- 02
SGND 03
04
Cable
RTS 05
PRINT
TXD 06
SGND 07
Figure 6.3-4 Connection of communication terminal
Pin1
Pin2
Pin3
Figure 6.3-5 Jumpers of clock synchronization port
NOTICE!
As shown in Figure 6.3-5, the external receiving mode of IRIG-B differential time
synchronization interface can be set by the jumper J8&J9.
Jumper RS-485 TTL

J8 Pin-1 and Pin-2 are connected. (RS-485+) Pin-2 and Pin-3 are connected. (TTL+)
J9 Pin-1 and Pin-2 are connected. (RS-485-) Pin-2 and Pin-3 are connected. (TTL-)
6.3.3 AI Plug-in Module (Analog Input)

AI module is applicable for power plant or substation with conventional VT and CT. It is assigned to
slot numbers 02 and 03. However, the module is not required if the device is used with ECT/EVT.
NR1401 module and NR1408 module are selectable for the device.

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For AI module, if the plug is not put in the socket, external CT circuit is closed itself. Just shown as
below.
Plug
Socket
In
Out
plug is not put in the socket
In
Out
Put the plug in the socket
Figure 6.3-5 Schematic diagram of CT circuit automatically closed
For the AI module NR1401, only one type of current channel (1A or 5A) is equipped. For the AI
module NR1408, the 1A and 5A current channels are all equipped. Please declare which kind of AI
module is needed before ordering. Maximum linear range of the current converter is 40In.
 NR1401
Three phase currents (Ia, Ib and Ic) are input to AI module separately, terminal 01, 03 and 05 are
polarity marks. It is assumed that polarity mark of CT installed on line is at line side. Three phase
voltages (Ua, Ub, and Uc) are input to AI module, terminal 13, 15 and 17 are polarity marks.

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P2 S2
P1 S1
02 01
04 03
06 05
Figure 6.3-6 Current connection of AI plug-in module
13 14
15 16
17 18
19 20
Figure 6.3-7 Voltage connection 1 of AI plug-in module

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13 14
15 16
17 18
19 20
Figure 6.3-8 Voltage connection 2 of AI plug-in module
If the synchronism voltage need to be connected, there are two situations:
1. Without synchronism voltage switchover
The synchronism voltage can be connected to terminal 19 and 20 (terminal 19 is polarity mark).
The synchronism voltage could be any phase-to-ground voltage or phase-to-phase voltage.
Ia 01 Ian 02
NR1401
Ib 03 Ibn 04
Ic 05 Icn 06
07 08
09 10
11 12
Ua 13 Uan 14
Ub 15 Ubn 16
Uc 17 Ucn 18
Us 19 Usn 20
21 22
23 24
Figure 6.3-9 View of AI plug-in module (without synchronism voltage switchover)

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Table 6.3-2 lists the terminal number and definition of AI module.
Terminal No. Definition Definition

01 Ia The current of A-phase (Polarity mark)
02 Ian The current of A-phase
03 Ib The current of B-phase (Polarity mark)
04 Ibn The current of B-phase
05 Ic The current of C-phase (Polarity mark)
06 Icn The current of C-phase
07 Reserved Reserved current channel
09 Blank
10 Blank
11 Blank
12 Blank
13 Ua The voltage of A-phase (Polarity mark)
14 Uan The voltage of A-phase
15 Ub The voltage of B-phase (Polarity mark)
16 Ubn The voltage of B-phase
17 Uc The voltage of C-phase (Polarity mark)
18 Ucn The voltage of C-phase
19 Us Synchronism voltage (Polarity mark)
20 Usn Synchronism voltage
21 Blank
22 Blank
23 Blank
24 Blank
25 GND Ground
2. With synchronism voltage switchover
UB1, UB2 and UL2 are the synchronism voltage from bus VT and line VT used for synchrocheck, it
could be any phase-to-ground voltage or phase-to-phase voltage. The device can automatically
switch synchronism voltage according to auxiliary contact of CB position or DS position.

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Ia 01 Ian 02
NR1401
Ib 03 Ibn 04
Ic 05 Icn 06
07 08
09 10
11 12
Ua 13 Uan 14
Ub 15 Ubn 16
Uc 17 Ucn 18
UB1 19 UB1n 20
UL2 21 UL2n 22
UB2 23 UB2n 24
Figure 6.3-10 View of AI plug-in module (with synchronism voltage switchover)
Table 6.3-3 Terminal definition of NR1401 module (with synchronism voltage switchover)

01 Ia The current of A-phase (Polarity mark)
02 Ian The current of A-phase
03 Ib The current of B-phase (Polarity mark)
04 Ibn The current of B-phase
05 Ic The current of C-phase (Polarity mark)
06 Icn The current of C-phase
19 UB1 The voltage of bus 1 (Polarity mark)
20 UB1n The voltage of bus 1

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21 UL2 The voltage of line 2 (Polarity mark)
22 UL2n The voltage of line 2
23 UB2 The voltage of bus 2 (Polarity mark)
24 UB2n The voltage of bus 2
25 GND Ground
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
 NR1408
Terminal 0201, 0205 and 0209 are polarity marks of CT-1A, terminal 0203, 0207 and 0211 are
polarity marks of CT-5A. NR1408 module can support up to four voltage channels, so if NR1408
module is used, synchronism voltage switchover function is not available.
NR1408
Ia-1A 01 Ian-1A 02
Ia-5A 03 Ian-5A 04
Ib-1A 05 Ibn-1A 06
Ib-5A 07 Ibn-5A 08
Ic-1A 09 Icn-1A 10
Ic-5A 11 Icn-5A 12
Ir-1A 13 Irn-1A 14
Ir-5A 15 Irn-5A 16
Ua 17 Uan 18
Ub 19 Ubn 20
Uc 21 Ucn 22
Us 23 Usn 24
Without synchronism voltage switchover
Figure 6.3-11 View of AI plug-in module NR1408

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01 Ia-1A The current of A-phase (Polarity mark)
02 Ian-1A The current of A-phase
03 Ia-5A The current of A-phase (Polarity mark)
04 Ian-5A The current of A-phase
05 Ib-1A The current of B-phase (Polarity mark)
06 Ibn-1A The current of B-phase
07 Ib-5A The current of B-phase (Polarity mark)
08 Ibn-5A The current of B-phase
09 Ic-1A The current of C-phase (Polarity mark)
10 Icn-1A The current of C-phase
11 Ic-5A The current of C-phase (Polarity mark)
12 Icn-5A The current of C-phase
13 Ir-1A Reserved current channel (1A)
14 Irn-1A Reserved current channel (1A)
15 Ir-5A Reserved current channel (5A)
16 Irn-5A Reserved current channel (5A)
23 Us Synchronism voltage (Polarity mark)
24 Usn Synchronism voltage
25 GND Ground

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6.3.4 DSP Plug-in Module (Logic Proces)
NR1161
Figure 6.3-12 View of DSP plug-in module
This device can be equipped with 2 DSP plug-in modules at most and 1 DSP plug-in module at
least. The default DSP plug-in module is necessary, which mainly is responsible for protection
function including fault detector and protection calculation.
The module consists of high-performance double DSP (digital signal processor), 16-digit
high-accuracy ADC that can perform synchronous sampling and manage other peripherals. One
of double DSP is responsible for protection calculation, and can fulfill analog data acquisition,
protection logic calculation and tripping output. The other is responsible for fault detector, and can
fulfill analog data acquisition, fault detector and providing power supply to output relay.
When the module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AI plug-in module. When the module is connected with ECT/EVT, it can
receive the real-time synchronous sampled value from merging unit through NET-DSP plug-in
module.
The other module is optional and it is not required unless control and manual closing with
synchronism check are equppied with this device. The default DSP plug-in module is fixed at slot
04 and the option DSP plug-in module is fixed at slot 06.
6.3.5 NET-DSP Plug-in Module (GOOSE and SV)
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.

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Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
NR1136A NR1136C
RX
Figure 6.3-13 View of NET-DSP plug-in module
This module consists of high-performance DSP (digital signal processor), 2~8 100Mbit/s
optical-fibre interface (LC type) and selectable IRIG-B interface (ST type). It supports GOOSE and
SV by IEC 61850-9-2 protocols. It can receive and send GOOSE messages to intelligent control
device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected.This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
The device can output q data by GOOSE, and an output signal is provided “Output_q”. This signal
is used to indicate the quality of all output signals. According to the standard definition about the
quality by IEC 61850, the value of this signal is “0” under normal conditions, and it will be “2048”
(Bit1 is “1”, and other bits is “0”) when the device is under maintenance condtion.
The definition of each bit about quality signal by IEC 61850 is as below.
Table 6.3-5 Encoding of IEC 61850-7-3 quality
Bit (s) IEC 61850-7-3 Bit-String

Bit Attribute name Attribute value Value Default
Good 00 00
0-1 Validity
Invalid 01

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Bit (s) IEC 61850-7-3 Bit-String

Reserved 10
Questionable 11
2 Overflow TRUE FALSE
3 OutofRange TRUE FALSE
4 BadReference TRUE FALSE
5 Oscillatory TRUE FALSE
6 Failure TRUE FALSE
7 OldData TRUE FALSE
8 Inconsistent TRUE FALSE
9 Inaccurate TRUE FALSE
Process 0 0
10 Source
Subsituted 1
11 Test TRUE FALSE
12 OperatorBlocked TRUE FALSE
The method of adding q data is as bellow steps.
1. Step1: Open the DEV file and find “Station_GOOSE_Output” page.
2. Step2: Taking “PTRC_out” module as an example, which can be found in “Symbol Library”
and instanced as bellow.

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3. Step3: Double click the instanced module, the parameter list is displayed as bellow. Tr1~Tr8
are used for sending signals, q1~q8 are used for q data, the relationship between them is one
to one. Only one total q data can be added to all 8 sending signals by “batch_q”.
4. Step4: The output q data, named “Output_q” in variable library, is used for all sending signals.
The path is shown as bellow which is marked in red color.

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5. Step5: Put the mouse on the “Output_q” signal, hold the left button of the mouse and drag it to
the corresponding position, and then release. The detail is as bellow.
After the above steps, save the modifications and compress driver file. Check the latest GOOSE
and CID file.
6.3.6 BI Plug-in Module (Binary Input)

There are five kinds of BI modules available, NR1503A, NR1503AR, NR1504A, NR1504AR and
NR1508A. Up to 3 BI modules can be equipped with one device.

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Voltage
264
176
154
140
110
87.5
77
62.5 Operation
55
Operation uncertain
No operation
0 110V 125V 220V 220V
Figure 6.3-14 Voltage dependence for binary inputs
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.3-15.
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.
Binary input state
Validate binary input state change & write it

into SOE record
1
Debounce time of Debounce time of

delayed pickup delayed dropout
Time
Figure 6.3-15 Debounce technique

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In order to meet flexible configurable requirement for different project feild, all binary inputs
provided by the device are configurable. The device provide two parameters to setup debounce
time of delayed pickup and debounce time of delayed dropout based on specific binary signal.
The configurable binary signals can be classified as follows:
1. Type 1
This type of binary inputs include enable/disable of protection functions, AR mode selection,
"BI_Print", "BI_RstTarg", "BI_Maintenance", disconnector position, settings group switch, open
and close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They is on the premise of reliability, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 100ms at least.
2. Type 2
This type of binary inputs include the time synchronization binary input "BI_TimeSyn", the
debounce time of delayed pickup and delayed dropout is usually set as 0ms.
3. Type 3
This type of binary inputs include "CSWIxx.Cmd_LocCtrl", "CSWIxx.Cmd_RmtCtrl".
Debounce time
BI Input Signal.X1 t1 t2 &

Time delay Output
SIG Operation condition
 Time delay is equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as 15ms, in
order to prevent binary signals from misoperation due to mixed connection of AC system and DC
system.
 Time delay is not equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as (-t1+
t2+Time delay)≥15ms, in order to prevent binary signals from misoperation due to mixed
connection of AC system and DC system.
ti is the debounce time of delayed pickup.
t2 is the debounce time of delayed dropout.
4. Type 4
This type of binary inputs are usually used as auxiliary input condition, and include the following
signals.

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No. Binary input

1 52b_PhA
2 52b_PhB
3 52b_PhC
4 52b
5 52a
6 TCCS.Input
7 50DZ.Init
8 PrepTrp3P
9 50BF.ExTrp3P_L
10 50BF.ExTrp3P_GT
11 50BF.ExTrpA
12 50BF.ExTrpB
13 50BF.ExTrpC
14 50BF.ExTrp_WOI
15 25.MCB_VT_UL1
16 25.MCB_VT_UL2
17 25.MCB_VT_UB1
18 25.MCB_VT_UB2
19 79.Trp
20 79.Trp3P
21 79.TrpA
22 79.TrpB
23 79.TrpC
24 79.WaitMaster
25 79.CB_Healthy
26 79.Clr_Counter
27 79.Ok_Chk
28 79.Lockout
29 79.PLC_Lost
30 VTS.MCB_VT
The debounce time of delayed pickup and delayed dropout is recommended to set as 5ms.
 NR1503A/1503AR
Each BI module is with a 22-pin connector for 11 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. Each binary input of NR1503A and NR1503AR has
independent negative power input of opto-coupler and can be configurable. NR1503A′s pickup
voltage and dropoff voltage are fixed value, and the range is from 55%Un to 70%Un. NR1503AR′s
pickup voltage and dropoff voltage are settable by the setting [xx.U_Pickup_BI] and
[xx.U_Dropoff_BI] from 55%Un to 80%Un.

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BI_01 01
NR1503 Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.3-16 View of BI plug-in module (NR1503)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1503 is shown as follows.

01 BI_01 Configurable binary input 1
02 Opto01- Negative supply of configurable binary input 1

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 NR1504A/NR1504AR
Each BI module is with a 22-pin connector for 18 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. All binary inputs of NR1504A and NR1504AR share one
common negative power input and can be configurable. NR1504A′s pickup voltage and dropoff
voltage are fixed value, and the range is from 55%Un to 70%Un. NR1504AR′s pickup voltage and
dropoff voltage are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI] from 55%Un to
80%Un.
Opto+ 01
NR1504 BI_01 02
BI_02 03
BI_03 04
BI_04 05
BI_05 06
BI_06 07
08
BI_07 09
BI_08 10
BI_09 11
BI_10 12
BI_11 13
BI_12 14
15
BI_13 16
BI_14 17
BI_15 18
BI_16 19
BI_17 20
BI_18 21
COM- 22
Figure 6.3-17 View of BI plug-in module (NR1504)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1504 is shown as follows.

01 Opto+ Positive supply of power supply of the module

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08 Blank Not used
15 Blank Not used
22 COM- Common terminal of negative supply of binary inputs
 NR1508
NR1508A is with a 22-pin connector for 11 binary inputs, and its rated voltage is 220Vdc. Each
binary input of NR1508A has independent negative power input of opto-coupler and can be
configurable. NR1508A′s pickup voltage and dropoff voltage are fixed value, and the range is from
75%Un to 80%Un.
BI_01 01
NR1508A Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.3-18 View of BI plug-in module (NR1508A)

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Terminal description for NR 1508A is shown as follows.

A default configuration is given for first four binary signals (BI_01, BI_02, BI_03, BI_04) in first BI
plug-in module, and they are [BI_TimeSyn], [BI_Print], [BI_Maintenance] and [BI_RstTarg]
respectively. They can alos be configured as other signals. Because the first binary signal [BI_01]
is set as [BI_TimeSyn] by default (the state change information of binary signal [BI_TimeSyn] does
not need be displayed), new binary signal should be added to state change message if it is set as
other signal.
1. Binary input: [BI_TimeSyn]
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from “0” to “1” once pulse signal is received. When the device
adopts “Conventional” mode as clock synchronization mode (refer to section “Communication
Settings”), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2. Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.

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3. Binary input: [BI_Maintenance]
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1) Processing mechanism for MMS (Manufacturing Message Specification) message
a) The protection device should send the state of this binary input to client.
b) When this binary input is energized, the bit “Test” of quality (Q) in the sent message changes
to “1”.
c) When this binary input is energized, the client cannot control the isolator link and circuit
breaker, modify settings and switch setting group remotely.
d) According to the value of the bit “Test” of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it correspondingly.
If the message is the maintenance message, the content of the message will not be displayed on
real-time message window, audio alarm not issued, but the picture is refreshed so as to ensure
that the state of the picture is in step with the actual state. The maintenance message will be
stored, and can be inquired, in independent window.
2) Processing mechanism for GOOSE message
a) When this binary input is energized, the bit “Test” in the GOOSE message sent by the
protection device changes to “1”.
b) For the receiving end of GOOSE message, it will compare the value of the bit “Test” in the
GOOSE message received by it with the state of its own binary input (i..e [BI_Maintenance]), the
message will be thought as invalid unless they are conformable.
3) Processing mechanism for SV (Sampling Value) message
a) When this binary input of merging unit is energized, the bit “Test” of quality (Q) of sampling
data in the SV message sent change “1”.
b) For the receiving end of SV message, if the value of bit “Test” of quality (Q) of sampling data
in the SV message received is “1”, the relevant protection functions will be disabled, but under
maintenance state, the protection device should calculate and display the magnitude of sampling
data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices and dual
merging units should be fully independent each other, and one of them is in maintenance state will
not affect the normal operation of the other.
4. Binary input: [BI_RstTarg]

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It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
NOTICE!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which MUST
BE specified when placed order. It is necessary to CHECK whether the rated voltage of
BI module complies with site DC supply rating before put the relay in service.
There three binary signals are fixed for measurement functions, they are [BI_Rmt/Loc],
[BI_ManSynCls] and [BI_ManOpen] respectively.
5. Binary input: [BI_Rmt/Loc]
It is used to select the remote control or the local control.
“1”: the remote control, all the binary outputs can only be remotely controlled by SCADA or control
centers.
“0” the local control, each binary output can only be applied to open/close CB/DS/ES locally. Each
binary output can also be applied issue a signal locally.
6. Binary input: [BI_ManSynCls]
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
synchronism check for closing circuit breaker will be initiated if it is energized.
7. Binary input: [BI_ManOpen]
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
control for open circuit breaker will be initiated if it is energized.
6.3.7 BO Plug-in Module (Binary Output)

Two standard binary output modules, NR1521A and NR1521C, and two optional binary output
module, NR1521F and 1580A, can be selected. The contacts provided by NR1521A, NR1521C,
NR1521F and NR1580A are all normally open (NO) contacts. Output contact can be configured as
a specified tripping output contact and a signal output contact respectively by PCS-Explorer
software according to user requirement.
NR1521A can provide 11 output contacts controlled by fault detector.

Date: 2015-08-13
6 Hardware
01
BO_01
NR1521A 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-19 View of BO plug-in module (NR1521A)
NR1521C can provide 11 output contacts without controlled by fault detector.
01
BO_01
NR1521C 02
03
BO_02
04
05
BO_03
06
07
BO_04
08
09
BO_05
10
11
BO_06
12
13
BO_07
14
15
BO_08
16
17
BO_09
18
19
BO_10
20
21
BO_11
22
Figure 6.3-20 View of BO plug-in module (NR1521C)

Date: 2015-08-13
6 Hardware
BO plug-in module (NR1521F) is dedicatedly for remote/manual open or closing to circuit breaker,
disconnector and earth switch. 5 pairs of binary outputs (one for open and the other for closing)
can be provided by this BO plug-in module configured in slot 15 if measurement and control
function is equipped with the device. Up to 10 pairs of binary outputs can be provided by two BO
plug-in modules that can be configured in slot 14 and 15 respectively. (BO plug-in module
configured in slot 14 is optional if open or closing contacts is not enough)
A normally open contact is presented via terminal 21-22 designated as ROS (i.e. remote operation
signal). Whenever any of binary output contacts for open or closing is closed, ROS contact will
close to issue a signal indicating that this device is undergoing a remote operation.
BO plug-in module (NR1521F) is displayed as shown in the following figure.
01
BO_CtrlOpn01
NR1521F 02
03
BO_CtrlCls01
04
05
BO_CtrlOpn02
06
07
BO_CtrlCls02
08
09
BO_CtrlOpn03
10
11
BO_CtrlCls03
12
13
BO_CtrlOpn04
14
15
BO_CtrlCls04
16
17
BO_CtrlOpn05
18
19
BO_CtrlCls05
20
21
BO_Ctrl
22
Figure 6.3-21 View of BO plug-in module (NR1521F)
NR1580A can provide 6 output contacts with controlled by fault detector. It is a heavy-capacity
binary output plug-in module, which can be used to control the circuit breaker directly.

Date: 2015-08-13
6 Hardware
+ 01
NR1580A BO_01 02
- 03
04
+ 05
BO_02 06
- 07
08
+ 09
BO_03 10
- 11
12
+ 13
BO_04 14
- 15
16
+ 17
BO_05 18
- 19
20
+ 21
BO_06
- 22
Figure 6.3-22 View of BO plug-in module (NR1580A)
6.3.8 HMI Module

The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through LAN port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.

Date: 2015-08-13
7 Settings
7 Settings
Table of Contents
7.1 Communication Settings ................................................................................ 7-1

7.1.1 Setting Description............................................................................................................... 7-2
7.1.2 Access Path ......................................................................................................................... 7-9
7.2 Device Settings ............................................................................................. 7-10

7.2.1 Setting Description............................................................................................................. 7-10
7.2.2 Access Path ........................................................................................................................7-11
7.3 System Settings ............................................................................................. 7-11

7.3.2 Access Path ....................................................................................................................... 7-12
7.4 Protection Settings ....................................................................................... 7-13

7.4.2 Access Path ....................................................................................................................... 7-33
7.5 Logic Link Settings ....................................................................................... 7-33

7.5.2 Access Path ....................................................................................................................... 7-34
7.6 Measurement and Control Settings ............................................................. 7-34

7.6.2 Access Path ....................................................................................................................... 7-36
List of Tables
Table 7.1-1 Communication settings ......................................................................................... 7-1
Table 7.2-1 Device settings....................................................................................................... 7-10
Table 7.3-1 System settings ..................................................................................................... 7-11

Date: 2017-12-12
7 Settings

Date: 2017-12-12
7 Settings
The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, communication settings, system
settings, device settings, logic link settings and measurement and control settings are common for
all protection setting groups.
NOTICE!
All current settings in this chapter are secondary current converted from primary current
by CT ratio. Zero-sequence current or voltage setting is configured according to 3I0 or
3U0 and negative sequence current or voltage setting according to I2 or U2.
7.1 Communication Settings

Table 7.1-1 Communication settings
No. Item Range

1 IEDNAME
2 IP_LAN1 000.000.000.000~255.255.255.255
3 Mask_LAN1 000.000.000.000~255.255.255.255
4 IP_LAN2 000.000.000.000~255.255.255.255
5 Mask_LAN2 000.000.000.000~255.255.255.255
6 En_LAN2 0 or 1
7 IP_LAN3 000.000.000.000~255.255.255.255
8 Mask_LAN3 000.000.000.000~255.255.255.255
9 En_LAN3 0 or 1
10 IP_LAN4 000.000.000.000~255.255.255.255
11 Mask_LAN4 000.000.000.000~255.255.255.255
12 En_LAN4 0 or 1
13 Gateway 000.000.000.000~255.255.255.255
14 En_Broadcast 0 or 1
15 Cfg_NetPorts_Bond 0~12
16 Addr_RS485A 0~255
17 Baud_RS485A 4800,9600,19200,38400,57600,115200 (bps)
18 Protocol_RS485A 0, 1 or 2
19 Addr_RS485B 0~255
20 Baud_RS485B 4800,9600,19200,38400,57600,115200 (bps)
21 Protocol_RS485B 0, 1 or 2
22 Threshold_Measmt_Net 0~100%
23 Period_Measmt_Net 0~65535s
24 Format_Measmt 0, 1
25 Baud_Printer 4800,9600,19200,38400,57600,115200 (bps)
26 En_AutoPrint 0 or 1
27 Opt_TimeSyn Conventional

Date: 2017-12-12
7 Settings
No. Item Range

SAS
Advanced
NoTimeSyn
28 IP_Server_SNTP 000.000.000.000~255.255.255.255
29 IP_StandbyServer_SNTP 000.000.000.000~255.255.255.255
30 OffsetHour_UTC -12~+12 (hrs)
31 OffsetMinute_UTC 0~60 (min)
32 Opt_Display_Status PriValue, SecValue
33 Num_Cyc_PreTrigDFR 0~120 (cycles)
34 t_Dly_Net_DNP 0~10000 (ms)
35 Format_Setting_DNP 0, 1, 2
36 En_TCPx_DNP 0 or 1
37 Addr_Slave_TCPx_DNP 0~65519
38 Addr_Master_TCPx_DNP 0~65519
39 IP_Master_TCPx_DNP 000.000.000.000~255.255.255.255
40 Opt_Map_TCPx_DNP 0~4
41 Obj01DefltVar_TCPx_DNP 0~1
46 t_AppLayer_TCPx_DNP 0~5 (s)
47 t_KeepAlive_TCPx_DNP 0~7200 (s)
48 En_UR_TCPx_DNP 0 or 1
49 Num_URRetry_TCPx_DNP 2~10
50 t_UROfflRetry_TCPx_DNP 1~5000 (s)
51 Class_BI_TCPx_DNP 0~3
52 Class_AI_TCPx_DNP 0~3
53 t_Select_TCPx_DNP 0~240 (s)
54 t_TimeSynIntvl_TCPx_DNP 0~3600 (s)
7.1.1 Setting Description

1. IEDNAME
IED name of this device. If this setting is modified, the IED name in ".cid" file will be changed
simultaneously and vice versa.
2. IP_LAN1, IP_LAN2, IP_LAN3, IP_LAN4
IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
3. Mask_LAN1, Mask_LAN2, Mask_LAN3, Mask_LAN4

Date: 2017-12-12
7 Settings
Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
4. En_LAN2, En_LAN3, En_LAN4
Put Ethernet port 2, Ethernet port 3 and Ethernet port 4 in service
They are used for Ethernet communication based on the IEC 60870-5-103 protocol. When the IEC
61850 protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.
Ethernet port 1 is always in service by default.
5. Gateway
IP address of Gateway (router)
6. En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as “1”.
0: the device does not send UDP messages through network
1: the device sends UDP messages through network
7. Cfg_NetPorts_Bond
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any two
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking NR1102D (with four Ethernet ports) as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.

Date: 2017-12-12
7 Settings
Bonding Bonding Bonding
Ethernet port 1 Ethernet port 2 Ethernet port 1 Ethernet port 3 Ethernet port 1 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 0 1 1 3 0 1 0 1 5 1 0 0 1 9
Bonding Bonding Bonding
Ethernet port 2 Ethernet port 3 Ethernet port 2 Ethernet port 4 Ethernet port 3 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 1 1 0 6 1 0 1 0 10 1 1 0 0 12
Ethernet port 1: Bit0, Ethernet port 2: Bit1, Ethernet port 3: Bit2, Ethernet port 4: Bit3
The switching logic is as below.
 After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.
 When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.
 When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.
 When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal.
8. Addr_RS485A, Addr_RS485B
They are the device′s communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
9. Baud_RS485A, Baud_RS485B
Baud rate of rear RS-485 serial port A or B
10. Protocol_RS485A, Protocol_RS485B
Communication protocol of rear RS-485 serial port A or B
0: IEC 60870-5-103 protocol
1: Modbus Protocol
2: Reserved
NOTICE!

Date: 2017-12-12
7 Settings
Above table listed all the communication settings, the device delivered to the user
maybe only show some settings of them according to the communication interface
configuration. If only the Ethernet ports are applied, the settings about the serial ports
(port A and port B) are not listed in this submenu. And the settings about the Ethernet
ports only listed in this submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined
when ordering). Set the IP address according to actual arrangement of Ethernet
numbers and the un-useful port/ports need not be configured. If PCS-Explorer
configuration tool auxiliary software is connected with this device through the Ethernet,
the IP address of PCS-Explorer must be set as one of the available IP address of this
device.
11. Threshold_Measmt_Net
Threshold value of sending measurement values to SCADA through IEC 60870-5-103 or

IEC61850 protocol.
Default value: “1%”
12. Period_Measmt_Net
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol.
Default value: “60”
13. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
14. Baud_Printer
Baud rate of printer port
15. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as “1”. Otherwise, it
should be set to “0”.
16. Opt_TimeSyn
There are four selections for clock synchronization of device, shown as follows.
 Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level

Date: 2017-12-12
7 Settings
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]
 SAS
SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
SNTP (BC): Broadcast SNTP mode via Ethernet network
Message (IEC103): Clock messages through IEC103 protocol
 Advanced
IEEE1588: Clock message via IEEE1588
IRIG-B (Fiber): IRIG-B via optical-fibre interface
PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface
 NoTimeSync
When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by the device, but “Advanced”
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.
2) When “Advanced” mode is selected, if there is no conventional clock synchronization signal

connected to NET-DSP module, “SAS” mode is enabled automatically with the alarm signal
[Alm_TimeSyn] issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
NOTICE!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives
the IRIG-B signal through RCS-485 port.
17. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
18. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are inefffective unless SNTP clock

Date: 2017-12-12
7 Settings
synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as “000.000.000.000”, the

deivce receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as “000.000.000.000”, the

deivce adopt the setting whose value is not equal to “000.000.000.000” as SNTP server address
and the deivce receives unicast SNTP synchronization message.
When neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] are set as “000.000.000.000”, the

deivce adopt the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive the server responses after 30s, the
deivce adopt the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast
SNTP synchronization message. The device will switch between [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] repeatedly if the device always can not receive the server responses
waiting 30s
19. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as “8”. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
Time zone GMT zone East 1st East 2nd East 3rd East 4th East 5th
Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11th
Setting 6 7 8 9 10 11
th st nd rd th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5th
Setting 12/-12 -1 -2 -3 -4 -5
th th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11
Setting -6 -7 -8 -9 -10 -11
20. Opt_Display_Status
This setting is used to set display mode of current in fault records, primary value or secondary
value. The sampled values of currents are displayed as secondary value by default. When it is set
as primary value, the secondary current are converted into primary current according to rated
secondary and primary value of CT respectively.
NOTICE!
After modifying this setting, the “HEALTHY” indicator of the protection device will GO
OUT, and the protection device will automatically restart and re-check the settings. The
device will be BLOCKED until the check process is finished.
21. Num_Cyc_PreTrigDFR

Date: 2017-12-12
7 Settings
The setting is used to set the cycle number recorded by the device before the trigger element
operating.
22. t_Dly_Net_DNP
The setting is used to set transmission time delay for transmitting multi-frame messages during
DNP process (the setting is valid only if network DNP3.0 protocol is configured)
23. Format_Setting_DNP
The setting is used to set settings uploading format during DNP process (this setting is valid only if
network or serial port DNP3.0 protocol is configured).
0: not upload settings
1: uploading settings adopts the mode of analog output
2: uploading settings adopts the mode of analog input
24. En_TCPx_DNP
The logic setting is used to enable or disable network No.x DNP client. (x=1, 2, 3, 4)
1: enable
0: disable
When network No.x DNP client is not configured to be in service by PCS-Explorer, DNP client
settings corresponding to network No.x will be hidden.
25. Addr_Slave_TCPx_DNP
It is the slave address of network No.x DNP client. (x=1, 2, 3, 4)
26. Addr_Master_TCPx_DNP
It is the master address of network No.x DNP client. (x=1, 2, 3, 4)
27. IP_Master_TCPx_DNP
It is the IP address of network No.x DNP client. (x=1, 2, 3, 4)
28. Opt_Map_TCPx_DNP
It is the communication map of network No.x DNP client. (x=1, 2, 3, 4)
29. Obj01DefltVar_TCPx_DNP
It is the “OBJ1” default variation of network No.x DNP client. (x=1, 2, 3, 4)

Date: 2017-12-12
7 Settings
34. t_AppLayer_TCPx_DNP
It is the timeout of application layer of network No.x DNP client. (x=1, 2, 3, 4)
35. t_KeepAlive_TCPx_DNP
It is the heartbeat time interval of network No.x DNP client. (x=1, 2, 3, 4)
36. En_UR_TCPx_DNP
The logic setting is used to enable or disable the unsolicited message function of network No.x
DNP client. (x=1, 2, 3, 4)
1: enable
0: disable
37. Num_URRetry_TCPx_DNP
It is the online retransmission number of the unsolicited message of network No.x DNP client. (x=1,
2, 3, 4)
38. t_UROfflRetry_TCPx_DNP
It is the offline timeout of the unsolicited message of network No.x DNP client. (x=1, 2, 3, 4)
39. Class_BI_TCPx_DNP
It is the class level of the “Binary Input” of network No.x DNP client. (x=1, 2, 3, 4)
40. Class_AI_TCPx_DNP
It is the class level of the “Analog Input” of network No.x DNP client. (x=1, 2, 3, 4)
41. t_Select_TCPx_DNP
It is the selection timeout of network No.x DNP client. (x=1, 2, 3, 4)
42. t_TimeSynIntvl_TCPx_DNP
It is the time interval of the time synchronization function of network No.x DNP client. (x=1, 2, 3, 4)
7.1.2 Access Path

MainMenuSettingsDevice SetupComm Settings

Date: 2017-12-12
7 Settings
7.2 Device Settings

Table 7.2-1 Device settings
No. Item Range

1 HDR_EncodedMode GB18030, UTF-8
2 Opt_Caption_103 0, 1 or 2
3 En_Send_MMS_Qual_Chg 0 or 1
4 Opt_DualNetMode_MMS 0, 1 or 2
5 Bxx.Un_BinaryInput 24V, 30V, 48V, 110V, 125V, 220V
6 Bxx.U_Pickup_BI 55%Un~80%Un
7 Bxx.U_Dropoff_BI 55%Un~80%Un
8 En_RevCT 0 or 1
9 En_Ctrl_SLD 0 or 1
10 En_PopupRecord_Blkd 0 or 1

1. HDR_EncodedMode
Select encoding format of header (HDR) file COMTRADE recording file
Default value is “UTF-8”.
2. Opt_Caption_103
Select the caption language sent to SAS via IEC103 protocol
0: Current language
1: Fixed Chinese
2: Fixed English
Default value of [Opt_Caption_103] is “0” (i.e. current language), and please set it as “1” (i.e. Fixed
Chinese) if the SAS is supplied by China Manufacturer.
3. En_Send_MMS_Qual_Chg
It is used to enable or disable that IEC 61850 communication program uploads tha variation of
data quality.
0: disable
1: enable
4. Opt_DualNetMode_MM
It is used to select network mode of MMS network for the communication with SCADA
0: Single network
1: Hot standby mode (always two ports in service)

Date: 2017-12-12
7 Settings
2: Cold standby mode (only one port in service)
5. Bxx.Un_BinaryInput
This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.
6. Bxx.U_Pickup_BI
This setting is used to set pickup voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
7. Bxx.U_Dropoff_BI
This setting is used to set dropoff voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
8. En_RevCT
1: Reverse the polarity mark of CT
0: Not reverse the polarity mark of CT
The default value is “0”, it can be set as “1” if the polarity of the CT on site is reverse.
9. En_Ctrl_SLD
This setting is used to enable or disable the switch control function from the single line diagram
displayed in the device LCD.
0: Disable
1: Enable
10. En_PopupRecord_Blkd
This setting is used to enable or disable the auto-popup function of event report in the device LCD.
0: Disable
1: Enable
7.2.2 Access Path

MainMenuSettingsDevice SetupDevice Settings
7.3 System Settings

Table 7.3-1 System settings
No. Item Range Unit

1 Active_Grp 1~10

Date: 2017-12-12
7 Settings
No. Item Range Unit

2 Opt_SysFreq 50 or 60 Hz
3 PrimaryEquip_Name Maximum 12 character

4 U1n 10.00~65500.00 kV
5 U2n 80.00~220.00 V
6 I1n 100~30000 A
7 I2n 1 or 5 A
8 f_High_FreqAlm 50~65 Hz
9 f_Low_FreqAlm 40~60 Hz

1. Active_Grp
The number of active setting group, 10 setting groups can be configured for protection settings,
and only one is active at a time.
2. PrimaryEquip_Name
It is recognized by the device automatically. Such setting is used for printing messages.
3. Opt_SysFreq
It is option of system frequency, and can be set as 50Hz or 60Hz.
4. Un1
Primary rated voltage of VT;
5. Un2
Secondary rated voltage of VT;
6. In1
Primary rated current of CT;
7. In2
Secondary rated current of CT;
8. f_High_FreqAlm
Frequency upper limit setting. The device will issue an alarm [Alm_Freq], when system frequency
is higher than the setting.
9. f_Low_FreqAlm
Frequency lower limit setting. The device will issue an alarm [Alm_Freq], when system frequency
is lower than the setting.
7.3.2 Access Path

MainMenuSettingsSystem Settings

Date: 2017-12-12
7 Settings
7.4 Protection Settings

All protection settings are based on secondary ratings of VT and CT.
Unn: rated secondary phase-to-phase voltage.
Un: rated secondary phase-to-ground voltage.
In: rated secondary current.

7.4.1.1 Fault Detector Settings (FD)
No. Item Remark Range

1 FD.DPFC.I_Set Current setting of DPFC current FD element (0.050~30.000)×In (A)
2 FD.ROC.3I0_Set Current setting of neutral current FD element (0.050~30.000)×In (A)
Current setting of negative-sequence current FD
3 FD.NOC.I2_Set (0.050~30.000)×In (A)
element
Enabling/disabling negative-sequence current FD
4 FD.NOC.En 0 or 1
element
7.4.1.2 Auxiliary Element Settings (Aux.E)

Extended time delay of current change auxiliary
1 AuxE.OCD.t_DDO 0.000~10.000 (s)
element
2 AuxE.OCD.En Enabling/disabling current change auxiliary element 0 or 1
Current setting of stage 1 residual current auxiliary
3 AuxE.ROC1.3I0_Set (0.050~30.000)×In
element
Enabling/disabling stage 1 residual current auxiliary
element
5 AuxE.ROC2.3I0_Set (0.050~30.000)×In
element
element
7 AuxE.ROC3.3I0_Set (0.050~30.000)×In
element
element
Current setting of stage 1 phase current auxiliary
9 AuxE.OC1.I_Set (0.050~30.000)×In
element
Enabling/disabling stage 1 phase current auxiliary
element
11 AuxE.OC2.I_Set (0.050~30.000)×In
element

Date: 2017-12-12
7 Settings

element
13 AuxE.OC3.I_Set (0.050~30.000)×In
element
element
15 AuxE.UVD.U_Set Voltage setting for voltage change auxiliary element 0.000~Un
Extended time delay of voltage change auxiliary
16 AuxE.UVD.t_DDO 0.000~10.000 (s)
element
17 AuxE.UVD.En Enabling/disabling voltage change auxiliary element 0 or 1
Voltage setting for phase-to-ground under voltage
18 AuxE.UVG.U_Set 0.000~Un
auxiliary element
Enabling/disabling phase-to-ground under voltage
19 AuxE.UVG.En 0 or 1
auxiliary element
Voltage setting for phase-to-phase under voltage
20 AuxE.UVS.U_Set 0.000~Unn
auxiliary element
Enabling/disabling phase-to-phase under voltage
21 AuxE.UVS.En 0 or 1
auxiliary element
22 AuxE.ROV.3U0_Set Voltage setting for residual voltage auxiliary element 0.000~Un
23 AuxE.ROV.En Enabling/disabling residual voltage auxiliary element 0 or 1
7.4.1.3 Current Direction Settings

The characteristic angle of directional phase
1 RCA_OC 30.00~89.00 (Deg)
overcurrent element
The characteristic angle of directional earth fault
2 RCA_ROC 30.00~89.00 (Deg)
element
3 RCA_NegOC 30.00~89.00 (Deg)
negative-sequence overcurrent element
4 Z0_Comp Zero-sequence compensation impedance setting (0.000~4Unn)/In (ohm)
Negative-sequence compensation impedance
5 Z2_Comp (0.000~4Unn)/In (ohm)
setting
7.4.1.4 Phase Overcurrent Protection (50/51P)

Setting of second harmonic component for
1 50/51P.K_Hm2 0.000~1.000
blocking phase overcurrent elements
Current setting for stage 1 of phase overcurrent
2 50/51P1.I_Set (0.050~30.000)×In (A)
protection
Time delay for stage 1 of phase overcurrent
3 50/51P1.t_Op 0.000~20.000 (s)
protection
4 50/51P1.En Enable stage 1 of phase overcurrent protection 0 or 1

Date: 2017-12-12
7 Settings
Enable auto-reclosing blocked when stage 1 of

5 50/51P1.En_BlkAR 0 or 1
phase overcurrent protection operates
Enable stage 1 of phase overcurrent protection
6 50/51P1.En_VTS_Blk 0 or 1
been blocked by VT circuit failure
Non_Directional
Direction option for stage 1 of phase overcurrent
protection
Reverse
Enable second harmonic blocking for stage 1 of
8 50/51P1.En_Hm2_Blk 0 or 1
phase overcurrent protection
DefTime, IECN, IECV,
IECE, IECST, IECLT,
Option of characteristic curve for stage 1 of phase ANSIE, ANSIV, ANSI,
9 50/51P1.Opt_Curve
overcurrent protection ANSIM, ANSILTE,
ANSILTV, ANSILT,
UserDefine
Time multiplier setting for stage 1 of inverse-time
10 50/51P1.TMS 0.010~20000.000
11 50/51P1.tmin 0.010~20.000 (s)
inverse-time phase overcurrent protection
12 50/51P1.Alpha inverse-time characteristic phase overcurrent 0.010~5.000
protection
13 50/51P1.C inverse-time characteristic phase overcurrent 0.000~20000.000
protection
14 50/51P1.K inverse-time characteristic phase overcurrent 0.050~20.000
protection
15 50/51P2.I_Set (0.050~30.000)×In (A)
protection
16 50/51P2.t_Op 0.000~20.000 (s)
protection
18 50/51P2.En_BlkAR 0 or 1
19 50/51P2.En_VTS_Blk 0 or 1
Non_Directional
protection
Reverse
21 50/51P2.En_Hm2_Blk 0 or 1

Date: 2017-12-12
7 Settings

IECE, IECST, IECLT,
Option of characteristic curve for stage 2 of phase
22 50/51P2.Opt_Curve ANSIE, ANSIV, ANSI,
ANSIM, ANSILTE,
ANSILTV, ANSILT
23 50/51P2.TMS 0.010~20000.000
phase overcurrent protection.
24 50/51P2.tmin 0.010~20.000 (s)
25 50/51P3.I_Set (0.050~30.000)×In (A)
protection
26 50/51P3.t_Op 0.000~20.000 (s)
protection
28 50/51P3.En_BlkAR 0 or 1
29 50/51P3.En_VTS_Blk 0 or 1
Non_Directional
protection
Reverse
31 50/51P3.En_Hm2_Blk 0 or 1
IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
33 50/51P3.TMS 0.010~20000.000
34 50/51P3.tmin 0.010~20.000 (s)
35 50/51P4.I_Set (0.050~30.000)×In (A)
protection
36 50/51P4.t_Op 0.000~20.000 (s)
protection
38 50/51P4.En_BlkAR 0 or 1
39 50/51P4.En_VTS_Blk 0 or 1

Date: 2017-12-12
7 Settings
Non_Directional
protection
Reverse
41 50/51P4.En_Hm2_Blk 0 or 1
IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
43 50/51P4.TMS 0.010~20000.000
44 50/51P4.tmin 0.010~20.000 (s)
7.4.1.5 Earth Fault Protection Settings (50/51G)

Setting of second harmonic component for
1 50/51G.K_Hm2 0.000~1.000
blocking earth fault elements
2 50/51G1.3I0_Set Current setting for stage 1 of earth fault protection (0.050~30.000)×In (A)
3 50/51G1.t_Op Time delay for stage 1 of earth fault protection 0.000~20.000 (s)
4 50/51G1.En Enable stage 1 of earth fault protection 0 or 1
5 50/51G1.En_BlkAR 0 or 1
earth fault protection operates
Non_Directional
Direction option for stage 1 of earth fault
protection
Reverse
7 50/51G1.En_Hm2_Blk 0 or 1
Enable blocking for stage 1 of earth fault
8 50/51G1.En_Abnor_Blk 0 or 1
protection under abnormal conditions
9 50/51G1.En_CTS_Blk 0 or 1
protection under CT failure conditions
IECE, IECST, IECLT,
Option of characteristic curve for stage 1 of earth ANSIE, ANSIV, ANSI,
10 50/51G1.Opt_Curve
fault protection ANSIM, ANSILTE,
ANSILTV, ANSILT,
UserDefine
11 50/51G1.TMS 0.010~200.000
12 50/51G1.tmin 0.050~20.000 (t)
inverse-time earth fault protection

Date: 2017-12-12
7 Settings

13 50/51G1.Alpha 0.010~5.000
inverse-time characteristic earth fault protection
14 50/51G1.C 0.000~20.000
15 50/51G1.K 0.050~20.000
Short time delay for stage 2 of earth fault
18 50/51G2.t_ShortDly 0.000~20.000 (s)
protection
20 50/51G2.En_ShortDly Enable accelerate stage 2 of earth fault protection 0 or 1
21 50/51G2.En_BlkAR 0 or 1
Non_Directional
protection
Reverse
23 50/51G2.En_Hm2_Blk 0 or 1
Enable blocking for stage 2 of earth faultv
25 50/51G2.En_CTS_Blk 0 or 1
IECE, IECST, IECLT,
Option of characteristic curve for stage 2 of earth
26 50/51G2.Opt_Curve ANSIE, ANSIV, ANSI,
fault protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
27 50/51G2.TMS 0.010~200.000
28 50/51G2.tmin 0.050~20.000 (s)
31 50/51G3.t_ShortDly 0.000~20.000 (s)
protection
34 50/51G3.En_BlkAR 0 or 1
Non_Directional
protection
Reverse

Date: 2017-12-12
7 Settings

36 50/51G3.En_Hm2_Blk 0 or 1
38 50/51G3.En_CTS_Blk 0 or 1
IECE, IECST, IECLT,
fault protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
40 50/51G3.TMS 0.010~200.000
41 50/51G3.tmin 0.050~20.000 (s)
44 50/51G4.t_ShortDly 0.000~20.000 (s)
protection
47 50/51G4.En_BlkAR 0 or 1
Non_Directional
protection
Reverse
49 50/51G4.En_Hm2_Blk 0 or 1
51 50/51G4.En_CTS_Blk 0 or 1
IECE, IECST, IECLT,
fault protection
ANSIM, ANSILTE,
ANSILTV, ANSILT
53 50/51G4.TMS 0.010~200.000
54 50/51G4.tmin 0.050~20.000 (s)

Date: 2017-12-12
7 Settings
7.4.1.6 Dead Zone Protection Settings (50DZ)
No. Name Remark Range

1 50DZ.I_Set Current setting of dead zone protection (0.050~30.000)×In (A)
2 50DZ.t_Op Time delay of dead zone protection 0.000~10.000 (s)
3 50DZ.En Enable dead zone protection 0 or 1
7.4.1.7 Overvoltage Protection Settings (59P)

1 59P1.U_Set Voltage setting for stage 1 of overvoltage protection Un~2Unn (V)
2 59P1.t_Op Time delay for stage 1 of overvoltage protection 0.000~30.000 (s)
3 59P1.En Enable stage 1 of overvoltage protection 0 or 1
4 59P1.Opt_1P/3P Option of 1-out-of-3 mode or 3-out-of-3 mode 0 or 1
5 59P1.Opt_Up/Upp Option of phase-to-phase voltage or phase voltage 0 or 1
Enable stage 1 of overvoltage protection for alarm
purpose
Enable transfer trip controlled by CB open position for
7 59P1.En_52b_TT 0 or 1
stage 1 of overvoltage protection
Enable stage 1 of overvoltage protection operate to
8 59P1.En_TT 0 or 1
initiate transfer trip
IECE, IECST, IECLT,
9 59P1.Opt_Curve ANSIE, ANSIV, ANSI,
ANSIM, ANSILTE,
ANSILTV, ANSILT
10 59P1.TMS 0.010~200.000
Minimum delay for stage 1 of inverse-time overvoltage
11 59P1.tmin 0.050~20.000 (s)
protection
17 59P2.En_Alm 0 or 1
purpose
18 59P2.En_52b_TT 0 or 1
19 59P2.En_TT 0 or 1

Date: 2017-12-12
7 Settings

IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
21 59P2.TMS 0.010~200.000
22 59P2.tmin 0.050~20.000 (s)
protection
28 59P3.En_Alm 0 or 1
purpose
29 59P3.En_52b_TT 0 or 1
30 59P3.En_TT 0 or 1
IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
32 59P3.TMS 0.010~200.000
33 59P3.tmin 0.050~20.000 (s)
protection
7.4.1.8 Undervoltage Protection Settings (27P)

1 27P1.U_Set 0~Unn (V)
protection
2 27P1.t_Op Time delay for stage 1 of undervoltage protection 0.000~30.000 (s)
3 27P1.En Enable stage 1 of undervoltage protection 0 or 1
Enable stage 1 of undervoltage protection operate
to alarm

Date: 2017-12-12
7 Settings

IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
8 27P1.TMS 0.010~200.000
9 27P1.tmin 0.050~20.000 (s)
Enable stage 1 of undervoltage protection been
10 27P1.En_FD_Ctrl 0 or 1
controlled by current related fault detector element
11 27P1.En_Curr_Ctrl 0 or 1
controlled by having current condition
12 27P1.En_VTS_Blk 0 or 1
blocked by VT circuit failure
13 27P2.U_Set 0~Unn (V)
protection
18 27P2.En_Alm 0 or 1
to alarm
IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
20 27P2.TMS 0.010~200.000
21 27P2.tmin 0.050~20.000 (s)
25 27P3.U_Set 0~Unn (V)
protection

Date: 2017-12-12
7 Settings

30 27P3.En_Alm 0 or 1
to alarm
IECE, IECST, IECLT,
ANSIM, ANSILTE,
ANSILTV, ANSILT
32 27P3.TMS 0.010~200.000
33 27P3.tmin 0.050~20.000 (s)
7.4.1.9 Negative Sequence Overvoltage Protection (59Q)

Voltage setting for negative sequence overvoltage
1 59Q.U_Set 0~Unn (V)
protection.
Time delay of negative sequence overvoltage
2 59Q.t_Op 0.000~30.000 (s)
protection.
3 59Q.En Enable negative sequence overvoltage protection 0 or 1
7.4.1.10 Negative-sequence Overcurrent Protection Settings (50/51Q)

Current setting for stage 1 of negative-sequence
1 50/51Q1.I2_Set (0.050~30.000)×In (A)
Ratio coefficient (I2/I1) for stage 1 of
2 50/51Q1.I2/I1_Set 0.00~1.00
negative-sequence overcurrent protection
Time delay for stage 1 of negative-sequence
3 50/51Q1.t_Op 0.000~20.000 (s)
Enable stage 1 of negative-sequence overcurrent
4 50/51Q1.En 0 or 1
protection
5 50/51Q1.En_BlkAR 0 or 1
negative-sequence overcurrent protection operates

Date: 2017-12-12
7 Settings
Non_Directional
Direction option for stage 1 of negative-sequence
6 50/51Q1.Opt_Dir Forward
Reverse
Enable blocking for stage 1 of negative-sequence
overcurrent protection under abnormal conditions
8 50/51Q1.En_CTS_Blk 0 or 1
overcurrent protection under CT failure conditions
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for stage 1 of ANSIE
9 50/51Q1.Opt_Curve
negative-sequence overcurrent protection ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
10 50/51Q1.TMS 0.010~200.000
Minimum operating time for stage 1 of inverse-time
11 50/51Q1.tmin 0.050~20.000 (s)
Constant “α” for stage 1 of customized inverse-time
12 50/51Q1.Alpha characteristic negative-sequence overcurrent 0.010~5.000
protection
Constant “C” for stage 1 of customized inverse-time
13 50/51Q1.C characteristic negative-sequence overcurrent 0.000~20.000
protection
Constant “K” for stage 1 of customized inverse-time
14 50/51Q1.K characteristic negative-sequence overcurrent 0.050~20.000
protection
15 50/51Q2.I2_Set (0.050~30.000)×In (A)
16 50/51Q2.I2/I1_Set 0.00~1.00
17 50/51Q2.t_Op 0.000~20.000 (s)
18 50/51Q2.En 0 or 1
protection
19 50/51Q2.En_BlkAR 0 or 1

Date: 2017-12-12
7 Settings
Non_Directional
Reverse
22 50/51Q2.En_CTS_Blk 0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
23 50/51Q2.Opt_Curve ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
24 50/51Q2.TMS 0.010~200.000
25 50/51Q2.tmin 0.050~20.000 (s)
26 50/51Q3.I2_Set (0.050~30.000)×In (A)
27 50/51Q3.I2/I1_Set 0.00~1.00
28 50/51Q3.t_Op 0.000~20.000 (s)
29 50/51Q3.En 0 or 1
protection
30 50/51Q3.En_BlkAR 0 or 1
Non_Directional
Reverse
33 50/51Q3.En_CTS_Blk 0 or 1

Date: 2017-12-12
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
35 50/51Q3.TMS 0.010~200.000
36 50/51Q3.tmin 0.050~20.000 (s)
37 50/51Q4.I2_Set (0.050~30.000)×In (A)
38 50/51Q4.I2/I1_Set 0.00~1.00
39 50/51Q4.t_Op 0.000~20.000 (s)
40 50/51Q4.En 0 or 1
protection
41 50/51Q4.En_Trp 0 or 1
protection operate to trip or alarm.
42 50/51Q4.En_BlkAR 0 or 1
Non_Directional
Reverse
45 50/51Q4.En_CTS_Blk 0 or 1

Date: 2017-12-12
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
47 50/51Q4.TMS 0.010~200.000
48 50/51Q4.tmin 0.050~20.000 (s)
7.4.1.11 Residual Overvoltage Protection Settings (59G)

Voltage setting of stage 1 of residual overvoltage
1 59G1.3U0_Set 0~Unn (V)
protection.
Time delay of stage 1 of residual overvoltage
2 59G1.t_Op 0.000~3600.000 (s)
protection.
3 59G1.En Enable stage 1 of residual overvoltage protection. 0 or 1
4 59G2.3U0_Set 0.000~Unn (V)
protection.
5 59G2.t_Op 0.000~3600.000 (s)
protection.

Date: 2017-12-12
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for stage 2 of residual ANSIE
7 59G2.Opt_Curve
overvoltage protection ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 2 of residual
8 59G2.TMS 0.010~200.000
Minimum operating time for stage 2 of residual
9 59G2.tmin 0.050~20.000 (s)
10 59G2.Alpha 0.010~5.000
characteristic residual overvoltage protection
11 59G2.C 0.000~20.000
12 59G2.K 0.050~20.000
13 59G3.3U0_Set 0~Unn (V)
protection.
14 59G3.t_Op 0.000~3600.000 (s)
protection.
Enable stage 3 of residual overvoltage protection for
16 59G3.En_Trp 0 or 1
trip purpose.

Date: 2017-12-12
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
Option of characteristic curve for stage 3 of residual ANSIE
17 59G3.Opt_Curve
overvoltage protection ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 3 of residual
18 59G3.TMS 0.010~200.00
Minimum operating time for stage 3 of residual
19 59G3.tmin 0.050~20.000 (s)
20 59G3.Alpha 0.010~5.000
21 59G3.C 0.000~20.000
22 59G3.K 0.050~20.000
7.4.1.12 Frequency Protection Settings (81U and 81O)

Frequency pickup setting for underfrequency
1 81U.f_Pkp 45.000~60.000 (Hz)
protection
Rate of frequency change for blocking
2 81U.df/dt_Blk 0.200~20.000 (Hz/s)
Frequency setting for stage 1 of underfrequency
3 81U.UF1.f_Set 45.000~60.000 (Hz)
protection
4 81U.UF1.t_Op Time delay for stage 1 of underfrequency protection 0.000~30.000 (s)
5 81U.UF1.En Enable stage 1 of underfrequency protection 0 or 1
Enable rate of frequency change to block stage 1 of
6 81U.UF1.En_df/dt_Blk 0 or 1
7 81U.UF2.f_Set 45.000~60.000 (Hz)
protection

Date: 2017-12-12
7 Settings

11 81U.UF3.f_Set 45.000~60.000 (Hz)
protection
15 81U.UF4.f_Set 45.000~60.000 (Hz)
protection
19 81O.f_Pkp Frequency pickup setting for overfrequency protection 50.000~65.000 (Hz)
Frequency setting for stage 1 of overfrequency
20 81O.OF1.f_Set 50.000~65.000 (Hz)
protection
21 81O.OF1.t_Op Time delay for stage 1 of overfrequency protection 0.000~20.000 (s)
22 81O.OF1.En Enable stage 1 of overfrequency protection 0 or 1
23 81O.OF2.f_Set 50.000~65.000 (Hz)
protection
26 81O.OF3.f_Set 50.000~65.000 (Hz)
protection
29 81O.OF4.f_Set 50.000~65.000 (Hz)
protection
7.4.1.13 Breaker Failure Protection Settings (50BF)

1 50BF.I_Set Current setting of phase current criterion for BFP (0.050~30.000 )×In (A)
Current setting of zero-sequence current criterion
2 50BF.3I0_Set (0.050~30.000 )×In (A)
for BFP
Current setting of negative-sequence current
3 50BF.I2_Set (0.050~30.000 )×In (A)
criterion for BFP
4 50BF.t_ReTrp Time delay of re-tripping for BFP 0.000~10.000 (s)
5 50BF.t1_Op Time delay of stage 1 for BFP 0.000~10.000 (s)
6 50BF.t2_Op Time delay of stage 2 for BFP 0.000~10.000 (s)
7 50BF.En Enable breaker failure protection 0 or 1

8 50BF.En_ReTrp Enable re-trip function for BFP 0 or 1

Date: 2017-12-12
7 Settings
Enable zero-sequence current criterion for BFP

9 50BF.En_3I0_1P 0 or 1
initiated by single-phase tripping contact
Enable zero-sequence current criterion for BFP
10 50BF.En_3I0_3P 0 or 1
initiated by three-phase tripping contact
Enable negative-sequence current criterion for BFP
11 50BF.En_I2_3P 0 or 1
initiated by three-phase tripping contact
Enable breaker failure protection can be initiated by
12 50BF.En_CB_Ctrl 0 or 1
normally closed contact of circuit breaker
7.4.1.14 Pole Discrepancy Protection Settings (62PD)

Current setting of residual current criterion for pole
1 62PD.3I0_Set (0.050~30.000 )×In (A)
Current setting of negative-sequence current
2 62PD.I2_Set (0.050~30.000 )×In (A)
criterion for pole discrepancy protection
3 62PD.t_Op Time delay of pole discrepancy protection 0.000~600.000 (s)
4 62PD.En Enable pole discrepancy protection 0 or 1

Enable residual current criterion and
5 62PD.En_3I0/I2_Ctrl negative-sequence current criterion for pole 0 or 1
7.4.1.15 Synchrocheck Settings (25)

Va; Vb; Vc; Vab;
1 25.Opt_Source_UL1 Voltage selecting mode for UL1.
Vbc; Vca
Va; Vb; Vc; Vab;
2 25.Opt_Source_UB1 Voltage selecting mode for UB1.
Vbc; Vca
Va; Vb; Vc; Vab;
3 25.Opt_Source_UL2 Voltage selecting mode for UL2.
Vbc; Vca
Va; Vb; Vc; Vab;
4 25.Opt_Source_UB2 Voltage selecting mode for UB2.
Vbc; Vca
NoVoltSel;
DblBusOneCB;
5 CBConfigMode Configuration mode of breaker.
3/2BusCB;
3/2TieCB
6 25.U_Dd Voltage threshold of dead check 0.05Un~0.8Un (V)
7 25.U_Lv Voltage threshold of live check 0.5Un~Un (V)
8 25.K_Usyn Compensation coefficient for synchronism voltage 0.20~5.00
9 25.phi_Diff Phase difference limit of synchronism check for AR 0~ 89 (Deg)
Compensation for phase difference between two

10 25.phi_Comp 0~359 (Deg)
synchronous voltages
11 25.f_Diff Frequency difference limit of synchronism check for AR 0.02~1.00 (Hz)
12 25.U_Diff Voltage difference limit of synchronism check for AR 0.02Un~0.8Un (V)

Date: 2017-12-12
7 Settings
13 25.t_DdChk Time delay to confirm dead check condition 0.010~25.000 (s)
14 25.t_SynChk Time delay to confirm synchronism check condition 0.010~25.000 (s)
15 25.SetOpt Synchrocheck mode selection 0 or 1

16 25.En_fDiffChk Enable frequency difference check 0 or 1
17 25.En_SynChk Enable synchronism check 0 or 1
18 25.En_DdL_DdB Enable dead line and dead bus (DLDB) check 0 or 1
19 25.En_DdL_LvB Enable dead line and live bus (DLLB) check 0 or 1
20 25.En_LvL_DdB Enable live line and dead bus (LLDB) check 0 or 1
21 25.En_NoChk Enable AR without any check 0 or 1
22 25.En_3PLvChk Enabling/disabling live three-phase check of line 0 or 1
7.4.1.16 Auto-reclosing Settings (79)

1 79.N_Rcls Maximum number of reclosing attempts 1~4
2 79.t_Dd_1PS1 Dead time of first shot 1-pole reclosing 0.000~600.000 (s)
3 79.t_Dd_3PS1 Dead time of first shot 3-pole reclosing 0.000~600.000 (s)
4 79.t_Dd_3PS2 Dead time of second shot 3-pole reclosing 0.000~600.000 (s)
5 79.t_Dd_3PS3 Dead time of third shot 3-pole reclosing 0.000~600.000 (s)
6 79.t_Dd_3PS4 Dead time of fourth shot 3-pole reclosing 0.000~600.000 (s)
Time delay of circuit breaker in closed position before
7 79.t_CBClsd 0.000~600.000 (s)
reclosing
Time delay to wait for CB healthy, and begin to timing
when the input signal [79.CB_Healthy] is de-energized
8 79.t_CBReady 0.000~600.000 (s)
and if it is not energized within this time delay, AR will
be blocked.
9 79.t_Wait_Chk Maximum wait time for synchronism check 0.000~600.000 (s)
Time delay allow for CB status change to conform
10 79.t_Fail 0.000~600.000 (s)
reclosing successful
11 79.t_PW_AR Pulse width of AR closing signal 0.000~600.000 (s)
12 79.t_Reclaim Reclaim time of AR 0.000~600.000 (s)
Time delay of excessive trip signal to block
13 79.t_PersistTrp 0.000~600.000 (s)
auto-reclosing
Drop-off time delay of blocking AR, when blocking
14 79.t_DDO_BlkAR signal for AR disappears, AR blocking condition drops 0.000~600.000 (s)
off after this time delay
15 79.t_AddDly Additional time delay for auto-reclosing 0.000~600.000 (s)
Maximum wait time for reclosing permissive signal from
16 79.t_WaitMaster 0.000~600.000 (s)
master AR

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7 Settings
Time delay of discriminating another fault, and begin to

times after 1-pole AR initiated, 3-pole AR will be
17 79.t_SecFault 0.000~600.000 (s)
initiated if another fault happens during this time delay.
AR will be blocked if another fault happens after that.
Enable auto-reclosing blocked when a fault occurs
18 79.En_PDF_Blk 0 or 1
under pole disagreement condition
Enable auto-reclosing with an additional dead time
19 79.En_AddDly 0 or 1
delay
20 79.En_CutPulse Enable adjust the length of reclosing pulse 0 or 1
Enable confirm whether AR is successful by checking
21 79.En_FailCheck 0 or 1
CB state
22 79.En Enable auto-reclosing 0 or 1
Enable AR by external input signal besides logic setting
23 79.En_ExtCtrl 0 or 1
[79.En]
24 79.En_CBInit Enable AR be initiated by open state of circuit breaker 0 or 1
25 79.Opt_Priority Option of AR priority None, High or Low
26 79.SetOpt Control option of AR mode 0 or 1
27 79.En_1PAR Enable 1-pole AR mode 0 or 1
28 79.En_3PAR Enable 3-pole AR mode 0 or 1
29 79.En_1P/3PAR Enable 1/3-pole AR mode 0 or 1
7.4.1.17 Trip Logic Settings

1 t_Dwell_Trp The dwell time of tripping command 0.000~10.000 (s)
7.4.1.18 VTS Settings

1 VTS.t_DPU Pick-up time delay of VT circuit supervision 0.200~100.000 (s)
2 VTS.t_DDO Drop-off time delay of VT circuit supervision 0.200~100.000 (s)
3 VTS. En_Out_VT VT is not connected to the protection device 0 or 1
If three-phase voltage used for protection measurement
comes from line side (for example, 3/2 breaker), it
4 VTS.En_LineVT 0 or 1
should be set as “1”. If three-phase voltage comes from
busbar side, it should be set as “0”.
5 VTS.En Enable alarm function of VT circuit supervision 0 or 1
7.4.2 Access Path

MainMenuSettingsProt Settings
7.5 Logic Link Settings

The logic link settings (in the submenu “Logic Links”) are used to determine whether the relevant
function of this device is enabled or disabled. If this device supports the logic link function, it will

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7 Settings
have a corresponding submenu in the submenu “Logic Links” for the logic link settings.
Each logic link settings is an “AND” condition of enabling the relevant function with the
corresponding binary input and logic setting. Through SAS or RTU, logic link settings can be set
as “1” or “0”; and it means that the relevant function can be in service or out of service through
remote command. It provides convenience for operation management.

7.5.1.1 GOOSE Link Settings
The GOOSE link settings (in the submenu “GOOSE Links”) are used to determine whether the
relevant GOOSE elements are enabled or disabled. See the GOOSE related instruction manual
for the more information and details.
7.5.1.2 Spare Link Settings
The spare link settings (in the submenu “Function Links”) are used for future application. It can
be defined according to project specification through the PCS-Explorer configuration tool.

1 Link_01 Spare link setting 01 0 or 1
7.5.2 Access Path

MainMenuSettingsLogic Links
7.6 Measurement and Control Settings

7.6.1.1 Synchronism Settings

Va; Vb; Vc; Vab;
1 MCBrd.25.Opt_Source_UL1 Voltage selecting mode for UL1.
Vbc; Vca
Va; Vb; Vc; Vab;
2 MCBrd.25.Opt_Source_UB1 Voltage selecting mode for UB1.
Vbc; Vca
Va; Vb; Vc; Vab;
3 MCBrd.25.Opt_Source_UL2 Voltage selecting mode for UL2.
Vbc; Vca
Va; Vb; Vc; Vab;
4 MCBrd.25.Opt_Source_UB2 Voltage selecting mode for UB2.
Vbc; Vca

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7 Settings
5 MCBrd.25.U_Dd Voltage threshold of dead check 1.000~100.000 (V)

6 MCBrd.25.U_Lv Voltage threshold of live check 1.000~100.000 (V)
Compensation coefficient for synchronism
7 MCBrd.25.K_Usyn 0.20-5.00
voltage
Phase difference limit of synchronism check
8 MCBrd.25.phi_Diff 0.10~ 180.00 (Deg)
for AR
Compensation for phase difference between
9 MCBrd.25.phi_Comp 0~360 (Deg)
two synchronous voltages
Frequency difference limit of synchronism
10 MCBrd.25.f_Diff 0.00~3.00 (Hz)
check for AR
Voltage difference limit of synchronism check
11 MCBrd.25.U_Diff 1.000~100.000 (V)
for AR
Synchrocheck mode selection for manual
12 MCBrd.25.SetOpt 0, 1
closing
13 MCBrd.25.En_SynChk Enable synchronism check 0 or 1
14 MCBrd.25.En_DdL_DdB Enable dead line and dead bus (DLDB) check 0 or 1
15 MCBrd.25.En_DdL_LvB Enable dead line and live bus (DLLB) check 0 or 1
16 MCBrd.25.En_LvL_DdB Enable live line and dead bus (LLDB) check 0 or 1
17 MCBrd.25.En_NoChk Enable AR without any check 0 or 1
Threshold of rate of frequency change
18 MCBrd.25.df/dt between both sides of CB for 0.10~5.00 (Hz/s)
synchronism-check.
Circuit breaker closing time. It is the time from
19 MCBrd.25.t_Close_CB receiving closing command pulse till the CB is 0~1000 (ms)
completely closed.
From receiving a closing command, this device
will continuously check whether between
incoming voltage and reference voltage
involved in synchronism check (or dead check)
20 MCBrd.25.t_Wait_Chk can meet the criteria. If the synchronism check 5.000~30.000 (s)
(or dead check) criteria are not met within the
duration of this time delay, the failure of
synchronism-check (or dead check) will be
confirmed.
Enable alarm function when VT circuit is
21 MCBrd.En_Alm_VTS 0 or 1
abnormal
Enable block synchronism check for manual
22 MCBrd.25.En_VTS_Blk_SynChk 0 or 1
closing when VT circuit is abnormal
Enable block dead check for manual closing
23 MCBrd.25.En_VTS_Blk_DdChk 0 or 1
when VT circuit is abnormal
7.6.1.2 Dual Point Binary Input Settings
Thses settings are applied to configure the status change confirmation time for No.xx double point

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7 Settings
binary inputs. Up to 10 virtual double point binary inputs are provided in this device.
If a double point binary input changes from normal status to invalid status, i.e.: double point error
occurs, [CSWIxx.t_DPU_DPS] will be applied as the debouncing time for No.xx double point
binary input.
These settings are applied to configure the debouncing

1 CSWIxx.t_DPU_DPS time. “DPU” is the abbreviation of “Delay Pick Up”. 0~60000 (ms)
(xx=01, 02….10)
7.6.1.3 Control Settings
No.xx holding time of a normal open contact of remote

1 CSWIxx.t_PW_Opn opening CB, disconnector or for signaling purpose. 0~60000 (ms)
(xx=01, 02….10)
No.xx closing time of a normal open contact of remote

2 CSWIxx.t_PW_Cls closing CB, disconnector or for signaling purpose. 0~60000 (ms)
(xx=01, 02….10)
7.6.1.4 Interlock Settings
Enable No.xx open output of the BO module be controlled

1 CSWIxx.En_Opn_Blk by the interlocking logic 0 or 1
(xx=01, 02….10)
Enable No.xx closing output of the BO module be

2 CSWIxx.En_Cls_Blk controlled by the interlocking logic 0 or 1
(xx=01, 02….10)
7.6.2 Access Path

MainMenu“Settings”“BCU Settings”

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Table of Contents
8.1 Overview .......................................................................................................... 8-1

8.1.1 Keypad Operation ................................................................................................................ 8-2
8.1.2 LED Indications .................................................................................................................... 8-3
8.1.3 Front Communication Port................................................................................................... 8-3
8.1.4 Ethernet Port Setup ............................................................................................................. 8-4
8.2 Menu Tree ........................................................................................................ 8-5

8.2.1 Overview .............................................................................................................................. 8-5
8.2.2 Main Menus ......................................................................................................................... 8-6
8.2.3 Sub Menus ........................................................................................................................... 8-7
8.3 Access Authority Management .................................................................... 8-21

8.3.1 Authority Classification ...................................................................................................... 8-21
8.3.2 Authority Identification........................................................................................................ 8-22
8.4 LCD Display ................................................................................................... 8-24

8.4.1 Overview ............................................................................................................................ 8-24
8.4.2 Function Shortcuts Key...................................................................................................... 8-24
8.4.3 Normal Display .................................................................................................................. 8-27
8.4.4 Display Disturbance Records ............................................................................................ 8-28
8.4.5 Display Supervision Event ................................................................................................. 8-30
8.4.6 Display IO Events .............................................................................................................. 8-31
8.4.7 Display Device Logs .......................................................................................................... 8-32
8.5 Keypad Operation ......................................................................................... 8-33

8.5.1 View Device Measurements .............................................................................................. 8-33
8.5.2 View Device Status ............................................................................................................ 8-33
8.5.3 View Device Records......................................................................................................... 8-33
8.5.4 Print Device Records ......................................................................................................... 8-34

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8.5.5 View Device Setting ........................................................................................................... 8-35
8.5.6 Modify Device Setting ........................................................................................................ 8-35
8.5.7 Copy Device Setting .......................................................................................................... 8-38
8.5.8 Switch Setting Group ......................................................................................................... 8-38
8.5.9 Delete Device Records ...................................................................................................... 8-39
8.5.10 Remote Control via Menu ................................................................................................ 8-40
8.5.11 Remote Control via SLD .................................................................................................. 8-43
8.5.12 Modify Device Clock ........................................................................................................ 8-45
8.5.13 View Module Information ................................................................................................. 8-46
8.5.14 Check Software Version .................................................................................................. 8-46
8.5.15 Communication Test ........................................................................................................ 8-47
8.5.16 Select Language .............................................................................................................. 8-48
List of Figures
Figure 8.1-1 Front panel .............................................................................................................. 8-1
Figure 8.1-2 Keypad buttons ...................................................................................................... 8-2
Figure 8.1-3 LED indications ...................................................................................................... 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel .................................. 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102C ................................................... 8-5
Figure 8.2-1 Menu tree ................................................................................................................ 8-7
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................. 8-4
Table 8.4-1 Tripping report messages ..................................................................................... 8-30
Table 8.4-2 User operating event list ....................................................................................... 8-32
Table 8.5-1 Primary equipment symbols in SLD .................................................................... 8-43

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The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including r.m.s. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad is also described in details.
NOTICE!
About three measurements in menu “Measurements”, please refer to the following

description:
“Measurements1” is use to display measured values from protection calculation DSP

(displayed in secondary value)
“Measurements2” is used to display measured values from fault detector DSP

(displayed in secondary value)
“Measurements3” is used to display measured primary values and other calculated

quantities
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.
1 11
HEALTHY PCS-9 21
2 12
5 BREAKER FAILURE RELAY
ALARM
3 13
4 14
GRP
5 15
6 16 ENT
ESC
7 17
4
8 18
1
9 19
3
10 20
Figure 8.1-1 Front panel
The function of HMI module:

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A 320×240 dot matrix backlight LCD display is visible in dim lighting
1 LCD conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, 2 LEDs are fixed as the signals of “HEALTHY”
2 LED (green) and “ALARM” (yellow), 18 LEDs are configurable with selectable
color among green, yellow and red.
3 Keypad Navigation keypad and command keys for full access to device
4 Communication port A multiplex RJ45 port for local communication with a PC
5 Logo Type and designation and manufacturer of device
8.1.1 Keypad Operation GR

P
ENT
ESC
Figure 8.1-2 Keypad buttons
1. “ESC”:
 Cancel the operation
 Quit the current menu
2. “ENT”:
 Execute the operation
 Confirm the interface
3. “GRP”
 Activate the switching interface of setting group
4. leftward and rightward direction keys (“◄” and “►”):
 Move the cursor horizontally
 Enter the next menu or return to the previous menu
5. upward and downward direction keys (“▲” and “▼”)
 Move the cursor vertically
 Select command menu within the same level of menu
6. plus and minus sign keys (“＋” and “－”)
 Modify the value

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 Modify and display the message number
 Page up/down
8.1.2 LED Indications
HEALTHY
ALARM
Figure 8.1-3 LED indications
A brief explanation has been made as bellow.
LED Display Description

When the equipment is out of service or any hardware error is defected during
Off
HEALTHY self-check.
Steady Green Lit when the equipment is in service and ready for operation.
Off When equipment in normal operating condition.

ALARM
Steady Yellow Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
NOTICE!
“HEALTHY” LED can only be turned on by energizing the device and no abnormality
detected.
“ALARM” LED is turned on when abnormalities of device occurs like above mentioned
and can be turned off after abnormalities are removed except alarm report [CTS.Alm]
which can only be reset only when the failure is removed and the device is rebooted or
re-energized.
Other LED indicators with no labels are configurable and user can configure them to be
lit by signals of operation element, alarm element and binary output contact according
to requirement through PCS-Explorer software, but as drawn in figure, 2 LEDs are fixed
as the signals of “HEALTHY” (green) and “ALARM” (yellow), 18 LEDs are configurable
with selectable color among green, yellow and red.
8.1.3 Front Communication Port

There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.

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P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Terminal Device side Computer side

Core color Function
No. (Left) (Right)
1 Orange & white TX+ of the ethernet port P1-1 P2-1
2 Orange TX- of the ethernet port P1-2 P2-2
3 Green & white RX+ of the ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the ethernet port P1-6 P2-6
7 Blue & white P1-7
The ground connection of the RS-232 port. P3-5
8 Brown P1-8
8.1.4 Ethernet Port Setup

MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, take NR1102C
as an example, as shown in Figure 8.1-5. Its rear view and the definition of terminals.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer)
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”

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The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled. If using
other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must be set as “1”.
NR1102C
ETHERNET
Network A
Network B
SYN+
SYN-
SGND
GND
RTS
TXD
SGND
Figure 8.1-5 Rear view and terminal definition of NR1102C
8.2 Menu Tree

8.2.1 Overview
Press “▲” of any running interface and enter the main menu. Select different submenu by “▲” and
“▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the previous
menu. Press “ESC” back to main menu directly. For sake of entering the command menu again, a
command menu will be recorded in the quick menu after its execution. Five latest command
menus can be recorded in the quick menu. When five command menus are recorded, the latest
command menu will cover the earliest one, adopting the “first in first out” principle. It is arranged
from top to bottom and in accordance with the execution order of command menus.
Press “▲” to enter the main menu with the interface as shown in the following diagram:

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MainMenu
Language
Clock
Quick Menu
For the first powered protective device, there is no record in quick menu. Press “▲” to enter the
main menu with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.
8.2.2 Main Menus

The menu of PCS-921 is organized into main menu and submenus, much like a PC directory
structure. The menu of PCS-921 is divided into 10 sections:

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Main Menu
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
Figure 8.2-1 Menu tree
Under the main interface, press “▲” to enter the main menu, and select submenu by pressing “▲”,
“▼” and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first level menus) under menu tree of the
protection device.
8.2.3 Sub Menus

8.2.3.1 Measurements
Main Menu
Measurements
Measurements1
Measurements2
Measurements3
Metering
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the device’s status. This
menu comprises following submenus. Please refer to Section “Measurement” about the detailed
measured values.

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No. Item Function description
Display measured values from protection calculation DSP (Displayed in

1 Measurements1
secondary value)
Display measured values from fault detector DSP (Displayed in

2 Measurements2
secondary value)
3 Measurements3 Display measured primary values and other calculated quantities
4 Metering Display metering values of active and reactive energy
8.2.3.2 Status
Main Menu
Status
Inputs
Contact Inputs
GOOSE Inputs
Outputs
Contact Outputs
GOOSE Outputs
Interlock Status
Superv State
Prot Superv
FD Superv
GOOSE Superv
SV Superv
BCU Superv
This menu is used to display real time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the device′s status. This menu comprises following
submenus. Please refer to Section “Signal List” about the detailed input and output signals, and
Section “Supervision Alarms” about alarm signals.
1 Inputs Display all input signal states
2 Outputs Display all output signal states

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3 Superv State Display supervision alarm states
The submenu “Inputs” comprises the following command menus.
1 Contact Inputs Display states of binary inputs derived from opto-isolated channels
2 GOOSE Inputs Display states of GOOSE binary inputs.
The submenu “Outputs” comprises the following command menus.
1 Contact Outputs Display states of contact binary outputs
2 GOOSE Outputs Display states of GOOSE binary outputs
3 Interlock Status Display states of interlock result of each remote control.
The submenu “Superv State” comprises the following command menus.
1 Prot Superv Display states of self-supervision signals from protection calculation DSP
2 FD Superv Display states of self-supervision signals from fault detector DSP
3 GOOSE Superv Display states of GOOSE self-supervision signals
4 SV Superv Display states of SV self-supervision signals
5 BCU Superv Display states of measurement and control self-supervision signals
8.2.3.3 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.

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1 Disturb Records Display disturbance records of the device
2 Superv Events Display supervision events of the device
3 IO Events Display binary events of the device
4 Device Logs Display device logs of the device
5 Control Logs Display control logs of the device
6 Clear Records Clear all records.

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8.2.3.4 Settings

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Main Menu
Settings
System Settings
Prot Settings
FD Settings
AuxE Settings
OC Settings
ROC Settings
NegOC Settings
BFP Settings
DeadZone Settings
OV Settings
UV Settings
NegOV Settings
ROV Settings
PD Settings
FreqProt Settings
VTS/CTS Settings
Trip Logic Settings
AR/Syn Settings
Copy Settings
BCU Settings
Syn Settings
BI Settings
Control Settings
Interlock Settings
Logic Links
Function Links
GOOSE Links
SV Links
Spare Links
Device Setup
Device Settings
Comm Settings
Label Settings

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This menu is used to check the device setup, system parameters, protection settings and logic
links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
1 System Settings Check or modify the system parameters
2 Prot Settings Check or modify the protection settings
3 BCU Settings Check or modify the measurement and control settings
Check or modify the logic links settings, including function links, SV links,
4 Logic Links
GOOSE links and spare links
5 Device Setup Check or modify the device setup
The submenu “Prot Settings” includes the following command menus.
1 FD Settings Check or modify fault detector settings
2 AuxE Settings Check or modify auxiliary element settings
3 OC Settings Check or modify phase overcurrent protection settings
4 ROC Settings Check or modify residual overcurrent protection settings
5 NegOC Settings Check or modify negative-sequence overcurrent protection settings
6 BFP Settings Check or modify breaker failure protection settings
7 DeadZone Settings Check or modify dead zone protection settings
8 OV Settings Check or modify overvoltage protection settings
9 UV Settings Check or modify undervoltage protection settings
10 NegOV Settings Check or modify negative-sequence overvoltage protection settings
11 ROV Settings Check or modify residual overvoltage protection settings
12 PD Settings Check or modify pole discrepancy protection settings
13 FreqProt Settings Check or modify frequency protection settings
Check or modify VT circuit supervision and CT circuit supervision

14 VTS/CTS Settings
settings
15 Trip Logic Settings Check or modify trip logic settings
16 AR/Syn Settings Check or modify auto-reclosing and synchronism check settings
17 Copy Settings Copy setting between different setting groups
The submenu “BCU Settings” includes the following command menus.
1 Syn Settings Check or modify manual sysnchronism check settings
2 BI Settings Check or modify binary input settings

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3 Control Settings Check or modify control settings
4 Interlock Settings Check or modify interlock settings
The submenu “Logic Links” comprises the following command menus.
1 Function Links Check or modify function links settings
2 GOOSE Links Check or modify GOOSE links settings
3 SV Links Check or modify SV links settings
4 Spare Links Check or modify spare links settings (used for programmable logic)
The submenu “Device Setup” comprises the following command menus.
1 Device Settings Check or modify the device settings.
2 Comm Settings Check or modify the communication settings.
3 Label Settings Check or modify the label settings of each protection element.

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8.2.3.5 Print
Main Menu
Print
Device Info
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings
Disturb Records
Superv Events
IO Events
Device Status
Waveforms
IEC103 Info
Cancel Print
This menu is used to print device description, settings, all kinds of records, waveforms, information
related with IEC60870-5-103 protocol, channel state and channel statistic.
Print the description information of the device, including software

1 Device Info
version.
Print device setup, system parameters, protection settings and logic

links settings. It can print by different classifications as well as printing all
2 Settings
settings of the device. Besides, it can also print the latest modified
settings.
3 Disturb Records Print the disturbance records
4 Superv Events Print the supervision events
5 IO Events Print the binary events

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Print the current state of the device, including the sampled value of
6 Device Status
voltage and current, the state of binary inputs, setting and so on
7 Waveforms Print the recorded waveforms
Print 103 Protocol information, including function type (FUN),

8 IEC103 Info information serial number (INF), general classification service group
number, and channel number (ACC)
9 Cancel Print Cancel the print command
The submenu “Settings” comprises the following submenus.
1 System Settings Print the system parameters
2 Prot Settings Print the protection settings
3 BCU Settings Print the measurement and control settings
4 Logic Links Print the logic links settings
5 Device Setup Print the settings related to device setup
Print all settings including device setup, system parameters, protection

6 All Settings
settings and logic links settings
7 Latest Chgd Settings Print the setting latest modified
The submenu “Prot Settings” comprises the following command menus.
1 FD Settings Print fault detector element settings
2 AuxE Settings Print auxiliary element settings
3 OC Settings Print phase overcurrent protection settings
4 ROC Settings Print directional earth-fault protection settings
5 NegOC Settings Print negative-sequence overcurrent protection settings
6 BFP Settings Print breaker failure protection settings
7 Deadzone Settings Print dead zone settings
8 OV Settings Print overvoltage protection settings
9 UV Settings Print undervoltage protection settings
10 NegOV Settings Print negative-sequence overvoltage protection settings
11 ROV Settings Print residual overvoltage protection settings
12 PD Settings Print pole discrepancy protection settings
13 FreqProt Settings Print frequency protection settings
14 VTS/CTS Settings Print VT circuit supervision and CT circuit supervision settings
15 Trip Logic Settings Print trippling logic settings
16 AR/Syn Settings Print synchronism check and auto-reclosing settings

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17 All Settings Print all settings included in “Prot Settings” submenu
The submenu “BCU Settings” includes the following command menus.
1 Syn Settings Print manual sysnchronism check settings
2 BI Settings Print binary input settings
3 Control Settings Print control settings
4 Interlock Settings Print interlock settings
5 All Settings Print all settings included in “BCU Settings” submenu
The submenu “Logic Links” comprises the following command menus.
1 Function Links Print function links settings
2 GOOSE Links Print GOOSE links settings
3 SV Links Print SV links settings
4 Spare Links Print spare links settings (used for programmable logic)
5 All Settings Print all settings included in “Logic Links” submenu
The submenu “Device Setup” comprises the following command menus.
1 Device Settings Print the device settings.
2 Comm Settings Print the communication settings.
3 Label Settings Print the label settings of each protection element.
4 All Settings Print all settings included in “Device Setup” submenu
8.2.3.6 Local Cmd
Main Menu
Local Cmd
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear AR Counter
Clear Energy Counter

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This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the resetting function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE SV AR and energy.
1 Reset Target Reset the local signal, indicator LED, LCD display and so on
2 Trig Oscillograph Trigger waveform recording
3 Control Manually operating to trip, close output or for signaling purpose
4 Download Send out the request of downloading program
5 Clear Counter Clear GOOSE and SV statistic data
6 Clear AR Counter Clear AR statistic data
Clear all energy metering values (i.e. PHr+_Pri, PHr-_Pri, Qr+_Pri,

7 Clear Energy Counter
QHr-_Pri)
8.2.3.7 Information
Main Menu
Information
Version Info
Board Info
MOT Info
In this menu, the LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information and MOT information can also be viewed.
This menu comprises the following command menus.
Display software information of DSP module, MON module and HMI module,
1 Version Info which consists of version, creating time of software, CRC codes and
management sequence number.
2 Board Info Monitor the current working state of each intelligent module.
3 MOT Info Display ordering code

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8.2.3.8 Test
Main Menu
Test
GOOSE Comm Counter
SV Comm Counter
AR Counter
Device Test
Disturb Events
Superv Events
IO Events
Internal Signal
HMI Setup
Contrast
BacklitDur
LgtIntnsty
SupervLCD
SupervLED
NetPortBond Info
This menu is mainly used for developers to debug the program and for engineers to maintain the
protection device. It can be used to fulfill the communication test function. It is also used to
generate all kinds of reports or events to transmit to the SAS without any external input, so as to
debug the communication on site. Besides, it can also display statistic information about GOOSE
SV and AR.
1 GOOSE Comm Counter Check communication statistics data of GOOSE
2 SV Comm Counter Check communication statistics data of SV (Sampled Values)
3 AR Counter Check AR counters
Automatically generate all kinds of reports or events to transmit to SCADA,

including disturbance records, self-supervision events and binary events.
4 Device Test
It can realize the report uploading by different classification, as well as the
uploading of all kinds of reports

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5 Internal Signal This submenu is only reserved for the manufacturer
6 HMI Setup Configure LCD display and check LCD display and LED indicators
7 NetPortBond Info Check link status of current working port and bonding ports
The submenu “Device Test” comprises the following submenus.
View the relevant information about disturbance records (only used for
1 Disturb Events
debugging persons)
View the relevant information about supervision events (only used for
2 Superv Events
debugging persons)
View the relevant information about binary events (only used for debugging
3 IO Events
persons)
Users can respectively execute the test automatically or manually by selecting commands “All
Test” or “Select Test”.
The submenu “Disturb Events” comprises the following command menus.
1 All Test Ordinal test of all protection elements
2 Select Test Selective test of corresponding classification
The submenu “Superv Events” comprises the following command menus.
1 All Test Ordinal test of all self-supervisions
The submenu “IO Events” comprises the following command menus.
1 All Test Ordinal test of change of all binary inputs
The submenu “HMI Setup” comprises the following submenus.
1 Contrast To adjust the contrast of LCD display
2 BacklitDur To adjust the duration of LCD backlight
3 Lgtlntnsty To adjust the brightness of LCD display
4 SupervLCD To find out dead pixel of LCD display
5 SupervLED To find out broken LED indicator 03~20

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8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss by default. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.
8.3 Access Authority Management

In order to conveniently manage access authority, the device support setup up to 40 users and
allow each user to own different password (user password can support 8 characters at most and
must include one lowercase letter, one capital letter and one number at least) and access authority
(such as modify settings, view records, remote control)
According to different access authority, the corresponding operations to the device by LCD panel
can be allowed to perform. For the operation that requires authorization, the corresponding user
logs in and the correct password must be input after the operation can be performed.
8.3.1 Authority Classification

The devie provide four kinds of authorities: View, Control, Setting, Project. The default
configuration of the device is no multi-users. Each item of different authority class can be enabled
or disabled independently, and the operation without access authority can be performed directly
no password provided. The valid time of the password can be set, and the password need not be
input again within the valid time ,which ensure both security and convenience.
Taking “User1” as an example, four kinds of authorities: View, Control, Setting, Project are shown
as below.

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8.3.2 Authority Identification

The operation is as follows:
1. Press the “▲” to enter the main menu, the following interface will be shown when performing
an operation. (Multi-users have been configured in advance)
2. Press the “◄” or “►” to select username, and press the “ESC” to exit this menu
Username User1
Password
3. Press the “ENT” or “▼” to move, and the following interface will be shown after the username
is confirmed.

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Username User1
Password ******
0 1 2 3 4 5 6 7 8 9 [OK]
4. Press the “◄” or “►” to select number or letter, and press “ENT” to ensure selected character.
5. Press the “▲” or “▼” to page up/down to select previous group or next group characters.
6. Press the “GRP” to switch uppercase or lowercase to be choosen characters.
7. When the password reaches to 8 bits, the device will verify whether the username and
password are correctly. If the password is shorter than 8 bits, select and press “OK” to begin
to verify whether the username and password are correctly.
8. Press the “ESC” to cancel entered character during entering password, and the password will
be cleared if the password check fails. When the password is cleared, press the “ESC” to
select the username again.
9. The device provides the function of password memory, the following interface will be shown if
the valid time of the password is set and last entered password is no timeout.
Username User1
Password *******
10. Press the “ENT” to verify the password, press the “◄” or “►” to switch the username and the

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password will be cleared, and press the “ESC” to exit the interface.
11. If the password is correct and the user owns the authority of the operation performed, the
operation will be performed.
If the password is incorrect, the device will issue an alarm signal “Password Error”. If the password
is correct but the user has no the authority of the operation performed, the device will issue an
alarm signal “Unauthorized”. If the password is incorrect or the user has no the authority of the
operation performed more than three times, the device will issue an alarm signal “PWD Error or
Unauthorized, Screen Locked” and the device will return to main interface after the screen is
locked for 1 minutes, which will be recorded in device log.
8.4 LCD Display

8.4.1 Overview
There are some kinds of LCD display, SLD (single line diagram) display, disturbance records,
supervison events, IO events, control logs and device logs. Disturbance records and supervison
events will not disappear until them are acknowledged by pressing the “RESET” button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). If any event is detected, the
corresponding event display will pop up automatically, and user can keep pressing “ENT” and then
press “ESC” to switch between normal display and event display. IO events will be displayed for 5s
and then it will return to the previous display interface automatically. Device logs will not pop up
and can only be viewed by navigating the corresponding menu.
8.4.2 Function Shortcuts Key

The device provide some function shortcuts key, which can be configured by PCS-Explorer and be
fulfilled by combination key of devices' keypad, to execute some operation quickly.
8.4.2.1 Shortcuts Key Configuration
1. Right-click the menu “LCD Graph”, and select the menu item “Edit Shortcut Key” to display
the configuration interface of function key shortcuts as shown below.
2. In configuration interface, double-click the table item in the list of “Extend Command” to select
LCD extend command of dropdown list corresponding with keypads in front panel as shown

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below. Select the first blank item in dropdown list to cancel the setup.
3. Double-click the table item in the list of “Attribute” to edit the attribute of keypad in front panel
as shown below. When the attribute is set as “1”, the corresponding operation can not excute
unless input correct password. When the attribute is set as “0” or blank, password is not
required. After finishing configuration, click the button “OK”.
4. The name description of extend command can be modified in signal setup interface, the
operation “Refresh” in the interface of “Source” must be excute at first before configuring
function shortcuts key or generating drive file package.

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5. Right-click device node and execute the menu “Compress Driver File” to generate drive file
package of the device. The file “LCDConfig.txt” in drive file package of the device records
related contents about shortcuts key. If shortcuts keys are not required, set “Extend
Command” corresponding with function shortcuts key as blank, and generate drive file
package of the device again.
In general, the function of “GRP” is switch setting group, however, the original function of “GRP” is
blocked when configuring function shortcuts key. (the setting group can be switched by shortcuts
key, binary input or modifying the setting) Under main interface, press “GRP” to display the
interface of function shortcuts key and press “ESC” to return to main interface.

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Shortcut keys
[ ] LCD.ExtCmd04
[ ] LCD.ExtCmd05
[ ] LCD.ExtCmd06
[ ] LCD.ExtCmd07
[ + ] LCD.ExtCmd08
[ - ] LCD.ExtCmd09
[ ENT ] LCD.ExtCmd10
The device support 10 extended command, Extended_Command01~Extended_Command10, and

the name can be modified by PCS-Explorer. The first three extend command is fixed in program,
so only Extended_Command04~Extended_Command10 are configurable, and configured as any
of seven function shortcuts key (“▲”, “▼”, “◄”, “►”, “＋”, “－” and “ENT”).
Password:
000
Under the interface of function shortcuts key, press a shortcuts key to excute corresponding
operation. If the attribute of the extend command is set as “1”, the corresponding operation can not
excute unless input correct password. The extend command excuted by shortcuts key outputs a
pulse signal with 500ms, and for the operation requiring latching signal, the device provides
“T_FF” and “RS_FF” to fulfill the application, which can be configured by PCS-Explorer.
8.4.3 Normal Display

After the device is powered and entered into the initiating interface, it takes tens of seconds to

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complete the initialization of the device. During the initialization of the device, the “HEALTHY”
indicator lamp of the device goes out.
The device can display single line diagram (SLD) and primary operation information, it can support
wiring configuration function. LCD configuration file can be downloaded via the network. Remote
control operation through single line diagram is also supported.
Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.
S 2010-06-08 10:10:00
Ia 0.00A
Ib 0.00A
Ic 0.00A
3I0 0.00A
Ua 0.02V
Ub 0.00V
Uc 0.00V
3U0 0.02V
U_Syn 0.00V
f 50.00Hz
Addr 24343 Group 01
The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current can’t be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is “xxx.xxx.a.b”, the displayed address equals to (a×256+b). For

example, If IP address of Ethernet A is “198.087.095.023”, the displayed address will be “95×
256+23=24343”.
If the device has detected any abnormal state, it′ll display the self-check alarm information.
“S” indicates that device clock is synchronized. If “S” disappears, it means that device clock is not
synchronized.
8.4.4 Display Disturbance Records

This device can store up to 32 groups of disturbance records with fault waveform. Each group
consists of disturbance records of operation elements and corresponding fault detector elements.

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Up to 1024 disturbance records can be stored in this device. If there is protection element
operation, LCD will automatically display the latest group of disturbance records, and two kinds of
LCD display interfaces will be available depending on whether there are supervision events or not.
For the situation that the disturbance records and the supervision events coexist, the upper half
part is the disturbance record, and the lower half part is the supervision event. The following items
are listed in the upper half part: record No., record name, generation time of the disturbance
record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
If there is no supervision event, disturbance records will be displayed as shown in the following
figure.
NO.001 2013-01-15 13:22:23:669 Disturb
0000ms FD.DPFC.Pkp
0024ms A 50/51P.Op
If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.

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NO.001 2013-01-15 13:22:23:669 Disturb
0000ms FD.DPFC.Pkp
0024ms A 50/51P.Op
Superv Events
Alm_Device
NO.001 shows the SOE No. of the disturbance record.
2013-01-15 13:22:23:669 shows the time of the disturbance record, the format is
“yyyy-mm-dd hh:mm:ss:fff”.
Disturb shows the title of the disturbance record.
0000ms FD.DPFC.Pkp shows fault detector element and its operation time (set as
“0000ms” fixedly).
0024ms A 50/51P.Op shows operation element and its relative operation time (with
reference to the corresponding fault detector element).
All the protection elements have been listed in Chapter “Operation Theory”, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.4-1 Tripping report messages
No. Message Description

1 TrigDFR_Man Oscillography function is triggered manually.
2 TrigDFR_Rmt Oscillography function is triggered remotely.
Oscillography function is triggered by binary input [BI_TrigDFR]. The
3 TrigDFR_BI binary input [BI_TrigDFR] is configurable, and it can be designated to
internal signal or external input.
8.4.5 Display Supervision Event

This device can store 1024 pieces of supervision events. During the running of the device, the
supervision event of hardware self-check errors or system running abnormity will be displayed
immediately.

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S Superv Events
Alm_Device
Alm_Version
S indicates that device clock is synchronized. If “S” disappears, it

means that device clock is not synchronized.
Superv Events shows the title of the supervision events.
Alm_Device shows the contents of supervision events.
Alm_Version
8.4.6 Display IO Events

This device can store 1024 pieces of binary events. During the running of the device, the binary
input will be displayed once its state has changed, i.e. from “0” to “1” or from “1” to “0”.
NO.001 2013-01-15 13:31:23:669 IO Chg
BI_Maintenance 0 1

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NO.001 shows the No. of the binary event.
2013-01-15 13:31:23:669 shows date and time when the report occurred, the format is
“yyyy-mm-dd hh:mm:ss:fff”.
IO Chg shows the title of the binary event.
BI_Maintenance 0→1 shows the state change of binary input, including binary input
name, original state and final state.
8.4.7 Display Device Logs

This device can store 1024 pieces of device logs. Please refer to Section “8.5.3” for LCD operation
4. Device Logs NO.4

2008-11-28 10:18:47:569ms
Reboot
Device Logs NO. 4 shows the title and the number of the device log
2008-11-28 10:18:47:569 shows date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Reboot shows the manipulation content of the device log
User operating information listed below may be displayed.
Table 8.4-2 User operating event list
No. Message Description

1 Reboot The device has been reboot.
2 Settings_Chg The device′s settings have been changed.
3 ActiveGrp_Chgd Active setting group has been changed.
4 Report_Cleared All reports have been deleted. (Device logs can not be deleted)
5 Waveform_Cleared All waveforms have been deleted.
6 Process_Exit A process has exited.
7 Counter_Cleared Clear counter
It will be displayed on LCD before disturbance records and supervision events are confirmed. Only

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pressing both “ENT” and “ESC” at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.
8.5 Keypad Operation

8.5.1 View Device Measurements
1. Press the “▲” to enter the main menu;
2. Press the “▲” or “▼” to move the cursor to the “Measurements” menu, and then press the
“ENT” or “►” to enter the menu;
3. Press the “▲” or “▼” to move the cursor to any command menu, and then press the “ENT” to
enter the menu;
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one display
screen, one screen can display 14 lines of information at most);
5. Press the “◄” or “►” to select pervious or next command menu;
6. Press the “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu);
8.5.2 View Device Status

1. Press the key “▲” to enter the main menu.
2. Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the “ENT”
or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press the
key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one display
screen, one screen can display 14 lines of information at most).
5. Press the key “◄” or “►” to select pervious or next command menu.
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
8.5.3 View Device Records

2. Press the “▲” or “▼” to move the cursor to the “Records” menu, and then press the “ENT” or
“►” to enter the menu;
enter the menu;

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4. Press the “▲” or “▼” to page up/down;
5. Press the “＋” or “－” to select pervious or next record;
7. Press the “ENT” or “ESC” to exit this menu (returning to the “Records” menu);
8.5.4 Print Device Records

2. Press the “▲” or “▼” to move the cursor to the “Print” menu, and then press the “ENT” or “►”
to enter the menu;
enter the menu;
Selecting the “Disturb Records”, and then press the “＋” or “－” to select pervious or next
record. After pressing the key “ENT”, the LCD will display “Start Printing... ”, and then
automatically exit this menu (returning to the menu “Print”). If the printer doesn’t complete its
current print task and re-start it for printing, and the LCD will display “Printer Busy…”. Press
the key “ESC” to exit this menu (returning to the menu “Print”).
Selecting the command menu “Superv Events” or “IO Events”, and then press the key “▲” or
“▼” to move the cursor. Press the “＋” or “－” to select the starting and ending numbers of
printing message. After pressing the key “ENT”, the LCD will display “Start Printing…”, and
then automatically exit this menu (returning to the menu “Print”). Press the key “ESC” to exit
this menu (returning to the menu “Print”).
4. If selecting the command menu “Device Info”, “Device Status“ or “IEC103_Info”, press the
key “ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5. If selecting the “Settings”, press the key “ENT” or “►” to enter the next level of menu.
6. After entering the submenu “Settings”, press the key “▲” or “▼” to move the cursor, and then
press the key “ENT” to print the corresponding default value. If selecting any item to printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu (returning
to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the menu
“Settings”).
7. After entering the submenu “Waveforms”, press the “＋” or “－” to select the waveform item
to be printed and press ”ENT” to enter. If there is no any waveform data, the LCD will display
“No Waveform Data!” (Before executing the command menu “Waveforms”, it is necessary to
execute the command menu “Trig Oscillograph” in the menu “Local Cmd”, otherwise the
LCD will display “No Waveform Data!”). With waveform data existing:

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Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”, the LCD
will display “Start Printing…”, and then automatically exit this menu (returning to the menu
“Waveforms”). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display “Printer Busy…”. Press the key “ESC” to exit this menu (returning to the menu
“Waveforms”).
8.5.5 View Device Setting

2. Press the “▲” or “▼” to move the cursor to the “Settings” menu, and then press the “ENT” or
enter the menu;
4. Press the “▲” or “▼” to move the cursor;
5. Press the “+” or “-” to page up/down;
7. Press the “ESC” to exit this menu (returning to the menu “Settings”).
NOTICE!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side
of the LCD to indicate the quantity of all displayed information of the command menu
and the relative location of information where the current cursor points at.
8.5.6 Modify Device Setting

enter the menu;
4. Press the “▲” or “▼” to move the cursor;
5. Press the “+” or “-” to page up/down;
7. Press the “ESC” to exit this menu (returning to the menu “Settings” );
8. If selecting the command menu “System Settings”, move the cursor to the setting item to be
modified, and then press the “ENT”;

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Press the “＋” or “－” to modify the value (if the modified value is of multi-bit, press the “◄” or “►”
to move the cursor to the digit bit, and then press the “＋” or “－” to modify the value), press the
“ESC” to cancel the modification and return to the displayed interface of the command menu
“System Settings”. Press the “ENT” to automatically exit this menu (returning to the displayed
interface of the command menu “System Settings”).
Move the cursor to continue modifying other setting items. After all setting values are modified,
press the “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”. Directly press the “ESC” or
press the “◄” or “►” to move the cursor. Select the “Cancel”, and then press the “ENT” to
automatically exit this menu (returning to the displayed interface of the command menu “System
Settings”).
Press the “◄” or “►” to move the cursor. Select “No” and press the “ENT”, all modified setting item
will restore to its original value, exit this menu (returning to the menu “Settings”).
Press the “◄” or “►” to move the cursor to select “Yes”, and then press the “ENT”, the LCD will
display password input interface.
Please Input Password:
____
Input a 4-bit password (“＋”, “◄”, “▲” and “－”). If the password is incorrect, continue inputting it,
and then press the “ESC” to exit the password input interface and return to the displayed interface
of the command menu “System Settings”. If the password is correct, LCD will display “Save
Setting Now…”, and then exit this menu (returning to the displayed interface of the command
menu “System Settings”), with all modified setting items as modified values.
NOTICE!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9. If selecting the submenu “Prot Settings”, and press “ENT” to enter. After selecting different
command menu, the LCD will display the following interface: (take “FD Settings” as an
example)

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FD Settings
Please Select Group for Config
Active Group : 01
Selected Group : 02
Press the “＋” or “－” to modify the value, and then press the “ENT” to enter it. Move the cursor to
the setting item to be modified, press the “ENT” to enter.
Take the setting [FD.DPFC.I_Set] as an example is selected to modify, then press the “ENT” to
enter and the LCD will display the following interface. is shown the “＋” or “－” to modify the value
and then press the “ENT” to confirm.
FD.DPFC.I_Set
Current Value 0.200
Modified Value 0.202
Min Value 0.050
Max Value 30.000
NOTICE!
After modifying protection settings in current active setting group or system parameters
of the device, the “HEALTHY” LED indicator the device will be lit off, and the MON
module will check the new settings. If the abnormality is detected during the setting
check, corresponding alarm signals will be issued. Moreover, if the critical error is
detected, the device will be blocked.

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8.5.7 Copy Device Setting

3. Press the “▲” or “▼” to move the cursor to the command menu “Copy Settings”, and then
press the “ENT” to enter the menu.
Copy Settings
Active Group: 01
Copy To Group: 02
Press the “＋” or “－” to modify the value. Press the “ESC”, and return to the menu “Settings”.
Press the “ENT”, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the “ESC” to exit the password input interface and return to the menu
“Settings”. If the password is correct, the LCD will display “Settings Copied!”, and exit this menu
(returning to the menu “Settings”).
8.5.8 Switch Setting Group

1. Exit the main menu;
2. Press the “GRP”

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Change Active Group
Active Group: 01
Change To Group: 02
Press the “＋” or “－” to modify the value, and then press the “ESC” to exit this menu (returning to
the main menu). After pressing the “ENT”, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the “ESC” to exit the password input
interface and return to its original state. If the password is correct, the “HEALTHY” indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesn’t pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.
8.5.9 Delete Device Records

1. Exit the main menu;
2. Press the “＋”, “－”, “＋”, “－” and “ENT”; Press the “ESC” to exit this menu (returning to the
original state). Press the “ENT” to carry out the deletion.
Press <ENT> To Clear

Press <ESC> To Exit

Date: 2017-06-15
NOTICE!
The operation of deleting device message will delete all messages saved by the
protection device, including disturbance records, supervision events, binary events, but
not including device logs. Furthermore, the message is IRRECOVERABLE after
deletion, so the application of the function shall be cautious.
8.5.10 Remote Control via Menu

Control operation method is introduced as below:
2. Press the key “▲” or “▼” to move the cursor to the command menu “Local Cmd”, and
then press the key “ENT” to enter submenus. Press the key “▲” or “▼” to move the
cursor to the command menu “Control”, and then press the key “ENT” to enter and the
following display will be shown on LCD.
Password:
___
Input a 3-bit password (“111”). If the password is incorrect, continue inputting it, and then press the
“ESC” to exit the password input interface and return to the displayed interface of the command
menu “Control”. If the password is correct, it will go to the following step.
3. Press the key “▲” or “▼” to move the cursor to the control object and press the key
“ENT” to select control object.

Date: 2017-06-15
Control
Step1: select Control Object
1. CSWI01
2. CSWI02
3. CSWI03
4. CSWI04
5. CSWI05
6. CSWI06
7. CSWI07
8. CSWI08
9. CSWI09
10. CSWI10
4. Press the key “◄” or “►” to select control command press the key “ENT” to the next step.
Three control commands are optional:
1) Open(Lower): Remote open
2) Close(Raise): Remote close
3) (Stop): Reserved
CSWI01
Step2: select Control Command
Open(Lower) Close(Raise) (Stop)
NoCheck SynchroCheck DeadCheck

LoopCheck EF Line Selection
InterlockChk InterlockNotChk
Select Execute Cancel
Result
5. Press the key “◄” or “►” to select synchronism check mode and press the key “ENT” to
the next step.
Five synchronism check modes are optional:
1) NoCheck: Without any check
2) SynchroCheck: Synchronism-check mode

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3) DeadCheck: Dead check mode
4) LoopCheck: Reserved
5) EF Line Selection: Reserved
CSWI01
Step3: select Execution Condition

InterlockChk InterlockNotChk
Result
6. Press the key “◄” or “►” to select interlock mode and press the key “ENT” to next step.
Two interlock check modes are optional:
1) InterlockChk: Check interlocking criteria
2) InterlockNotChk: Not check interlocking criteria
CSWI01
Step4: select Interlock Condition

InterlockChk InterLockNotChk
Result
7. Press the key “◄” or “►” to select control type and press the key “ENT”.
As shown in the following figure, operation results will be shown after “Result” at the bottom of the
LCD.

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Three synchronism control types are optional:
1) Select: Select control object
2) Execute: Execute control operation
3) Cancel: Cancel control operation
CSWI01
Step5: select Control Type

InterlockChk InterLockNotChk
Result
NOTICE!
“Exectue” operation must be operated after “Select” operation.
8.5.11 Remote Control via SLD

The control operation (close or open) also can be executed on the single line diagram (SLD) of the
default display under normal operation condition. The signs of the circuit breaker (abbreviated as
CB) and switch (DS or ES) are listed in the following table.
Table 8.5-1 Primary equipment symbols in SLD
Sign Explanation Sign Explanation
Position of CB: Open Position of switch: Open
Position of CB: Closed Position of switch: Closed
? Position of CB: Intermediate state ? Position of switch: Intermediate state
× Position of CB: Bad state × Position of switch: Bad state
An example of normal display with SLD is shown in the following figure. The single line diagram of
the default display on the LCD is shown as below when the device is in normal situation, if this
device adopts the single line diagram as default display.

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S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Feeder M01
Press key “▼” continuously to select a circuit breaker or a switch which will be opened or closed.
Then press key “ENT” to start to control the selected circuit breaker or switch. If it is the first time to
do control operation after a long time, it needs to input a correct password. The control operation
window will be valid for 150s after inputting correct password. The password for control operation
is fixed, and it is “111”.
S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171 Password：
Feeder M01 000
After inputting correct password, press key “ENT” to control the selected circuit breaker or switch.
Press key “▼” continuously to select the expected circuit breaker or switch with closed position,
and then press key “ENT” to start to open the selected circuit breaker or switch.

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S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Feeder M01 Open Close?
If control operation is succeed, the following figure will be shown.
S Addr:150 2008-11-28 10:10:00 Group 01
Bus1
Bus2
M011 M0112
M0131
M01
M0151
M0171
Feeder M01 Op Success
8.5.12 Modify Device Clock

2. Press the “▲” or “▼” to move the cursor to the “Clock” menu, and then press the “ENT” to
enter clock display
3. Press the “▲” or “▼” to move the cursor to the date or time to be modified;
4. Press the “+” or “-” to modify value, and then press the “ENT” to save the modification and
return to the main menu;
5. Press the “ESC” to cancel the modification and return to the main menu.
NOTICE!

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Move the cursor to select the item “Format” to setup time display format. Press the “+”
or “-” to modify from the following options.
1. YYYY-MM-DD (Default display format)
2. YYYY/MM/dd
3. DD-MM-YYYY
4. DD/MM/YYYY
5. MM-DD-YYYY
6. MM/DD/YYYY
Clock
Year: 2008
Month: 11
Day: 28
Hour: 20
Minute: 59
Format: YYYY/MM/DD
8.5.13 View Module Information

2. Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the “ENT”
or “►” to enter the menu;
3. Press the “▲” or “▼” to move the cursor to the command menu “Board Info”, and then press
the “ENT” to enter the menu;
4. Press the “▲” or “▼” to move the scroll bar;
5. Press the “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
8.5.14 Check Software Version

1. Press the “▲” to enter the main menu.
2. Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the “ENT”

Date: 2017-06-15
to enter the submenu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Version Info”, and then
press the key “ENT” to display the software version.
4. Press the “ESC” to return to the main menu.
8.5.15 Communication Test

2. Press the key “▲” or “▼” to move the cursor to the “Test” menu, and then press the key
“ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the submenu “Device Test”, and then press
the key “ENT” to enter the submenu, to select test item. If “Disturb Events” “Superv Events”
or “IO Events” is selected, two options “All Test” and “Select Test” are provided.
Prot Element
All Test
Select Test
4. Press the key “▲” or “▼” to move the cursor to select the corresponding command menu “All
Test” or “Select Test”. If selecting the “All Test”, press the “ENT”, and the device will
successively carry out all operation element message test one by one.
5. If “Select Test” is selected, press the key “ENT”. Press the “＋” or “－” to page up/down, and
then press the key “▲” or “▼” to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key “ENT” to execute the communication test of
this protection element, the substation automatic system (SAS) will receive the corresponding
message.
NOTICE!
If no input operation is carried out within 60s, exit the communication transmission and
return to the “Test” menu, at this moment, the LCD will display “Communication Test
Timeout and Exiting...”.

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Press the key “ESC” to exit this menu (returning to the menu “Test”, at this moment, the LCD will
display “Communication Test Exiting…”.
8.5.16 Select Language
2. Press the key “▲” or “▼” to move the cursor to the command menu “Language”, and then
press the key “ENT” to enter the menu and the following display will be shown on LCD.
Please Select Language:
1 中文
2 English
3 XXXX
Third language selected by the user
3. Press the key “▲” or “▼” to move the cursor to the language user preferred and press the key
“ENT” to execute language switching. After language switching is finished, LCD will return
to the menu “Language”, and the display language is changed. Otherwise, press the key
“ESC” to cancel language switching and return to the menu “Language”.
NOTICE!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.

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Table of Contents
9.1 General Description ........................................................................................ 9-1

9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 GOOSE Introduction ....................................................................................... 9-2
9.3.1 Overview .............................................................................................................................. 9-2
9.3.3 Maintenance Mechanism ..................................................................................................... 9-5
9.4 Signal List ........................................................................................................ 9-6

9.4.1 Input Signals ........................................................................................................................ 9-6
9.4.2 Output Signals ................................................................................................................... 9-13
List of Figures
Figure 9.3-1 Typical GOOOSE networking scheme ................................................................. 9-2
Figure 9.3-2 GOOSE send mechanism...................................................................................... 9-3
List of Tables
Table 9.4-1 Input signals ............................................................................................................. 9-6
Table 9.4-2 Output signals ........................................................................................................ 9-13

Date: 2016-07-15

Date: 2016-07-15
9.1 General Description
By adoption of PCS-Explorer software, it is able to make device configuration, function

configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-921.
9.2 Introduction on PCS-Explorer Software
PCS-Explorer software is developed in order to meet customer’s demand on functions of UAPC

platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supporting one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand.
After function configuration is finished, disabled protection function will be hidden in the device and
in setting configuration list of PCS-Explorer Software. The user can select to show or hide some
setting by this way, and modify the setting value.
Please refer to the instruction manual “PCS-Explorer Auxiliary Software” for details.
Overall functions:
 Programmable logic (off-line function)
 Device configuration (off-line function)
 Function configuration (off-line function)
 LCD configuration (off-line function)
 LED indicators configuration (off-line function)
 Binary signals configuration (off-line function)
 Setting configuration (off-line & on-line function)
 Real-time display of analogue and digital quantity of device (on-line function)
 Display of sequence of report (SOE) (on-line function)
 Analysis of waveform (off-line & on-line function)
 File downloading/uploading (on-line function)
 LCD function shortcut keys configuration
 DNP communication information map configuration
 Export RIO file

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 Multi-user access authority management
9.3 GOOSE Introduction
9.3.1 Overview
Generic Object Oriented Substation Event (GOOSE) is the mechanism in IEC61850 standard
used to satisfy fast message demand of substation automation system, and provides means of
fast information transmission and exchange under network communication conditions. In case of
any status change, intelligent electronic device (IED) will use change report to transmit binary
objects in high speed, i.e. GOOSE report. Information exchange among IEDs is realized by
GOOSE.
PCS-900 series features GOOSE network message interface independent of MMS message
interface and of high real-time property. Therefore, PCS-900 series can receive binary inputs via
opto-coupler and send output commands via binary output contact, as well as GOOSE input
signals, and can configure GOOSE output commands and GOOSE output signals. Configuration
of GOOSE signals is obtained by GOOSE file based on SCD file.
PCS-900 series supports single network mode and dual network mode, P2P mode and networking
mode, as well as mode based on station level network MMS or process level network. Networking
mode can be selected by parameters setup or configuration tool PCS-Explorer. For important
occasions, in order to ensure no loss of data during transmission, it is recommended to configure
dual GOOSE network in which process level is independent of station level for the protection
device. Refer to the figure as below.
Control Center
Server A/ Server B/ Engineering Maintenance GPS

Printer
Workstation Workstation Workstation Workstation
Station Level Satellite-Synchronized

Clock
Gateway
Switch Station Bus: MMS, GOOSE (Interlocking), SNTP
……
Protocol Converter
PCS-900 PCS-900 PCS-9700

Bay Level Protection Protection Bay Control Unit
Third-Party IEDs
Switch Process Bus: Sampled Value, GOOSE (Tripping/Binary Input), IEEE 1588, GMRP Clock Synchronization
PCS-221 PCS-222
Process Level Merging Unit Circuit Breaker Controller
Optical Fiber ……
Electronic/Optical CT & VT
Circuit Breaker: GIS/AIS
Figure 9.3-1 Typical GOOOSE networking scheme
The above figure shows a typical dual network mode, in which process level network is separate
from station level network, to ensure that important information (e.g. tripping signal) is not affected

Date: 2016-07-15
by data on the MMS data network.
Ring network is not recommended for GOOSE network configuration, to avoid the problem of
network storm. Duplicated protection configuration and their GOOSE networks shall be totally
independent of each other, to ensure that in case of any network fault in one set of duplicated
protection configuration, the other set will not be affected.

IEC 61850 provides substation configuration language (SCL) based on XML, which has
standardized description of substation systems and device configuration. There are four types of
SCL files:
 SSD: Substation Specification Description
 SCD: Substation Configuration Description
 ICD: IED Capability Description
 CID: Configured IED Description
Normally, manufacturers provide ICD file, system integrator prepare SCD file of the whole
substation according to design blueprints, and each IED manufacturer exports its CID file after
receiving SCD configuration model.
9.3.2.1 GOOSE Transmission
GOOSE service is directly mapped to network data link layer. To ensure important information
transmission priority, broadcast address is used for multi-channle transmission of information.
GOOSE message allows high-speed transmission of tripping signals, which has high transmission
success rate.
GOOSE message is not sent at fixed interval. When there is no GOOSE event, interval of GOOSE
message transmission is fixed and relatively long. However, after an event occurs, data
transmission will change, and the interval set for this occasion is the shortest. GOOSE adopts
continual repeated transmission to realize reliable transmission, and during this period,
transmission interval will gradually increase, till the event status becomes stable. Later, GOOSE
message transmission will be back to fixed interval. The whole process is shown as below:
Transmission Time
Event
Figure 9.3-2 GOOSE send mechanism
Where:
T0 is retransmission in stable conditions (no event for a long time), and it can be configured
(typical value is 5000ms)

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T1 is the shortest retransmission time after the event, and it can be configured (typical value is
2ms)
T2 is retransmission times until achieving the stable conditions time, and it is fixed at 2T1.
T3 is retransmission times until achieving the stable conditions time, and it is fixed at 4T1.
GOOSE transmission adopts retransmission mechanism and has 4 transmission times: T0, T1, T2,
and T3. After the event occurs, a frame message will be transmitted, transmitting again after
interval T1, and still transmitting after another interval T1. And then, transmitting again after
interval T2 and yet transmitting after interval T3. At this time, if no new event occurs, transmission
will continue at interval T0 again.
Data transmitted are defined by definition of GOOSE transmission dataset and GOOSE control
blocks. PCS-900 series supports transmission of 8 GOOSE control blocks at maximum. GOOSE
can transmit both binary quantities and analog quantities of not large change, e.g. temperature
and humidity.
9.3.2.2 GOOSE Reception
At maximum, PCS-900 series can receive 128 control block data, subject to control by GOOSE
Links. GOOSE reception control block is controlled by GOOSE links of corresponding serial
number, and provides corresponding alarm signal of the same serial number.
After the receiver receives GOOSE data, if GOOSE data is invalid (refer to section 9.3.2.3), the
GOOSE data shall be processed accordingly, i.e. clear (zero), force to 1, or keep.
9.3.2.3 Invalid GOOSE Data
In case of any of the following, invalid GOOSE data will be reported:
1. The next frame of GOOSE message is not received within 1.1 times of maximum message
survival time
2. GOOSE reception link is disabled
3. Inconsistent version No. or mismatching dataset data
4. Device test mode is inconsistent with message “Test” state
NOTICE!
Each frame of transmitted GOOSE data includes maximum message survival time,
normally 2 times of GOOSE heartbeat time (t0).
“Test” state of GOOSE message is set to 1 if the reception control block receives
message with “Test” bit, otherwise it is set to 0 if message without “Test” bit is received.
9.3.2.4 GOOSE Data Link Disconnection
If GOOSE message is not received within 2 times of maximum message survival time, GOOSE
link disconnection will be reported. For example, receiver sets GOOSE heartbeat time (t0) to 5s,
so that specified message survival time in transmitted message is 10s. After GOOSE receives one

Date: 2016-07-15
frame of message, if the next frame is not received within 11s, , GOOSE data is invalid. If not
received in 20s (2 times of message survival time), GOOSE link disconnection will be reported.
If invalid data or data link disconnection is tested by unplugging network wire, note that since
network line disconnection occurs at any time between two groups of heartbeat messages, invalid
GOOSE data is normally reported in 6~11s after actual disconnection, and GOOSE network link
disconnection is normally reported in 15~20s after actual disconnection.
NOTICE!
Invalid GOOSE data is not synchronized with GOOSE link disconnection in time. The
former is reported when message is not received within 1.1 times maximum message
survival time, while the latter is only reported when message is not received within 2
times maximum message survival time.
9.3.2.5 GOOSE Message Handling Mechanism under Network Storm
This device features fast detection of network storm and fast handling of network messages. In
case of network storm in single network, this device can ensure no loss of normal network
messages, and protection functions will not be affected.
In case of network storm in dual network, this device can maintain reception and handling of
messages in one of the networks, and actual test has shown that protection functions are basically
not affected.
9.3.3 Maintenance Mechanism

For important GOOSE output signal, such as, tripping, reclosing, breaker failure etc., it is
selectable whether they are controlled by “Start” signal, which is monitoring signal of GOOSE
output, and provided by fault detector DSP and separated from protection DSP, to ensure reliability
of output signals.
GOOSE reception and transmission message provide a “Test” bit. The receiver will compare this
“Test” bit in received message with its own “Test” bit. If they are consistent, operation will occur,
otherwise, invalid GOOSE data will be reported (refer to section 9.3.2.3). This eliminates mutual
effect between device in operation and device in maintainence.
Different from traditional contact signals, which can can be set to enable/disable corresponding
signals, PCS-900 series adopts the following modes to enable and disable corresponding signals
including “Test” state.
1. When the “Test” bit in GOOSE message is consistent with the “Test” of the receiver, GOOSE
data is valid, otherwise it is invalid (refer to section 9.3.2.3). In this way, the device in service
and device in maintainence do not affect each other.
2. In “Test” state, the receiver still has event recording and state display functions, to facilitate
check of circuit.
3. GOOSE logic link is provided to solve the problem of selective transmission of signals.
Transmitter can be isolated from receiver by disabling relevant GOOSE logic link. The setup
of transmission and reception logic links can be consistent with traditional logic links.

Date: 2016-07-15
4. For transmitter, GOOSE element will perform AND of data value and transmission logic link
state, and then detect change of data, so as to decide activation of a new round of
transmission flow.
9.4 Signal List
9.4.1 Input Signals
All input signals for this device are listed in the following table.
If an input signal is gray in PCS-Explorer, it means the input signal is not configurable. If a input
signal is dark in PCS-Explorer, it means the input signal is configurable.
Table 9.4-1 Input signals

Circuit breaker position
Normally closed auxiliary contact of phase A of corresponding circuit
1 52b_PhA
breaker
Normally closed auxiliary contact of phase B of corresponding circuit
2 52b_PhB
breaker
Normally closed auxiliary contact of phase C of corresponding circuit
3 52b_PhC
breaker
External manual closing input signal, it is applied to manual closing
4 ManCls
switch-onto-fault logic
5 52b Normally closed contact of three-phase of circuit breaker
6 52a Normally open contact of three-phase of circuit breaker
Control circuit failure (normally closed contact and normally open
7 TCCS.Input contact of three-phase circuit breaker are all de-energized due to DC
power loss of control circuit)
Auxiliary element
Current change auxiliary element enabling input, it is triggered from
1 AuxE.OCD.En
Current change auxiliary element blocking input, it is triggered from
2 AuxE.OCD.Blk
Stage 1 of residual current auxiliary element enabling input, it is
3 AuxE.ROC1.En
Stage 1 of residual current auxiliary element blocking input, it is
4 AuxE.ROC1.Blk
5 AuxE.ROC2.En
6 AuxE.ROC2.Blk
7 AuxE.ROC3.En

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8 AuxE.ROC3.Blk
Stage 1 of phase current auxiliary element enabling input, it is
9 AuxE.OC1.En
Stage 1 of phase current auxiliary element blocking input, it is
10 AuxE.OC1.Blk
11 AuxE.OC2.En
12 AuxE.OC2.Blk
13 AuxE.OC3.En
14 AuxE.OC3.Blk
Voltage change auxiliary element enabling input, it is triggered from
15 AuxE.UVD.En
Voltage change auxiliary element blocking input, it is triggered from
16 AuxE.UVD.Blk
Phase-to-ground under voltage auxiliary element enabling input, it is
17 AuxE.UVG.En
Phase-to-ground under voltage auxiliary element blocking input, it is
18 AuxE.UVG.Blk
Phase-to-phase under voltage auxiliary element enabling input, it is
19 AuxE.UVS.En
Phase-to-phase under voltage auxiliary element blocking input, it is
20 AuxE.UVS.Blk
Residual voltage auxiliary element enabling input, it is triggered from
21 AuxE.ROV.En
Residual voltage auxiliary element blocking input, it is triggered from
22 AuxE.ROV.Blk
Phase overcurrent protection
Stage x of phase overcurrent protection enabling input 1, it is triggered
1 50/51Px.En1
Stage x of phase overcurrent protection enabling input 2, it is triggered
2 50/51Px.En2
Stage x of phase overcurrent protection blocking input, it is triggered
3 50/51Px.Blk
Earth-fault protection
Stage x of earth fault protection enabling input 1, it is triggered from
1 50/51Gx.En1
Stage x of earth fault protection enabling input 2, it is triggered from
2 50/51Gx.En2
3 50/51Gx.Blk Stage x of earth fault protection blocking input, it is triggered from

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4 50/51Gx.En_ShortDly Enable accelerating stage x of earth fault protection. (x=2, 3, 4)
5 50/51Gx.Blk_ShortDly Accelerating stage x of earth fault protection is disabled. (x=2, 3, 4)
Negative-sequence overcurrent protection
Stage x of negative-sequence overcurrent protection enabling input 1,
1 50/51Qx.En1
it is triggered from binary input or programmable logic etc. (x=1, 2, 3)
Stage x of negative-sequence overcurrent protection enabling input 2,
2 50/51Qx.En2
it is triggered from binary input or programmable logic etc. (x=1, 2, 3)
Stage x of negative-sequence overcurrent protection blocking input, it
3 50/51Qx.Blk
is triggered from binary input or programmable logic etc. (x=1, 2, 3)
Dead zone protection
Dead zone protection enabling input 1, it is triggered from binary input
1 50DZ.En1
Dead zone protection enabling input 2, it is triggered from binary input
2 50DZ.En2
Dead zone protection blocking input, it is triggered from binary input or
3 50DZ.Blk
4 50DZ.Init Initiation signal input of the dead zone protection.
Voltage protection
Stage x of overvoltage protection enabling input 1, it is triggered from
1 59Px.En1
Stage x of overvoltage protection enabling input 2, it is triggered from
2 59Px.En2
Stage x of overvoltage protection blocking input, it is triggered from
3 59Px.Blk
Negative-sequence overvoltage protection enabling input 1, it is
4 59Q.En1
Negative-sequence overvoltage protection enabling input 2, it is
5 59Q.En2
Negative-sequence overvoltage protection blocking input, it is
6 59Q.Blk
Stage x of residual overvoltage protection enabling input 1, it is
7 59Gx.En1
triggered from binary input or programmable logic etc. (x=1, 2, 3)
Stage x of residual overvoltage protection enabling input 2, it is
8 59Gx.En2
triggered from binary input or programmable logic etc. (x=1, 2, 3)
Stage x of overvoltage protection blocking input, it is triggered from
9 59Gx.Blk
binary input or programmable logic etc. (x=1, 2, 3)
Stage x of undervoltage protection enabling input 1, it is triggered from
10 27Px.En1
Stage x of undervoltage protection enabling input 2, it is triggered from
11 27Px.En2
Stage x of undervoltage protection blocking input, it is triggered from
12 27Px.Blk

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Negative sequence overvoltage protection

Negative sequence overvoltage protection enabling input 1, it is
1 59Q.En1
Negative sequence overvoltage protection enabling input 2, it is
2 59Q.En2
Negative sequence overvoltage protection blocking input, it is
3 59Q.Blk
triggered from binary input or programmable logic etc
Frequency calculation function
Frequency calculation function enabling input , it is triggered from
1 FreqCal.En
Frequency calculation function blocking input, it is triggered from
2 FreqCal.Blk
binary input or programmable logic etc
Frequency protection
Underfrequency protection enabling input 1, it is triggered from binary
1 81U.En1
Underfrequency protection enabling input 2, it is triggered from binary
2 81U.En2
Underfrequency protection blocking input, it is triggered from binary
3 81U.Blk
Overfrequency protection enabling input 1, it is triggered from binary
4 81O.En1
Overfrequency protection enabling input 2, it is triggered from binary
5 81O.En2
Overfrequency protection blocking input, it is triggered from binary
6 81O.Blk
Breaker failure protection
1 50BF.ExTrp3P_L Input signal of three-phase tripping contact from line protection
Input signal of three-phase tripping contact from generator or
2 50BF.ExTrp3P_GT
transformer protection
3 50BF.ExTrpA Input signal of phase-A tripping contact from external device
4 50BF.ExTrpB Input signal of phase-B tripping contact from external device
5 50BF.ExTrpC Input signal of phase-C tripping contact from external device
Input signal of three-phase tripping contact from external device. Once
it is energized, normally closed auxiliary contact of circuit breaker is
6 50BF.ExTrp_WOI
chosen in addition to breaker failure current check to trigger breaker
failure timers.
Breaker failure protection enabling input, it is triggered from binary
7 50BF.En
Breaker failure protection blocking input, such as function blocking
binary input.
8 50BF.Blk
When the input is 1, breaker failure protection is reset and time delay
is cleared.
Pole discrepancy protection

Date: 2016-07-15
Pole discrepancy protection enabling input 1, it is triggered from binary

1 62PD.En1
Pole discrepancy protection enabling input 2, it is triggered from binary
2 62PD.En2
Pole discrepancy protection blocking input, it is triggered from binary
3 62PD.Blk
4 62PD.In_PD Pole discrepancy binary input
Synchronism check
1 25.Blk_Chk Input signal of blocking synchrocheck function for AR.
Input signal of blocking synchronism check for AR. If the value is “1”,
2 25.Blk_SynChk
the output of synchronism check is “0”.
3 25.Blk_DdChk Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting
4 25.Start_Chk
signal of AR from auto-reclosing module.
Input signal of starting live three-phase check, usually it was starting
5 25.Start_3PLvChk
signal of 1-pole AR
6 25.Sel_SynChk Selecting synchronism check
7 25.Sel_DdL_DdB Selecting dead line and dead bus check
8 25.Sel_DdL_LvB Selecting dead line and live bus check
9 25.Sel_LvL_DdB Selecting live line and dead bus check
10 25.Sel_NoChk Selecting no check
11 25.Blk_VTS_Usyn VT circuit supervision of the synchronism voltage (Usyn) is blocked
12 25.Blk_VTS_Uref VT circuit supervision of the reference voltage (Uref) is blocked

Auto-reclosure
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
1 79.En
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
2 79.Blk
disabling AR will be controlled by the external input
3 79.Sel_1PAR
breaker

Date: 2016-07-15

4 79.Sel_3PAR
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
5 79.Sel_1P/3PAR
breaker
6 79.Trp Input signal of single-phase tripping from line protection to initiate AR
7 79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
8 79.TrpA Input signal of A-phase tripping from line protection to initiate AR
9 79.TrpB Input signal of B-phase tripping from line protection to initiate AR
10 79.TrpC Input signal of C-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the
11 79.LockOut operating signals of definite-time protection, transformer protection
and busbar differential protection, etc.
12 79.PLC_Lost Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master AR
13 79.WaitMaster
(when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
14 79.CB_Healthy
perform the close function
15 79.Clr_Counter Clear the reclosing counter
16 79.Ok_Chk Synchrocheck condition of AR is met
17 79.Ok_3PLvChk Live three-phase check condition of AR is met
Trip logic
Trip enabling input, it is triggered from binary input or programmable
1 TRP.En
logic etc.
Trip blocking input, it is triggered from binary input or programmable

2 TRP.Blk
logic etc.
3 Op_CBProt breaker tripping elements except line fault
Input signal of permitting three-phase tripping
4 PrepTrp3P When this signal is valid, three-phase tripping will be adopted for any
kind of faults.
VT circuit supervision
VT supervision enabling input, it is triggered from binary input or
1 VTS.En
VT supervision blocking input, it is triggered from binary input or
2 VTS.Blk
VT neutral point supervision enabling input, it is triggered from binary
3 VTNS.En
VT neutral point supervision blocking input, it is triggered from binary
4 VTNS.Blk
5 VTS.MCB_VT Binary input for VT MCB auxiliary contact
CT circuit supervision
CT circuit supervision enabling input, it is triggered from binary input or
1 CTS.En
2 CTS.Blk CT circuit supervision blocking input, it is triggered from binary input or

Date: 2016-07-15

Control and synchrocheck for manual closing
It is the interlock status of No.xx open output of BO module
1 CSWIxx.CILO.EnOpn
(xx=01~10)
It is the interlock status of No.xx closing output of BO module
2 CSWIxx.CILO.EnCls
(xx=01~10)
From receiving a closing command, this device will continuously
check whether the 2 voltages (Incoming voltage and reference
voltage) involved in synchronism check(or dead check) can meet the
criteria.
3 MCBrd.25.Ok_Chk
Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism
check(or dead check) criteria are not met, [MCBrd.25.Ok_Chk] will be
set as “0”; if the synchronism check(or dead check) criteria are met,
[MCBrd.25.Ok_Chk] will be set as “1”.
Access the menu “Local Cmd→Control” to issue control command
locally.
4 CSWIxx.LocCtrl It is used to select the local control to No.xx controlled object
(CB/DS/ES). When the local control is active, No.xx binary outputs
can only be locally controlled.
It is used to select the remote control to No.xx controlled object
5 CSWIxx.RmtCtrl (CB/DS/ES). When the remote control is active, No.xx binary outputs
can only be remotely controlled by SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
6 CSWIxx.CILO.Disable the signal “CSWIxx.CILO.Disable” is “1”, No.xx binary outputs of the
device will not be blocked by interlock conditions.
It is used to select the remote control to No.xx controlled object
7 BIinput.RmtCtrl (CB/DS/ES). When the remote control is active, all binary outputs can
only be remotely controlled by SCADA or control centers.
It is used to select the local control to No.xx controlled object
8 BIinput.LocCtrl (CB/DS/ES). When the local control is active, all binary outputs can
only be locally controlled.
It is used to disable the interlock blocking function for control output. If
9 BIinput.CILO.Disable the signal “CSWIxx.CILO.Disable” is “1”, all binary outputs of this
device will not be blocked by interlock conditions.
“CSWI01.ManSynCls” is “1”, the output contact [BO_CtrlCls01] is
10 CSWI01.ManSynCls
closed to execute manually closing the circuit breaker with
synschrochcek.
11 CSWI01.ManOpn “CSWI01.ManOpn” is “1”, the output contact [BO_CtrlOpn01] is closed
to execute manually open the circuit breaker.
12 MCBrd.25.Sel_SynChk Synchronism check for manual closing is selected.
13 MCBrd.25.Sel_NoChk No check for manual closing is selected.

Date: 2016-07-15
9.4.2 Output Signals

All output signals for this device have been listed in the following table.
If a output signal is gray in PCS-Explorer, it means the output signal is not configurable. If a output
signal is dark in PCS-Explorer, it means the output signal is configurable.
Table 9.4-2 Output signals

Circuit breaker position
1 Alm_52b CB position is abnormal
2 TCCS.Alm Control circuit of circuit breaker is abnormal
Fault detector
1 FD.Pkp The device picks up
2 FD.DPFC.Pkp DPFC current fault detector element operates.
3 FD.ROC.Pkp Residual current fault detector element operates.
4 FD.NOC.Pkp Negative-sequence fault detector element operates.
Auxiliary element
1 AuxE.St Any auxiliary element of the device operates
2 AuxE.OCD.St_DDO Current change auxiliary element operates (7s delayed drop off).
3 AuxE.OCD.On Current change auxiliary element is enabled
25 AuxE.UVD.St Voltage change auxiliary element operates.
26 AuxE.UVD.St_DDO Voltage change auxiliary element operates (7s delayed drop off).

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27 AuxE.UVD.On Voltage change auxiliary element is enabled

28 AuxE.UVG.St Phase-to-ground under voltage auxiliary element operates.
29 AuxE.UVG.StA Phase-to-ground under voltage auxiliary element operates (phase A).
30 AuxE.UVG.StB Phase-to-ground under voltage auxiliary element operates (phase B).
31 AuxE.UVG.StC Phase-to-ground under voltage auxiliary element operates (phase C).
32 AuxE.UVG.On Phase-to-ground under voltage auxiliary element is enabled
33 AuxE.UVS.St Phase-to-phase under voltage auxiliary element operates.
34 AuxE.UVS.StAB Phase-to-phase under voltage auxiliary element operates (phase AB).
35 AuxE.UVS.StBC Phase-to-phase under voltage auxiliary element operates (phase BC).
36 AuxE.UVS.StCA Phase-to-phase under voltage auxiliary element operates (phase CA).
37 AuxE.UVS.On Phase-to-phase under voltage auxiliary element is enabled
38 AuxE.ROV.St Residual voltage auxiliary element operates.
39 AuxE.ROV.On Residual voltage auxiliary element is enabled
Current direction
1 FwdDir_ROC The forward direction of zero-sequence power
2 RevDir_ROC The reverse direction of zero-sequence power
3 FwdDir_NegOC The forward direction of negative-sequence power
4 RevDir_NegOC The reverse direction of negative-sequence power
5 FwdDir_A The forward direction of phase-A current
6 FwdDir_B The forward direction of phase-B current
7 FwdDir_C The forward direction of phase-C current
8 RevDir_A The reverse direction of phase-A current
9 RevDir_B The reverse direction of phase-B current
10 RevDir_C The reverse direction of phase-C current
11 FwdDir_AB The forward direction of phase-AB current
12 FwdDir_BC The forward direction of phase-BC current
13 FwdDir_CA The forward direction of phase-CA current
14 RevDir_AB The reverse direction of phase-AB current
15 RevDir_BC The reverse direction of phase-BC current
16 RevDir_CA The reverse direction of phase-CA current
Phase Overcurrent Protection
1 50/51Px.On Stage x of phase overcurrent protection is enabled
2 50/51Px.St Stage x of phase overcurrent protection starts
3 50/51Px.StA Stage x of phase overcurrent protection starts (A-Phase).
4 50/51Px.StB Stage x of phase overcurrent protection starts (B-Phase).
5 50/51Px.StC Stage x of phase overcurrent protection starts (C-Phase).
6 50/51Px.Op Stage x of phase overcurrent protection operates
Earth-fault Protection
1 50/51Gx.On Stage x of residual overcurrent protection is enabled.
2 50/51Gx.St Stage x of residual overcurrent protection starts.
3 50/51Gx.Op Stage x of residual overcurrent protection operates.
Negative-sequence overcurrent protection
4 50/51Qx.On Stage x of negative-sequence overcurrent protection is enabled. (x=1, 2, 3)

Date: 2016-07-15
5 50/51Qx.St Stage x of negative-sequence overcurrent protection starts. (x=1, 2, 3)

6 50/51Qx.Op Stage x of negative-sequence overcurrent protection operates. (x=1, 2, 3)
7 50/51Q3.Alm Stage 3 of negative-sequence overcurrent protection operates to alarm.
Dead zone protection
1 50DZ.On Dead zone protection is enabled.
2 50DZ.St Dead zone protection starts.
3 50DZ.Op Dead zone protection operates.
Voltage protection
1 59Px.On Stage x of overvoltage protection is enabled.
2 59Px.Op Stage x of overvoltage protection operates.
3 59Px.St Stage x of overvoltage protection starts.
4 59Px.St1 Stage x of overvoltage protection starts (A or AB).
5 59Px.St2 Stage x of overvoltage protection starts (B or BC).
6 59Px.St3 Stage x of overvoltage protection starts (C or CA).
7 59Px.Op_InitTT Stage x of overvoltage protection operates to initiate transfer trip.
8 59Px.Alm Stage x of overvoltage protection alarms.
9 59Q.On Negative-sequence overvoltage protection is enabled.
10 59Q.Op Negative-sequence overvoltage protection operates.
11 59Q.St Negative-sequence overvoltage protection starts.
12 59G x.On Stage x of residual overvoltage protection is enabled. (x=1, 2, 3)
13 59G x.Op Stage x of residual overvoltage protection operates. (x=1, 2, 3)
14 59Gx.St Stage x of residual overvoltage protection start. (x=1, 2, 3)
15 59G3.Alm Stage 3 of residual overvoltage protection operates to alarm.
16 27Px.On Stage x of undervoltage protection is enabled.
17 27Px.Op Stage x of undervoltage protection operates.
18 27Px.Alm Stage x of undervoltage protection alarms.
19 27Px.St Stage x of undervoltage protection starts.
20 27Px.St1 Stage x of undervoltage protection starts (A or AB).
21 27Px.St2 Stage x of undervoltage protection starts (B or BC).
22 27Px.St3 Stage x of undervoltage protection starts (C or CA).
23 27Px.U_Absent No voltage is detected after the device is powered
Negative sequence overvoltage protection
1 59Q.On Negative sequence overvoltage protection is enabled.
2 59Q.St Negative sequence overvoltage protection starts.
3 59Q.Op Negative sequence overvoltage protection operates.
Frequency calculation function
1 f Frequency calculation result
2 Alm_Freq Frequency abnormality alarm
Frequency protection
1 81O.OFx.On Stage x of overfrequency protection is enabled (x=1, 2, 3 or 4).
2 81O.OFx.Op Stage x of overfrequency protection operates (x=1, 2, 3 or 4).
3 81O.St Overfrequency protection starts.
4 81U.UFx.On Stage x of underfrequency protection is enabled (x=1, 2, 3 or 4).

Date: 2016-07-15
5 81U.UFx.Op Stage x of underfrequency protection operates (x=1, 2, 3 or 4).

6 81U.St Underfrequency protection starts.
Breaker failure protection
1 50BF.On Breaker failure protection is enabled
2 50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker
3 50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker
4 50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker
5 50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phase circuit breaker
6 50BF.Op_t1 Stage 1 of breaker failure protection operates
7 50BF.Op_t2 Stage 2 of breaker failure protection operates
Pole discrepancy protection
1 62PD.On Pole discrepancy protection is enabled
2 62PD.St Pole discrepancy protection starts
3 62PD.Op Pole discrepancy protection operates to trip
Synchronism check
5 Alm_Invalid_Sel Synchronism voltage selection is invalid.
6 25.On_SynChk Synchronism check is enabled.
7 25.On_DdL_DdB Dead line and dead bus check is enabled.
8 25.On_DdL_LvB Dead line and live bus check is enabled.
9 25.On_LvL_DdB Live line and dead bus check is enabled.
10 25.On_NoChk No check is enabled.
To indicate that frequency difference condition for synchronism check of AR is
11 25.Ok_fDiffChk
met, frequency difference between Usyn and Uref is smaller than [25.f_Diff].
To indicate that voltage difference condition for synchronism check of AR is
12 25.Ok_UDiffChk
met, voltage difference between Usyn and Uref is smaller than [25.U_Diff]
To indicate phase difference condition for synchronism check of AR is met,
13 25.Ok_phiDiffChk
phase difference between Usyn and Uref is smaller than [25.phi_Diff].
Dead reference voltage and dead synchronism voltage condition is met (both
14 25.Ok_DdL_DdB reference voltage and synchronism voltage are low than voltage threshold of
dead check)
Dead reference voltage and live synchronism voltage condition is met
15 25.Ok_DdL_LvB (reference voltage is low than voltage threshold of dead check and
synchronism voltage is higher than voltage threshold of live check)
Live reference voltage and dead synchronism voltage condition is met
16 25.Ok_LvL_DdB (reference voltage is higher than voltage threshold of live check and
synchronism voltage is low than voltage threshold of dead check)
Reference voltage is greater than the voltage threshold of live check
17 25.Chk_LvL
[25.U_Lv]
18 25.Chk_DdL Reference voltage is smaller than the voltage threshold of dead check

Date: 2016-07-15
[25.U_Dd]
Synchronism voltage is greater than the voltage threshold of live check
19 25.Chk_LvB
[25.U_Lv]
Synchronism voltage is smaller than the voltage threshold of dead check
20 25.Chk_DdB
[25.U_Dd]
21 25.Ok_DdChk To indicate that dead charge check condition of AR is met
22 25.Ok_SynChk To indicate that synchronism check condition of AR is met
23 25.Ok_Chk To indicate that synchrocheck condition of AR is met
24 25.Ok_3PLvChk To indicate that live three-phase check condition is met
25 25.Alm_VTS_Uref Reference voltage circuit is abnormal
26 25.Alm_VTS_Usyn Synchronism voltage circuit is abnormal
Auto-reclosure
1 79.On Automatic reclosure is enabled
2 79.Off Automatic reclosure is disabled
3 79.Close Output of auto-reclosing signal
4 79.Ready Automatic reclosure have been ready for reclosing cycle
5 79.AR_Blkd Automatic reclosure is blocked
6 79.Active Automatic reclosing logic is actived
7 79.Inprog Automatic reclosing cycle is in progress
8 79.Inprog_1P The first 1-pole AR cycle is in progress
9 79.Inprog_3P 3-pole AR cycle is in progress
10 79.Inprog_3PS1 First 3-pole AR cycle is in progress
11 79.Inprog_3PS2 Second 3-pole AR cycle is in progress
12 79.Inprog_3PS3 Third 3-pole AR cycle is in progress
13 79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
Waiting signal of automatic reclosing which will be sent to slave (when
14 79.WaitToSlave
reclosing multiple circuit breakers)
15 79.Perm_Trp1P Single-phase circuit breaker will be tripped once protection device operates
16 79.Perm_Trp3P Three-phase circuit breaker will be tripped once protection device operates
Automatic reclosure status (0: AR is ready; 1: AR is in progress; 2: AR is

17 79.Rcls_Status
successful)
18 79.Fail_Rcls Auto-reclosing fails
19 79.Succ_Rcls Auto-reclosing is successful
20 79.Fail_Chk Synchrocheck for AR fails
23 79.Mode_1/3PAR Output of 1/3-pole AR mode
Tripping logic
1 TRP.On Trip output is enabled
2 TRP.BlkAR Blocking auto-reclosing
3 TrpA Tripping phase-A circuit breaker
4 TrpB Tripping phase-B circuit breaker

Date: 2016-07-15
5 TrpC Tripping phase-C circuit breaker

6 Trp Tripping any phase of circuit breaker
7 Trp3P Tripping three-phase circuit breaker
VT circuit supervision
1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTNS.Alm Alarm signal to indicate VT neutral point fails
CT circuit supervision
1 CTS.Alm Alarm signal to indicate CT circuit fails
Control and synchrocheck for manual closing
1 CSWIxx.Op_Opn No.xx command output for open. (xx=01~10)
2 CSWIxx.Op_Cls No.xx command output for closing. (xx=01~10)
3 BIinput.RmtCtrl In order to be convenient to user configure control output, three same output
signals with input signals are available. The relationship with 10 binary output
4 BIinput.LocCtrl
have been configured inside the device. The user only assigns a specific
binary input to input signal, the relevant function can be gained. If some
5 BIinput.CILO.Disable binary output need not be controlled by three signals, please cancle the
configuration by PCS-Explorer, and configure it independently.
6 MCBrd.Alm_VTS VT circuit of circuit breaker No.x is abnormal.

Date: 2016-07-15
10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................. 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface.............................................................................................................. 10-1
10.2.2 Ethernet Interface ............................................................................................................ 10-3
10.2.3 IEC60870-5-103 Communication .................................................................................... 10-4
10.2.4 DNP3.0 Communication .................................................................................................. 10-4
10.3 IEC60870-5-103 Interface over Serial Port ................................................ 10-4

10.3.1 Physical Connection and Link Layer ............................................................................... 10-5
10.3.2 Initialization ...................................................................................................................... 10-5
10.3.3 Time Synchronization ...................................................................................................... 10-5
10.3.4 Spontaneous Events ........................................................................................................ 10-5
10.3.5 General Interrogation ....................................................................................................... 10-6
10.3.6 General Service ............................................................................................................... 10-6
10.3.7 Disturbance Records ....................................................................................................... 10-6
10.4 Messages Description for IEC61850 Protocol .......................................... 10-6

10.4.1 Overview .......................................................................................................................... 10-6
10.4.2 Communication Profiles................................................................................................... 10-7
10.4.3 MMS Communication Network Deployment ................................................................... 10-8
10.4.4 Server Data Organization ...............................................................................................10-11
10.4.5 Server Features and Configuration ............................................................................... 10-14
10.4.6 ACSI Conformance ........................................................................................................ 10-15
10.4.7 Logical Nodes ................................................................................................................ 10-21
10.5 DNP3.0 Interface........................................................................................ 10-24

10.5.1 Overview ........................................................................................................................ 10-24

Date: 2015-07-15
10 Communication
10.5.2 Link Layer Functions...................................................................................................... 10-24
10.5.3 Transport Functions ....................................................................................................... 10-24
10.5.4 Application Layer Functions........................................................................................... 10-24
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ..................................................... 10-2
Figure 10.2-2 Ethernet communication cable ........................................................................ 10-3
Figure 10.2-3 Ethernet communication structure .................................................................. 10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance ......................... 10-9
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance ..................... 10-10
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances .................. 10-11

Date: 2015-07-15
10 Communication
10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu “Settings→Device Setup→Comm Settings”.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be “daisy chained” together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information
10.2.1 RS-485 Interface

This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. The rear ports provide RS-485
serial data communication and are intended for use with a permanently wired connection to a
remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.

Date: 2015-07-15
10 Communication
EIA RS-485
Master 120 Ohm
120 Ohm
Slave Slave Slave
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm 2 per core is normally adequate. Total cable length must
not exceed 500m. The screen must be continuous and connected to ground at one end, normally
at the master connection point; it is important to avoid circulating currents, especially when the
cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the product’s chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.

Date: 2015-07-15
10 Communication
NOTICE!
It is extremely important that the 120Ω termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR cannot assume responsibility
for any damage that may occur to a device connected to the network as a result of
incorrect application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface

This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the menu “Settings→Device
Setup→Comm Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
also connected to the exchanger and will play a role of master station, so the every equipment
which has been connected to the exchanger will play a role of slave unit.

Date: 2015-07-15
10 Communication
SCADA
Switch: Net A
Switch: Net B
……
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication

The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings to the protective
device must be configured.
10.2.4 DNP3.0 Communication

The DNP3.0 (Distributed Network Protocol) protocol can support the OSI/EPA model of the ISO
(International Organization for Standards), and it includes four parts: application layer protocol,
transport functions, data link layer protocol and data object library. The DNP3.0 protocol is
recommended to use the Ethernet network. This relay operates as a slave in the system,
responding to commands from a master station.
10.3 IEC60870-5-103 Interface over Serial Port
The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:
 Initialization (reset)

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10 Communication
 Time synchronization
 Event record extraction
 General interrogation
 General commands
 Disturbance records
10.3.1 Physical Connection and Link Layer

Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization

The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.
10.3.4 Spontaneous Events

Events are categorized using the following information:
 Type identification (TYP)
 Function type (FUN)
 Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103

protocol. Operating elements are sent by ASDU2 (time-tagged message with relative time), and

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10 Communication
status of binary signal and alarm element are sent by ASDU1 (time-tagged message). The cause
of transmission (COT) of these responses is 1.
All spontaneous events can be gained by printing, implementing submenu “IEC103 Info” in the
menu “Print”.
10.3.5 General Interrogation

The GI can be used to read the status of the relay, the function numbers, and information numbers
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Service

The generic functions can be used to read the setting and protection measurement of the
protective device, and modify the setting. Two supported type identifications are ASDU 21 and
ASDU 10. For more details about generic functions, see the IEC60870-5-103 standard.
All general classification service group numbers can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.3.7 Disturbance Records

This protective device can store up to 32 disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
All channel numbers (ACC) of disturbance data can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.4 Messages Description for IEC61850 Protocol
10.4.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
 IEC 61850-5: Communications and requirements for functions and device models

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 IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs
 IEC 61850-7-1: Basic communication structure for substation and feeder equipment–
Principles and models
 IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)
Common data classes
Compatible logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.4.2 Communication Profiles

The PCS-900 series relay supports IEC 61850 server services over TCP/IP communication
protocol stacks. The TCP/IP profile requires the PCS-900 series to have an IP address to establish
communications. These addresses are located in the menu “Settings→Device Setup→Comm
Settings”.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3. Peer-to-peer

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10 Communication
This is a non-connection-oriented, high speed type of communication usually between substation

equipment, such as protection relays, intelligent terminal. GOOSE is the method of peer-to-peer
communication.
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.
10.4.3 MMS Communication Network Deployment

In order to enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This
section is applied to introduce the details of dual-MMS Ethernet technology. Generally,
single-MMS Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels,
while dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above
110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
NOTICE!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is
broken.

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10 Communication
10.4.3.1 Dual-net Full Duplex Mode Sharing the Same RCB Instance
Client Client
Net A Net B Net A Net B
Report Instance 1 Report Instance 1

RptEna = true RptEna = true
Report Control Block Report Control Block
IED (Server) IED (Server)

Normal operation status Abnormal operation status
TCP Link MMS Link
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.

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10.4.3.2 Dual-net Hot-standby Mode Sharing the Same RCB Instance
Client Client
Report Instance 1 Report Instance 1

RptEna = true RptEna = true

TCP Link Main MMS Link Standby MMS Link
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance
In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
 Main MMS Link: Physically connected, TCP level connected, MMS report service available.
 Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
NOTICE!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is “255.255.0.0”, network prefix of Net A is

“198.120.0.0”, network prefix of Net B is “198.121.0.0”, Net A IP address of the IED is
“198.120.1.2”, and then Net B IP address of the IED must be configured as
“198.121.1.2”, i.e., Net A IED host address =1x256+2=258, Net B IED host address
=1x256+2=258, Net A IED host address equals to Net B IED host address.

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10.4.3.3 Dual-net Full Duplex Mode with 2 Independent RCB Instances
Client Client
Report Instance 1 Report Instance 2 Report Instance 1 Report Instance 2

RptEna = true RptEna = true RptEna = true RptEna = true

TCP Link MMS Link
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances
In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion, for the second mode, it’s difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.
10.4.4 Server Data Organization

IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common

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10 Communication
information about the IED logical device.
10.4.4.1 Digital Status Values
The GGIO logical node is available in the PCS-900 series relays to provide access to digital status
points (including general I/O inputs and warnings) and associated timestamps and quality flags.
The data content must be configured before the data can be used. GGIO provides digital status
points for access by clients. It is intended that clients use GGIO in order to access digital status
values from the PCS-900 series relays. Clients can utilize the IEC61850 buffered reporting
features available from GGIO in order to build sequence of events (SOE) logs and HMI display
screens. Buffered reporting should generally be used for SOE logs since the buffering capability
reduces the chances of missing data state changes. All needed status data objects are transmitted
to HMI clients via buffered reporting, and the corresponding buffered reporting control block
(BRCB) is defined in LLN0.
10.4.4.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from a IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:
 MMXU.MX.Hz: frequency
 MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.MX.A.phsA: phase A current magnitude and angle
 MMXU.MX.A.phsB: phase B current magnitude and angle
 MMXU.MX.A.phsC: phase C current magnitude and angle
10.4.4.3 Protection Logical Nodes
The following list describes the protection elements for PCS-921 series relays. The specified relay
will contain a subset of protection elements from this list.
 PTUV: Undervoltage

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10 Communication
 PTOV: Overvoltage
 PTOF: Overfrequency
 PTUF: Underfrequency
 PPDP: Pole discrepancy
 PTOC: Phase overcurrent, earth fault overcurrent
 PSCH: Protection scheme
 RBRF:Breaker failure
 RREC: Automatic reclosing
 RSYN: Synchronism-check
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PTOC1 is “PTOC1.ST.Op.general”. For
PCS-921 series relays protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-900 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:
 MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
accuracy for these functions has to be provided.
 LPHD: Physical device information, the logical node to model common issues for physical
device.
 PTRC: Protection trip conditioning, it shall be used to connect the “operate” outputs of one or
more protection functions to a common “trip” to be transmitted to XCBR. In addition or
alternatively, any combination of “operate” outputs of protection functions may be combined to

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a new “operate” of PTRC.
 RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System”
(IEC 60255-24). All enabled channels are included in the recording, independently of the
trigger mode.
10.4.5 Server Features and Configuration

10.4.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
 TrgOps: Trigger options.
The following bits are supported by the PCS-900 series relays:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields.
The following bits are supported by the PCS-900 series relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
 IntgPd: Integrity period.
10.4.5.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from
a PCS-900 series relay.

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10.4.5.3 Timestamps
The Universal Time Coordinated(UTC for short) timestamp associated with all IEC61850 data
items represents the latest change time of either the value or quality flags of the data item.
10.4.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The PCS-900 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-900 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
10.4.6 ACSI Conformance

10.4.6.1 ACSI Basic Conformance Statement
Client/ Server/ Value/

Subscriber Publisher Comments
Client-Server roles

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10 Communication

B11 Server side (of  Y

TWO-PARTY-APPLICATION-ASSOCIATION)
B12 Client side of N 

(TWO-PARTY-APPLICATION-ASSOCIATION)
SCSMs supported
B21 SCSM: IEC 6185-8-1 used N Y
B22 SCSM: IEC 6185-9-1 used N
B23 SCSM: IEC 6185-9-2 used N
B24 SCSM: other N
Generic substation event model (GSE)
B31 Publisher side  Y
B32 Subscriber side Y 
Transmission of sampled value model (SVC)
B41 Publisher side  N
B42 Subscriber side N 

– = not applicable
Y = supported
N or empty = not supported
10.4.6.2 ACSI Models Conformance Statement

If Server or Client side (B11/12) supported
M1 Logical device N Y
M2 Logical node N Y
M3 Data N Y
M4 Data set N Y
M5 Substitution N Y
M6 Setting group control N Y
Reporting
M7 Buffered report control N Y
M7-1 sequence-number N Y
M7-2 report-time-stamp N Y

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10 Communication

M7-3 reason-for-inclusion N Y
M7-4 data-set-name N Y
M7-5 data-reference N Y
M7-6 buffer-overflow N Y
M7-7 entryID N Y
M7-8 BufTm N Y
M7-9 IntgPd N Y
M7-10 GI N Y
M7-11 conf-revision N Y
M8 Unbuffered report control N Y
M8-1 sequence-number N Y
M8-2 report-time-stamp N Y
M8-3 reason-for-inclusion N Y
M8-4 data-set-name N Y
M8-5 data-reference N Y
M8-6 BufTm N Y
M8-7 IntgPd N Y
M8-8 GI N Y
M8-9 conf-revision N Y
Logging N N
M9 Log control N N
M9-1 IntgPd N N
M10 Log N N
M11 Control N Y
If GSE (B31/32) is supported
M12 GOOSE Y Y
M13 GSSE N N
If SVC (41/42) is supported
M14 Multicast SVC N N
M15 Unicast SVC N N
If Server or Client side (B11/12) supported
M16 Time Y Y Time source

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10 Communication

with required
accuracy shall
be available.
Only Time
Master are time
server. All other
Client / Server
devices are
time clients
M17 File Transfer N Y
Y = service is supported
N or empty = service is not supported
10.4.6.3 ACSI Services Conformance Statement
Services AA: Client Server Comments

TP/MC (C) (S)
Server
S1 GetServerDirectory TP N Y
Application association
S2 Associate N Y
S3 Abort N Y
S4 Release N Y
Logical device
S5 GetLogicalDeviceDirectory TP N Y
Logical node
S6 GetLogicalNodeDirectory TP N Y
S7 GetAllDataValues TP N Y
Data
S8 GetDataValues TP N Y
S9 SetDataValues TP N Y
S10 GetDataDirectory TP N Y
S11 GetDataDefinition TP N Y
Data set
S12 GetDataSetValues TP N Y
S13 SetDataSetValues TP N N

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TP/MC (C) (S)
S14 CreateDataSet TP N N
S15 DeleteDataSet TP N N
S16 GetDataSetDirectory TP N Y
Substitution
S17 SetDataValues TP N Y
Setting group control
S18 SelectActiveSG TP N Y
S19 SelectEditSG TP N Y
S20 SetSGValues TP N Y
S21 ConfirmEditSGValues TP N Y
S22 GetSGValues TP N Y
S23 GetSGCBValues TP N Y
Reporting
Buffered report control block (BRCB)
S24 Report TP N Y
S24-1 data-change (dchg) N Y
S24-2 quality-change (qchg) N N
S24-3 data-update (dupd) N N
S25 GetBRCBValues TP N Y
S26 SetBRCBValues TP N Y
Unbuffered report control block (URCB)
S27 Report TP N Y
S27-1 data-change (dchg) N Y
S27-2 quality-change (qchg) N N
S27-3 data-update (dupd) N N
S28 GetURCBValues TP N Y
S29 SetURCBValues TP N Y
Logging
Log control block
S30 GetLCBValues TP N N
S31 SetLCBValues TP N N
Log

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TP/MC (C) (S)
S32 QueryLogByTime TP N N
S33 QueryLogAfter TP N N
S34 GetLogStatusValues TP N N
Generic substation event model (GSE)
GOOSE-CONTROL-BLOCK
S35 SendGOOSEMessage MC N Y
S36 GetGoReference TP N Y
S37 GetGOOSEElementNumber TP N N
S38 GetGoCBValues TP N Y
S39 SetGoCBValues TP N N
GSSE-CONTROL-BLOCK
S40 SendGSSEMessage MC N N
S41 GetReference TP N N
S42 GetGSSEElementNumber TP N N
S43 GetGsCBValues TP N N
S44 SetGsCBValues TP N N
Transmission of sampled value model (SVC)
Multicast SVC
S45 SendMSVMessage MC N N
S46 GetMSVCBValues TP N N
S47 SetMSVCBValues TP N N
Unicast SVC
S48 SendUSVMessage TP N N
S49 GetUSVCBValues TP N N
S50 SetUSVCBValues TP N N
Control
S51 Select N N
S52 SelectWithValue TP N Y
S53 Cancel TP N Y
S54 Operate TP N Y
S55 CommandTermination TP N Y
S56 TimeActivatedOperate TP N N

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TP/MC (C) (S)
File transfer
S57 GetFile TP N Y
S58 SetFile TP N N
S59 DeleteFile TP N N
S60 GetFileAttributeValues TP N Y
Time
T1 Time resolution of internal 10 nearest negative power of 2 in seconds

clock
T2 Time accuracy of internal clock T1 TL (ms) (low accuracy), T3 < 7) (only

Ed2)
T0 (ms) (<= 10 ms), 7 <= T3 < 9
T1 (µs) (<= 1 ms), 10 <= T3 < 13
T2 (µs) (<= 100 µS), 13 <= T3 < 15
T3 (µs) (<= 25 µS), 15 <= T3 < 18
T4 (µs) (<= 25 µS), 15 <= T3 < 18
T5 (µs) (<= 1 µS), T3 >= 20
T3 Supported TimeStamp - n=10 Nearest value of 2-n in seconds

resolution (1ms) (number 0 .. 24)
10.4.7 Logical Nodes

The PCS-921 series relays support IEC61850 logical nodes as indicated in the following table.
Note that the actual instantiation of each logical node is determined by the product order code.
Nodes PCS-921 Series

L: System Logical Nodes
LPHD: Physical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential －
PDIR: Direction comparison －
PDIS: Distance －
PDOP: Directional overpower －
PDUP: Directional underpower －
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint YES
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent －
PMRI: Motor restart inhibition －

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10 Communication
PMSS: Motor starting time supervision －

POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault －
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload －
PTUC: Undercurrent －
PPDP: Pole discrepancy YES
PTUV: Undervoltage YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent －
PVPH: Volts per Hz －
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure YES
RDIR: Directional element YES
RFLO: Fault locator YES
RPSB: Power swing detection/blocking －
RREC: Autoreclosing YES
RRTC: Remote Trip －
RSYN: Synchronism-check or synchronizing YES
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving

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10 Communication
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements －
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement YES
MMXU: Measurement YES
MSQI: Sequence and imbalance YES
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
XCBR: Circuit breaker YES
XSWI: Circuit switch －
T: Logical Nodes For instrument transformers
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer －
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －

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10 Communication
ZGIL: Gas insulated line －

ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor －
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.5 DNP3.0 Interface
10.5.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.5.2 Link Layer Functions

Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.5.3 Transport Functions

Please see the DNP3.0 protocol standard for the details about the transport functions.
10.5.4 Application Layer Functions

10.5.4.1 Function Code
Function Code Function

0 (0x00) Confirm
1 (0x01) Read
2 (0x02) Write
3 (0x03) Select
4 (0x04) Operate
5 (0x05) Direct Operate
6 (0x06) Direct Operate No Acknowledgment
13 (0x0D) Cold Restart
14 (0x0E) Warm Restart
20 (0x14) Enable Unsolicited Responses
21 (0x15) Disable Unsolicited Responses
22 (0x16) Assign Class

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10 Communication
Function Code Function

23 (0x17) Delay Measurement
10.5.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
REQUEST RESPONSE
OBJECT GROUP & VARIATION Master may issue Master shall parse
Outstation shall parse Outstation may issue
Group Variation Function Qualifier Function Qualifier
Description
Number Number Code (DEC) Code (HEX) Code (DEC) Code (HEX)
1
00, 01
(read)
Binary Input: (start, stop)
1 0 22
Any Variation 06
(assign
(no range, or all)
class)
00, 01
Binary Input: 1 (start, stop) 129 00, 01
1 1
Packed format (read) 06 (response) (start, stop)
(no range, or all)
00, 01
Binary Input: 1 (start, stop) 129 00, 01
1 2
With flags (read) 06 (response) (start, stop)
(no range, or all)
06
Binary Input Event: 1 (no range, or all)
2 0
Any Variation (read) 07, 08
(limited qty)
06 129
Binary Input Event: 1 (no range, or all) (response) 17, 28
2 1
Without time (read) 07, 08 130 (index)
(limited qty) (unsol. resp)
06 129
2 2
With absolute time (read) 07, 08 130 (index)
06 129
2 3
With relative time (read) 07, 08 130 (index)
00, 01
Binary output: 1 (start, stop)
10 0
Any Variation (read) 06
(no range, or all)

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10 Communication
REQUEST RESPONSE
Description
00, 01
Binary output: 1 (start, stop)
10 0
Any Variation (read) 06
(no range, or all)
Binary output: 2 00, 01
10 1
Packed format (write) (start, stop)
3
(select)
4 17, 28 129 echo of
Binary Command:
(operate) (index) (response) request
Control relay output
12 1 5
block
(direct op)
(CROB)
6
17, 28
(dir. op, no
(index)
ack)
1
00, 01
(read)
Analog Input: (start, stop)
30 0 22
Any Variation 06
(assign
(no range, or all)
class)
00, 01
Analog Input: 1 (start, stop) 129 00, 01
30 1
32-bit with flag (read) 06 (response) (start, stop)
(no range, or all)
00, 01
30 2
16-bit with flag (read) 06 (response) (start, stop)
(no range, or all)
00, 01
30 3
32-bit without flag (read) 06 (response) (start, stop)
(no range, or all)
00, 01
30 4
16-bit without flag (read) 06 (response) (start, stop)
(no range, or all)

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10 Communication
REQUEST RESPONSE
Description
00, 01
Analog Input:
1 (start, stop) 129 00, 01
30 5 Single-prec flt-pt
(read) 06 (response) (start, stop)
with flag
(no range, or all)
06
Analog Input Event: 1 (no range, or all)
32 0
Any Variation (read) 07, 08
(limited qty)
06 129
Analog Input Event: 1 (no range, or all) (response) 17,28
32 1
32-bit without time (read) 07, 08 130 (index)
06 129
Analog Input Event: 1 (no range, or all) (response) 17,28
32 2
16-bit without time (read) 07, 08 130 (index)
06 129
Analog Input Event:
1 (no range, or all) (response) 17,28
32 5 Single-prec flt-pt
(read) 07, 08 130 (index)
without time
00, 01
Analog Input
1 (start, stop)
34 0 Deadband:
(read) 06
Any Variation
(no range, or all)
00, 01
1 (start, stop) 129 00, 01
Analog Input
(no range, or all)
34 1 Deadband:
00, 01
16-bit
2 (start, stop)
(write) 17,28
(index)
00, 01
Analog Input
1 (start, stop) 129 00, 01
34 2 Deadband:
32-bit
(no range, or all)

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10 Communication
REQUEST RESPONSE
Description
00, 01
2 (start, stop)
(write) 17, 28
(index)
00, 01
1 (start, stop) 129 00, 01
Analog Input
(no range, or all)
34 3 Deadband:
00, 01
Single-prec flt-pt
2 (start, stop)
(write) 17, 28
(index)
00, 01
Analog Output
1 (start, stop)
40 0 Status:
(read) 06
Any Variation
(no range, or all)
00, 01
Analog Output
1 (start, stop) 129 00, 01
40 1 Status:
32-bit with flag
(no range, or all)
00, 01
Analog Output
1 (start, stop) 129 00, 01
40 2 Status:
16-bit with flag
(no range, or all)
Analog Output 00, 01
Status: 1 (start, stop) 129 00, 01
40 3
single-prec flt-pt with (read) 06 (response) (start, stop)
flag (no range, or all)
3
(select)
4 17, 28 129 echo of
Analog Output:
41 1 5
32-bit
(direct op)
6
17, 28
(dir. Op, no
(index)
ack)

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10 Communication
REQUEST RESPONSE
Description
3
(select)
4 17,28 129 echo of
Analog Output:
41 2 5
16-bit
(direct op)
6
17, 28
(dir. Op, no
(index)
ack)
3
(select)
4 17,28 129 echo of
Analog Output:
41 3 5
Single-prec ft-pt
(direct op)
6
17, 28
(dir. Op, no
(index)
ack)
07
1 07 129
(limited
Time and Data: (read) (limited qty = 1) (response)
50 1 qty = 1)
Absolute time
2 07
(write) (limited qty = 1)
Time and Data:
2 07
50 3 Absolute time at last
(write) (limited qty = 1)
recorded time
129
Time and Data CTO: 07
(response)
51 1 Absolute time, (limited
130
synchronized qty = 1)
(unsol. resp)
129
Time and Data CTO: 07
(response)
51 2 Absolute time, (limited
130
unsynchronized qty = 1)
(unsol. resp)
1
(read)
Class Objects: 06
60 1 22
Class 0 data (no range, or all)
(assign
class)

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10 Communication
REQUEST RESPONSE
Description
06
1 (no range, or all)
(read) 07, 08
(limited qty)
20
(enable
Class Objects:
60 2 unsol.)
Class 1 data
21
06
(disable
(no range, or all)
unsol.)
22
(assign
class)
06
(read) 07, 08
(limited qty)
20
(enable
Class Objects:
60 3 unsol.)
Class 2 data
21
06
(disable
(no range, or all)
unsol.)
22
(assign
class)
06
(read) 07, 08
(limited qty)
20
(enable
Class Objects :
60 4 unsol.)
Class 3 data
21
06
(disable
(no range, or all)
unsol.)
22
(assign
class)

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10 Communication
10.5.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user-defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure by
the user.
The user can configure the user-defined communication table through the PCS-Explorer
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.5.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be configured
independently. To the analog outputs, only the attribute “factor” of each analog output needs to be
configured. If the integer mode is adopted for the data formats of analog values (to “Analog Input”,
“Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.), the analog
values will be multiplied by the “factor” respectively to ensure their accuracy. And if the float mode
is adopted for the data formats of analog values, the actual float analog values will be sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be created.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.5.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.
Information Point Pulse On/Null Pulse On/Close Pulse On/Trip Latch On/Null Latch Off/Null
Remote Control Not supported Close Trip Close Trip
Logic Link Not supported Set Clear Set Clear
Extended Output See following description
To an extended output command, if a selected command is controlled remotely, this command

point will output a high-level pulse. The pulse width can be decided by the “On-time” in the related
“Binary Command” which is from the DNP3.0 master. If the “On-time” is set as “0”, the default
pulse width is 500ms.
10.5.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages are transmitted, the related logic setting should be set as “1” firstly and then
the DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function
Code 20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference
value of the “Analog Input” is greater than the “deadband” value, this device will transmit

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10 Communication
unsolicited messages. If the DNP3.0 master needs not to receive the unsolicited messages, it
should forbid this relay to transmit the unsolicited messages through “Function Code 21” (Disable
Unsolicited Messages).
10.5.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22” (Assign
Class).

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11 Installation
11 Installation
Table of Contents
11 Installation...................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Check the Shipment ..................................................................................... 11-2
11.4 Material and Tools Required........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .......................................................................................................11-4
11.7.2 Cubicle Grounding ............................................................................................................11-4
11.7.3 Ground Connection on the Device ...................................................................................11-5
11.7.4 Grounding Strips and their Installation ..............................................................................11-6
11.7.5 Guidelines for Wiring.........................................................................................................11-6
11.7.6 Wiring for Electrical Cables...............................................................................................11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-921 ..................................................... 11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot .................. 11-4
Figure 11.7-1 Cubicle grounding system ................................................................................ 11-5
Figure 11.7-2 Ground terminal of this device ......................................................................... 11-6
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7

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11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the device. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the device and terminated correctly and
pay special attention to grounding. Strictly observe the corresponding guidelines contained in this
section.
11.2 Safety Information

Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the device.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To this
end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
NOTICE!
Jumper links may ONLY be changed on a workbench for electronic equipment.

Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
NOTICE!
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
 Should boards have to be removed from this device installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.

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11 Installation
 Only hold electronic boards at the edges, taking care not to touch the components.
 Only works on the board which has been removed from the cubicle on a workbench designed
for electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
 Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Check the Shipment

Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required

The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this device is mounted in cubicles).
11.5 Device Location and Ambient Conditions

NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1. The location should not be exposed to excessive air pollution (dust, aggressive substances).
2. Surge voltages of high amplitude and short rise time, extreme changes of temperature, high
levels of humidity, severe vibration and strong induced magnetic fields should be avoided as
far as possible.

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3. Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
11.6 Mechanical Installation

NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
The device adopts IEC standard chassis and is rack with modular structure. It uses an integral
faceplate and plug terminal block on backboard for external connections. PCS-921 series is IEC
4U high. Figure 11.6-1 shows its dimensions and panel cut-out.
F ron t S id e
C u t-O u t
Figure 11.6-1 Dimensions and panel cut-out of PCS-921
Following figure shows the installation way of a module being plugged into a corresponding slot.

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11 Installation
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring

11.7.1 Grounding Guidelines
NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding

The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced
interference.

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11 Installation
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device

There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this device, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this device. Therefore, the ground terminal on the
rear panel (see Figure 11.7-2) is the only ground terminal of this device.

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11 Installation
Figure 11.7-2 Ground terminal of this device
11.7.4 Grounding Strips and their Installation

High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring
There are several types of cables that are used in the connection of this device: braided copper
cable, serial communication cable etc. Recommendation of each cable:
 AC voltage input: stranded conductor, 1.5mm 2
 AC current input: stranded conductor, 2.5mm 2
 Power supply, binary input & output: stranded conductor, 1.0mm 2 ~ 2.5mm2
 Earthing connection: braided copper cable, 2.5mm 2 ~ 6.0mm 2
 Serial communication: 4-core shielded cable
 Electrical Ethernet communication: 4-pair twisted shielded cable (category 5E)
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high

Date: 2015-07-15
11 Installation
voltage that cause death.
A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
Figure 11.7-4 Glancing demo about the wiring for electrical cables

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11 Installation

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12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................ 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-1
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-2
12.5.1 With the Device De-energized ......................................................................................... 12-3
12.5.2 With the Device Energized .............................................................................................. 12-5
12.5.3 On-load Checks ............................................................................................................... 12-6
12.6 Final Checks ................................................................................................ 12-7

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12 Commissioning

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12 Commissioning
12.1 Overview
This device is numerical in their design, implementing all functions in software. The device
employs a high degree self-checking, so in the unlikely event of a failure, it will give an alarm.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the device, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the device’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current

leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This
personnel MUST be familiar with all safety regulations and service procedures
described in this manual. During operating of electrical device, certain part of the
device is under high voltage. Severe personal injury and significant device damage
could result from improper behavior.
Particular attention must be drawn to the following:
 The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
 Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
 Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
 The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
 When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
may be close commands to the circuit breakers and other primary switches are disconnected
from the device unless expressly stated.
12.3 Commission Tools

Minimum equipment required:

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12 Commissioning
NOTICE!
Modern test set may contain many of the above features in one unit.
 Multifunctional dynamic current and voltage injection test set with interval timer.
 Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
 Continuity tester (if not included in the multimeter).
 Phase angle meter.
 Phase rotation meter.
Optional equipment:
 An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
 A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
 EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
 Tester: HELP-9000.
12.4 Setting Familiarization

When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this device is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 HMI software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
12.5 Product Checks

These product checks cover all aspects of the device which should be checked to ensure that it
has not been physically damaged prior to commissioning, is functioning correctly and all input
quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the device prior to commissioning, it is

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12 Commissioning
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the device itself via printer or manually creating a setting record.
12.5.1 With the Device De-energized
This device is fully numerical and the hardware is continuously monitored. Commissioning tests
can be kept to a minimum and need only include hardware tests and conjunctive tests. The
function tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
 Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
 User interfaces test
 Binary input circuits and output circuits test
 AC input circuits test
 Function tests
These tests are performed for the following functions that are fully software-based.
 Measuring elements test
 Timers test
 Conjunctive tests
The tests are performed after the device is connected with the primary equipment and other
external equipment.
 On load test.
 Phase sequence check and polarity check.
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the device case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed are
necessary.
 Device panel
Carefully examine the device panel, device inside and other parts inside to see that no
physical damage has occurred since installation.
 Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section

Date: 2015-07-15
12 Commissioning
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
 Device plug-in modules
Check each plug-in module of the equipment on the panel to make sure that they are well
installed into the equipment without any screw loosened.
 Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
 Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons
work normally and smoothly.
12.5.1.2 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
 Voltage transformer circuits
 Current transformer circuits
 DC power supply
 Optic-isolated control inputs
 Output contacts
 Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this device, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly
reconnected to the device.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant device diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.

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12 Commissioning
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
the Chapter “Technical Data”.
The device only can be operated under the auxiliary power supply depending on the device’s
nominal power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the device, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Device Energized
The following groups of checks verify that the device hardware and software is functioning
correctly and should be carried out with the auxiliary supply applied to the device.
The current and voltage transformer connections must remain isolated from the device for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the device to DC power supply correctly and turn the device on. Check program version
and forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “Clock”.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date
will be maintained. Therefore when the auxiliary supply is restored the time and date will be
correct and not need to set again.
To test this, remove the auxiliary supply from the device for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the device is healthy.
The device has latched signal devices which remember the state of the trip, auto-reclose when
the device was last energized from an auxiliary supply. Therefore these indicators may also
illuminate when the auxiliary supply is applied. If any of these LEDs are on then they should be

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12 Commissioning
reset before proceeding with further testing. If the LED successfully reset, the LED goes out.
There is no testing required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.6 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.7 Testing Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
The status of each binary input can be viewed using device menu. Sign “1” denotes an energized
input and sign “0” denotes a de-energized input.
12.5.3 On-load Checks
The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.

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12 Commissioning
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the device in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and
voltage transformer wiring.
12.6 Final Checks

After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the device in order to perform the wiring
verification tests, it should be ensured that all connections are replaced in accordance with the
relevant external connection or scheme diagram.
Ensure that the device has been restored to service.
If the device is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the device is put into service.
Ensure that all event records, fault records and alarms have been cleared and LED’s has been
reset before leaving the device.

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12 Commissioning

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13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................. 13-a
13.1 Appearance Check ...................................................................................... 13-1
13.2 Failure Tracing and Repair ......................................................................... 13-1
13.3 Replace Failed Modules ............................................................................. 13-2
13.4 Cleaning ....................................................................................................... 13-3
13.5 Storage ......................................................................................................... 13-3

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13 Maintenance

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13 Maintenance
This device is designed to require no special maintenance. All measurement and signal
processing circuit are fully solid state. All input modules are also fully solid state. The output relays
are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.1 Appearance Check

1. The device case should be clean without any dust stratification. Case cover should be sealed
well. No component has any mechanical damage and distortion, and they should be firmly
fixed in the case. Device terminals should be in good condition. The keys on the front panel
with very good feeling can be operated flexibly.
2. It is only allowed to plug or withdraw device board when the supply is reliably switched off.
Never allow the CT secondary circuit connected to this equipment to be opened while the
primary system is live when withdrawing an AC module. Never try to insert or withdraw the
device board when it is unnecessary.
3. Check weld spots on PCB whether they are well soldered without any rosin joint. All dual
inline components must be well plugged.
13.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “Superv State” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
1. Test circuit connections are correct
2. Modules are securely inserted in position
3. Correct DC power voltage is applied
4. Correct AC inputs are applied
5. Test procedures comply with those stated in the manual

Date: 2015-07-15
13 Maintenance
13.3 Replace Failed Modules
WARNING!
Module can ONLY be replaced while the device power supply is switched off.
ONLY appropriately trained and qualified personnel can perform the replacement by
strictly observing the precautions against electrostatic discharge.
WARNING!
Five seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Take anti-static measures such as wearing an earthed wristband and placing modules
on an earthed conductive mat when handling a module. Otherwise, electronic
components could be damaged.
CAUTION!
Check the device configuration after a replacement of module. Unintended operation of

device may occur.
If the failure is identified to be in the device module and the user has spare modules, the user can
recover the device by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, MON, BI, BO, etc.)
and hardware type-form as the removed module. Furthermore, the MON module replaced should
have the same software version. In addition, the AI and PWR module replaced should have the
same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Information”->“Version Info”.
1) Replacing a module
 Switch off the DC power supply
 Disconnect the trip outputs
 Short circuit all AC current inputs and disconnect all AC voltage inputs
 Unscrew the module connector
 Unplug the connector from the target module.

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13 Maintenance
 Unscrew the module.
 Pull out the module
 Inset the replacement module in the reverser procedure.
 After replacing the MON module, input the application-specific setting values again.
2) Replacing the Human Machine Interface Module (front panel)
 Open the device front panel
 Unplug the ribbon cable on the front panel by pushing the catch outside.
 Detach the HMI module from the device
 Attach the replacement module in the reverse procedure.
13.4 Cleaning
Before cleaning the device, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.5 Storage
The spare device or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40°C to +70°C, but the temperature of from 0°C
to +40°C is recommended for long-term storage.

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13 Maintenance

Date: 2015-07-15
Table of Contents
14 Decommissioning and Disposal ................................................. 14-a
14.1 Decommissioning ....................................................................................... 14-1
14.2 Disposal ....................................................................................................... 14-1

Date: 2015-07-15

Date: 2015-07-15
14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1. Switching off
To switch off this device, switch off the external miniature circuit breaker of the power supply.
2. Disconnecting cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3. Dismantling
The device rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.

Date: 2015-07-15

Date: 2015-07-15

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
R1.00 R1.00 2011-11-07 Form the original manual.
R1.00
R1.00 R1.01 and 2011-12-29 Chapter 3, Chapter 7 and Chapter 9 are amended.
R1.10
Modify remote control function.
Two system settings are added.
Two settings are added for VT circuit supervision module.
Add GOOSE alarm signals.
Modify logic of reclosing failure and success.
R1.01 R1.02 R2.00 2013-03-01 Add common alarm signal [Alm_Insuf_Memory].
Modify the breaking capacity of binary output contact.
Add symbol corresponding relationship about phase
sequence.
Add corresponding description about double circuit
breakers application.
R1.02 R1.03 R2.00 2013-06-21 Mechnical dimension of the device is changed.
Synchrocheck and automatic reclosure function are
R1.03 R1.04 R3.00 2013-10-22 modified, especially for the description related to
synchronism voltage and reference voltage.
R1.04 R1.05 R3.00 2013-11-18 Some technical data (section 2.7~2.9) are added.
The Section 3.15 “Control and Synchrocheck for Manual
R1.05 R1.06 R3.00 2014-01-15
Closing” are added.
Phase overcurrent protection and earth fault protection are
modified; overvoltage protection, undervoltage protection,
R1.06 R1.07 R3.00 2014-09-05
negative sequence overvoltage protection, frequency
calculation function and frequency protection are added.
Negative-sequence overcurrent protection is added;
BI, BO and AI modules are modified;
Some device settings and communication settings are
R1.07 R2.00 R3.10 2015-07-15
added;
Some measurement values are added;
GOOSE and DNP3.0 related contents are modified.
Some technical data are modified;
R2.00 R2.01 R3.10 2015-08-15
The Section “AI Plug-in Module (Analog Input)” in Chapter

Date: 2017-10-15
6 is modified
Jumpers configuration of clock synchronization port of
MON module is added;
Add system phase sequence selection, ABC or ACB;
Add the settings [En_Send_MMS_Qual_Chg],
[Opt_DualNetMode_MMS], [En_Ctrl_SLD] and
[En_PopupRecord_Blkd] in “device settings”;
Add the settings [IEDNAME] and [En_BICheckBO] in
“communication settings”;
R2.01 R2.02 R3.30 2016-07-15 DNP protocol related communication settings are added;
Add the menu “HMI Setup”;
Add the keypad operation: modify the time display format
and remote control via SLD;
Add the setting [Cfg_NetPorts_Bond] and its related
description;
Add the monitoring about bonding network ports;
Modify the lower limit of the setting [81O.OFx.t_Op] and
[81U.UFx.t_Op].
Section 3.20 is modified
R2.02 R2.03 R3.30 2017-06-15
Section 8.4 and Section 8.5.3 are added
The normally closed and normally open auxiliary contact in
the voltage selection logic diagram of Section 3.15.2.2 and
R2.03 R2.04 R3.40 2017-10-15
Section 3.15.2.3 are exchanged;
The device setting [En_RevCT] is added

Date: 2017-10-15

PCS-921 - X - Instruction Manual - EN - Overseas General - X - R2.05 Breaker Failure Relay

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Breaker Failure Relay

NR Electric Co., Ltd.

Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

Instructions and Warnings

PCS-921 Breaker Failure Relay i

Securely earthed the earthing terminal of the device.

ii PCS-921 Breaker Failure Relay

 Printed circuit board

Carefully handle connection cables without applying excessive force.

The firmware may be upgraded to add new features or enhance/modify existing

Copyright © 2017 NR. All rights reserved.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888

P/N: ZL_PCS-921_X_Instruction Manual_EN_Overseas General_X Version: R2.05

PCS-921 Breaker Failure Relay iii

All contents provided by this manual are summarized as below:

5 Measurement and Recording

8 Human Machine Interface

iv PCS-921 Breaker Failure Relay

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols are used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

OTH Input of other signal

PCS-921 Breaker Failure Relay v

XXX Output signal

IDMT Timer (inverse-time characteristic)

---xxx is the symbol

Symbol Corresponding Relationship

vi PCS-921 Breaker Failure Relay

1.1 Application....................................................................................................... 1-1

Figure 1.1-1 Function diagram of PCS-921............................................................................... 1-1

PCS-921 Breaker Failure Relay 1-a

1-b PCS-921 Breaker Failure Relay

59Q 81 50DZ 25 79 50/51Q

Figure 1.1-1 Function diagram of PCS-921

No. Function ANSI

PCS-921 Breaker Failure Relay 1-1

 Breaker failure protection (50BF)

 Three stages overvoltage protection (59)

 Three stages undervoltage protection (27)

 Negative sequence overvoltage protection (59Q)

 Residual overvoltage protection (59G)

 Frequency protection (81)

 Pole discrepancy protection (62PD)

 Dead zone protection (50DZ)

 Four stages overcurrent protection (50/51P)

 Four stages earth-fault protection (50/51G)

 Four stages negative sequence overcurrent protection (50/51Q)

2. Measurement and control function

 Remote control (open and closing)

 Synchronism check for remote and manual closing

 User programmable logic

 VT circuit supervision (VTS)

 CT circuit supervision (CTS)

 DC power supply supervision