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    The document discusses phase-locked loops (PLL) and clock and data recovery (CDR) circuits. It explains that PLLs are used to multiply clock frequencies from low-cost crystals to higher frequencies needed for communication links. PLLs maintain phase alignment while minimizing jitter and power. CDR circuits recover the clock from received data and align the sampling clock phase. Different types of phase detectors are described, including linear and bang-bang designs, as well as voltage-controlled oscillators and loop filters used in PLL and CDR systems.

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    The document discusses phase-locked loops (PLL) and clock and data recovery (CDR) circuits. It explains that PLLs are used to multiply clock frequencies from low-cost crystals to higher frequencies needed for communication links. PLLs maintain phase alignment while minimizing jitter and power. CDR circuits recover the clock from received data and align the sampling clock phase. Different types of phase detectors are described, including linear and bang-bang designs, as well as voltage-controlled oscillators and loop filters used in PLL and CDR systems.

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    Download as PDF, TXT or read online from Scribd
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    3 views3 pages

    Lecture24 PLL CDR 6up

    Uploaded by

    nadeemjutt
    The document discusses phase-locked loops (PLL) and clock and data recovery (CDR) circuits. It explains that PLLs are used to multiply clock frequencies from low-cost crystals to higher frequencies needed for communication links. PLLs maintain phase alignment while minimizing jitter and power. CDR circuits recover the clock from received data and align the sampling clock phase. Different types of phase detectors are described, including linear and bang-bang designs, as well as voltage-controlled oscillators and loop filters used in PLL and CDR systems.

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    © All Rights Reserved
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    of 3

    Linear Model cont’d

    EECS240 – Spring 2009

    Lecture 24: PLL and CDR Overview

    Elad Alon
    Dept. of EECS

    EECS240 Lecture 24 4 4

    Clock Generation Stability and Loop Bandwidth

    ÷N

    • Typical (low-cost) crystals give <500 MHz clock


    • 5 Gb/s link Æ where to get a 5 GHz clock?

    • PLL: multiply frequency up, align phase


    • While maintaining low jitter, power

    EECS240 Lecture 24 2 2 EECS240 Lecture 24 5 5

    PLL: Linear Model Loop Components: Phase Detectors


    • Basic idea: create pulses with width α to
    phase difference

    ÷N

    EECS240 Lecture 24 3 EECS240 Lecture 24 6


    Loop Filter Clock Recovery

    Skewed Ideal
    • Voltage margin strongly dependent on exact
    sampling position
    • How do we set the clock at the “best” place?

    EECS240 Lecture 24 7 7 EECS240 Lecture 24 10 10

    VCOs Conceptual CDR

    EECS240 Lecture 24 8 8 EECS240 Lecture 24 11 11

    Noise and Jitter System Types


    • (Source) Synchronous
    • Same frequency & phase

    • Mesochronous
    • Same frequency,
    unknown phase

    • Plesiochronous
    • Almost same frequency

    * From EE371, Stanford University


    EECS240 Lecture 24 9 9 EECS240 Lecture 24 12 12
    Linear (Hogge) Phase Detector

    EECS240 Lecture 24 13

    Bang-Bang (Alexander) Phase Detector

    Vin dn

    data Clk

    en

    edge Clk

    • Edge clock Tsym/2 away


    from data
    • Derive early/late from data
    and edge samples:
    • Dn: (dn != en) & (dn-1 != dn)
    • Up: (dn == en) & (dn-1 != dn)
    EECS240 Lecture 24 14 14

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