Bogotá, Colombia - July 11th, 2016: Microprocessors" With Me

This
document is a tutorial guide for professors and colleagues.

In this example, the reader will find the step-‐by-‐step soluIon to one of the
problems proposed in the second evaluaIon of 2016-‐10 period. This assessment
was worth 30% of the course and this quesIon was worth 20% of the evaluaIon.

Because the reader will be at a different, I will cover some topics that I do not
explain to first-‐year students in the course who have taken “So7ware for
Microprocessors” with me.

My goal with this problem was to evaluate the ability to transform a given
“Flowchart Diagram” into a “State-‐TransiCon Diagram” that describes a “Finite
State Machine in So7ware”.

My intenIon with this document is to show the relaIonship between flowcharts
and FSMs to share in a next delivery how it is taught the design of Embedded
Computer Systems by using Concurrent FSM. I believe in the effecIveness of the
approach as a tool to develop complex Embedded Computer Systems without
the need of using RTOS.

I would appreciate comments to my e-‐mail if you find this material somewhat
useful for you.

Best regards,
Ing. Juan C. Giraldo M.Sc.

jcgiraldo@javeriana.edu.co
Department of Electronics
School of Engineering
Bogotá, Colombia – July 11th, 2016

Ir order to tackle this issue, I proposed to develop this
document in the following order:

1.  The Problem Statement
2.  RepresentaIon of Graphs by Adjacency Matrices
3.  Flowcharts as Graphs
4.  Transforming a Flowchart into a FSM
5.  Coding an FSM
6.  Summary
7.  SuggesIons & Discussions

Bogotá, Colombia – July 11th, 2016

1. The Problem Statement

Adaptar el algoritmo de diagrama de flujo para el cálculo del determinante de
una matriz a Máquinas de Estados Finitos. La solución debe incluir el diagrama
con tabla de convención de estados y comentarios, así como su implementación
en Lenguaje C.

This flowchart computes determinant “det” of
square matrices “mtx” of “n” order in two steps:
Begin
(1)  Diagonal preparaIon (white symbols) and,
(2)  ComputaIon of trace (grey symbols)
Read
mtx & n
Variable “d” stands for “diagonal” and will guide

preparaIon of diagonal elements in order to
d = 0
perform following computaIon of trace (grey
symbols), which is the product of diagonal elements
yes
d<n-‐1
no
i = d + 1
yes
i < n
no mtx[d][d] must be
tmp =
mtx[i][d] / mtx[d][d] different to 0.0. If
so det=0.0 and exit
det = 1.0 d = d + 1
j = d If (j=0) “Diagonal
PreparaIon” will
become “Gaussian
d = 0 EliminaIon”
yes
j < n
no
yes mtx[i][j] -‐=
d < n tmp * mtx[d][j]
no
det *=mtx[d][d] i = i + 1
j = j + 1
Write
d = d + 1
det
End
So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Flowchart: Mtx_Determinant Elaborated by: Ing. Juan C. Giraldo M.Sc.
double!
Mtx_Determinant( double mtx[][COLS], int n )!
{!
Begin register int j, i, diagonal;!
double temporal, determinant = 1.0;!
!
for( diagonal = 0; diagonal < n-1; diagonal++ )!
Read for( i = diagonal+1; i < n; i++ ) {!
mtx & n temporal = mtx[i][diagonal]/mtx[diagonal][diagonal];!
for( j = diagonal; j < n; j++ )!
mtx[i][j] -= ( temporal*mtx[diagonal][j] );!
}!
d = 0 !
for( diagonal = 0; diagonal < n; diagonal++ )!
determinant = determinant * mtx[diagonal][diagonal];!
!
return determinant;!
!
yes } /* Mtx_Determinant */!
d<n-‐1
no ¡ Before the 4th week, students
i = d + 1 must be able to code a flowchart
in C language or to draw a
flowchart from a given code !
yes
i < n
no
tmp =
mtx[i][d] / mtx[d][d]
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

This flowchart performes Gaussian_EliminaIon of
matrices “mtx” of “n x n+1” dimensions. It leaves
Begin
lower triangular elements with zero. It applies
“loop inversion” to march decreasing counters.
Read
mtx & n
Variable “d” stands for “diagonal” and will guide

preparaIon of elements below diagonal elements in
d = n -‐ 1
order to leave them with zero values. This flowchart
is very similar to previous Mtx_Determinant.
yes
d > 0
no VariaIons to previous flowchart
i = d -‐ 1 could be used to design
algorithms for Gaussian
EliminaIon & Matrix Inversion
yes
i >= 0
no mtx[d][d] must be
tmp =
mtx[i][d] / mtx[d][d] different to 0.0.
d = d -‐ 1
j = 0 If (j<2n) flowchart
can be used with
Jordan to compute
Mtx_Inversion
yes
j <n+1
no
mtx[i][j] -‐=
tmp * mtx[d][j]
i = i -‐ 1
j = j + 1
End

Flowchart: Mtx_Gaussian_EliminaCon Elaborated by: Ing. Juan C. Giraldo M.Sc.
2. RepresentaIon of Graphs
by Adjacency Matrices
It is used a five-‐node graph to
remember how to represent this link
in an adjacency matrix.
A 5x5 matrix will be proposed, where

rows will be source nodes and
columns desIny nodes, then put
number “1” if there is a directed link
from node “A” to node “B.”
DesIny Nodes
Source Nodes
Node “B” is a terminal or “absorbing node” because every

possible link points to it and no link starts from this node.
Images taken from hrp://www.math.umaine.edu/~farlow/sec35.pdf

3. Flowcharts as Graphs
A BRIEF INTRODUCTION TO FLOWCHARTS AND SEQUENCES

The three basic construcIons in flowcharts are:
• Linear sequences.
• SelecIon sequences.
• RepeIIon sequences.

LINEAR SEQUENCES:
• A linear sequence can be ordered or disordered.
• The ordered sequence of instrucIons is organized one aver the another. In a
flowchart, instrucRons usually are drawn from the top of the page to the boSom.
• The disordered sequence of instrucIons is graphically represented by arrows or by
using numbers designaIng the order in which instrucIons must be executed.
ObservaRons:
• A pointer is represented graphically by an arrow or logically by an address.
• In the ordered sequence, arrows may be omired.
• There are jumps, but they ARE NOT CONDITIONED.
• An unordered sequence is spaIally disordered ... but logically ordered (We usually
called a linked list)

SELECTION SEQUENCES:
• A selecIon sequence can be of binary choice or mulIple choice.
• The bifurcaIon in a sequence of binary selecIon may be either binary or bypass.

REPETITION SEQUENCES:
• A repeIIon sequence may have a pre-‐test condiIon (while "condiIon holds" do
instrucIons) or may have a post-‐test condiIon (repeat instrucIons unIl “condiIon
appears”)
• The evaluaIon is done by a senInel condiIon or by a counIng controlled
condiIon.
• In a senInel, the condiIonals are queried by the occurrence of a parIcular event.
• A counIng controlled condiIonal is the same as a senInel condiIon with
controlling variable.
• A counIng controlled condiIon has the following four elements: (a) iniIaIon of
controlling variable, (b) query controlling variable, (c) increase controlling variable,
(d) execuIon of instrucIons.
Students are taught to differenIate
Begin “structure” from “funcIonality”, and similarly
the difference between “syntaxis” and
“semanIcs”.
Read
mtx & n
Another important issue is “abstracIon”
which is the eliminaIon of some irrelevant
d = 0 aspects at a certain level.
At the beginning, I will focus on

yes
“structure” mainly.
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

If we replace every symbol by a circle we can
Begin obtain a graph diagram to represent a
flowchart.
Read
mtx & n
To represent a flowchart as a
connected and directed graph…
d = 0
Instruccions will be nodes
yes
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

When every instrucIon is replaced by a node,
Begin the diagram conforms a legiImal connected
graph.

Read mtx & n; The objecIve of a flowchart is performing a
sequence from “Begin” to “End”. In the
terminology of graphs the last instrucIon is
d = 0; an absorbent node.

The objecIve of this specific algorithm is
compuIng determinant and “wriIng result.”
d<n-‐1
yes
no
i = d + 1;
i < n
yes
no
tmp = mtx[i][d] / mtx[d][d];
det = 1.0;
d = d + 1;
j = d;
d = 0;
j < n
yes
d<n no
yes mtx[i][j] -‐=
tmp * mtx[d][j];
no
det *= i = i + 1;
mtx[d][d];
j = j + 1;
Write det; d = d + 1;
End

When we fuse some nodes, connected
Begin
graph can be slightly simplified.
Read mtx & n;

d = 0;
d<n-‐1
yes
no
i = d + 1;
i < n
yes
no
det = 1.0;
d = d + 1; tmp = mtx[i][d] / mtx[d][d];
d = 0;
j = d;
j < n
yes
d<n no
yes mtx[i][j] -‐=
tmp * mtx[d][j];
no det *= j = j + 1;
mtx[d][d]; i = i + 1;
d = d + 1;
Write det;
End

DesIny Nodes
Begin
Source Nodes
A Read mtx & n;
d = 0;
d<n-‐1
yes
B
no
C i = d + 1;
i < n
yes
D
no
J det = 1.0;
I d = d + 1; tmp = mtx[i][d] / mtx[d][d];
d = 0; E j = d;
j < n
yes
F
d<n no
K
yes mtx[i][j] -‐=
tmp * mtx[d][j];
G
no det *= j = j + 1;
L mtx[d][d]; H i = i + 1;
d = d + 1;
M Write det;
End

Every single node
may be considered
an atomic instrucIon
ConnecIvity of nodes

describing all the sequences

This “seems” a linear sequence
But it is not because of black circles connecCng “RepeCCon Sequences”
Disjointed parts of flowchart

Connected by common node “9”

Beginnig node
Ending (absorbent) node

Nodes with bifurcaIon
Nodes with arrivals

4.  Transforming
a Flowchart into a FSM
Flowcharts and Finite State Machines can be modeled by
using Connected Directed Graphs.

Connected Directed Graphs are composed of nodes and
directed links. From an iniIal node, it is possible to WALK
through every single node in the Connected Directed Graph.

In Flowcharts, instrucIons are nodes and pointers to
following instrucIons are links. What triggers the iniIaIon of
the next instrucIon is the compleIon of the previous one. At
a machine level, links can be understood as a pointer to next
instrucIon or Program Counter (PC).

In Finite State Machines, states are nodes and transiIons are
links. Every transiIon is the pair (condiIon plus instrucIon).
What triggers the change of a state is an event or condiIon.
An event may be internal or external. Internal events might be
triggered by condiIons when comparing internal variables.
External events might be inputs.

Finally, let us remember that Outputs can be predicted from
the present State of the Finite State Machine and current
Inputs at a present Ime.

ALTHOUGH FLOWCHARTS ARE USED FOR SOFTWARE AND
FINITE STATE MACHINES ARE USED FOR HARDWARE, ONE
MAY WONDER IF:
A Finite State Machine can be obtained from a Flowchart, and
a Flowchart can be obtained from a Finite State Machine.
S tate
Image taken from
hrps://images-‐na.ssl-‐images-‐amazon.com/images/I/51X9eyt%2BJ2L._SX396_BO1,204,203,200_.jpg
“A state is a situaIon or condiIon in the life of a system during

which some (usually implicit) invariant holds, the system
performs some acIvity, or the system waits for some external
event [OMG 01].”

“A state captures the relevant aspects of the system's history very
efficiently. For example, when you strike a key on a keyboard, the
character code generated will be either an uppercase or a
lowercase character, depending on whether the Caps Lock is
acIve. Therefore, the keyboard is in the capsLocked state, or the
default state (most keyboards have an LED that indicates when
the keyboard is in the capsLocked state). The behavior of a
keyboard depends only on certain aspects of its history, namely
whether Caps Lock has been acIvated, but not, for example, on
how many and which specific characters have been typed
previously. A state can abstract away all possible (but irrelevant)
event sequences and capture only the relevant ones.”

Miro Samek In
“PracCcal Statecharts in C/C++:
Quantum Programming for Embedded Systems”
1 “A state is a situaIon or condiIon in the life of a system
during which some (usually implicit) invariant holds, …”

This is the fuzzy case and from my understanding THE
MOST important.

At a Ime when an invariant holds… is the point of
execuIon where you may halt the system, store all the
context in a permanent memory, turn off the system, wait
a while, turn on the system again, retrieve the context
including the point where you stopped execuIon, and
conInue working as if NOTHING had happened… in other
words… invariant holds.

This situaIon let the users change the context between to
different tasks to allow concurrency.

during which … the system performs some acIvity, …”

When naming a STATE, I recommend my students to use
v e r b s i n g e r u n d w i t h – I N G t e r m i n a I o n i . e .
PROCESSING_DATA, COMPUTING_TRACE, etc.

during which … the system waits for some external event.”

Similarly… WAITING_DATA, WAITING_RESPONSE, etc.

The algorithm to transform a flowchart into a FSM

cannot be any simpler:

“Nodes will be Links,

and

Links will be Nodes”

To convert the flowchart into a Finite State
Begin Machine, every link is idenIfied as a possible
node or state in FSM. ExcepIons will be, links
between a condiIonal and following
Read
mtx & n instrucIons.
d = 0
yes
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

To convert the flowchart into a Finite State
Begin Machine, every link is idenIfied as a possible
node or state in FSM. ExcepIons will be, links
between a condiIonal and following
Read
mtx & n instrucIons.

In this diagram, red links in the flowchart will
d = 0 be converted into nodes in the FSM. Dash
blue links won’t be converted at all.
yes
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

Begin
Read
mtx & n
d = 0
yes
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

Do you Remember the nodes in the Connected
Begin Directed Graph representaIon of flowchart?

Well, I put that diagram in background.
The excepRons are the condiRonal nodes because I
fused them with following instrucRons.

Very soon, this will be explained and clarified.

Because the counIng of WHITE BIG nodes
here is 14, there will be 14 links in FSM.
yes
no
yes
no
yes
no
yes
no
End

Please, check the counIng of links.
Begin
¿It is 14, right?

Now, we are ready to recover every instrucIon
wriren as a pair ( condiIon / instrucIon )
yes
no
yes
no
yes
no
yes
no
End

Every orginal instrucIon in a linear sequence will be the pair: (NULL / instrucIon).
NULL / Read mtx & n; Now, it might be lirle bit clear the reason I fused
condiIonal and following node in just one node.
NULL / d = 0;
d<n-‐1 / i = d + 1;
Now, we can simplify the graph in a

two-‐step process…
1. Choosing only some STATES
d>=n-‐1 /
det = 1.0;
i < n /
i >= n /
d = d + 1;
NULL / j = d;
NULL / d = 0;
j < n /
d<n /
d>=n / mtx[i][j] -‐=
det *=
Write tmp * mtx[d][j];
mtx[d][d];
det; j >= n /
i = i + 1;
NULL /
j = j + 1;
NULL / d = d + 1;

FSM: Mtx_Determinant Elaborated by: Ing. Juan C. Giraldo M.Sc.
Aver

NULL / Read mtx & n; 1. Choosing only some STATES

We can then…
NULL / d = 0;
2. Fuse some transiIons
d<n-‐1 / i = d + 1;
d>=n-‐1 /
det = 1.0;
i < n /
i >= n /
d = d + 1;
NULL / j = d;
NULL / d = 0;
j < n /
d<n /
d>=n / mtx[i][j] -‐=
det *=
mtx[d][d];
det; j >= n /
i = i + 1;
NULL /
j = j + 1;
NULL / d = d + 1;

NULL / Read mtx & n;
NULL / d = 0;
d<n-‐1 / i = d + 1;
d>=n-‐1 /
det = 1.0;
i < n /
i >= n /
d = d + 1;
NULL / j = d;
NULL / d = 0;
j < n /
d<n /
d>=n / mtx[i][j] -‐=
det *=
mtx[d][d];
det; j >= n /
i = i + 1;
NULL /
j = j + 1;
NULL / d = d + 1;

Now, some arrangement is desirable…
NULL /
Read mtx & n;
d = 0;
d<n-‐1 / i = d + 1;
d>=n-‐1 /
det = 1.0;
d = 0;
i < n /
j = d;
i >= n /
d = d + 1;
j < n /
mtx[i][j] -‐=
d>=n / tmp * mtx[d][j];
Write j = j + 1;
det; j >= n /
d<n /
i = i + 1;
det *=
mtx[d][d];
d = d + 1;

Let us…

1.  Assign idenIfiers to states.
2.  Explain the FSM and comment.
NULL /
Read mtx & n; 3.  Finally, check that we idenIfy the
d = 0; author, filiaIon, and any other
relevant informaIon.
d<n-‐1 / i = d + 1;
d>=n-‐1 /
det = 1.0;
d = 0;
i >= n /
d = d + 1;
i < n /
j = d;
j >= n /
i = i + 1;
d<n /
det *=
j < n /
mtx[d][d];
mtx[i][j] -‐=
d = d + 1;
tmp * mtx[d][j];
j = j + 1;
d>=n /
Write det;

Esta FSM calcula el determinante “det” de matrices
No. ESTADO
cuadradas “mtx” de orden “n” en dos pasos:
(1)  Preparación de Diagonal y, 0 RUNNING_SUBMTX
(2)  Cálculo del “trace” (estado verde)
1 RUNNING_ROWS
2 RUNNING_COLS
NULL /
Read mtx & n; 3 COMPUTING_TRACE
d = 0;
d<n-‐1 / i = d + 1;
0
d>=n-‐1 /
det = 1.0;
d = 0; 1
i >= n /
d = d + 1;
i < n /
j = d;
j >= n /
i = i + 1;
2
d<n /
det *=
3 mtx[d][d];
j < n /
mtx[i][j] -‐=
d = d + 1;
tmp * mtx[d][j];
j = j + 1;
d>=n /
Write det;

Esta FSM calcula el determinante “det” de matrices
No. ESTADO
cuadradas “mtx” de orden “n” en dos pasos:
(1)  Preparación de Diagonal (estados blancos) y, 0 RUNNING_SUBMTX
(2)  Cálculo del “trace” (estado gris)
1 RUNNING_ROWS
A 2 RUNNING_COLS
NULL /
Read mtx & n; 3 COMPUTING_TRACE
d = 0;
B
d<n-‐1 / i = d + 1;
0
C
d>=n-‐1 /
det = 1.0;
d = 0;
E 1
i >= n / D
d = d + 1;
i < n /
j = d;
G
j >= n /
i = i + 1;
H 2 F
d<n /
det *=
3 mtx[d][d];
j < n /
mtx[i][j] -‐=
d = d + 1;
tmp * mtx[d][j];
j = j + 1;
I
d>=n /
Write det;

No. ESTADO
0 RUNNING_SUBMTX
1 RUNNING_ROWS
2 RUNNING_COLS
3 COMPUTING_TRACE
You could ask to your students the following quesIons:

•  How long does it take a processor to execute every transiIon?
•  Which does it take longest and shortest Ime?
•  Can this Ime be accurately measured?
A flowchart represented by an Adjaceny Matrix
vs.
A FSM represented by an Adjaceny Matrix
Research quesIon:

¿Could this process be automaIcally systemaIzed?

Of course, It can be… ¿Why not?
Aver many exercises, the RULE OF
Begin
THUMB that students may infer about:

Read
mtx & n Could it be possible to esRmate the
number of states from a flowchart?
d = 0
Count the number of condiIonals
yes
d<n-‐1
no
i = d + 1
yes
i < n
no
tmp =
det = 1.0 d = d + 1
j = d
d = 0
yes
j < n
no
yes mtx[i][j] -‐=
no
j = j + 1
Write
d = d + 1
det
End

Flowchart & FSM: Mtx_Determinant Elaborated by: Ing. Juan C. Giraldo M.Sc.
Here we can see the
mapping of elements
between the flowchart
and the final FSM.

Flowchart & FSM: Mtx_Determinant Elaborated by: Ing. Juan C. Giraldo M.Sc.
5. Coding an FSM
You must idenIfy the STATES. You may use symbolic constants
1
!
#define RUNNING_SUBMTX 0!
!
#define RUNNING_ROWS 1!
!
#define RUNNING_COLS 2!
!
#define COMPUTING_TRACE 3!
!
… but I reccomend the use of “enum” type, because you do not have to think of
labeling every idenIfier with numbers:
! !
typedef enum STATE_T STATE_T;! typedef enum STATE_T STATE_T;!
enum STATE_T {! enum STATE_T {!
! !
!RUNNING_SUBMTX,! !RUNNING_ROWS,!
! !
!RUNNING_ROWS,! !COMPUTING_TRACE,!
! !
!RUNNING_COLS,! !RUNNING_SUBMTX,!
! !
!COMPUTING_TRACE! !RUNNING_COLS!
! !
};! };!
! !
I suggest to introduce a NEW “BOOLEAN” variable “finish” to indicate the
2 temporary halt in the execuIon of the Finite State Machine to QUIT the
repeIIon sequence when MACHINE reaches the ending point.
!
typedef enum BOOLEAN BOOLEAN;!
enum BOOLEAN {!
!
!FALSE,!
!
!TRUE!
!
};!
!
double!
There are some strategies to
3
{!
int diagonal, i, j;!
implement a FSM but the use of
double tmp, determinant = 1.0;! a “switch-‐case” proposiIon is
int finish = FALSE;!
STATE_T state;! very easy to use, teach,
!
diagonal = 0;! implement, and test.
state = RUNNING_SUBMTX;!
!
while( ! finish ) {!
!
switch( state ) {!
!
case RUNNING_SUBMTX:!
if( diagonal < n-1 ) {!
i = diagonal + 1;!
state = RUNNING_ROWS;!
} else {!
determinant = 1.0;!
diagonal = 0;!
state = COMPUTING_TRACE;!
}!
break;!
!
case RUNNING_ROWS:!
if( i < n ) {!
tmp = mtx[i][diagonal] /!
mtx[diagonal][diagonal];! This “while” loop is THE ENGINE
j = diagonal;!
state = RUNNING_COLS;! of the Finite State Machine:
} else {!
diagonal = diagonal + 1;!
}! ExecuIon is done unIl an event
break;!
! defined with variable “finish” is
case RUNNING_COLS:!
if( i < n ) {! reached, otherwise…
mtx[i][j] -=!
( tmp / mtx[diagonal][j] );!
j = j + 1;!
state = RUNNING_COLS;! “while NOT finish, … FSM will
} else {!
i = i + 1;! keep working”.
}!
break;!
!
case COMPUTING_TRACE:!
if( diagonal < n ) {!
determinant *=!
mtx[diagonal][diagonal];!
} else {!
finish = TRUE;!
}!
break;!
!
} /* switch */!
!
} /* while */!
!
!
} /* Mtx_Determinant */!
!
double! double!
Mtx_Determinant( double mtx[][COLS], int n )! Mtx_Determinant( double mtx[][COLS], int n )!
{! {!
int diagonal, i, j;! int diagonal, i, j;!
The order of “case” proposiIons is not important,

double tmp, determinant = 1.0;!
as long as connecIvity among nodes be right.

STATE_T state;! STATE_T state;!
! !
diagonal = 0;! diagonal = 0;!
state = RUNNING_SUBMTX;! state = RUNNING_SUBMTX;!
! !
while( ! finish ) {! while( ! finish ) {!
! !
switch( state ) {! switch( state ) {!
! !
case RUNNING_SUBMTX:! case COMPUTING_TRACE:!
if( diagonal < n-1 ) {! if( diagonal < n ) {!
i = diagonal + 1;! determinant *=!
state = RUNNING_ROWS;! mtx[diagonal][diagonal];!
} else {! diagonal = diagonal + 1;!
determinant = 1.0;! state = COMPUTING_TRACE;!
diagonal = 0;! } else {!
state = COMPUTING_TRACE;! finish = TRUE;!
}! }!
break;! break;!
! !
case RUNNING_ROWS:! case RUNNING_COLS:!
if( i < n ) {! if( i < n ) {!
tmp = mtx[i][diagonal] /! mtx[i][j] -=!
mtx[diagonal][diagonal];! ( tmp / mtx[diagonal][j] );!
j = diagonal;! j = j + 1;!
state = RUNNING_COLS;! state = RUNNING_COLS;!
} else {! } else {!
diagonal = diagonal + 1;! i = i + 1;!
state = RUNNING_SUBMTX;! state = RUNNING_ROWS;!
}! }!
break;! break;!
! !
case RUNNING_COLS:! case RUNNING_SUBMTX:!
if( i < n ) {! if( diagonal < n-1 ) {!
mtx[i][j] -=! i = diagonal + 1;!
( tmp / mtx[diagonal][j] );! state = RUNNING_ROWS;!
j = j + 1;! } else {!
state = RUNNING_COLS;! determinant = 1.0;!
} else {! diagonal = 0;!
i = i + 1;! state = COMPUTING_TRACE;!
state = RUNNING_ROWS;! }!
}! break;!
break;! !
! case RUNNING_ROWS:!
case COMPUTING_TRACE:! if( i < n ) {!
if( diagonal < n ) {! tmp = mtx[i][diagonal] /!
determinant *=! mtx[diagonal][diagonal];!
mtx[diagonal][diagonal];! j = diagonal;!
diagonal = diagonal + 1;! state = RUNNING_COLS;!
state = COMPUTING_TRACE;! } else {!
} else {! diagonal = diagonal + 1;!
finish = TRUE;! state = RUNNING_SUBMTX;!
}! }!
break;! break;!
! !
} /* switch */! } /* switch */!
! !
} /* while */! } /* while */!
! !
return determinant;! return determinant;!
! !
} /* Mtx_Determinant */! } /* Mtx_Determinant */!
! !
The ENGINE of the FS-‐MACHINE
double!
{!
int diagonal, i, j;!
STATE_T state;!
!
diagonal = 0;!
!
while( ! finish ) {!
!
switch( state ) {!
!
case RUNNING_SUBMTX:!
if( diagonal < n-1 ) {!
i = diagonal + 1;!
} else {!
determinant = 1.0;!
diagonal = 0;!
}!
break;!
! These lines are not mandatory, but I
case RUNNING_ROWS:!
if( i < n ) {! STRONGLY recommend my students
tmp = mtx[i][diagonal] /!
using them, no marer if the FSM will
j = diagonal;!
state = RUNNING_COLS;!
be in same state next transiIon.
} else {!
state = RUNNING_SUBMTX;! “I don’t want to find mistakes
}!
break;!
because of omissions, so that, the
!
case RUNNING_COLS:!
transiRons to following states MUST
if( i < n ) {! be explicit.”
mtx[i][j] -=!
( tmp / mtx[diagonal][j] );!
j = j + 1;!
state = RUNNING_COLS;!
} else {!
i = i + 1;!
}!
break;!
!
case COMPUTING_TRACE:!
if( diagonal < n ) {!
determinant *=!
} else {!
finish = TRUE;!
}!
break;!
!
!
} /* switch */!
These could be omired but I
} /* while */!
!
recommend ALWAYS using them,
!
no marer if only one proposiIon
} /* Mtx_Determinant */!
!
is used INSIDE.
Although both segments are RIGHT,
I recommend my students to use
the one at the right!!!
! !
case RUNNING_SUBMTX:! case RUNNING_SUBMTX:!
if( diagonal < n-1 ) {! if( diagonal < n-1 ) {!
i = diagonal + 1;! i = diagonal + 1;!
state = RUNNING_ROWS;! state = RUNNING_ROWS;!
} else if( diagonal >= n-1 ) {! } else {!
determinant = 1.0;! determinant = 1.0;!
diagonal = 0;! diagonal = 0;!
state = COMPUTING_TRACE;! state = COMPUTING_TRACE;!
}! }!
break;! break;!
! !
In this example, selecIon sequences inside every STATE (case)

were binary choices to test transiIons. In an Embedded
Computer System YOU MUST prioriIze:
!
case ANY_STATE:!
if( event_0() ) {!
instruction_0();! 1st priority
state = NEXT_STATE_0;!
} else if( event_1() ) {!
instruction_1();!
2nd priority
state = NEXT_STATE_1;!
} else if( event_2() ) {!
instruction_2();!
state = NEXT_STATE_2;! 3rd priority
} else { // everything else!
instruction_3();!
state = ANY_STATE;!
Last priority
}!
break;!
!
6. Summary
SUMMARY (1/4)
Flowcharts Finite State Machine

Flowcharts are usually used for FSMs are usually used for
designing, and analyzing designing, and analyzing
sovware. hardware.
When a flowchart is When a FSM is represented by a
represented by a graph, nodes graph, nodes are states and
are instrucIons and links are links are transiIons composed
pointers to following by the pair condiIon /
instrucIons. instrucIon.
Flowcharts are meant to FSMs are meant to query a set
process a flow of instrucIon of events at the input and react
sequences. to them at the output.
Flowcharts are meant to reach FSMs are meant to keep going,
an ending point, and stop and never stop.
running.
A flowchart begins whenever it A FSM begins once and never
is required, performs a task and stops. The context MUST be
stops. The context is destroyed. stored all the Ime for the state
This never happens when you to be monitored.
implement co-‐rouCnes, but you
need a very good knowledge in
Assembly Language to do so.
Reaching an absorbing or Absorbing nodes MUST BE
ending node is THE GOAL. AVOIDED by Ime-‐outs or
watchdog mechanisms.
SUMMARY (2/4)

Inputs are mandated by the Inputs are mandated by
program at specific points of the environment or users whenever
flow: Flowchart WAITS unIl they are required. If an input is
inputs are entered as if they not completely entered, there
were blocking calls. must be Ime-‐out mechanisms.
Calls MUST be non-‐blocking.
The most important thing is The most important thing is
devising good processes. devising mechanisms for the
arenIon of inputs giving
outputs on Ime.
Every instrucIon is executed in Every input, every output, every
sequence ONCE AT A TIME. process “could seem” to be
executed ALL THE TIME. System
must be ROBUST to do so.
For the flowchart, all the For the FSM, resources are
resources are available for the meant to be shared, and THE
task. Resources are memory, main resource to be shared is
processing power, input/ THE PROCESSOR.
outputs.
Time to process a task is not Time is a MUST, always. Time
important… what it takes is OK, diagrams are mandatory. FSMs
depending on processor’s must deal with responses in
speed. Time diagrams seem to human Ime and machine Ime.
be irrelevant at this level.
SUMMARY (3/4)

Programming without a Programming without an FSM
flowchart is possible, and it is diagram IS VERY HARD and
very likely to work well. unlikely to work well.
Recognizing visually what the Recognizing visually what the
flowchart does is possible. FSM does is impossible (at least
for me).
Re-‐configuraIon in execuIon If the FSM is coded carefully, it
Ime is NOT easy. A quesIon can be re-‐configurable on
that might rise: EXECUTION Ime. This is a VERY
Why would be this useful? NICE goal in advanced courses.
Re-‐use of available and limited Why is this useful?
resources. A learning machine, perhaps.
TransiIon to digital hardware TransiIon to digital hardware
design is NOT direct because design is direct because you
you can not design hardware as must think of inter-‐independent
if you were programming. modules as if they were
different blocks.
Desk tesIng is somewhat easy. Desk tesIng is challenging.
You just follow THE FLOW of Inputs might come anyIme,
sequences toward the ending which produces mulIple
node. bifurcaIons. The stop condiIon
is difficult to idenIfy.
Debugging may seem to be Finding a BUG is auwful. Similar
easy. It is not desirable, but you to digital systems, so that
may design, code and debug at designing process must be
the same Ime. STRICT.
SUMMARY (4/4)

THE SKILL to be developed: THE SKILL to be developed:
Algorithmic Thinking. Systemic Thinking.
Nice tool for Sovware Nice tool for Electronic
Engineers. Engineers.
Killer applicaIon: CompuIng Killer complex applicaIon:
processes. RoboIcs is an example.
Embedded Computer Systems
in general.
7. SuggesIons & Discussion
PLEASE, never, ever, ever, ever, … introduce Finite State
Machine by transforming a flowchart into an FSM.

Personally, I think THIS IS NOT THE WAY.

FIRST: I recommend teaching this relaIonship once students
have worked a lot of designings of many FSM from the
ground.

SECOND: In my first experiences with this course, I tried to
teach FSM by designing, but I have found that the best
approach to teaching FSM is by performing many desk
tesIngs to exisIng FSM.

This way… I am teaching FIRST: HOW TO TEST and then: HOW
TO DESIGN. For me, this is the best order in so3ware, but
your opinions and suggesRons are widely welcomed!!!

Other suggesIons, when students are involved in designing,
you can suggest that their classmates perform DESK TESTING
each other, in a peer review approach!

THIRD: Do whatever you want i.e.: OPTMIZINING, STUDY O
CASES, REVERSE ENGINEERING, ANALYZING, MEASURING
PERFORMANCE.

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This

document is a tutorial guide for professors and colleagues.

Ing. Juan C. Giraldo M.Sc.

Bogotá, Colombia – July 11th, 2016

Bogotá, Colombia – July 11th, 2016

Variable “d” stands for “diagonal” and will guide

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Variable “d” stands for “diagonal” and will guide

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

A 5x5 matrix will be proposed, where

Node “B” is a terminal or “absorbing node” because every

Images taken from hrp://www.math.umaine.edu/~farlow/sec35.pdf

At the beginning, I will focus on

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Read mtx & n;

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

ConnecIvity of nodes

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Disjointed parts of ﬂowchart

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Ending (absorbent) node

Nodes with arrivals

“A state is a situaIon or condiIon in the life of a system during

2 “A state is a situaIon or condiIon in the life of a system

3 “A state is a situaIon or condiIon in the life of a system

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

Now, we can simplify the graph in a

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

You could ask to your students the following quesIons:

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

So3ware for Microprocessors @ “Electrónica Javeriana” – Bogotá – Colombia

The order of “case” proposiIons is not important,

as long as connecIvity among nodes be right.

In this example, selecIon sequences inside every STATE (case)

Flowcharts Finite State Machine

Flowcharts Finite State Machine

Flowcharts Finite State Machine

Flowcharts Finite State Machine

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