Ink-jet printed ZnO nanowire field effect transistors

Yong-Young Noh, Xiaoyang Cheng, Henning Sirringhaus, Jung Inn Sohn, Mark E. Welland et al.

Citation: Appl. Phys. Lett. 91, 043109 (2007); doi: 10.1063/1.2760041

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 APPLIED PHYSICS LETTERS 91, 043109 共2007兲

Ink-jet printed ZnO nanowire field effect transistors

Yong-Young Noh,a兲 Xiaoyang Cheng, and Henning Sirringhaus
OE Group, Cavendish Laboratory, University of Cambridge, J. J. Thomson Avenue,
Cambridge CB3 0HE, United Kingdom
Jung Inn Sohn and Mark E. Welland
Nanoscience Centre, University of Cambridge, J. J. Thomson Avenue,
Cambridge CB3 0FF, United Kingdom
Dae Joon Kang
BK 21, Physics Research Division, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University,
Suwon 440-746, Korea and Center for Nanotubes and Nanostructured Composites, Sungkyunkwan
University, Suwon 440-746, Korea
共Received 30 May 2007; accepted 26 June 2007; published online 26 July 2007兲
Semiconducting nanowires provide routes for realizing high-performance electronic devices, but for
many applications of such devices low-cost manufacturing techniques are needed. The authors
demonstrate here top-gated zinc oxide nanowire field effect transistors 共NW-FETs兲 fabricated by
ink-jet printing. High resolution submicrometer gold gaps between source and drain electrodes were
defined by a self-aligned ink-jet printing technique, and the nanowires were deposited from solution
onto these electrode arrays and gated from the top using a spin-coated poly共methyl methacrylate兲
gate dielectric. The typical NW-FETs exhibited a mobility of 2 – 4 cm2 / V s, a current on/off ratio of
104, and a transconductance of 20.5 nS. The process provides a pathway for fabrication of NW-FETs
by low-cost, large-area solution processing and direct printing techniques. © 2007 American
Institute of Physics. 关DOI: 10.1063/1.2760041兴

Inorganic semiconductor nanowire field effect transistors
共NW-FETs兲 have recently attracted significant attention as
they potentially allow combining high device performance
with the attractive features of solution processing for appli-
cations such as gas or biological sensors, flexible displays,
memory, and ambient intelligent devices.1–4 The perfor-
mance of NW-FETs has been much improved through
growth of high-quality materials, optimized device geometry,
encapsulation of the nanowire, and improvement of contact
resistance.5–8 Nevertheless, several key challenges remain to
be addressed. One of them is the development of low-cost
manufacturing processes based on direct-write printing tech-
niques, which make full use of the compatibility of the nano-
wires with solution processing. The application of graphic-
art printing techniques to solution-based patterning of
functional materials is considered as a promising paradigm
for manufacturing of large-area, low-cost electronic circuits
on flexible substrates.9 In the literature to date, most NW-
FETs have been fabricated using short channel source-drain
electrode patterns defined by slow, conventional processes
such as electron beam lithography. Using printing technique
to contact the nanowire poses several problems. On the one
hand the relatively short length of the nanowires of typically
less than 10 ␮m requires printing techniques with suffi-
ciently high resolution that can define reliable contacts to the
two ends of the nanowire. This excludes many graphic-art
printing techniques such as offset or gravure printing the
resolution of which is limited to 20– 50 ␮m with presently
available equipment. On the other hand the formation of a
good Ohmic contact to the nanowire 共NW兲 is essential to
achieve a good performance. However, little is known about
how to form an Ohmic contact between a metal and an inor-
ganic semiconductor if the interface is formed from solution.
a兲
Electronic mail: yyn21@cam.ac.uk
A particularly interesting class of materials for solution
processed NW-FETs is the metal oxide semiconductor such
as zinc oxide 共ZnO兲 共Ref. 10兲 or tin dioxide 共SnO2兲 NWs.11
They are environmentally stable, and when exposed to air
they do not form insulating surface oxides. This makes for-
mation of an Ohmic contact using simple solution processing
less difficult than it would be, for example, for a silicon
nanowire. Here we report on a methodology for integrating
ZnO NW into all-solution processed and printed field effect
transistors 共FETs兲. In order to contact ZnO nanowires of
typically 5 ␮m length, we use a recently developed self-
aligned ink-jet printing 共SAP兲 technique. The SAP technique
allows defining electrode patterns of conducting polymers
such as poly共3,4-ethylenedioxithiophene兲 doped with poly-
共styrene sulfonate兲 共PEDOT:PSS兲 or metal 关gold 共Au兲, sil-
ver兴 nanoparticle ink with channel lengths of
50– 400 nm.12,13 The SAP process is based on defining the
electrode pattern in two steps. In a first printing or other
patterning step, a first electrode is defined, the surface of
which is then modified to become dewetting to the ink for a
second conductive electrode. The ink flows off the surface of
the first electrode and dries in close proximity, but not in
electrical contact to the edge of the first electrode pattern.
Using simple ink-jet printing equipment, a small gap can
thus be defined between the two electrodes in a reliable man-
ner with high yield.
The ZnO NW-FETs were fabricated in a top-gate device
configuration by an all-solution process. A submicrometer
ink-jet pattern was realized by SAP of Au nanoparticle ink
onto a prefabricated first Au electrode, the surface of which
was modified with fluorinated self-assembled monolayer
关Figs. 1共a兲 and 1共b兲兴. ZnO NWs were deposited on the pat-
tern by spin casting or ink-jet printing of a highly diluted
isopropanol 共IPA兲 共spin coating兲 or IPA and ethylene glycol
mixture 共ink-jet printing兲 solution of the NWs

0003-6951/2007/91共4兲/043109/3/$23.00 91, 043109-1 © 2007 American Institute of Physics

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 043109-2 Noh et al.
FIG. 1. 共Color online兲 共a兲 Schematic diagram of the self-aligned ink-jet
printing 共SAP兲 process. 共b兲 Example of the SAP pattern observed by a
transmittance mode of an optical micrograph 共scale bar: 100 ␮m兲 with the
enlarged view of the indicated area shown as an atomic force microscope
共AFM兲 image 共2 ⫻ 2 ␮m2兲 on the top. 共c兲 Optical micrograph view, 共d兲
AFM 共6.2⫻ 6.2 ␮m2兲 and 共e兲 scanning electron microscope image of a
single ZnO NW placed across the SAP gap 共length of ZnO NW: 5 ␮m兲.
关Figs. 1共c兲–1共e兲兴. The top-gated transistor was completed by
spin coating of poly共methyl methacrylate兲 共PMMA兲 and ink-
jet printing of PEDOT:PSS as the gate dielectric and gate
electrode, respectively. Corning 7059 glass slides were used
as substrates after cleaning sequentially with acetone and
IPA for 10 min in each step and then rinsing with de-ionized
water. The first electrode Au was patterned using conven-
tional lift-off photolithography technique into an ink confine-
ment structure comprising two Au pads separated by a gap of
typical 50 ␮m dimension 关see Fig. 1共b兲兴. The surface of the
first Au electrode was modified by 1H, 1H, 2H,
2H-perflourodecanethiol 共Fluorochem Ltd., UK兲 using Au-
thiol chemistry to get perfect dewetting of the subsequently
printed Au nanoparticle ink. The Au nanoparticles function-
alized by organic ligands 共average diameter of ⬃4 nm兲 were
obtained from Harima Co. Ltd and diluted with xylene sol-
vent to print. Au nanoparticle ink droplets were deposited
into the confinement gap defined by the first electrode pattern
using a homebuilt ink-jet printing setup with a standard
single-nozzle drop-on-demand piezoelectric print head 共Mi-
crodrop GmbH, Germany兲. The samples were annealed on
hot plate 共250 ° C, 1 h兲 to increase the Au conductivity. After
annealing the printed Au line exhibited a conductivity of
over 104 S / cm. We emphasize that the Au patterns for the
first electrode can also formed by ink-jet printing of Au
nanoparticle as described in our previous report.13 ZnO NWs
were grown on a-plane sapphire substrates by thermal
chemical vapor deposition. ZnO powder and graphite pow-
der were mixed in a 1:1 weight ratio. Then, source materials
were ground together and placed on an alumina boat which
was loaded into an alumina reaction tube located in a high
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Appl. Phys. Lett. 91, 043109 共2007兲
FIG. 2. 共Color online兲 共a兲 Schematic diagram of top-gate NW-FET with
SAP source-drain electrodes. 共b兲 Current vs voltage characteristics between
two self-aligned printed Au electrodes separated by a 500 nm with 共filled
squares兲 or without 共filled circles兲 single ZnO NW. The same measurement
was done after annealing 共200 ° C, 1 h兲 in oxygen and moisture-free glove-
box 共filled triangles兲. No current is observed in the absence of the nanowire.
共c兲 Output and 共d兲 transfer curve of all solution processed ZnO NW-FET.
The gate leakage currents were measured at VD = 1 V 共filled triangles兲 at the
same time.
temperature tube furnace. Argon as the carrier gas for the
vapor reactants was introduced into the reaction tube at a
flow rate of 50 SCCM 共SCCM denotes cubic centimeter per
minute at STP兲, while the furnace was heated to 930 ° C at a
rate of 40 ° C / min. After the growth process the samples
were cooled slowly to room temperature in argon gas ambi-
ent. ZnO NWs were dispersed in IPA 共spin coating兲 or IPA
and ethylene glycol mixture 共ink-jet printing兲, and a single
NW was transferred onto pattern by spin casting or ink-jet
printing 关see Figs. 1共c兲–1共e兲兴. The main benefit of applying
ink-jet printing technique to deposition of the NW solution is
the ability to selectively deposit the NWs into the channel
area with a relative high yield compared to spin casting from
diluted ZnO NW solution. The sample was then annealed
共200 ° C, 1 h兲 in an oxygen and moisture-free glovebox
共⬍5 ppm兲 to remove adsorbed oxygen on the NW surface
and to improve the electrical contact at the NW-Au interface.
A 100– 200 nm thick PMMA 共Aldrich, molecular weight
= 120 000兲 gate dielectric film was then spin coated from
anhydrous n-butyl acetate solution 共40 mg/ ml兲. FETs were
completed by ink-jet printing of PEDOT:PSS as a gate elec-
trode 关see Fig. 2共a兲兴. We found that the annealing process
gives an enough adhesion between NW and Au electrode to
avoid washing away by spin coating of PMMA overlayer.
The samples prepared without the annealing process exhib-
ited a relatively low yield due to partly vanish of NW from
the substrate after spin coating of PMMA. The electrical
characteristics were measured with an HP 4155B semicon-
ductor parameter analyzer in nitrogen atmosphere under yel-
low light.
The current flow between Au source and drain through
the single ZnO NW was first measured in the absence of a
gate electrode 关Fig. 2共b兲兴. The samples were prepared with
the same process like above without a printing PEDOT:PSS
gate electrode. A high current density of 3184 A / cm2 at
0.1 MV/ cm was observed to flow from source to drain
through a single ZnO NWs. The amount of current flow was
improved around 1.5 times after annealing 共200 ° C, 1 h兲
 043109-3 Noh et al.
FIG. 3. 共Color online兲 Output 共a兲 and transfer 共b兲 curve of top-gated ZnO
NW-FET having 2 ␮m channel length fabricated by optical lithography.
samples in the glovebox due to a better contact at ZnO
NW-Au interface, the reduction in depletion width, and the
effect of surface passivation with the PMMA dielectric.7
Figures 2共c兲 and 2共d兲 show typical n-type output and transfer
characteristics of the solution processed ZnO NW-FET. We
observe good modulation of the channel conductance by the
applied gate voltage with low gate leakage in the transfer
curve and a clean saturation and pinch-off behavior in the
output curve. The characteristics indicate that the transistors
operate in n-type depletion mode. Maximum transconduc-
tance 共gm兲 was 20.5 nS at VD = 1 V and at VG = 4 V. The field
effect mobility 共␮兲 of our ZnO NW-FETs was estimated
from the following equation; ␮ = L2gm / CbVD,14 where L is
the channel length 共500 nm兲 and Cb the capacitance of the
PMMA gate dielectric 共0.07 fF兲. Cb was calculated using
Cb = 2␲␧0␧rL / ln共2h / rNW兲,14 where ␧r is the dielectric con-
stant of PMMA 共3.5兲, h the thickness of PMMA 共100 nm兲,
and rNW the radius of the NW 共50 nm兲. The maximum cal-
culated field effect mobility was estimated to be 4 cm2 / V s
共typically 1 – 4 cm2 / V s兲. The performance was comparable
to that of typical bottom-gated ZnO-FETs,6 although less
than the recently published high-performance ZnO NW-FETs
with omega-shaped gate or polyimide encapsulation layer.6,7
The lower performance of our NW-FET can be ex-
plained by a nonoptimum contact between ZnO and Au. Au
is not the ideal choice of metal for electron injection to ZnO
because of the significant mismatch between the electron af-
finity of ZnO 共4.35 eV兲 and work function of Au 共5.1 eV兲.15
We expect that the contact resistance degrades the perfor-
mance of the device when the channel length is reduced to
submicrometer dimensions.16
To check the effect of contact resistance in our SAP ZnO
NW-FET, the same transistor structure was fabricated on a
photolithographically defined 共L = 2 ␮m兲 electrode pattern as
a reference. All other conditions were identical with the ink-
jet printed NW-FETs except for the thickness of the PMMA
gate dielectric 共500 nm, which was necessary to achieve ad-
equate gate isolation over the larger electrode structure兲.
Figures 3共a兲 and 3共b兲 display transfer and output character-
istics of ZnO NW-FET having 2 ␮m channel length. Maxi-
mum gm was 513 nS and significantly improved compared to
the transistor with 500 nm channel length. The estimated
maximum field effect mobility was 21.3 cm2 / V s 共typically
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Appl. Phys. Lett. 91, 043109 共2007兲
15– 20 cm2 / V s兲 with high on/off current ratio of 105. The
significantly better performance of the long-channel length
devices indicates that the properties of the submicrometer
ZnO NW-FET are mainly limited by contact resistance, as
opposed to other possible reasons such as other issues related
to the solution fabrication or the crystalline quality of the
nanowires used. Further improvement of the performance of
ink-jet printed ZnO NW-FETs is expected from using SAP
source-drain patterned electrodes of lower work function
metal nanoparticles, such as Ag or modification of contact
between ZnO and Au electrodes by self-assembled
monolayer.17
In conclusion, we have demonstrated all-solution pro-
cessed ZnO NW-FETs. Using SAP of Au nanoparticles sub-
micrometer channel length for source and drain gaps was
realized into which solution-dispersed single ZnO nanowire
was deposited by spin casting or ink-jet printing. We believe
that our approach can be applied to a broad range of
solution-dispersible NW semiconductors, and that it can be
extended to other device configurations, such as, for ex-
ample, configuration in which the NW is first deposited onto
the substrate and the electrodes are then printed by the SAP
process to contact the nanowires. Although further optimiza-
tion of contact formation and choice of gate dielectric and
nanowire surface passivation are needed to enhance perfor-
mance, our printing approach provides a potential pathway
for the cost-effective, solution-based manufacturing of NW-
FETs.
The research was supported by the Engineering and
Physical Sciences Research Council 共EPSRC兲 and Samsung
Electronics, Korea. One of the authors 共D.J.K.兲 is also sup-
ported by the SRC program 共Center for Nanotubes and
Nanostructured Composites兲 of Ministry of Science and
Technology of Korea/Korea Science and Engineering
Foundation.
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