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  • Feux

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    Farhat Rahma
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    This document describes a VHDL code for a finite state machine with 10 states (E0 to E9). On each clock cycle, the state signal E transitions to the next state. The output ports rp, op, vp, rs, os, vs, rpi, and vpi are assigned different values depending on the current state of E. The state machine transitions through each state in order from E0 to E9 and then loops back to E0.

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    feux

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    This document describes a VHDL code for a finite state machine with 10 states (E0 to E9). On each clock cycle, the state signal E transitions to the next state. The output ports rp, op, vp, rs, os, vs, rpi, and vpi are assigned different values depending on the current state of E. The state machine transitions through each state in order from E0 to E9 and then loops back to E0.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    13 views1 page

    Feux

    Uploaded by

    Farhat Rahma
    This document describes a VHDL code for a finite state machine with 10 states (E0 to E9). On each clock cycle, the state signal E transitions to the next state. The output ports rp, op, vp, rs, os, vs, rpi, and vpi are assigned different values depending on the current state of E. The state machine transitions through each state in order from E0 to E9 and then loops back to E0.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    of 1

    entity tpfeusem is

    port(clk: in bit;rp,op,vp,rs,os,vs,rpi,vpi:out bit);


    end tpfeusem;
    Architecture Atpfeusem of tpfeusem is
    type etat is (E0,E1,E2,E3,E4,E5,E6,E7,E8,E9);
    signal E: etat;
    begin
    process (clk)
    begin
    if (clk'event and clk='1') then
    case E is
    when E0 => E<=E1;
    when E1 => E<=E2;
    when E2 => E<=E3;
    when E3 => E<=E4;
    when E4 => E<=E5;
    when E5 => E<=E6;
    when E6 => E<=E7;
    when E7 => E<=E8;
    when E8 => E<=E9;
    when E9 => E<=E0;
    end case;
    if (E=E0) then
    rp<='1';op<='0';vp<='0';rs<='1';os<='0';vs<='0';rpi<='1';vpi<='0';end if;
    if (E=E1) then
    rp<='0';op<='0';vp<='1';rs<='1';os<='0';vs<='0';rpi<='1';vpi<='0';end if;
    if (E=E2) then
    rp<='0';op<='0';vp<='1';rs<='1';os<='0';vs<='0';rpi<='1';vpi<='0';end if;
    if (E=E3) then
    rp<='0';op<='1';vp<='0';rs<='1';os<='0';vs<='0';rpi<='1';vpi<='0';end if;
    if (E=E4) then
    rp<='1';op<='0';vp<='0';rs<='0';os<='0';vs<='1';rpi<='1';vpi<='0';end if;
    if (E=E5) then
    rp<='1';op<='0';vp<='0';rs<='0';os<='0';vs<='1';rpi<='1';vpi<='0';end if;
    if (E=E6) then
    rp<='1';op<='0';vp<='0';rs<='0';os<='1';vs<='0';rpi<='1';vpi<='0';end if;
    if (E=E7) then
    rp<='1';op<='0';vp<='0';rs<='1';os<='0';vs<='0';rpi<='0';vpi<='1';end if;
    if (E=E8) then
    rp<='1';op<='0';vp<='0';rs<='1';os<='0';vs<='0';rpi<='0';vpi<='1';end if;
    if (E=E9) then
    rp<='1';op<='0';vp<='0';rs<='1';os<='0';vs<='0';rpi<='0';vpi<='1';end if;
    end if;
    end process;end Atpfeusem;

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