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  • Exerice N1 Examen Code VHDL PartieA

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    Mariem Tlili
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    This document defines an entity called FSM_VentA that contains a finite state machine with 4 states (E0, E1, E2, E3). It has two inputs, S0 and H, and two outputs, V1 and V2. The state transitions are defined by a case statement on the current state and the input S0. The current state is stored in the signal Ep and next state in Ef. The state is updated on the rising edge of clock H. The outputs V1 and V2 are assigned logic values based on the current state.

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    Exerice-N1-Examen-Code-VHDL-PartieA-

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    This document defines an entity called FSM_VentA that contains a finite state machine with 4 states (E0, E1, E2, E3). It has two inputs, S0 and H, and two outputs, V1 and V2. The state transitions are defined by a case statement on the current state and the input S0. The current state is stored in the signal Ep and next state in Ef. The state is updated on the rising edge of clock H. The outputs V1 and V2 are assigned logic values based on the current state.

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    4 views1 page

    Exerice N1 Examen Code VHDL PartieA

    Uploaded by

    Mariem Tlili
    This document defines an entity called FSM_VentA that contains a finite state machine with 4 states (E0, E1, E2, E3). It has two inputs, S0 and H, and two outputs, V1 and V2. The state transitions are defined by a case statement on the current state and the input S0. The current state is stored in the signal Ep and next state in Ef. The state is updated on the rising edge of clock H. The outputs V1 and V2 are assigned logic values based on the current state.

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    © All Rights Reserved
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    of 1

    Library IEEE;

    Use IEEE.STD_LOGIC_1164.ALL;
    Use IEEE.STD_LOGIC_arith.ALL;

    entity FSM_VentA is
    Port (S0,H ,Reset :IN std_logic;
    V1,V2:OUT std_logic);
    end FSM_Vent1;

    ARCHITECTURE Arch_VentA of FSM_VentA is


    Type Etats_FSM is (E0,E1,E2,E3);
    Signal Ep,Ef: Etats_FSM;
    begin
    Combinatoire:process(S0,Ep)
    begin
    Case Ep is
    when E0 => if S0='1' then Ef <= E1;
    else Ef <= E0;
    end if;
    when E1 => if S0='0' then Ef <= E2;
    else Ef <= E1;
    end if;
    when E2 => if S0='1' then Ef <= E3;
    else Ef <= E2;
    end if;
    when E3 => if S0='0' then Ef <= E0;
    else Ef <= E3;
    end if;
    end case;
    end process;

    Memoire: Process(H,Reset)
    begin
    if (Reset = '1') then EP <= E0;
    elsif (H = '1' and H'event) then Ep <= Ef;
    end if;
    end process;

    Sortie: process(Ep)
    begin
    case Ep is
    when E0 => V1<='0';V2<='0';
    when E1 => V1<='1';V2<='0';
    when E2 => V1<='0';V2<='0';
    when E3 => V1<='0';V2<='1';
    end case;
    end process;
    end Arch_VentA;

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