Corrigé type TD03

Exercice 01 :
Table de vérité d’un multiplexeur 2 à 1 : Expression logique pour le mux2x1 :
Sel S
0 .e0
1 .e1
S = e0 . sel + e1 . sel
Table de vérité d’un multiplexeur 4 à 1 : Expression logique pour le mux4x1 :

.sel1 .sel0 s
0 0 .e0
0 1 .e1
1 0 .e2
1 1 .e3
S = e0 . sel1 . sel0 + e1 . sel1 . sel0 + e2 . sel1 . sel0 + e3 . sel1 . sel0

Code VHDL pour le mux 2 à 1 :

Entity MUX2x1is
Port ( e0, e1, sel : in std_logic ;
S : out std_logic) ;
End MUX2x1 ;
Architecture BEHAV of MUX2x1 is
Begin
Process(sel)
Begin
If (sel =’0’) then
S <= e0;
Else
S <= e1;
End if; end process; end BEHAV;

Code VHDL pour le mux 4 à 1 :

Entity MUX4x1is
Port ( e0, e1, e2,e3, sel1,sel0 : in std_logic ;
S : out std_logic) ;
End MUX4x1 ;
Architecture BEHAV of MUX4x1 is
Sel <= sel1&sel0 ;
Signal sel : std_logic;
Begin
Process(sel )
Begin
Case sel is
When “00” => s<=e0;
When “01” => s<=e1;
When “10” => s<=e2;
When others => s<=e3;
End case; end process; end BEHAV;

Exercice 02 :
Table de vérité d’un additionneur complet :

Rin A B S Rout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Expressions logiques des sorties : (+) représente le xor

S = Rin . (A .B + A. B) + Rin . (A .B + A. B) = Rin . (A (+) B) + Rin . (A (+) B) = Rin (+) A (+) B
Rout = Rin . (A (+) B) + A.B

Code VHDL FADD de type data flow :

Entity FADD is
Port(Rin, A,B: in std_logic;
S, Rout: out std_logic) ;
End FADD ;
Architecture DF of FADD is
Begin
S <= Rin xor A xor B;
Rout <= (Rin and (A xor B)) or (A and B);
End DF;
Code VHDL FADD de type comportemental :
Entity FADD is
Port(Rin, A,B: in std_logic;
S, Rout: out std_logic) ;
End FADD ;
Architecture DF of FADD is
Signal inp: std_logic_vector(2 downto 0);
Begin
Process(inp)
Begin
Case inp is
When “000” => S <= ‘0’, Rout <= ‘0’;
When “001” => S <= ‘1’, Rout <= ‘0’;
When “010” => S <= ‘1’, Rout <= ‘0’;
When “011” => S <= ‘0’, Rout <= ‘1’;
When “100” => S <= ‘1’, Rout <= ‘0’;
When “101” => S <= ‘0’, Rout <= ‘1’;
When “110” => S <= ‘0’, Rout <= ‘1’;
When others => S <= ‘1’, Rout <= ‘1’;
End case;
End process;
End DF;