Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_arith.ALL;

entity FSM_VentB is
Port (S0, S1,H ,Reset :IN std_logic;
V1,V2:OUT std_logic);
end FSM_VentB;

ARCHITECTURE Arch_VentB of FSM_VentB is

Type Etats_FSM is (E0,E1,E2,E3,E4,E5);
Signal Ep,Ef: Etats_FSM;
begin
Combinatoire:process(S0,S1,Ep)
begin
Case Ep is
when E0 => if S0='1' and S1='0' then Ef <= E1;
else Ef <= E0;
end if;
when E1 => if S0='0' and S1='0' then Ef <= E2;
else Ef <= E1;
end if;
when E2 => if S0='1' and S1='0' then Ef <= E3;
else Ef <= E2;
end if;
when E3 => if S0='1' and S1='1' then Ef <= E4;
else Ef <= E3;
end if;
when E4 => if S0='1' and S1='0' then Ef <= E5;
else Ef <= E4;
end if;
when E5 => if S0='0' and S1='0' then Ef <= E0;
else Ef <= E5;
end if;
end case;
end process;

Memoire: Process(H,Reset)
begin
if (Reset = '1') then EP <= E0;
elsif (H = '1' and H'event) then Ep <= Ef;
end if;
end process;

Sortie: process(Ep)
begin
case Ep is
when E0 => V1<='0';V2<='0';
when E1 => V1<='1';V2<='0';
when E2 => V1<='0';V2<='0';
when E3 => V1<='0';V2<='1';
when E4 => V1<='1';V2<='1';
when E5 => V1<='1';V2<='0';
end case;
end process;
end Arch_VentB;