Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_arith.ALL;

entity FSM_Coca is
Port (E1,E2 ,Annuler ,H ,Reset :IN std_logic;
B,A:OUT std_logic);
end FSM_Coca;

ARCHITECTURE Arch_Coca of FSM_Coca is

Type Etats_FSM is (0m,100m,200m,300m,400m,500m);
Signal Ep,Ef: Etats_FSM;
begin
Combinatoire:process(E1,E2,Ep)
begin
Case Ep is
when 0m => if (E1='1'and E2='0') then Ef <= 100m; A<='0';B<='0';
elsif (E1='0' and E2='1') then Ef <= 500m; A<='0';B<='0';
else Ef <= 0m; A<='0';B<='0';
end if;
when 100m => if (E1='1'and E2='0') then Ef <= 200m; A<='0';B<='0';
elsif (E1='0'and E2='1') then Ef <=0m; A<='0';B<='1';
elsif (Annuler='1') then Ef <= 0m; A<='1';B<='0';
else Ef <= 100m; A<='0';B<='0';
end if;
when 200m => if (E1='1'and E2='0') then Ef <= 300m; A<='0';B<='0';
elsif (E1='0'and E2='1') then Ef <=0m; A<='1';B<='0';
elsif (Annuler='1') then Ef <= 0m; A<='1';B<='0';
else Ef <= 200m; A<='0';B<='0';
end if;
when 300m => if (E1='1'and E2='0') then Ef <= 400m; A<='0';B<='0';
elsif (E1='0'and E2='1') then Ef <=0m; A<='1';B<='0';
elsif (Annuler='1') then Ef <= 0m; A<='1';B<='0';
else Ef <= 300m; A<='0';B<='0';
end if;
when 400m => if (E1='1'and E2='0') then Ef <= 500m; A<='0';B<='0';
elsif (E1='0'and E2='1') then Ef <=0m; A<='1';B<='0';
elsif (Annuler='1') then Ef <= 0m; A<='1';B<='0';
else Ef <= 400m; A<='0';B<='0';
end if;
when 500m => if (E1='1'and E2='0') then Ef <= 0m; A<='0';B<='1';
elsif (E1='0'and E2='1') then Ef <=0m; A<='1';B<='0';
elsif (Annuler='1') then Ef <= 0m; A<='1';B<='0';
else Ef <= 500m; A<='0';B<='0';
end if;
end case;
end process;

Memoire: Process(H,Reset)
begin
if (Reset = '1') then EP <= E0;
elsif (H = '1' and H'event) then Ep <= Ef;
end if;
end process;

end Arch_Coca;