Smart Combiner for Fixed Commercial Photovoltaic Systems Using
Power Line Communication
Chad Herndon, Yunus Erkaya, Chunsheng Xin, Isaac Flory, Shirshak Dhali, Sylvain X. Marsillac
Virginia Institute of Photovoltaics (VIPV), Norfolk, VA 23529 USA
Abstract — Every year in the US, over 1000MW of
photovoltaic (PV) panels are installed in the commercial sector. In
order to increase this installation rate, lifecycle cost of ownership
is a critical and transformative issue. Operation and maintenance
costs must be lowered to improve the return on investment for
owners. By creating a smart combiner, faulty PV panels can be
immediately identified and replaced, minimizing down time and
man-hours spent locating faulty PV panels. Further cost
reductions are achievable by using the existing DC powerline for
communication. Powerline communication (PLC) or Distribution
Line Carrier Communication simplifies the installation of
photovoltaic fault detection systems and provides a reliable means
for fault isolation. Electrical parameters at the panel level can be
continuously monitored and alarms initiated when faults are
detected. This paper highlights the features of PLC as a reliable
means for communication and presents the experimental results
of a prototype system that is capable of fault detection.
Index Terms — fault detection, photovoltaic, powerline
communication.
I. INTRODUCTION
The National Renewable Energy Laboratory (NREL) Solar
Technologies Market reported that the global photovoltaic
(PV) industry has seen tremendous growth in cell/module
manufacturing in the past decade exhibiting a 5-year
compound annual growth rate of 56% [1]. The Solar Energy
Industries Association reported that in the third quarter of
2012 the commercial market (including government and
institutions) rose 24% above the previous quarter to 257
megawatts. With system prices for photovoltaic (PV) declining
every year, this growth trend is expected to continue in the
future and will be driven by innovations particularly in
efficiency and reliability.
At the device level, PV modules are about 14%-16%
efficient, and in complex integrated systems the additional
losses can be as a high as 25% due to mismatches of I-V
characteristics resulting from defective modules and
shadowing. Although inverters optimize the performance by
using maximum power point tracking (MPPT) algorithms,
having too many inverters can be expensive and results in
additional losses [2]. Therefore, to minimize the cost of PV
systems, in most installations, strings of panels are connected
together and fed to a single inverter. Mismatches of the
interconnected strings are a serious problem because the
output of the combined strings is determined by the worst
performing panel. In general, the reduction in power is worse
for series connected panels, which are used to boost the DC
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voltage to a level of 240-480V. Although bypass and blocking
diodes are used to mitigate the effect, even a moderate shading
or failure of a single panel can result in significantly lower
power generation. Even failures resulting in a large energy
deficit are difficult to detect due to the fluctuating nature of the
energy yield inherent of PV systems. Detecting the fault and
pinpointed the exact location is an engineering challenge and
there is no industry standard for fault location; installers tend
to use ad hoc schemes such as thermal imaging.
Our smart combiner is designed to be capable of detecting
faults at the panel level while minimizing wiring by using
power lines for communication as shown in Fig. 1. The system
is comprised of two modules: the combiner and the
display/alarm. The combiner module will have voltage
sensors, hall current sensors, and a microcontroller. The
microcontroller is used to control and interface these sensors
to a Frequency Shift Keying (FSK) modem, which will
superimpose a high frequency Alternating Current (AC) signal
over the Direct Current (DC) power supplied by the PV
panels. A high voltage coupling capacitor is used to block the
DC voltage and current to protect the modem. A display/alarm
module will be mounted near the inverter and will be used to
demodulate the FSK signal, display the current, voltage,
power, and indicate the presence of a faulty panel.
Combiner Module
Display Module
Microcontroller FSK Module Interface FSK Module
/Sensor module Interface Display/alarm
DC Powerline coupling DC Powerline coupling
circuits (40-400 V) circuits (40-400 V)
PV Panels
Inverter
DC Power line
Fig. 1. The architecture of smart combiner.
II. POWERLINE COMMUNICATION
In order to utilize the existing wiring for communication,
special attention must be given to safeguarding signal integrity
through DC power lines, and associated circuitry. Since the
communication signal is high frequency AC, consideration
must be made to the carrier frequency and the effects of
dynamic impedance on signal propagation. High frequency AC
has the benefit of fast data rates, at the expense of increased
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attenuation due to increased impedance. Low frequency results CY8CPLC10 PLC, external microcontroller, panel sensors,
in a lower data rate, but better attenuation characteristics. and alarm indication.
Since the panel diagnostics does not need expedient results, a
low/medium frequency and data-rate is desired. Additionally,
the system must prevent collisions during communication. A
master/slave scheme is preferred where the master listens to
the line before requesting information from the slave devices,
subsequently the slaves respond when the line is clear.
Specialized integrated circuits are available in order to
facilitate reliable power line communication. Specifically,
Cypress Semiconductor has designed the CY8CPLC10
powerline communication IC chip as a robust communication
device capable of secure and reliable communication over
power lines [3].
Cypress PLC features many optimizations for power line
communication. A powerline optimized Network Protocol is Fig. 2. CY8CPLC10 fault detection scheme.
used to create Power Line Transceiver (PLT) packets
supporting bidirectional communication with
III. PROTOTYPE
acknowledgement based signaling. An integrated Power line
Physical Layer (PHY) modem with optimized filters and Cypress Semiconductor sells PLC evaluation kits to test the
amplifier is included for reliable half duplex communication. CY8CPLC10 before designing a printed circuit board (PCB).
An 8-bit cyclic redundancy check (CRC) is included for error The CY2373 PLC evaluation kit was useful for first
detection and data packet retransmission. Band-In-Use (BIU) demonstrating the CY8CPLC10 PLC solution was feasible for
detects line status, and a Carrier Sense Multiple Access many nodes connected on the same DC powerline and to
(CSMA) scheme senses the line and waits for between 85 and develop the software for fault detection. Accurate and reliable
115 ms of silence before transmitting in order to indicate if the transfer of data was achieved for voltage of individual PV
line is in use. These features are built into the Network panels. After validating the CY8CPLC10 chip for operation
Protocol to minimize collisions of packets on the power line prototype master and slave units were developed.
[3]. Each feature of the CY8CPLC10 facilitates the secure and The prototype units incorporate the Cypress PSoC 1
reliable transfer of data over the DC powerline. microcontroller. PSoC 1 is a programmable system on a chip
Every panel must be supplied with an analog sensor module used to configure the modem and the network protocol of the
capable of voltage and current measurements, which in turn PLC chip as well as gather I/V sensor readings for diagnostics.
communicates with the microcontroller. The analog data is The PSoC 1 chip receives analog data from the sensors and
converted to a digital signal and sent to the CY8CPLC10 PLC converts it to digital information for powerline
chip via I2C serial protocol. Before coupling to the power line, communication. The following algorithm in Fig. 3 was
the CY8CPLC10 chip modulates the signal using a local developed to retrieve the analog voltage signal and convert to
oscillator for FSK at 131.8 kHz for logic ‘1’ and 133.3 kHz a useful voltage reading.
for logic ‘0’ to send the sensor information over the powerline.
At the master location demodulation occurs. A CY8CPLC10
amplifies the signal and sends it to a High Frequency (HF)
Band Pass Filter. This filters out everything except for signals
within the desired spectrum of 125 kHz to 140 kHz. A
correlator produces a DC signal with Logic ‘1’s and ‘0’s and
demodulated digital data at 2400 baud is constructed. This
information is sent to the host microcontroller. The
microcontroller has firmware capable of calculating power and
determining if the associated panel is defective. Once a panel
is determined to be defective, an alarm is initiated warning the
owner of the string with the potential panel failure, and a local
light emitting diode (LED) is illuminated to provide quick
visual identification of a failed panel. This greatly aids the
operator in faulty panel detection and isolation. Fig. 2
illustrates the connection of each component including: Fig. 3. Voltage monitoring.
powerline coupling (coupling capacitors), the Cypress

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Using the installed firmware the PSoC microcontroller sends
the analog data to a programmable gain amplifier (PGA), and
then passes the data to the analog to digital converter (ADC);
finally the digital voltage is converted to a useful voltage by
multiplying by a scale factor and conversion to ASCII
characters for display on the LCD. PV panel current data is
gathered in the same manner. A different analog-in pin is used
and the scale factor is changed to create an accurate current
readout. The current and voltage readings are then used to
calculate power. The three measurements are used to
determine if a panel is faulty. The average power is calculated,
and then each panel is compared to the average. If the
individual panel’s power falls 20% below the average for a
period of time an alarm is initiated and the local LED lights
indicating a faulty panel.
In order to drive the signal onto the low impedance line, an
amplifier circuit was incorporated into the circuit. The
amplifier consists of an inverting OPAMP configuration
driving a pair of matched transistors in a push/pull
configuration. Figure 4 is a captured image of the prototype
breadboard.
Fig. 4. Prototype breadboard of system
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The prototype shown above has a 5V power supply, which
is supplied from the local PV panel. The power supply
provides power to the OPAMP, PSoC 1, CY8CPLC10, as well
as secondary components. A receiver circuit is included which
filters out unnecessary noise present in the line and provides
the VCC/2 biasing required by the PLC chip. The transmit
circuitry contains the push/pull transistors and has a DC
blocking capacitor to protect the device side of the circuit. The
prototype shown is capable of sensing the analog electrical
parameters and performs the power line communication for
data transfer to the master board.
IV. TESTING AND RESULTS
In order to verify that the CY8CPLC10 and the prototype
board was a suitable PLC solution, several tests were needed.
First, since PV panels exhibit dynamic resistance qualities
under various operating conditions, it was mandatory to
demonstrate that FSK signals could propagate through the DC
system under several operating conditions. Sensor verification
was needed to ensure that accurate electrical characteristics
could be detected and used to determine if a panel was faulty.
Additionally, since PV installations have long runs of wires,
signal integrity tests were performed through various lengths
of wire.
Software was written to obtain the address of a slave node to
demonstrate that signals could propagate over the DC power
line. Two prototype boards were connected to two series
connected PV panels. One prototype board was designated as
the master, and the second as the slave. The master requested
logical address information at regular intervals, and the slave
successfully complied by sending its logical address. The
following image in Figure 5 is the continuous stream of
packets from the master, the slave complying, and the
acknowledge packets from the master. This clearly
demonstrates that the signal was capable of propagating
through the system.
Fig. 5. Screenshot of data packet transmission
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This test was performed with various lengths of wire and the
PV panel operating at several points along the power curve.
The following image is the signal that was received after
propagating through the test system. Minimal attenuation was
observed and the packet arrived with high reliability.
Fig. 6. Received signal with minimal attenuation
Since the packets transmitted successfully the CY8CPLC10
was chosen for prototype development.
Next, the accuracy of the sensor data was verified. The
voltage and current sensors were attached to the PV panels and
the prototype was connected. The following figure is of the
correlation of the measured voltage to the actual voltage
(Figure 7). Clearly the measured and actual voltage readings
correlate which supports accurate current, voltage, and power
indications.
Fig. 7. Measured vs. actual voltage
PV installations have many long runs of wire from the
panels to the inverters. These wires have inherent resistance
and impedance which interferes with signal propagation. To
ensure signal integrity over long lengths of wire, tests were
performed which measured the number of dropped signals due
to signal degradation. The nodes were loaded with firmware,
which forced the master node to continuously send pulses to
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the slave and wait for an acknowledgement from the slave.
The master counted the number of pulses sent and the number
of acknowledgements received. The length of the wire was
varied from 1 foot up to 300 feet. Figure 8 illustrates the
percentage of failed acknowledgements versus feet of wire
using 500 pulses for a given length of wire. One can observe
that up to 130 feet of cabling resulted in 0.02% failed
acknowledgements, while at 300 feet only 0.8% was observed.
This high success rate guarantees reliable data transfer through
long runs of cabling.
Fig. 8. Experimental data of failed acknowledgements.
After performing the prior tests, the system was ready to test
for fault diagnostics capability. Three panels connected
together in series had the prototypes installed and a master
controller was connected to the DC bus. The master
continually polled the status of the sensors for each PV and
calculated the average of the system. Whenever the PV panel
fell 20% below the average, an alarm was initiated and an
LED lit on the failing panel. To simulate a failure one panel
was partially covered with a blanket. This poorly operating
panel fell below the average of the system and an alarm was
initiated. The LED illuminated and properly indicated the
faulty panel. The following graphs are of a normal string of
panels and one with a failure. The normal string in Figure 9
has all panels and the average track with the actual voltage.
Fig. 9. Voltage signal of normal string.
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 replaced, saving valuable resources and therefore reducing the
operational costs of PV installations. This is important for the
future of solar power by making it more marketable to both
residential and commercial markets. By utilizing the existing
powerlines for communication, it is possible to design a
solution that provides accurate panel fault indication while
minimizing the effort needed to install other diagnostics
means.

IV. ACKNOWLEDGEMENT
This work has been supported by the Center for Innovative
Technology (Virginia).
Fig. 10. Voltage signal of faulty string.

Conversely, Figure 10 depicts a string with a faulty panel. REFERENCES

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